2 * Qualcomm PCIe root complex driver
4 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 * Copyright 2015 Linaro Limited.
7 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 and
11 * only version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
24 #include <linux/iopoll.h>
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/of_device.h>
28 #include <linux/of_gpio.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/phy/phy.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/reset.h>
34 #include <linux/slab.h>
35 #include <linux/types.h>
37 #include "pcie-designware.h"
39 #define PCIE20_PARF_PHY_CTRL 0x40
40 #define PCIE20_PARF_PHY_REFCLK 0x4C
41 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
42 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
43 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
45 #define PCIE20_ELBI_SYS_CTRL 0x04
46 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
48 #define PCIE20_CAP 0x70
50 #define PERST_DELAY_US 1000
52 struct qcom_pcie_resources_v0 {
53 struct clk *iface_clk;
56 struct reset_control *pci_reset;
57 struct reset_control *axi_reset;
58 struct reset_control *ahb_reset;
59 struct reset_control *por_reset;
60 struct reset_control *phy_reset;
61 struct regulator *vdda;
62 struct regulator *vdda_phy;
63 struct regulator *vdda_refclk;
66 struct qcom_pcie_resources_v1 {
69 struct clk *master_bus;
70 struct clk *slave_bus;
71 struct reset_control *core;
72 struct regulator *vdda;
75 union qcom_pcie_resources {
76 struct qcom_pcie_resources_v0 v0;
77 struct qcom_pcie_resources_v1 v1;
82 struct qcom_pcie_ops {
83 int (*get_resources)(struct qcom_pcie *pcie);
84 int (*init)(struct qcom_pcie *pcie);
85 void (*deinit)(struct qcom_pcie *pcie);
91 union qcom_pcie_resources res;
96 struct gpio_desc *reset;
97 struct qcom_pcie_ops *ops;
100 #define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
102 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
104 gpiod_set_value(pcie->reset, 1);
105 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
108 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
110 gpiod_set_value(pcie->reset, 0);
111 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
114 static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
116 struct pcie_port *pp = arg;
118 return dw_handle_msi_irq(pp);
121 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
125 if (dw_pcie_link_up(&pcie->pp))
128 /* enable link training */
129 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
130 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
131 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
133 return dw_pcie_wait_for_link(&pcie->pp);
136 static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
138 struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
139 struct device *dev = pcie->dev;
141 res->vdda = devm_regulator_get(dev, "vdda");
142 if (IS_ERR(res->vdda))
143 return PTR_ERR(res->vdda);
145 res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
146 if (IS_ERR(res->vdda_phy))
147 return PTR_ERR(res->vdda_phy);
149 res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
150 if (IS_ERR(res->vdda_refclk))
151 return PTR_ERR(res->vdda_refclk);
153 res->iface_clk = devm_clk_get(dev, "iface");
154 if (IS_ERR(res->iface_clk))
155 return PTR_ERR(res->iface_clk);
157 res->core_clk = devm_clk_get(dev, "core");
158 if (IS_ERR(res->core_clk))
159 return PTR_ERR(res->core_clk);
161 res->phy_clk = devm_clk_get(dev, "phy");
162 if (IS_ERR(res->phy_clk))
163 return PTR_ERR(res->phy_clk);
165 res->pci_reset = devm_reset_control_get(dev, "pci");
166 if (IS_ERR(res->pci_reset))
167 return PTR_ERR(res->pci_reset);
169 res->axi_reset = devm_reset_control_get(dev, "axi");
170 if (IS_ERR(res->axi_reset))
171 return PTR_ERR(res->axi_reset);
173 res->ahb_reset = devm_reset_control_get(dev, "ahb");
174 if (IS_ERR(res->ahb_reset))
175 return PTR_ERR(res->ahb_reset);
177 res->por_reset = devm_reset_control_get(dev, "por");
178 if (IS_ERR(res->por_reset))
179 return PTR_ERR(res->por_reset);
181 res->phy_reset = devm_reset_control_get(dev, "phy");
182 if (IS_ERR(res->phy_reset))
183 return PTR_ERR(res->phy_reset);
188 static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
190 struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
191 struct device *dev = pcie->dev;
193 res->vdda = devm_regulator_get(dev, "vdda");
194 if (IS_ERR(res->vdda))
195 return PTR_ERR(res->vdda);
197 res->iface = devm_clk_get(dev, "iface");
198 if (IS_ERR(res->iface))
199 return PTR_ERR(res->iface);
201 res->aux = devm_clk_get(dev, "aux");
202 if (IS_ERR(res->aux))
203 return PTR_ERR(res->aux);
205 res->master_bus = devm_clk_get(dev, "master_bus");
206 if (IS_ERR(res->master_bus))
207 return PTR_ERR(res->master_bus);
209 res->slave_bus = devm_clk_get(dev, "slave_bus");
210 if (IS_ERR(res->slave_bus))
211 return PTR_ERR(res->slave_bus);
213 res->core = devm_reset_control_get(dev, "core");
214 if (IS_ERR(res->core))
215 return PTR_ERR(res->core);
220 static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
222 struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
224 reset_control_assert(res->pci_reset);
225 reset_control_assert(res->axi_reset);
226 reset_control_assert(res->ahb_reset);
227 reset_control_assert(res->por_reset);
228 reset_control_assert(res->pci_reset);
229 clk_disable_unprepare(res->iface_clk);
230 clk_disable_unprepare(res->core_clk);
231 clk_disable_unprepare(res->phy_clk);
232 regulator_disable(res->vdda);
233 regulator_disable(res->vdda_phy);
234 regulator_disable(res->vdda_refclk);
237 static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
239 struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
240 struct device *dev = pcie->dev;
244 ret = regulator_enable(res->vdda);
246 dev_err(dev, "cannot enable vdda regulator\n");
250 ret = regulator_enable(res->vdda_refclk);
252 dev_err(dev, "cannot enable vdda_refclk regulator\n");
256 ret = regulator_enable(res->vdda_phy);
258 dev_err(dev, "cannot enable vdda_phy regulator\n");
262 ret = reset_control_assert(res->ahb_reset);
264 dev_err(dev, "cannot assert ahb reset\n");
268 ret = clk_prepare_enable(res->iface_clk);
270 dev_err(dev, "cannot prepare/enable iface clock\n");
274 ret = clk_prepare_enable(res->phy_clk);
276 dev_err(dev, "cannot prepare/enable phy clock\n");
280 ret = clk_prepare_enable(res->core_clk);
282 dev_err(dev, "cannot prepare/enable core clock\n");
286 ret = reset_control_deassert(res->ahb_reset);
288 dev_err(dev, "cannot deassert ahb reset\n");
289 goto err_deassert_ahb;
292 /* enable PCIe clocks and resets */
293 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
295 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
297 /* enable external reference clock */
298 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
300 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
302 ret = reset_control_deassert(res->phy_reset);
304 dev_err(dev, "cannot deassert phy reset\n");
308 ret = reset_control_deassert(res->pci_reset);
310 dev_err(dev, "cannot deassert pci reset\n");
314 ret = reset_control_deassert(res->por_reset);
316 dev_err(dev, "cannot deassert por reset\n");
320 ret = reset_control_deassert(res->axi_reset);
322 dev_err(dev, "cannot deassert axi reset\n");
326 /* wait for clock acquisition */
327 usleep_range(1000, 1500);
332 clk_disable_unprepare(res->core_clk);
334 clk_disable_unprepare(res->phy_clk);
336 clk_disable_unprepare(res->iface_clk);
338 regulator_disable(res->vdda_phy);
340 regulator_disable(res->vdda_refclk);
342 regulator_disable(res->vdda);
347 static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
349 struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
351 reset_control_assert(res->core);
352 clk_disable_unprepare(res->slave_bus);
353 clk_disable_unprepare(res->master_bus);
354 clk_disable_unprepare(res->iface);
355 clk_disable_unprepare(res->aux);
356 regulator_disable(res->vdda);
359 static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
361 struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
362 struct device *dev = pcie->dev;
365 ret = reset_control_deassert(res->core);
367 dev_err(dev, "cannot deassert core reset\n");
371 ret = clk_prepare_enable(res->aux);
373 dev_err(dev, "cannot prepare/enable aux clock\n");
377 ret = clk_prepare_enable(res->iface);
379 dev_err(dev, "cannot prepare/enable iface clock\n");
383 ret = clk_prepare_enable(res->master_bus);
385 dev_err(dev, "cannot prepare/enable master_bus clock\n");
389 ret = clk_prepare_enable(res->slave_bus);
391 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
395 ret = regulator_enable(res->vdda);
397 dev_err(dev, "cannot enable vdda regulator\n");
401 /* change DBI base address */
402 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
404 if (IS_ENABLED(CONFIG_PCI_MSI)) {
405 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
408 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
413 clk_disable_unprepare(res->slave_bus);
415 clk_disable_unprepare(res->master_bus);
417 clk_disable_unprepare(res->iface);
419 clk_disable_unprepare(res->aux);
421 reset_control_assert(res->core);
426 static int qcom_pcie_link_up(struct pcie_port *pp)
428 struct qcom_pcie *pcie = to_qcom_pcie(pp);
429 u16 val = readw(pcie->dbi + PCIE20_CAP + PCI_EXP_LNKSTA);
431 return !!(val & PCI_EXP_LNKSTA_DLLLA);
434 static void qcom_pcie_host_init(struct pcie_port *pp)
436 struct qcom_pcie *pcie = to_qcom_pcie(pp);
439 qcom_ep_reset_assert(pcie);
441 ret = pcie->ops->init(pcie);
445 ret = phy_power_on(pcie->phy);
449 dw_pcie_setup_rc(pp);
451 if (IS_ENABLED(CONFIG_PCI_MSI))
452 dw_pcie_msi_init(pp);
454 qcom_ep_reset_deassert(pcie);
456 ret = qcom_pcie_establish_link(pcie);
462 qcom_ep_reset_assert(pcie);
463 phy_power_off(pcie->phy);
465 pcie->ops->deinit(pcie);
468 static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
471 /* the device class is not reported correctly from the register */
472 if (where == PCI_CLASS_REVISION && size == 4) {
473 *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
474 *val &= 0xff; /* keep revision id */
475 *val |= PCI_CLASS_BRIDGE_PCI << 16;
476 return PCIBIOS_SUCCESSFUL;
479 return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
482 static struct pcie_host_ops qcom_pcie_dw_ops = {
483 .link_up = qcom_pcie_link_up,
484 .host_init = qcom_pcie_host_init,
485 .rd_own_conf = qcom_pcie_rd_own_conf,
488 static const struct qcom_pcie_ops ops_v0 = {
489 .get_resources = qcom_pcie_get_resources_v0,
490 .init = qcom_pcie_init_v0,
491 .deinit = qcom_pcie_deinit_v0,
494 static const struct qcom_pcie_ops ops_v1 = {
495 .get_resources = qcom_pcie_get_resources_v1,
496 .init = qcom_pcie_init_v1,
497 .deinit = qcom_pcie_deinit_v1,
500 static int qcom_pcie_probe(struct platform_device *pdev)
502 struct device *dev = &pdev->dev;
503 struct resource *res;
504 struct qcom_pcie *pcie;
505 struct pcie_port *pp;
508 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
512 pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
515 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
516 if (IS_ERR(pcie->reset))
517 return PTR_ERR(pcie->reset);
519 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
520 pcie->parf = devm_ioremap_resource(dev, res);
521 if (IS_ERR(pcie->parf))
522 return PTR_ERR(pcie->parf);
524 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
525 pcie->dbi = devm_ioremap_resource(dev, res);
526 if (IS_ERR(pcie->dbi))
527 return PTR_ERR(pcie->dbi);
529 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
530 pcie->elbi = devm_ioremap_resource(dev, res);
531 if (IS_ERR(pcie->elbi))
532 return PTR_ERR(pcie->elbi);
534 pcie->phy = devm_phy_optional_get(dev, "pciephy");
535 if (IS_ERR(pcie->phy))
536 return PTR_ERR(pcie->phy);
538 ret = pcie->ops->get_resources(pcie);
544 pp->dbi_base = pcie->dbi;
545 pp->root_bus_nr = -1;
546 pp->ops = &qcom_pcie_dw_ops;
548 if (IS_ENABLED(CONFIG_PCI_MSI)) {
549 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
553 ret = devm_request_irq(dev, pp->msi_irq,
554 qcom_pcie_msi_irq_handler,
555 IRQF_SHARED, "qcom-pcie-msi", pp);
557 dev_err(dev, "cannot request msi irq\n");
562 ret = phy_init(pcie->phy);
566 ret = dw_pcie_host_init(pp);
568 dev_err(dev, "cannot initialize host\n");
572 platform_set_drvdata(pdev, pcie);
577 static const struct of_device_id qcom_pcie_match[] = {
578 { .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
579 { .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
580 { .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
584 static struct platform_driver qcom_pcie_driver = {
585 .probe = qcom_pcie_probe,
588 .suppress_bind_attrs = true,
589 .of_match_table = qcom_pcie_match,
592 builtin_platform_driver(qcom_pcie_driver);