MAINTAINERS: mmc: Move the mmc tree to kernel.org
[cascardo/linux.git] / drivers / pci / host / pcie-spear13xx.c
1 /*
2  * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
3  *
4  * SPEAr13xx PCIe Glue Layer Source Code
5  *
6  * Copyright (C) 2010-2014 ST Microelectronics
7  * Pratyush Anand <pratyush.anand@gmail.com>
8  * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
9  *
10  * This file is licensed under the terms of the GNU General Public
11  * License version 2. This program is licensed "as is" without any
12  * warranty of any kind, whether express or implied.
13  */
14
15 #include <linux/clk.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/of.h>
20 #include <linux/pci.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24
25 #include "pcie-designware.h"
26
27 struct spear13xx_pcie {
28         void __iomem            *app_base;
29         struct phy              *phy;
30         struct clk              *clk;
31         struct pcie_port        pp;
32         bool                    is_gen1;
33 };
34
35 struct pcie_app_reg {
36         u32     app_ctrl_0;             /* cr0 */
37         u32     app_ctrl_1;             /* cr1 */
38         u32     app_status_0;           /* cr2 */
39         u32     app_status_1;           /* cr3 */
40         u32     msg_status;             /* cr4 */
41         u32     msg_payload;            /* cr5 */
42         u32     int_sts;                /* cr6 */
43         u32     int_clr;                /* cr7 */
44         u32     int_mask;               /* cr8 */
45         u32     mst_bmisc;              /* cr9 */
46         u32     phy_ctrl;               /* cr10 */
47         u32     phy_status;             /* cr11 */
48         u32     cxpl_debug_info_0;      /* cr12 */
49         u32     cxpl_debug_info_1;      /* cr13 */
50         u32     ven_msg_ctrl_0;         /* cr14 */
51         u32     ven_msg_ctrl_1;         /* cr15 */
52         u32     ven_msg_data_0;         /* cr16 */
53         u32     ven_msg_data_1;         /* cr17 */
54         u32     ven_msi_0;              /* cr18 */
55         u32     ven_msi_1;              /* cr19 */
56         u32     mst_rmisc;              /* cr20 */
57 };
58
59 /* CR0 ID */
60 #define RX_LANE_FLIP_EN_ID                      0
61 #define TX_LANE_FLIP_EN_ID                      1
62 #define SYS_AUX_PWR_DET_ID                      2
63 #define APP_LTSSM_ENABLE_ID                     3
64 #define SYS_ATTEN_BUTTON_PRESSED_ID             4
65 #define SYS_MRL_SENSOR_STATE_ID                 5
66 #define SYS_PWR_FAULT_DET_ID                    6
67 #define SYS_MRL_SENSOR_CHGED_ID                 7
68 #define SYS_PRE_DET_CHGED_ID                    8
69 #define SYS_CMD_CPLED_INT_ID                    9
70 #define APP_INIT_RST_0_ID                       11
71 #define APP_REQ_ENTR_L1_ID                      12
72 #define APP_READY_ENTR_L23_ID                   13
73 #define APP_REQ_EXIT_L1_ID                      14
74 #define DEVICE_TYPE_EP                          (0 << 25)
75 #define DEVICE_TYPE_LEP                         (1 << 25)
76 #define DEVICE_TYPE_RC                          (4 << 25)
77 #define SYS_INT_ID                              29
78 #define MISCTRL_EN_ID                           30
79 #define REG_TRANSLATION_ENABLE                  31
80
81 /* CR1 ID */
82 #define APPS_PM_XMT_TURNOFF_ID                  2
83 #define APPS_PM_XMT_PME_ID                      5
84
85 /* CR3 ID */
86 #define XMLH_LTSSM_STATE_DETECT_QUIET           0x00
87 #define XMLH_LTSSM_STATE_DETECT_ACT             0x01
88 #define XMLH_LTSSM_STATE_POLL_ACTIVE            0x02
89 #define XMLH_LTSSM_STATE_POLL_COMPLIANCE        0x03
90 #define XMLH_LTSSM_STATE_POLL_CONFIG            0x04
91 #define XMLH_LTSSM_STATE_PRE_DETECT_QUIET       0x05
92 #define XMLH_LTSSM_STATE_DETECT_WAIT            0x06
93 #define XMLH_LTSSM_STATE_CFG_LINKWD_START       0x07
94 #define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT       0x08
95 #define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT       0x09
96 #define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT      0x0A
97 #define XMLH_LTSSM_STATE_CFG_COMPLETE           0x0B
98 #define XMLH_LTSSM_STATE_CFG_IDLE               0x0C
99 #define XMLH_LTSSM_STATE_RCVRY_LOCK             0x0D
100 #define XMLH_LTSSM_STATE_RCVRY_SPEED            0x0E
101 #define XMLH_LTSSM_STATE_RCVRY_RCVRCFG          0x0F
102 #define XMLH_LTSSM_STATE_RCVRY_IDLE             0x10
103 #define XMLH_LTSSM_STATE_L0                     0x11
104 #define XMLH_LTSSM_STATE_L0S                    0x12
105 #define XMLH_LTSSM_STATE_L123_SEND_EIDLE        0x13
106 #define XMLH_LTSSM_STATE_L1_IDLE                0x14
107 #define XMLH_LTSSM_STATE_L2_IDLE                0x15
108 #define XMLH_LTSSM_STATE_L2_WAKE                0x16
109 #define XMLH_LTSSM_STATE_DISABLED_ENTRY         0x17
110 #define XMLH_LTSSM_STATE_DISABLED_IDLE          0x18
111 #define XMLH_LTSSM_STATE_DISABLED               0x19
112 #define XMLH_LTSSM_STATE_LPBK_ENTRY             0x1A
113 #define XMLH_LTSSM_STATE_LPBK_ACTIVE            0x1B
114 #define XMLH_LTSSM_STATE_LPBK_EXIT              0x1C
115 #define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT      0x1D
116 #define XMLH_LTSSM_STATE_HOT_RESET_ENTRY        0x1E
117 #define XMLH_LTSSM_STATE_HOT_RESET              0x1F
118 #define XMLH_LTSSM_STATE_MASK                   0x3F
119 #define XMLH_LINK_UP                            (1 << 6)
120
121 /* CR4 ID */
122 #define CFG_MSI_EN_ID                           18
123
124 /* CR6 */
125 #define INTA_CTRL_INT                           (1 << 7)
126 #define INTB_CTRL_INT                           (1 << 8)
127 #define INTC_CTRL_INT                           (1 << 9)
128 #define INTD_CTRL_INT                           (1 << 10)
129 #define MSI_CTRL_INT                            (1 << 26)
130
131 /* CR19 ID */
132 #define VEN_MSI_REQ_ID                          11
133 #define VEN_MSI_FUN_NUM_ID                      8
134 #define VEN_MSI_TC_ID                           5
135 #define VEN_MSI_VECTOR_ID                       0
136 #define VEN_MSI_REQ_EN          ((u32)0x1 << VEN_MSI_REQ_ID)
137 #define VEN_MSI_FUN_NUM_MASK    ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
138 #define VEN_MSI_TC_MASK         ((u32)0x7 << VEN_MSI_TC_ID)
139 #define VEN_MSI_VECTOR_MASK     ((u32)0x1F << VEN_MSI_VECTOR_ID)
140
141 #define EXP_CAP_ID_OFFSET                       0x70
142
143 #define to_spear13xx_pcie(x)    container_of(x, struct spear13xx_pcie, pp)
144
145 static int spear13xx_pcie_establish_link(struct pcie_port *pp)
146 {
147         u32 val;
148         struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
149         struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
150         u32 exp_cap_off = EXP_CAP_ID_OFFSET;
151
152         if (dw_pcie_link_up(pp)) {
153                 dev_err(pp->dev, "link already up\n");
154                 return 0;
155         }
156
157         dw_pcie_setup_rc(pp);
158
159         /*
160          * this controller support only 128 bytes read size, however its
161          * default value in capability register is 512 bytes. So force
162          * it to 128 here.
163          */
164         dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
165         val &= ~PCI_EXP_DEVCTL_READRQ;
166         dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
167
168         dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
169         dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
170
171         /*
172          * if is_gen1 is set then handle it, so that some buggy card
173          * also works
174          */
175         if (spear13xx_pcie->is_gen1) {
176                 dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
177                                         4, &val);
178                 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
179                         val &= ~((u32)PCI_EXP_LNKCAP_SLS);
180                         val |= PCI_EXP_LNKCAP_SLS_2_5GB;
181                         dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
182                                 PCI_EXP_LNKCAP, 4, val);
183                 }
184
185                 dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
186                                         2, &val);
187                 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
188                         val &= ~((u32)PCI_EXP_LNKCAP_SLS);
189                         val |= PCI_EXP_LNKCAP_SLS_2_5GB;
190                         dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
191                                         PCI_EXP_LNKCTL2, 2, val);
192                 }
193         }
194
195         /* enable ltssm */
196         writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
197                         | (1 << APP_LTSSM_ENABLE_ID)
198                         | ((u32)1 << REG_TRANSLATION_ENABLE),
199                         &app_reg->app_ctrl_0);
200
201         return dw_pcie_wait_for_link(pp);
202 }
203
204 static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
205 {
206         struct pcie_port *pp = arg;
207         struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
208         struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
209         unsigned int status;
210
211         status = readl(&app_reg->int_sts);
212
213         if (status & MSI_CTRL_INT) {
214                 BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
215                 dw_handle_msi_irq(pp);
216         }
217
218         writel(status, &app_reg->int_clr);
219
220         return IRQ_HANDLED;
221 }
222
223 static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
224 {
225         struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
226         struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
227
228         /* Enable MSI interrupt */
229         if (IS_ENABLED(CONFIG_PCI_MSI)) {
230                 dw_pcie_msi_init(pp);
231                 writel(readl(&app_reg->int_mask) |
232                                 MSI_CTRL_INT, &app_reg->int_mask);
233         }
234 }
235
236 static int spear13xx_pcie_link_up(struct pcie_port *pp)
237 {
238         struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
239         struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
240
241         if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
242                 return 1;
243
244         return 0;
245 }
246
247 static void spear13xx_pcie_host_init(struct pcie_port *pp)
248 {
249         spear13xx_pcie_establish_link(pp);
250         spear13xx_pcie_enable_interrupts(pp);
251 }
252
253 static struct pcie_host_ops spear13xx_pcie_host_ops = {
254         .link_up = spear13xx_pcie_link_up,
255         .host_init = spear13xx_pcie_host_init,
256 };
257
258 static int spear13xx_add_pcie_port(struct pcie_port *pp,
259                                          struct platform_device *pdev)
260 {
261         struct device *dev = &pdev->dev;
262         int ret;
263
264         pp->irq = platform_get_irq(pdev, 0);
265         if (!pp->irq) {
266                 dev_err(dev, "failed to get irq\n");
267                 return -ENODEV;
268         }
269         ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
270                                IRQF_SHARED | IRQF_NO_THREAD,
271                                "spear1340-pcie", pp);
272         if (ret) {
273                 dev_err(dev, "failed to request irq %d\n", pp->irq);
274                 return ret;
275         }
276
277         pp->root_bus_nr = -1;
278         pp->ops = &spear13xx_pcie_host_ops;
279
280         ret = dw_pcie_host_init(pp);
281         if (ret) {
282                 dev_err(dev, "failed to initialize host\n");
283                 return ret;
284         }
285
286         return 0;
287 }
288
289 static int spear13xx_pcie_probe(struct platform_device *pdev)
290 {
291         struct spear13xx_pcie *spear13xx_pcie;
292         struct pcie_port *pp;
293         struct device *dev = &pdev->dev;
294         struct device_node *np = pdev->dev.of_node;
295         struct resource *dbi_base;
296         int ret;
297
298         spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
299         if (!spear13xx_pcie)
300                 return -ENOMEM;
301
302         spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
303         if (IS_ERR(spear13xx_pcie->phy)) {
304                 ret = PTR_ERR(spear13xx_pcie->phy);
305                 if (ret == -EPROBE_DEFER)
306                         dev_info(dev, "probe deferred\n");
307                 else
308                         dev_err(dev, "couldn't get pcie-phy\n");
309                 return ret;
310         }
311
312         phy_init(spear13xx_pcie->phy);
313
314         spear13xx_pcie->clk = devm_clk_get(dev, NULL);
315         if (IS_ERR(spear13xx_pcie->clk)) {
316                 dev_err(dev, "couldn't get clk for pcie\n");
317                 return PTR_ERR(spear13xx_pcie->clk);
318         }
319         ret = clk_prepare_enable(spear13xx_pcie->clk);
320         if (ret) {
321                 dev_err(dev, "couldn't enable clk for pcie\n");
322                 return ret;
323         }
324
325         pp = &spear13xx_pcie->pp;
326
327         pp->dev = dev;
328
329         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
330         pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
331         if (IS_ERR(pp->dbi_base)) {
332                 dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
333                 ret = PTR_ERR(pp->dbi_base);
334                 goto fail_clk;
335         }
336         spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
337
338         if (of_property_read_bool(np, "st,pcie-is-gen1"))
339                 spear13xx_pcie->is_gen1 = true;
340
341         ret = spear13xx_add_pcie_port(pp, pdev);
342         if (ret < 0)
343                 goto fail_clk;
344
345         platform_set_drvdata(pdev, spear13xx_pcie);
346         return 0;
347
348 fail_clk:
349         clk_disable_unprepare(spear13xx_pcie->clk);
350
351         return ret;
352 }
353
354 static const struct of_device_id spear13xx_pcie_of_match[] = {
355         { .compatible = "st,spear1340-pcie", },
356         {},
357 };
358
359 static struct platform_driver spear13xx_pcie_driver = {
360         .probe          = spear13xx_pcie_probe,
361         .driver = {
362                 .name   = "spear-pcie",
363                 .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
364         },
365 };
366
367 static int __init spear13xx_pcie_init(void)
368 {
369         return platform_driver_register(&spear13xx_pcie_driver);
370 }
371 device_initcall(spear13xx_pcie_init);