2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names);
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
37 EXPORT_SYMBOL(pci_pci_problems);
39 unsigned int pci_pm_d3_delay;
41 static void pci_pme_list_scan(struct work_struct *work);
43 static LIST_HEAD(pci_pme_list);
44 static DEFINE_MUTEX(pci_pme_list_mutex);
45 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47 struct pci_pme_device {
48 struct list_head list;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev *dev)
56 unsigned int delay = dev->d3_delay;
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported = 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
80 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
83 * The default CLS is used if arch didn't set CLS explicitly and not
84 * all pci devices agree on the same value. Arch can override either
85 * the dfl or actual value as it sees fit. Don't forget this is
86 * measured in 32-bit words, not bytes.
88 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
89 u8 pci_cache_line_size;
92 * If we set up a device for bus mastering, we need to check the latency
93 * timer as certain BIOSes forget to set it properly.
95 unsigned int pcibios_max_latency = 255;
97 /* If set, the PCIe ARI capability will not be used. */
98 static bool pcie_ari_disabled;
101 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
102 * @bus: pointer to PCI bus structure to search
104 * Given a PCI bus, returns the highest PCI bus number present in the set
105 * including the given PCI bus and its list of child PCI buses.
107 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
109 struct list_head *tmp;
110 unsigned char max, n;
112 max = bus->subordinate;
113 list_for_each(tmp, &bus->children) {
114 n = pci_bus_max_busnr(pci_bus_b(tmp));
120 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
122 #ifdef CONFIG_HAS_IOMEM
123 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
126 * Make sure the BAR is actually a memory resource, not an IO resource
128 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
132 return ioremap_nocache(pci_resource_start(pdev, bar),
133 pci_resource_len(pdev, bar));
135 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
140 * pci_max_busnr - returns maximum PCI bus number
142 * Returns the highest PCI bus number present in the system global list of
145 unsigned char __devinit
148 struct pci_bus *bus = NULL;
149 unsigned char max, n;
152 while ((bus = pci_find_next_bus(bus)) != NULL) {
153 n = pci_bus_max_busnr(bus);
162 #define PCI_FIND_CAP_TTL 48
164 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
165 u8 pos, int cap, int *ttl)
170 pci_bus_read_config_byte(bus, devfn, pos, &pos);
174 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
180 pos += PCI_CAP_LIST_NEXT;
185 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
188 int ttl = PCI_FIND_CAP_TTL;
190 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
193 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
195 return __pci_find_next_cap(dev->bus, dev->devfn,
196 pos + PCI_CAP_LIST_NEXT, cap);
198 EXPORT_SYMBOL_GPL(pci_find_next_capability);
200 static int __pci_bus_find_cap_start(struct pci_bus *bus,
201 unsigned int devfn, u8 hdr_type)
205 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
206 if (!(status & PCI_STATUS_CAP_LIST))
210 case PCI_HEADER_TYPE_NORMAL:
211 case PCI_HEADER_TYPE_BRIDGE:
212 return PCI_CAPABILITY_LIST;
213 case PCI_HEADER_TYPE_CARDBUS:
214 return PCI_CB_CAPABILITY_LIST;
223 * pci_find_capability - query for devices' capabilities
224 * @dev: PCI device to query
225 * @cap: capability code
227 * Tell if a device supports a given PCI capability.
228 * Returns the address of the requested capability structure within the
229 * device's PCI configuration space or 0 in case the device does not
230 * support it. Possible values for @cap:
232 * %PCI_CAP_ID_PM Power Management
233 * %PCI_CAP_ID_AGP Accelerated Graphics Port
234 * %PCI_CAP_ID_VPD Vital Product Data
235 * %PCI_CAP_ID_SLOTID Slot Identification
236 * %PCI_CAP_ID_MSI Message Signalled Interrupts
237 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
238 * %PCI_CAP_ID_PCIX PCI-X
239 * %PCI_CAP_ID_EXP PCI Express
241 int pci_find_capability(struct pci_dev *dev, int cap)
245 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
247 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
253 * pci_bus_find_capability - query for devices' capabilities
254 * @bus: the PCI bus to query
255 * @devfn: PCI device to query
256 * @cap: capability code
258 * Like pci_find_capability() but works for pci devices that do not have a
259 * pci_dev structure set up yet.
261 * Returns the address of the requested capability structure within the
262 * device's PCI configuration space or 0 in case the device does not
265 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
270 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
272 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
274 pos = __pci_find_next_cap(bus, devfn, pos, cap);
280 * pci_find_ext_capability - Find an extended capability
281 * @dev: PCI device to query
282 * @cap: capability code
284 * Returns the address of the requested extended capability structure
285 * within the device's PCI configuration space or 0 if the device does
286 * not support it. Possible values for @cap:
288 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
289 * %PCI_EXT_CAP_ID_VC Virtual Channel
290 * %PCI_EXT_CAP_ID_DSN Device Serial Number
291 * %PCI_EXT_CAP_ID_PWR Power Budgeting
293 int pci_find_ext_capability(struct pci_dev *dev, int cap)
297 int pos = PCI_CFG_SPACE_SIZE;
299 /* minimum 8 bytes per capability */
300 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
302 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
305 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
309 * If we have no capabilities, this is indicated by cap ID,
310 * cap version and next pointer all being 0.
316 if (PCI_EXT_CAP_ID(header) == cap)
319 pos = PCI_EXT_CAP_NEXT(header);
320 if (pos < PCI_CFG_SPACE_SIZE)
323 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
329 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
332 * pci_bus_find_ext_capability - find an extended capability
333 * @bus: the PCI bus to query
334 * @devfn: PCI device to query
335 * @cap: capability code
337 * Like pci_find_ext_capability() but works for pci devices that do not have a
338 * pci_dev structure set up yet.
340 * Returns the address of the requested capability structure within the
341 * device's PCI configuration space or 0 in case the device does not
344 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
349 int pos = PCI_CFG_SPACE_SIZE;
351 /* minimum 8 bytes per capability */
352 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
354 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
356 if (header == 0xffffffff || header == 0)
360 if (PCI_EXT_CAP_ID(header) == cap)
363 pos = PCI_EXT_CAP_NEXT(header);
364 if (pos < PCI_CFG_SPACE_SIZE)
367 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
374 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
376 int rc, ttl = PCI_FIND_CAP_TTL;
379 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
380 mask = HT_3BIT_CAP_MASK;
382 mask = HT_5BIT_CAP_MASK;
384 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
385 PCI_CAP_ID_HT, &ttl);
387 rc = pci_read_config_byte(dev, pos + 3, &cap);
388 if (rc != PCIBIOS_SUCCESSFUL)
391 if ((cap & mask) == ht_cap)
394 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
395 pos + PCI_CAP_LIST_NEXT,
396 PCI_CAP_ID_HT, &ttl);
402 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
403 * @dev: PCI device to query
404 * @pos: Position from which to continue searching
405 * @ht_cap: Hypertransport capability code
407 * To be used in conjunction with pci_find_ht_capability() to search for
408 * all capabilities matching @ht_cap. @pos should always be a value returned
409 * from pci_find_ht_capability().
411 * NB. To be 100% safe against broken PCI devices, the caller should take
412 * steps to avoid an infinite loop.
414 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
416 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
418 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
421 * pci_find_ht_capability - query a device's Hypertransport capabilities
422 * @dev: PCI device to query
423 * @ht_cap: Hypertransport capability code
425 * Tell if a device supports a given Hypertransport capability.
426 * Returns an address within the device's PCI configuration space
427 * or 0 in case the device does not support the request capability.
428 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
429 * which has a Hypertransport capability matching @ht_cap.
431 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
435 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
437 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
441 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
444 * pci_find_parent_resource - return resource region of parent bus of given region
445 * @dev: PCI device structure contains resources to be searched
446 * @res: child resource record for which parent is sought
448 * For given resource region of given device, return the resource
449 * region of parent bus the given region is contained in or where
450 * it should be allocated from.
453 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
455 const struct pci_bus *bus = dev->bus;
457 struct resource *best = NULL, *r;
459 pci_bus_for_each_resource(bus, r, i) {
462 if (res->start && !(res->start >= r->start && res->end <= r->end))
463 continue; /* Not contained */
464 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
465 continue; /* Wrong type */
466 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
467 return r; /* Exact match */
468 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
469 if (r->flags & IORESOURCE_PREFETCH)
471 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
479 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
480 * @dev: PCI device to have its BARs restored
482 * Restore the BAR values for a given device, so as to make it
483 * accessible by its driver.
486 pci_restore_bars(struct pci_dev *dev)
490 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
491 pci_update_resource(dev, i);
494 static struct pci_platform_pm_ops *pci_platform_pm;
496 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
498 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
499 || !ops->sleep_wake || !ops->can_wakeup)
501 pci_platform_pm = ops;
505 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
507 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
510 static inline int platform_pci_set_power_state(struct pci_dev *dev,
513 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
516 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
518 return pci_platform_pm ?
519 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
522 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
524 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
527 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
529 return pci_platform_pm ?
530 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
533 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
535 return pci_platform_pm ?
536 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
540 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
542 * @dev: PCI device to handle.
543 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
546 * -EINVAL if the requested state is invalid.
547 * -EIO if device does not support PCI PM or its PM capabilities register has a
548 * wrong version, or device doesn't support the requested state.
549 * 0 if device already is in the requested state.
550 * 0 if device's power state has been successfully changed.
552 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
555 bool need_restore = false;
557 /* Check if we're already there */
558 if (dev->current_state == state)
564 if (state < PCI_D0 || state > PCI_D3hot)
567 /* Validate current state:
568 * Can enter D0 from any state, but if we can only go deeper
569 * to sleep if we're already in a low power state
571 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
572 && dev->current_state > state) {
573 dev_err(&dev->dev, "invalid power transition "
574 "(from state %d to %d)\n", dev->current_state, state);
578 /* check if this device supports the desired state */
579 if ((state == PCI_D1 && !dev->d1_support)
580 || (state == PCI_D2 && !dev->d2_support))
583 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
585 /* If we're (effectively) in D3, force entire word to 0.
586 * This doesn't affect PME_Status, disables PME_En, and
587 * sets PowerState to 0.
589 switch (dev->current_state) {
593 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
598 case PCI_UNKNOWN: /* Boot-up */
599 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
600 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
602 /* Fall-through: force to D0 */
608 /* enter specified state */
609 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
611 /* Mandatory power management transition delays */
612 /* see PCI PM 1.1 5.6.1 table 18 */
613 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
614 pci_dev_d3_sleep(dev);
615 else if (state == PCI_D2 || dev->current_state == PCI_D2)
616 udelay(PCI_PM_D2_DELAY);
618 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
619 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
620 if (dev->current_state != state && printk_ratelimit())
621 dev_info(&dev->dev, "Refused to change power state, "
622 "currently in D%d\n", dev->current_state);
624 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
625 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
626 * from D3hot to D0 _may_ perform an internal reset, thereby
627 * going to "D0 Uninitialized" rather than "D0 Initialized".
628 * For example, at least some versions of the 3c905B and the
629 * 3c556B exhibit this behaviour.
631 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
632 * devices in a D3hot state at boot. Consequently, we need to
633 * restore at least the BARs so that the device will be
634 * accessible to its driver.
637 pci_restore_bars(dev);
640 pcie_aspm_pm_state_change(dev->bus->self);
646 * pci_update_current_state - Read PCI power state of given device from its
647 * PCI PM registers and cache it
648 * @dev: PCI device to handle.
649 * @state: State to cache in case the device doesn't have the PM capability
651 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
656 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
657 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
659 dev->current_state = state;
664 * pci_platform_power_transition - Use platform to change device power state
665 * @dev: PCI device to handle.
666 * @state: State to put the device into.
668 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
672 if (platform_pci_power_manageable(dev)) {
673 error = platform_pci_set_power_state(dev, state);
675 pci_update_current_state(dev, state);
676 /* Fall back to PCI_D0 if native PM is not supported */
678 dev->current_state = PCI_D0;
681 /* Fall back to PCI_D0 if native PM is not supported */
683 dev->current_state = PCI_D0;
690 * __pci_start_power_transition - Start power transition of a PCI device
691 * @dev: PCI device to handle.
692 * @state: State to put the device into.
694 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
697 pci_platform_power_transition(dev, PCI_D0);
701 * __pci_complete_power_transition - Complete power transition of a PCI device
702 * @dev: PCI device to handle.
703 * @state: State to put the device into.
705 * This function should not be called directly by device drivers.
707 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
709 return state >= PCI_D0 ?
710 pci_platform_power_transition(dev, state) : -EINVAL;
712 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
715 * pci_set_power_state - Set the power state of a PCI device
716 * @dev: PCI device to handle.
717 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
719 * Transition a device to a new power state, using the platform firmware and/or
720 * the device's PCI PM registers.
723 * -EINVAL if the requested state is invalid.
724 * -EIO if device does not support PCI PM or its PM capabilities register has a
725 * wrong version, or device doesn't support the requested state.
726 * 0 if device already is in the requested state.
727 * 0 if device's power state has been successfully changed.
729 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
733 /* bound the state we're entering */
734 if (state > PCI_D3hot)
736 else if (state < PCI_D0)
738 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
740 * If the device or the parent bridge do not support PCI PM,
741 * ignore the request if we're doing anything other than putting
742 * it into D0 (which would only happen on boot).
746 __pci_start_power_transition(dev, state);
748 /* This device is quirked not to be put into D3, so
749 don't put it in D3 */
750 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
753 error = pci_raw_set_power_state(dev, state);
755 if (!__pci_complete_power_transition(dev, state))
758 * When aspm_policy is "powersave" this call ensures
759 * that ASPM is configured.
761 if (!error && dev->bus->self)
762 pcie_aspm_powersave_config_link(dev->bus->self);
768 * pci_choose_state - Choose the power state of a PCI device
769 * @dev: PCI device to be suspended
770 * @state: target sleep state for the whole system. This is the value
771 * that is passed to suspend() function.
773 * Returns PCI power state suitable for given device and given system
777 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
781 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
784 ret = platform_pci_choose_state(dev);
785 if (ret != PCI_POWER_ERROR)
788 switch (state.event) {
791 case PM_EVENT_FREEZE:
792 case PM_EVENT_PRETHAW:
793 /* REVISIT both freeze and pre-thaw "should" use D0 */
794 case PM_EVENT_SUSPEND:
795 case PM_EVENT_HIBERNATE:
798 dev_info(&dev->dev, "unrecognized suspend event %d\n",
805 EXPORT_SYMBOL(pci_choose_state);
807 #define PCI_EXP_SAVE_REGS 7
809 #define pcie_cap_has_devctl(type, flags) 1
810 #define pcie_cap_has_lnkctl(type, flags) \
811 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
812 (type == PCI_EXP_TYPE_ROOT_PORT || \
813 type == PCI_EXP_TYPE_ENDPOINT || \
814 type == PCI_EXP_TYPE_LEG_END))
815 #define pcie_cap_has_sltctl(type, flags) \
816 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
817 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
818 (type == PCI_EXP_TYPE_DOWNSTREAM && \
819 (flags & PCI_EXP_FLAGS_SLOT))))
820 #define pcie_cap_has_rtctl(type, flags) \
821 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
822 (type == PCI_EXP_TYPE_ROOT_PORT || \
823 type == PCI_EXP_TYPE_RC_EC))
824 #define pcie_cap_has_devctl2(type, flags) \
825 ((flags & PCI_EXP_FLAGS_VERS) > 1)
826 #define pcie_cap_has_lnkctl2(type, flags) \
827 ((flags & PCI_EXP_FLAGS_VERS) > 1)
828 #define pcie_cap_has_sltctl2(type, flags) \
829 ((flags & PCI_EXP_FLAGS_VERS) > 1)
831 static struct pci_cap_saved_state *pci_find_saved_cap(
832 struct pci_dev *pci_dev, char cap)
834 struct pci_cap_saved_state *tmp;
835 struct hlist_node *pos;
837 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
838 if (tmp->cap.cap_nr == cap)
844 static int pci_save_pcie_state(struct pci_dev *dev)
847 struct pci_cap_saved_state *save_state;
851 pos = pci_pcie_cap(dev);
855 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
857 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
860 cap = (u16 *)&save_state->cap.data[0];
862 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
864 if (pcie_cap_has_devctl(dev->pcie_type, flags))
865 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
866 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
867 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
868 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
869 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
870 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
871 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
872 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
873 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
874 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
875 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
876 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
877 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
882 static void pci_restore_pcie_state(struct pci_dev *dev)
885 struct pci_cap_saved_state *save_state;
889 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
890 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
891 if (!save_state || pos <= 0)
893 cap = (u16 *)&save_state->cap.data[0];
895 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
897 if (pcie_cap_has_devctl(dev->pcie_type, flags))
898 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
899 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
900 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
901 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
902 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
903 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
904 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
905 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
906 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
907 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
908 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
909 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
910 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
914 static int pci_save_pcix_state(struct pci_dev *dev)
917 struct pci_cap_saved_state *save_state;
919 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
923 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
925 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
929 pci_read_config_word(dev, pos + PCI_X_CMD,
930 (u16 *)save_state->cap.data);
935 static void pci_restore_pcix_state(struct pci_dev *dev)
938 struct pci_cap_saved_state *save_state;
941 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
942 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
943 if (!save_state || pos <= 0)
945 cap = (u16 *)&save_state->cap.data[0];
947 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
952 * pci_save_state - save the PCI configuration space of a device before suspending
953 * @dev: - PCI device that we're dealing with
956 pci_save_state(struct pci_dev *dev)
959 /* XXX: 100% dword access ok here? */
960 for (i = 0; i < 16; i++)
961 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
962 dev->state_saved = true;
963 if ((i = pci_save_pcie_state(dev)) != 0)
965 if ((i = pci_save_pcix_state(dev)) != 0)
970 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
971 u32 saved_val, int retry)
975 pci_read_config_dword(pdev, offset, &val);
976 if (val == saved_val)
980 dev_dbg(&pdev->dev, "restoring config space at offset "
981 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
982 pci_write_config_dword(pdev, offset, saved_val);
986 pci_read_config_dword(pdev, offset, &val);
987 if (val == saved_val)
994 static void pci_restore_config_space(struct pci_dev *pdev, int start, int end,
999 for (index = end; index >= start; index--)
1000 pci_restore_config_dword(pdev, 4 * index,
1001 pdev->saved_config_space[index],
1006 * pci_restore_state - Restore the saved state of a PCI device
1007 * @dev: - PCI device that we're dealing with
1009 void pci_restore_state(struct pci_dev *dev)
1011 if (!dev->state_saved)
1014 /* PCI Express register must be restored first */
1015 pci_restore_pcie_state(dev);
1016 pci_restore_ats_state(dev);
1018 pci_restore_config_space(dev, 10, 15, 0);
1020 * The Base Address register should be programmed before the command
1023 pci_restore_config_space(dev, 4, 9, 10);
1024 pci_restore_config_space(dev, 0, 3, 0);
1026 pci_restore_pcix_state(dev);
1027 pci_restore_msi_state(dev);
1028 pci_restore_iov_state(dev);
1030 dev->state_saved = false;
1033 struct pci_saved_state {
1034 u32 config_space[16];
1035 struct pci_cap_saved_data cap[0];
1039 * pci_store_saved_state - Allocate and return an opaque struct containing
1040 * the device saved state.
1041 * @dev: PCI device that we're dealing with
1043 * Rerturn NULL if no state or error.
1045 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1047 struct pci_saved_state *state;
1048 struct pci_cap_saved_state *tmp;
1049 struct pci_cap_saved_data *cap;
1050 struct hlist_node *pos;
1053 if (!dev->state_saved)
1056 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1058 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1059 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1061 state = kzalloc(size, GFP_KERNEL);
1065 memcpy(state->config_space, dev->saved_config_space,
1066 sizeof(state->config_space));
1069 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1070 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1071 memcpy(cap, &tmp->cap, len);
1072 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1074 /* Empty cap_save terminates list */
1078 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1081 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1082 * @dev: PCI device that we're dealing with
1083 * @state: Saved state returned from pci_store_saved_state()
1085 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1087 struct pci_cap_saved_data *cap;
1089 dev->state_saved = false;
1094 memcpy(dev->saved_config_space, state->config_space,
1095 sizeof(state->config_space));
1099 struct pci_cap_saved_state *tmp;
1101 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1102 if (!tmp || tmp->cap.size != cap->size)
1105 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1106 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1107 sizeof(struct pci_cap_saved_data) + cap->size);
1110 dev->state_saved = true;
1113 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1116 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1117 * and free the memory allocated for it.
1118 * @dev: PCI device that we're dealing with
1119 * @state: Pointer to saved state returned from pci_store_saved_state()
1121 int pci_load_and_free_saved_state(struct pci_dev *dev,
1122 struct pci_saved_state **state)
1124 int ret = pci_load_saved_state(dev, *state);
1129 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1131 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1135 err = pci_set_power_state(dev, PCI_D0);
1136 if (err < 0 && err != -EIO)
1138 err = pcibios_enable_device(dev, bars);
1141 pci_fixup_device(pci_fixup_enable, dev);
1147 * pci_reenable_device - Resume abandoned device
1148 * @dev: PCI device to be resumed
1150 * Note this function is a backend of pci_default_resume and is not supposed
1151 * to be called by normal code, write proper resume handler and use it instead.
1153 int pci_reenable_device(struct pci_dev *dev)
1155 if (pci_is_enabled(dev))
1156 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1160 static int __pci_enable_device_flags(struct pci_dev *dev,
1161 resource_size_t flags)
1167 * Power state could be unknown at this point, either due to a fresh
1168 * boot or a device removal call. So get the current power state
1169 * so that things like MSI message writing will behave as expected
1170 * (e.g. if the device really is in D0 at enable time).
1174 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1175 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1178 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1179 return 0; /* already enabled */
1181 /* only skip sriov related */
1182 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1183 if (dev->resource[i].flags & flags)
1185 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1186 if (dev->resource[i].flags & flags)
1189 err = do_pci_enable_device(dev, bars);
1191 atomic_dec(&dev->enable_cnt);
1196 * pci_enable_device_io - Initialize a device for use with IO space
1197 * @dev: PCI device to be initialized
1199 * Initialize device before it's used by a driver. Ask low-level code
1200 * to enable I/O resources. Wake up the device if it was suspended.
1201 * Beware, this function can fail.
1203 int pci_enable_device_io(struct pci_dev *dev)
1205 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1209 * pci_enable_device_mem - Initialize a device for use with Memory space
1210 * @dev: PCI device to be initialized
1212 * Initialize device before it's used by a driver. Ask low-level code
1213 * to enable Memory resources. Wake up the device if it was suspended.
1214 * Beware, this function can fail.
1216 int pci_enable_device_mem(struct pci_dev *dev)
1218 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1222 * pci_enable_device - Initialize device before it's used by a driver.
1223 * @dev: PCI device to be initialized
1225 * Initialize device before it's used by a driver. Ask low-level code
1226 * to enable I/O and memory. Wake up the device if it was suspended.
1227 * Beware, this function can fail.
1229 * Note we don't actually enable the device many times if we call
1230 * this function repeatedly (we just increment the count).
1232 int pci_enable_device(struct pci_dev *dev)
1234 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1238 * Managed PCI resources. This manages device on/off, intx/msi/msix
1239 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1240 * there's no need to track it separately. pci_devres is initialized
1241 * when a device is enabled using managed PCI device enable interface.
1244 unsigned int enabled:1;
1245 unsigned int pinned:1;
1246 unsigned int orig_intx:1;
1247 unsigned int restore_intx:1;
1251 static void pcim_release(struct device *gendev, void *res)
1253 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1254 struct pci_devres *this = res;
1257 if (dev->msi_enabled)
1258 pci_disable_msi(dev);
1259 if (dev->msix_enabled)
1260 pci_disable_msix(dev);
1262 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1263 if (this->region_mask & (1 << i))
1264 pci_release_region(dev, i);
1266 if (this->restore_intx)
1267 pci_intx(dev, this->orig_intx);
1269 if (this->enabled && !this->pinned)
1270 pci_disable_device(dev);
1273 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1275 struct pci_devres *dr, *new_dr;
1277 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1281 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1284 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1287 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1289 if (pci_is_managed(pdev))
1290 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1295 * pcim_enable_device - Managed pci_enable_device()
1296 * @pdev: PCI device to be initialized
1298 * Managed pci_enable_device().
1300 int pcim_enable_device(struct pci_dev *pdev)
1302 struct pci_devres *dr;
1305 dr = get_pci_dr(pdev);
1311 rc = pci_enable_device(pdev);
1313 pdev->is_managed = 1;
1320 * pcim_pin_device - Pin managed PCI device
1321 * @pdev: PCI device to pin
1323 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1324 * driver detach. @pdev must have been enabled with
1325 * pcim_enable_device().
1327 void pcim_pin_device(struct pci_dev *pdev)
1329 struct pci_devres *dr;
1331 dr = find_pci_dr(pdev);
1332 WARN_ON(!dr || !dr->enabled);
1338 * pcibios_disable_device - disable arch specific PCI resources for device dev
1339 * @dev: the PCI device to disable
1341 * Disables architecture specific PCI resources for the device. This
1342 * is the default implementation. Architecture implementations can
1345 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1347 static void do_pci_disable_device(struct pci_dev *dev)
1351 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1352 if (pci_command & PCI_COMMAND_MASTER) {
1353 pci_command &= ~PCI_COMMAND_MASTER;
1354 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1357 pcibios_disable_device(dev);
1361 * pci_disable_enabled_device - Disable device without updating enable_cnt
1362 * @dev: PCI device to disable
1364 * NOTE: This function is a backend of PCI power management routines and is
1365 * not supposed to be called drivers.
1367 void pci_disable_enabled_device(struct pci_dev *dev)
1369 if (pci_is_enabled(dev))
1370 do_pci_disable_device(dev);
1374 * pci_disable_device - Disable PCI device after use
1375 * @dev: PCI device to be disabled
1377 * Signal to the system that the PCI device is not in use by the system
1378 * anymore. This only involves disabling PCI bus-mastering, if active.
1380 * Note we don't actually disable the device until all callers of
1381 * pci_enable_device() have called pci_disable_device().
1384 pci_disable_device(struct pci_dev *dev)
1386 struct pci_devres *dr;
1388 dr = find_pci_dr(dev);
1392 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1395 do_pci_disable_device(dev);
1397 dev->is_busmaster = 0;
1401 * pcibios_set_pcie_reset_state - set reset state for device dev
1402 * @dev: the PCIe device reset
1403 * @state: Reset state to enter into
1406 * Sets the PCIe reset state for the device. This is the default
1407 * implementation. Architecture implementations can override this.
1409 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1410 enum pcie_reset_state state)
1416 * pci_set_pcie_reset_state - set reset state for device dev
1417 * @dev: the PCIe device reset
1418 * @state: Reset state to enter into
1421 * Sets the PCI reset state for the device.
1423 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1425 return pcibios_set_pcie_reset_state(dev, state);
1429 * pci_check_pme_status - Check if given device has generated PME.
1430 * @dev: Device to check.
1432 * Check the PME status of the device and if set, clear it and clear PME enable
1433 * (if set). Return 'true' if PME status and PME enable were both set or
1434 * 'false' otherwise.
1436 bool pci_check_pme_status(struct pci_dev *dev)
1445 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1446 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1447 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1450 /* Clear PME status. */
1451 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1452 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1453 /* Disable PME to avoid interrupt flood. */
1454 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1458 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1464 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1465 * @dev: Device to handle.
1466 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1468 * Check if @dev has generated PME and queue a resume request for it in that
1471 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1473 if (pme_poll_reset && dev->pme_poll)
1474 dev->pme_poll = false;
1476 if (pci_check_pme_status(dev)) {
1477 pci_wakeup_event(dev);
1478 pm_request_resume(&dev->dev);
1484 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1485 * @bus: Top bus of the subtree to walk.
1487 void pci_pme_wakeup_bus(struct pci_bus *bus)
1490 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1494 * pci_pme_capable - check the capability of PCI device to generate PME#
1495 * @dev: PCI device to handle.
1496 * @state: PCI state from which device will issue PME#.
1498 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1503 return !!(dev->pme_support & (1 << state));
1506 static void pci_pme_list_scan(struct work_struct *work)
1508 struct pci_pme_device *pme_dev, *n;
1510 mutex_lock(&pci_pme_list_mutex);
1511 if (!list_empty(&pci_pme_list)) {
1512 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1513 if (pme_dev->dev->pme_poll) {
1514 pci_pme_wakeup(pme_dev->dev, NULL);
1516 list_del(&pme_dev->list);
1520 if (!list_empty(&pci_pme_list))
1521 schedule_delayed_work(&pci_pme_work,
1522 msecs_to_jiffies(PME_TIMEOUT));
1524 mutex_unlock(&pci_pme_list_mutex);
1528 * pci_pme_active - enable or disable PCI device's PME# function
1529 * @dev: PCI device to handle.
1530 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1532 * The caller must verify that the device is capable of generating PME# before
1533 * calling this function with @enable equal to 'true'.
1535 void pci_pme_active(struct pci_dev *dev, bool enable)
1542 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1543 /* Clear PME_Status by writing 1 to it and enable PME# */
1544 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1546 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1548 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1550 /* PCI (as opposed to PCIe) PME requires that the device have
1551 its PME# line hooked up correctly. Not all hardware vendors
1552 do this, so the PME never gets delivered and the device
1553 remains asleep. The easiest way around this is to
1554 periodically walk the list of suspended devices and check
1555 whether any have their PME flag set. The assumption is that
1556 we'll wake up often enough anyway that this won't be a huge
1557 hit, and the power savings from the devices will still be a
1560 if (dev->pme_poll) {
1561 struct pci_pme_device *pme_dev;
1563 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1568 mutex_lock(&pci_pme_list_mutex);
1569 list_add(&pme_dev->list, &pci_pme_list);
1570 if (list_is_singular(&pci_pme_list))
1571 schedule_delayed_work(&pci_pme_work,
1572 msecs_to_jiffies(PME_TIMEOUT));
1573 mutex_unlock(&pci_pme_list_mutex);
1575 mutex_lock(&pci_pme_list_mutex);
1576 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1577 if (pme_dev->dev == dev) {
1578 list_del(&pme_dev->list);
1583 mutex_unlock(&pci_pme_list_mutex);
1588 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1592 * __pci_enable_wake - enable PCI device as wakeup event source
1593 * @dev: PCI device affected
1594 * @state: PCI state from which device will issue wakeup events
1595 * @runtime: True if the events are to be generated at run time
1596 * @enable: True to enable event generation; false to disable
1598 * This enables the device as a wakeup event source, or disables it.
1599 * When such events involves platform-specific hooks, those hooks are
1600 * called automatically by this routine.
1602 * Devices with legacy power management (no standard PCI PM capabilities)
1603 * always require such platform hooks.
1606 * 0 is returned on success
1607 * -EINVAL is returned if device is not supposed to wake up the system
1608 * Error code depending on the platform is returned if both the platform and
1609 * the native mechanism fail to enable the generation of wake-up events
1611 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1612 bool runtime, bool enable)
1616 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1619 /* Don't do the same thing twice in a row for one device. */
1620 if (!!enable == !!dev->wakeup_prepared)
1624 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1625 * Anderson we should be doing PME# wake enable followed by ACPI wake
1626 * enable. To disable wake-up we call the platform first, for symmetry.
1632 if (pci_pme_capable(dev, state))
1633 pci_pme_active(dev, true);
1636 error = runtime ? platform_pci_run_wake(dev, true) :
1637 platform_pci_sleep_wake(dev, true);
1641 dev->wakeup_prepared = true;
1644 platform_pci_run_wake(dev, false);
1646 platform_pci_sleep_wake(dev, false);
1647 pci_pme_active(dev, false);
1648 dev->wakeup_prepared = false;
1653 EXPORT_SYMBOL(__pci_enable_wake);
1656 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1657 * @dev: PCI device to prepare
1658 * @enable: True to enable wake-up event generation; false to disable
1660 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1661 * and this function allows them to set that up cleanly - pci_enable_wake()
1662 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1663 * ordering constraints.
1665 * This function only returns error code if the device is not capable of
1666 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1667 * enable wake-up power for it.
1669 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1671 return pci_pme_capable(dev, PCI_D3cold) ?
1672 pci_enable_wake(dev, PCI_D3cold, enable) :
1673 pci_enable_wake(dev, PCI_D3hot, enable);
1677 * pci_target_state - find an appropriate low power state for a given PCI dev
1680 * Use underlying platform code to find a supported low power state for @dev.
1681 * If the platform can't manage @dev, return the deepest state from which it
1682 * can generate wake events, based on any available PME info.
1684 pci_power_t pci_target_state(struct pci_dev *dev)
1686 pci_power_t target_state = PCI_D3hot;
1688 if (platform_pci_power_manageable(dev)) {
1690 * Call the platform to choose the target state of the device
1691 * and enable wake-up from this state if supported.
1693 pci_power_t state = platform_pci_choose_state(dev);
1696 case PCI_POWER_ERROR:
1701 if (pci_no_d1d2(dev))
1704 target_state = state;
1706 } else if (!dev->pm_cap) {
1707 target_state = PCI_D0;
1708 } else if (device_may_wakeup(&dev->dev)) {
1710 * Find the deepest state from which the device can generate
1711 * wake-up events, make it the target state and enable device
1714 if (dev->pme_support) {
1716 && !(dev->pme_support & (1 << target_state)))
1721 return target_state;
1725 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1726 * @dev: Device to handle.
1728 * Choose the power state appropriate for the device depending on whether
1729 * it can wake up the system and/or is power manageable by the platform
1730 * (PCI_D3hot is the default) and put the device into that state.
1732 int pci_prepare_to_sleep(struct pci_dev *dev)
1734 pci_power_t target_state = pci_target_state(dev);
1737 if (target_state == PCI_POWER_ERROR)
1740 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1742 error = pci_set_power_state(dev, target_state);
1745 pci_enable_wake(dev, target_state, false);
1751 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1752 * @dev: Device to handle.
1754 * Disable device's system wake-up capability and put it into D0.
1756 int pci_back_from_sleep(struct pci_dev *dev)
1758 pci_enable_wake(dev, PCI_D0, false);
1759 return pci_set_power_state(dev, PCI_D0);
1763 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1764 * @dev: PCI device being suspended.
1766 * Prepare @dev to generate wake-up events at run time and put it into a low
1769 int pci_finish_runtime_suspend(struct pci_dev *dev)
1771 pci_power_t target_state = pci_target_state(dev);
1774 if (target_state == PCI_POWER_ERROR)
1777 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1779 error = pci_set_power_state(dev, target_state);
1782 __pci_enable_wake(dev, target_state, true, false);
1788 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1789 * @dev: Device to check.
1791 * Return true if the device itself is cabable of generating wake-up events
1792 * (through the platform or using the native PCIe PME) or if the device supports
1793 * PME and one of its upstream bridges can generate wake-up events.
1795 bool pci_dev_run_wake(struct pci_dev *dev)
1797 struct pci_bus *bus = dev->bus;
1799 if (device_run_wake(&dev->dev))
1802 if (!dev->pme_support)
1805 while (bus->parent) {
1806 struct pci_dev *bridge = bus->self;
1808 if (device_run_wake(&bridge->dev))
1814 /* We have reached the root bus. */
1816 return device_run_wake(bus->bridge);
1820 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1823 * pci_pm_init - Initialize PM functions of given PCI device
1824 * @dev: PCI device to handle.
1826 void pci_pm_init(struct pci_dev *dev)
1831 pm_runtime_forbid(&dev->dev);
1832 device_enable_async_suspend(&dev->dev);
1833 dev->wakeup_prepared = false;
1837 /* find PCI PM capability in list */
1838 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1841 /* Check device's ability to generate PME# */
1842 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1844 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1845 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1846 pmc & PCI_PM_CAP_VER_MASK);
1851 dev->d3_delay = PCI_PM_D3_WAIT;
1853 dev->d1_support = false;
1854 dev->d2_support = false;
1855 if (!pci_no_d1d2(dev)) {
1856 if (pmc & PCI_PM_CAP_D1)
1857 dev->d1_support = true;
1858 if (pmc & PCI_PM_CAP_D2)
1859 dev->d2_support = true;
1861 if (dev->d1_support || dev->d2_support)
1862 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1863 dev->d1_support ? " D1" : "",
1864 dev->d2_support ? " D2" : "");
1867 pmc &= PCI_PM_CAP_PME_MASK;
1869 dev_printk(KERN_DEBUG, &dev->dev,
1870 "PME# supported from%s%s%s%s%s\n",
1871 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1872 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1873 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1874 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1875 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1876 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1877 dev->pme_poll = true;
1879 * Make device's PM flags reflect the wake-up capability, but
1880 * let the user space enable it to wake up the system as needed.
1882 device_set_wakeup_capable(&dev->dev, true);
1883 /* Disable the PME# generation functionality */
1884 pci_pme_active(dev, false);
1886 dev->pme_support = 0;
1891 * platform_pci_wakeup_init - init platform wakeup if present
1894 * Some devices don't have PCI PM caps but can still generate wakeup
1895 * events through platform methods (like ACPI events). If @dev supports
1896 * platform wakeup events, set the device flag to indicate as much. This
1897 * may be redundant if the device also supports PCI PM caps, but double
1898 * initialization should be safe in that case.
1900 void platform_pci_wakeup_init(struct pci_dev *dev)
1902 if (!platform_pci_can_wakeup(dev))
1905 device_set_wakeup_capable(&dev->dev, true);
1906 platform_pci_sleep_wake(dev, false);
1909 static void pci_add_saved_cap(struct pci_dev *pci_dev,
1910 struct pci_cap_saved_state *new_cap)
1912 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
1916 * pci_add_save_buffer - allocate buffer for saving given capability registers
1917 * @dev: the PCI device
1918 * @cap: the capability to allocate the buffer for
1919 * @size: requested size of the buffer
1921 static int pci_add_cap_save_buffer(
1922 struct pci_dev *dev, char cap, unsigned int size)
1925 struct pci_cap_saved_state *save_state;
1927 pos = pci_find_capability(dev, cap);
1931 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1935 save_state->cap.cap_nr = cap;
1936 save_state->cap.size = size;
1937 pci_add_saved_cap(dev, save_state);
1943 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1944 * @dev: the PCI device
1946 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1950 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1951 PCI_EXP_SAVE_REGS * sizeof(u16));
1954 "unable to preallocate PCI Express save buffer\n");
1956 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1959 "unable to preallocate PCI-X save buffer\n");
1962 void pci_free_cap_save_buffers(struct pci_dev *dev)
1964 struct pci_cap_saved_state *tmp;
1965 struct hlist_node *pos, *n;
1967 hlist_for_each_entry_safe(tmp, pos, n, &dev->saved_cap_space, next)
1972 * pci_enable_ari - enable ARI forwarding if hardware support it
1973 * @dev: the PCI device
1975 void pci_enable_ari(struct pci_dev *dev)
1980 struct pci_dev *bridge;
1982 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
1985 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1989 bridge = dev->bus->self;
1990 if (!bridge || !pci_is_pcie(bridge))
1993 pos = pci_pcie_cap(bridge);
1997 /* ARI is a PCIe v2 feature */
1998 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
1999 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
2002 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
2003 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2006 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
2007 ctrl |= PCI_EXP_DEVCTL2_ARI;
2008 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
2010 bridge->ari_enabled = 1;
2014 * pci_enable_ido - enable ID-based ordering on a device
2015 * @dev: the PCI device
2016 * @type: which types of IDO to enable
2018 * Enable ID-based ordering on @dev. @type can contain the bits
2019 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2020 * which types of transactions are allowed to be re-ordered.
2022 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2027 pos = pci_pcie_cap(dev);
2031 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2032 if (type & PCI_EXP_IDO_REQUEST)
2033 ctrl |= PCI_EXP_IDO_REQ_EN;
2034 if (type & PCI_EXP_IDO_COMPLETION)
2035 ctrl |= PCI_EXP_IDO_CMP_EN;
2036 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2038 EXPORT_SYMBOL(pci_enable_ido);
2041 * pci_disable_ido - disable ID-based ordering on a device
2042 * @dev: the PCI device
2043 * @type: which types of IDO to disable
2045 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2050 if (!pci_is_pcie(dev))
2053 pos = pci_pcie_cap(dev);
2057 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2058 if (type & PCI_EXP_IDO_REQUEST)
2059 ctrl &= ~PCI_EXP_IDO_REQ_EN;
2060 if (type & PCI_EXP_IDO_COMPLETION)
2061 ctrl &= ~PCI_EXP_IDO_CMP_EN;
2062 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2064 EXPORT_SYMBOL(pci_disable_ido);
2067 * pci_enable_obff - enable optimized buffer flush/fill
2069 * @type: type of signaling to use
2071 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2072 * signaling if possible, falling back to message signaling only if
2073 * WAKE# isn't supported. @type should indicate whether the PCIe link
2074 * be brought out of L0s or L1 to send the message. It should be either
2075 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2077 * If your device can benefit from receiving all messages, even at the
2078 * power cost of bringing the link back up from a low power state, use
2079 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2083 * Zero on success, appropriate error number on failure.
2085 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2092 if (!pci_is_pcie(dev))
2095 pos = pci_pcie_cap(dev);
2099 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2100 if (!(cap & PCI_EXP_OBFF_MASK))
2101 return -ENOTSUPP; /* no OBFF support at all */
2103 /* Make sure the topology supports OBFF as well */
2105 ret = pci_enable_obff(dev->bus->self, type);
2110 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2111 if (cap & PCI_EXP_OBFF_WAKE)
2112 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2115 case PCI_EXP_OBFF_SIGNAL_L0:
2116 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2117 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2119 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2120 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2121 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2124 WARN(1, "bad OBFF signal type\n");
2128 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2132 EXPORT_SYMBOL(pci_enable_obff);
2135 * pci_disable_obff - disable optimized buffer flush/fill
2138 * Disable OBFF on @dev.
2140 void pci_disable_obff(struct pci_dev *dev)
2145 if (!pci_is_pcie(dev))
2148 pos = pci_pcie_cap(dev);
2152 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2153 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2154 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2156 EXPORT_SYMBOL(pci_disable_obff);
2159 * pci_ltr_supported - check whether a device supports LTR
2163 * True if @dev supports latency tolerance reporting, false otherwise.
2165 bool pci_ltr_supported(struct pci_dev *dev)
2170 if (!pci_is_pcie(dev))
2173 pos = pci_pcie_cap(dev);
2177 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2179 return cap & PCI_EXP_DEVCAP2_LTR;
2181 EXPORT_SYMBOL(pci_ltr_supported);
2184 * pci_enable_ltr - enable latency tolerance reporting
2187 * Enable LTR on @dev if possible, which means enabling it first on
2191 * Zero on success, errno on failure.
2193 int pci_enable_ltr(struct pci_dev *dev)
2199 if (!pci_ltr_supported(dev))
2202 pos = pci_pcie_cap(dev);
2206 /* Only primary function can enable/disable LTR */
2207 if (PCI_FUNC(dev->devfn) != 0)
2210 /* Enable upstream ports first */
2212 ret = pci_enable_ltr(dev->bus->self);
2217 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2218 ctrl |= PCI_EXP_LTR_EN;
2219 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2223 EXPORT_SYMBOL(pci_enable_ltr);
2226 * pci_disable_ltr - disable latency tolerance reporting
2229 void pci_disable_ltr(struct pci_dev *dev)
2234 if (!pci_ltr_supported(dev))
2237 pos = pci_pcie_cap(dev);
2241 /* Only primary function can enable/disable LTR */
2242 if (PCI_FUNC(dev->devfn) != 0)
2245 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2246 ctrl &= ~PCI_EXP_LTR_EN;
2247 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2249 EXPORT_SYMBOL(pci_disable_ltr);
2251 static int __pci_ltr_scale(int *val)
2255 while (*val > 1023) {
2256 *val = (*val + 31) / 32;
2263 * pci_set_ltr - set LTR latency values
2265 * @snoop_lat_ns: snoop latency in nanoseconds
2266 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2268 * Figure out the scale and set the LTR values accordingly.
2270 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2272 int pos, ret, snoop_scale, nosnoop_scale;
2275 if (!pci_ltr_supported(dev))
2278 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2279 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2281 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2282 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2285 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2286 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2289 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2293 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2294 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2298 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2299 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2305 EXPORT_SYMBOL(pci_set_ltr);
2307 static int pci_acs_enable;
2310 * pci_request_acs - ask for ACS to be enabled if supported
2312 void pci_request_acs(void)
2318 * pci_enable_acs - enable ACS if hardware support it
2319 * @dev: the PCI device
2321 void pci_enable_acs(struct pci_dev *dev)
2327 if (!pci_acs_enable)
2330 if (!pci_is_pcie(dev))
2333 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2337 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2338 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2340 /* Source Validation */
2341 ctrl |= (cap & PCI_ACS_SV);
2343 /* P2P Request Redirect */
2344 ctrl |= (cap & PCI_ACS_RR);
2346 /* P2P Completion Redirect */
2347 ctrl |= (cap & PCI_ACS_CR);
2349 /* Upstream Forwarding */
2350 ctrl |= (cap & PCI_ACS_UF);
2352 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2356 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2357 * @dev: the PCI device
2358 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2360 * Perform INTx swizzling for a device behind one level of bridge. This is
2361 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2362 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2363 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2364 * the PCI Express Base Specification, Revision 2.1)
2366 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2370 if (pci_ari_enabled(dev->bus))
2373 slot = PCI_SLOT(dev->devfn);
2375 return (((pin - 1) + slot) % 4) + 1;
2379 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2387 while (!pci_is_root_bus(dev->bus)) {
2388 pin = pci_swizzle_interrupt_pin(dev, pin);
2389 dev = dev->bus->self;
2396 * pci_common_swizzle - swizzle INTx all the way to root bridge
2397 * @dev: the PCI device
2398 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2400 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2401 * bridges all the way up to a PCI root bus.
2403 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2407 while (!pci_is_root_bus(dev->bus)) {
2408 pin = pci_swizzle_interrupt_pin(dev, pin);
2409 dev = dev->bus->self;
2412 return PCI_SLOT(dev->devfn);
2416 * pci_release_region - Release a PCI bar
2417 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2418 * @bar: BAR to release
2420 * Releases the PCI I/O and memory resources previously reserved by a
2421 * successful call to pci_request_region. Call this function only
2422 * after all use of the PCI regions has ceased.
2424 void pci_release_region(struct pci_dev *pdev, int bar)
2426 struct pci_devres *dr;
2428 if (pci_resource_len(pdev, bar) == 0)
2430 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2431 release_region(pci_resource_start(pdev, bar),
2432 pci_resource_len(pdev, bar));
2433 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2434 release_mem_region(pci_resource_start(pdev, bar),
2435 pci_resource_len(pdev, bar));
2437 dr = find_pci_dr(pdev);
2439 dr->region_mask &= ~(1 << bar);
2443 * __pci_request_region - Reserved PCI I/O and memory resource
2444 * @pdev: PCI device whose resources are to be reserved
2445 * @bar: BAR to be reserved
2446 * @res_name: Name to be associated with resource.
2447 * @exclusive: whether the region access is exclusive or not
2449 * Mark the PCI region associated with PCI device @pdev BR @bar as
2450 * being reserved by owner @res_name. Do not access any
2451 * address inside the PCI regions unless this call returns
2454 * If @exclusive is set, then the region is marked so that userspace
2455 * is explicitly not allowed to map the resource via /dev/mem or
2456 * sysfs MMIO access.
2458 * Returns 0 on success, or %EBUSY on error. A warning
2459 * message is also printed on failure.
2461 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2464 struct pci_devres *dr;
2466 if (pci_resource_len(pdev, bar) == 0)
2469 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2470 if (!request_region(pci_resource_start(pdev, bar),
2471 pci_resource_len(pdev, bar), res_name))
2474 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2475 if (!__request_mem_region(pci_resource_start(pdev, bar),
2476 pci_resource_len(pdev, bar), res_name,
2481 dr = find_pci_dr(pdev);
2483 dr->region_mask |= 1 << bar;
2488 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2489 &pdev->resource[bar]);
2494 * pci_request_region - Reserve PCI I/O and memory resource
2495 * @pdev: PCI device whose resources are to be reserved
2496 * @bar: BAR to be reserved
2497 * @res_name: Name to be associated with resource
2499 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2500 * being reserved by owner @res_name. Do not access any
2501 * address inside the PCI regions unless this call returns
2504 * Returns 0 on success, or %EBUSY on error. A warning
2505 * message is also printed on failure.
2507 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2509 return __pci_request_region(pdev, bar, res_name, 0);
2513 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2514 * @pdev: PCI device whose resources are to be reserved
2515 * @bar: BAR to be reserved
2516 * @res_name: Name to be associated with resource.
2518 * Mark the PCI region associated with PCI device @pdev BR @bar as
2519 * being reserved by owner @res_name. Do not access any
2520 * address inside the PCI regions unless this call returns
2523 * Returns 0 on success, or %EBUSY on error. A warning
2524 * message is also printed on failure.
2526 * The key difference that _exclusive makes it that userspace is
2527 * explicitly not allowed to map the resource via /dev/mem or
2530 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2532 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2535 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2536 * @pdev: PCI device whose resources were previously reserved
2537 * @bars: Bitmask of BARs to be released
2539 * Release selected PCI I/O and memory resources previously reserved.
2540 * Call this function only after all use of the PCI regions has ceased.
2542 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2546 for (i = 0; i < 6; i++)
2547 if (bars & (1 << i))
2548 pci_release_region(pdev, i);
2551 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2552 const char *res_name, int excl)
2556 for (i = 0; i < 6; i++)
2557 if (bars & (1 << i))
2558 if (__pci_request_region(pdev, i, res_name, excl))
2564 if (bars & (1 << i))
2565 pci_release_region(pdev, i);
2572 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2573 * @pdev: PCI device whose resources are to be reserved
2574 * @bars: Bitmask of BARs to be requested
2575 * @res_name: Name to be associated with resource
2577 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2578 const char *res_name)
2580 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2583 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2584 int bars, const char *res_name)
2586 return __pci_request_selected_regions(pdev, bars, res_name,
2587 IORESOURCE_EXCLUSIVE);
2591 * pci_release_regions - Release reserved PCI I/O and memory resources
2592 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2594 * Releases all PCI I/O and memory resources previously reserved by a
2595 * successful call to pci_request_regions. Call this function only
2596 * after all use of the PCI regions has ceased.
2599 void pci_release_regions(struct pci_dev *pdev)
2601 pci_release_selected_regions(pdev, (1 << 6) - 1);
2605 * pci_request_regions - Reserved PCI I/O and memory resources
2606 * @pdev: PCI device whose resources are to be reserved
2607 * @res_name: Name to be associated with resource.
2609 * Mark all PCI regions associated with PCI device @pdev as
2610 * being reserved by owner @res_name. Do not access any
2611 * address inside the PCI regions unless this call returns
2614 * Returns 0 on success, or %EBUSY on error. A warning
2615 * message is also printed on failure.
2617 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2619 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2623 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2624 * @pdev: PCI device whose resources are to be reserved
2625 * @res_name: Name to be associated with resource.
2627 * Mark all PCI regions associated with PCI device @pdev as
2628 * being reserved by owner @res_name. Do not access any
2629 * address inside the PCI regions unless this call returns
2632 * pci_request_regions_exclusive() will mark the region so that
2633 * /dev/mem and the sysfs MMIO access will not be allowed.
2635 * Returns 0 on success, or %EBUSY on error. A warning
2636 * message is also printed on failure.
2638 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2640 return pci_request_selected_regions_exclusive(pdev,
2641 ((1 << 6) - 1), res_name);
2644 static void __pci_set_master(struct pci_dev *dev, bool enable)
2648 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2650 cmd = old_cmd | PCI_COMMAND_MASTER;
2652 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2653 if (cmd != old_cmd) {
2654 dev_dbg(&dev->dev, "%s bus mastering\n",
2655 enable ? "enabling" : "disabling");
2656 pci_write_config_word(dev, PCI_COMMAND, cmd);
2658 dev->is_busmaster = enable;
2662 * pcibios_set_master - enable PCI bus-mastering for device dev
2663 * @dev: the PCI device to enable
2665 * Enables PCI bus-mastering for the device. This is the default
2666 * implementation. Architecture specific implementations can override
2667 * this if necessary.
2669 void __weak pcibios_set_master(struct pci_dev *dev)
2673 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2674 if (pci_is_pcie(dev))
2677 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2679 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2680 else if (lat > pcibios_max_latency)
2681 lat = pcibios_max_latency;
2684 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2685 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2689 * pci_set_master - enables bus-mastering for device dev
2690 * @dev: the PCI device to enable
2692 * Enables bus-mastering on the device and calls pcibios_set_master()
2693 * to do the needed arch specific settings.
2695 void pci_set_master(struct pci_dev *dev)
2697 __pci_set_master(dev, true);
2698 pcibios_set_master(dev);
2702 * pci_clear_master - disables bus-mastering for device dev
2703 * @dev: the PCI device to disable
2705 void pci_clear_master(struct pci_dev *dev)
2707 __pci_set_master(dev, false);
2711 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2712 * @dev: the PCI device for which MWI is to be enabled
2714 * Helper function for pci_set_mwi.
2715 * Originally copied from drivers/net/acenic.c.
2716 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2718 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2720 int pci_set_cacheline_size(struct pci_dev *dev)
2724 if (!pci_cache_line_size)
2727 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2728 equal to or multiple of the right value. */
2729 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2730 if (cacheline_size >= pci_cache_line_size &&
2731 (cacheline_size % pci_cache_line_size) == 0)
2734 /* Write the correct value. */
2735 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2737 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2738 if (cacheline_size == pci_cache_line_size)
2741 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2742 "supported\n", pci_cache_line_size << 2);
2746 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2748 #ifdef PCI_DISABLE_MWI
2749 int pci_set_mwi(struct pci_dev *dev)
2754 int pci_try_set_mwi(struct pci_dev *dev)
2759 void pci_clear_mwi(struct pci_dev *dev)
2766 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2767 * @dev: the PCI device for which MWI is enabled
2769 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2771 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2774 pci_set_mwi(struct pci_dev *dev)
2779 rc = pci_set_cacheline_size(dev);
2783 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2784 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2785 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2786 cmd |= PCI_COMMAND_INVALIDATE;
2787 pci_write_config_word(dev, PCI_COMMAND, cmd);
2794 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2795 * @dev: the PCI device for which MWI is enabled
2797 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2798 * Callers are not required to check the return value.
2800 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2802 int pci_try_set_mwi(struct pci_dev *dev)
2804 int rc = pci_set_mwi(dev);
2809 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2810 * @dev: the PCI device to disable
2812 * Disables PCI Memory-Write-Invalidate transaction on the device
2815 pci_clear_mwi(struct pci_dev *dev)
2819 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2820 if (cmd & PCI_COMMAND_INVALIDATE) {
2821 cmd &= ~PCI_COMMAND_INVALIDATE;
2822 pci_write_config_word(dev, PCI_COMMAND, cmd);
2825 #endif /* ! PCI_DISABLE_MWI */
2828 * pci_intx - enables/disables PCI INTx for device dev
2829 * @pdev: the PCI device to operate on
2830 * @enable: boolean: whether to enable or disable PCI INTx
2832 * Enables/disables PCI INTx for device dev
2835 pci_intx(struct pci_dev *pdev, int enable)
2837 u16 pci_command, new;
2839 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2842 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2844 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2847 if (new != pci_command) {
2848 struct pci_devres *dr;
2850 pci_write_config_word(pdev, PCI_COMMAND, new);
2852 dr = find_pci_dr(pdev);
2853 if (dr && !dr->restore_intx) {
2854 dr->restore_intx = 1;
2855 dr->orig_intx = !enable;
2861 * pci_intx_mask_supported - probe for INTx masking support
2862 * @dev: the PCI device to operate on
2864 * Check if the device dev support INTx masking via the config space
2867 bool pci_intx_mask_supported(struct pci_dev *dev)
2869 bool mask_supported = false;
2872 pci_cfg_access_lock(dev);
2874 pci_read_config_word(dev, PCI_COMMAND, &orig);
2875 pci_write_config_word(dev, PCI_COMMAND,
2876 orig ^ PCI_COMMAND_INTX_DISABLE);
2877 pci_read_config_word(dev, PCI_COMMAND, &new);
2880 * There's no way to protect against hardware bugs or detect them
2881 * reliably, but as long as we know what the value should be, let's
2882 * go ahead and check it.
2884 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2885 dev_err(&dev->dev, "Command register changed from "
2886 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2887 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2888 mask_supported = true;
2889 pci_write_config_word(dev, PCI_COMMAND, orig);
2892 pci_cfg_access_unlock(dev);
2893 return mask_supported;
2895 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2897 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2899 struct pci_bus *bus = dev->bus;
2900 bool mask_updated = true;
2901 u32 cmd_status_dword;
2902 u16 origcmd, newcmd;
2903 unsigned long flags;
2907 * We do a single dword read to retrieve both command and status.
2908 * Document assumptions that make this possible.
2910 BUILD_BUG_ON(PCI_COMMAND % 4);
2911 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2913 raw_spin_lock_irqsave(&pci_lock, flags);
2915 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2917 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
2920 * Check interrupt status register to see whether our device
2921 * triggered the interrupt (when masking) or the next IRQ is
2922 * already pending (when unmasking).
2924 if (mask != irq_pending) {
2925 mask_updated = false;
2929 origcmd = cmd_status_dword;
2930 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
2932 newcmd |= PCI_COMMAND_INTX_DISABLE;
2933 if (newcmd != origcmd)
2934 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
2937 raw_spin_unlock_irqrestore(&pci_lock, flags);
2939 return mask_updated;
2943 * pci_check_and_mask_intx - mask INTx on pending interrupt
2944 * @dev: the PCI device to operate on
2946 * Check if the device dev has its INTx line asserted, mask it and
2947 * return true in that case. False is returned if not interrupt was
2950 bool pci_check_and_mask_intx(struct pci_dev *dev)
2952 return pci_check_and_set_intx_mask(dev, true);
2954 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
2957 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
2958 * @dev: the PCI device to operate on
2960 * Check if the device dev has its INTx line asserted, unmask it if not
2961 * and return true. False is returned and the mask remains active if
2962 * there was still an interrupt pending.
2964 bool pci_check_and_unmask_intx(struct pci_dev *dev)
2966 return pci_check_and_set_intx_mask(dev, false);
2968 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
2971 * pci_msi_off - disables any msi or msix capabilities
2972 * @dev: the PCI device to operate on
2974 * If you want to use msi see pci_enable_msi and friends.
2975 * This is a lower level primitive that allows us to disable
2976 * msi operation at the device level.
2978 void pci_msi_off(struct pci_dev *dev)
2983 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2985 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2986 control &= ~PCI_MSI_FLAGS_ENABLE;
2987 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2989 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2991 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2992 control &= ~PCI_MSIX_FLAGS_ENABLE;
2993 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2996 EXPORT_SYMBOL_GPL(pci_msi_off);
2998 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3000 return dma_set_max_seg_size(&dev->dev, size);
3002 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3004 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3006 return dma_set_seg_boundary(&dev->dev, mask);
3008 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3010 static int pcie_flr(struct pci_dev *dev, int probe)
3015 u16 status, control;
3017 pos = pci_pcie_cap(dev);
3021 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
3022 if (!(cap & PCI_EXP_DEVCAP_FLR))
3028 /* Wait for Transaction Pending bit clean */
3029 for (i = 0; i < 4; i++) {
3031 msleep((1 << (i - 1)) * 100);
3033 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
3034 if (!(status & PCI_EXP_DEVSTA_TRPND))
3038 dev_err(&dev->dev, "transaction is not cleared; "
3039 "proceeding with reset anyway\n");
3042 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
3043 control |= PCI_EXP_DEVCTL_BCR_FLR;
3044 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
3051 static int pci_af_flr(struct pci_dev *dev, int probe)
3058 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3062 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3063 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3069 /* Wait for Transaction Pending bit clean */
3070 for (i = 0; i < 4; i++) {
3072 msleep((1 << (i - 1)) * 100);
3074 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3075 if (!(status & PCI_AF_STATUS_TP))
3079 dev_err(&dev->dev, "transaction is not cleared; "
3080 "proceeding with reset anyway\n");
3083 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3090 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3091 * @dev: Device to reset.
3092 * @probe: If set, only check if the device can be reset this way.
3094 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3095 * unset, it will be reinitialized internally when going from PCI_D3hot to
3096 * PCI_D0. If that's the case and the device is not in a low-power state
3097 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3099 * NOTE: This causes the caller to sleep for twice the device power transition
3100 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3101 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3102 * Moreover, only devices in D0 can be reset by this function.
3104 static int pci_pm_reset(struct pci_dev *dev, int probe)
3111 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3112 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3118 if (dev->current_state != PCI_D0)
3121 csr &= ~PCI_PM_CTRL_STATE_MASK;
3123 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3124 pci_dev_d3_sleep(dev);
3126 csr &= ~PCI_PM_CTRL_STATE_MASK;
3128 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3129 pci_dev_d3_sleep(dev);
3134 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3137 struct pci_dev *pdev;
3139 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3142 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3149 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
3150 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3151 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3154 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3155 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3161 static int pci_dev_reset(struct pci_dev *dev, int probe)
3168 pci_cfg_access_lock(dev);
3169 /* block PM suspend, driver probe, etc. */
3170 device_lock(&dev->dev);
3173 rc = pci_dev_specific_reset(dev, probe);
3177 rc = pcie_flr(dev, probe);
3181 rc = pci_af_flr(dev, probe);
3185 rc = pci_pm_reset(dev, probe);
3189 rc = pci_parent_bus_reset(dev, probe);
3192 device_unlock(&dev->dev);
3193 pci_cfg_access_unlock(dev);
3200 * __pci_reset_function - reset a PCI device function
3201 * @dev: PCI device to reset
3203 * Some devices allow an individual function to be reset without affecting
3204 * other functions in the same device. The PCI device must be responsive
3205 * to PCI config space in order to use this function.
3207 * The device function is presumed to be unused when this function is called.
3208 * Resetting the device will make the contents of PCI configuration space
3209 * random, so any caller of this must be prepared to reinitialise the
3210 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3213 * Returns 0 if the device function was successfully reset or negative if the
3214 * device doesn't support resetting a single function.
3216 int __pci_reset_function(struct pci_dev *dev)
3218 return pci_dev_reset(dev, 0);
3220 EXPORT_SYMBOL_GPL(__pci_reset_function);
3223 * __pci_reset_function_locked - reset a PCI device function while holding
3224 * the @dev mutex lock.
3225 * @dev: PCI device to reset
3227 * Some devices allow an individual function to be reset without affecting
3228 * other functions in the same device. The PCI device must be responsive
3229 * to PCI config space in order to use this function.
3231 * The device function is presumed to be unused and the caller is holding
3232 * the device mutex lock when this function is called.
3233 * Resetting the device will make the contents of PCI configuration space
3234 * random, so any caller of this must be prepared to reinitialise the
3235 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3238 * Returns 0 if the device function was successfully reset or negative if the
3239 * device doesn't support resetting a single function.
3241 int __pci_reset_function_locked(struct pci_dev *dev)
3243 return pci_dev_reset(dev, 1);
3245 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3248 * pci_probe_reset_function - check whether the device can be safely reset
3249 * @dev: PCI device to reset
3251 * Some devices allow an individual function to be reset without affecting
3252 * other functions in the same device. The PCI device must be responsive
3253 * to PCI config space in order to use this function.
3255 * Returns 0 if the device function can be reset or negative if the
3256 * device doesn't support resetting a single function.
3258 int pci_probe_reset_function(struct pci_dev *dev)
3260 return pci_dev_reset(dev, 1);
3264 * pci_reset_function - quiesce and reset a PCI device function
3265 * @dev: PCI device to reset
3267 * Some devices allow an individual function to be reset without affecting
3268 * other functions in the same device. The PCI device must be responsive
3269 * to PCI config space in order to use this function.
3271 * This function does not just reset the PCI portion of a device, but
3272 * clears all the state associated with the device. This function differs
3273 * from __pci_reset_function in that it saves and restores device state
3276 * Returns 0 if the device function was successfully reset or negative if the
3277 * device doesn't support resetting a single function.
3279 int pci_reset_function(struct pci_dev *dev)
3283 rc = pci_dev_reset(dev, 1);
3287 pci_save_state(dev);
3290 * both INTx and MSI are disabled after the Interrupt Disable bit
3291 * is set and the Bus Master bit is cleared.
3293 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3295 rc = pci_dev_reset(dev, 0);
3297 pci_restore_state(dev);
3301 EXPORT_SYMBOL_GPL(pci_reset_function);
3304 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3305 * @dev: PCI device to query
3307 * Returns mmrbc: maximum designed memory read count in bytes
3308 * or appropriate error value.
3310 int pcix_get_max_mmrbc(struct pci_dev *dev)
3315 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3319 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3322 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3324 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3327 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3328 * @dev: PCI device to query
3330 * Returns mmrbc: maximum memory read count in bytes
3331 * or appropriate error value.
3333 int pcix_get_mmrbc(struct pci_dev *dev)
3338 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3342 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3345 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3347 EXPORT_SYMBOL(pcix_get_mmrbc);
3350 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3351 * @dev: PCI device to query
3352 * @mmrbc: maximum memory read count in bytes
3353 * valid values are 512, 1024, 2048, 4096
3355 * If possible sets maximum memory read byte count, some bridges have erratas
3356 * that prevent this.
3358 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3364 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3367 v = ffs(mmrbc) - 10;
3369 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3373 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3376 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3379 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3382 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3384 if (v > o && dev->bus &&
3385 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3388 cmd &= ~PCI_X_CMD_MAX_READ;
3390 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3395 EXPORT_SYMBOL(pcix_set_mmrbc);
3398 * pcie_get_readrq - get PCI Express read request size
3399 * @dev: PCI device to query
3401 * Returns maximum memory read request in bytes
3402 * or appropriate error value.
3404 int pcie_get_readrq(struct pci_dev *dev)
3409 cap = pci_pcie_cap(dev);
3413 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3415 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3419 EXPORT_SYMBOL(pcie_get_readrq);
3422 * pcie_set_readrq - set PCI Express maximum memory read request
3423 * @dev: PCI device to query
3424 * @rq: maximum memory read count in bytes
3425 * valid values are 128, 256, 512, 1024, 2048, 4096
3427 * If possible sets maximum memory read request in bytes
3429 int pcie_set_readrq(struct pci_dev *dev, int rq)
3431 int cap, err = -EINVAL;
3434 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3437 cap = pci_pcie_cap(dev);
3441 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3445 * If using the "performance" PCIe config, we clamp the
3446 * read rq size to the max packet size to prevent the
3447 * host bridge generating requests larger than we can
3450 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3451 int mps = pcie_get_mps(dev);
3459 v = (ffs(rq) - 8) << 12;
3461 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3462 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3464 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3470 EXPORT_SYMBOL(pcie_set_readrq);
3473 * pcie_get_mps - get PCI Express maximum payload size
3474 * @dev: PCI device to query
3476 * Returns maximum payload size in bytes
3477 * or appropriate error value.
3479 int pcie_get_mps(struct pci_dev *dev)
3484 cap = pci_pcie_cap(dev);
3488 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3490 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3496 * pcie_set_mps - set PCI Express maximum payload size
3497 * @dev: PCI device to query
3498 * @mps: maximum payload size in bytes
3499 * valid values are 128, 256, 512, 1024, 2048, 4096
3501 * If possible sets maximum payload size
3503 int pcie_set_mps(struct pci_dev *dev, int mps)
3505 int cap, err = -EINVAL;
3508 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3512 if (v > dev->pcie_mpss)
3516 cap = pci_pcie_cap(dev);
3520 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3524 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3525 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3527 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3534 * pci_select_bars - Make BAR mask from the type of resource
3535 * @dev: the PCI device for which BAR mask is made
3536 * @flags: resource type mask to be selected
3538 * This helper routine makes bar mask from the type of resource.
3540 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3543 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3544 if (pci_resource_flags(dev, i) & flags)
3550 * pci_resource_bar - get position of the BAR associated with a resource
3551 * @dev: the PCI device
3552 * @resno: the resource number
3553 * @type: the BAR type to be filled in
3555 * Returns BAR position in config space, or 0 if the BAR is invalid.
3557 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3561 if (resno < PCI_ROM_RESOURCE) {
3562 *type = pci_bar_unknown;
3563 return PCI_BASE_ADDRESS_0 + 4 * resno;
3564 } else if (resno == PCI_ROM_RESOURCE) {
3565 *type = pci_bar_mem32;
3566 return dev->rom_base_reg;
3567 } else if (resno < PCI_BRIDGE_RESOURCES) {
3568 /* device specific resource */
3569 reg = pci_iov_resource_bar(dev, resno, type);
3574 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3578 /* Some architectures require additional programming to enable VGA */
3579 static arch_set_vga_state_t arch_set_vga_state;
3581 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3583 arch_set_vga_state = func; /* NULL disables */
3586 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3587 unsigned int command_bits, u32 flags)
3589 if (arch_set_vga_state)
3590 return arch_set_vga_state(dev, decode, command_bits,
3596 * pci_set_vga_state - set VGA decode state on device and parents if requested
3597 * @dev: the PCI device
3598 * @decode: true = enable decoding, false = disable decoding
3599 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3600 * @flags: traverse ancestors and change bridges
3601 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3603 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3604 unsigned int command_bits, u32 flags)
3606 struct pci_bus *bus;
3607 struct pci_dev *bridge;
3611 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3613 /* ARCH specific VGA enables */
3614 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3618 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3619 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3621 cmd |= command_bits;
3623 cmd &= ~command_bits;
3624 pci_write_config_word(dev, PCI_COMMAND, cmd);
3627 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3634 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3637 cmd |= PCI_BRIDGE_CTL_VGA;
3639 cmd &= ~PCI_BRIDGE_CTL_VGA;
3640 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3648 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3649 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3650 static DEFINE_SPINLOCK(resource_alignment_lock);
3653 * pci_specified_resource_alignment - get resource alignment specified by user.
3654 * @dev: the PCI device to get
3656 * RETURNS: Resource alignment if it is specified.
3657 * Zero if it is not specified.
3659 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3661 int seg, bus, slot, func, align_order, count;
3662 resource_size_t align = 0;
3665 spin_lock(&resource_alignment_lock);
3666 p = resource_alignment_param;
3669 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3675 if (sscanf(p, "%x:%x:%x.%x%n",
3676 &seg, &bus, &slot, &func, &count) != 4) {
3678 if (sscanf(p, "%x:%x.%x%n",
3679 &bus, &slot, &func, &count) != 3) {
3680 /* Invalid format */
3681 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3687 if (seg == pci_domain_nr(dev->bus) &&
3688 bus == dev->bus->number &&
3689 slot == PCI_SLOT(dev->devfn) &&
3690 func == PCI_FUNC(dev->devfn)) {
3691 if (align_order == -1) {
3694 align = 1 << align_order;
3699 if (*p != ';' && *p != ',') {
3700 /* End of param or invalid format */
3705 spin_unlock(&resource_alignment_lock);
3710 * pci_is_reassigndev - check if specified PCI is target device to reassign
3711 * @dev: the PCI device to check
3713 * RETURNS: non-zero for PCI device is a target device to reassign,
3716 int pci_is_reassigndev(struct pci_dev *dev)
3718 return (pci_specified_resource_alignment(dev) != 0);
3722 * This function disables memory decoding and releases memory resources
3723 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3724 * It also rounds up size to specified alignment.
3725 * Later on, the kernel will assign page-aligned memory resource back
3728 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
3732 resource_size_t align, size;
3735 if (!pci_is_reassigndev(dev))
3738 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
3739 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
3741 "Can't reassign resources to host bridge.\n");
3746 "Disabling memory decoding and releasing memory resources.\n");
3747 pci_read_config_word(dev, PCI_COMMAND, &command);
3748 command &= ~PCI_COMMAND_MEMORY;
3749 pci_write_config_word(dev, PCI_COMMAND, command);
3751 align = pci_specified_resource_alignment(dev);
3752 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
3753 r = &dev->resource[i];
3754 if (!(r->flags & IORESOURCE_MEM))
3756 size = resource_size(r);
3760 "Rounding up size of resource #%d to %#llx.\n",
3761 i, (unsigned long long)size);
3766 /* Need to disable bridge's resource window,
3767 * to enable the kernel to reassign new resource
3770 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3771 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
3772 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
3773 r = &dev->resource[i];
3774 if (!(r->flags & IORESOURCE_MEM))
3776 r->end = resource_size(r) - 1;
3779 pci_disable_bridge_window(dev);
3783 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3785 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3786 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3787 spin_lock(&resource_alignment_lock);
3788 strncpy(resource_alignment_param, buf, count);
3789 resource_alignment_param[count] = '\0';
3790 spin_unlock(&resource_alignment_lock);
3794 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3797 spin_lock(&resource_alignment_lock);
3798 count = snprintf(buf, size, "%s", resource_alignment_param);
3799 spin_unlock(&resource_alignment_lock);
3803 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3805 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3808 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3809 const char *buf, size_t count)
3811 return pci_set_resource_alignment_param(buf, count);
3814 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3815 pci_resource_alignment_store);
3817 static int __init pci_resource_alignment_sysfs_init(void)
3819 return bus_create_file(&pci_bus_type,
3820 &bus_attr_resource_alignment);
3823 late_initcall(pci_resource_alignment_sysfs_init);
3825 static void __devinit pci_no_domains(void)
3827 #ifdef CONFIG_PCI_DOMAINS
3828 pci_domains_supported = 0;
3833 * pci_ext_cfg_enabled - can we access extended PCI config space?
3834 * @dev: The PCI device of the root bridge.
3836 * Returns 1 if we can access PCI extended config space (offsets
3837 * greater than 0xff). This is the default implementation. Architecture
3838 * implementations can override this.
3840 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3845 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3848 EXPORT_SYMBOL(pci_fixup_cardbus);
3850 static int __init pci_setup(char *str)
3853 char *k = strchr(str, ',');
3856 if (*str && (str = pcibios_setup(str)) && *str) {
3857 if (!strcmp(str, "nomsi")) {
3859 } else if (!strcmp(str, "noaer")) {
3861 } else if (!strncmp(str, "realloc=", 8)) {
3862 pci_realloc_get_opt(str + 8);
3863 } else if (!strncmp(str, "realloc", 7)) {
3864 pci_realloc_get_opt("on");
3865 } else if (!strcmp(str, "nodomains")) {
3867 } else if (!strncmp(str, "noari", 5)) {
3868 pcie_ari_disabled = true;
3869 } else if (!strncmp(str, "cbiosize=", 9)) {
3870 pci_cardbus_io_size = memparse(str + 9, &str);
3871 } else if (!strncmp(str, "cbmemsize=", 10)) {
3872 pci_cardbus_mem_size = memparse(str + 10, &str);
3873 } else if (!strncmp(str, "resource_alignment=", 19)) {
3874 pci_set_resource_alignment_param(str + 19,
3876 } else if (!strncmp(str, "ecrc=", 5)) {
3877 pcie_ecrc_get_policy(str + 5);
3878 } else if (!strncmp(str, "hpiosize=", 9)) {
3879 pci_hotplug_io_size = memparse(str + 9, &str);
3880 } else if (!strncmp(str, "hpmemsize=", 10)) {
3881 pci_hotplug_mem_size = memparse(str + 10, &str);
3882 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3883 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3884 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3885 pcie_bus_config = PCIE_BUS_SAFE;
3886 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3887 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3888 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3889 pcie_bus_config = PCIE_BUS_PEER2PEER;
3891 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3899 early_param("pci", pci_setup);
3901 EXPORT_SYMBOL(pci_reenable_device);
3902 EXPORT_SYMBOL(pci_enable_device_io);
3903 EXPORT_SYMBOL(pci_enable_device_mem);
3904 EXPORT_SYMBOL(pci_enable_device);
3905 EXPORT_SYMBOL(pcim_enable_device);
3906 EXPORT_SYMBOL(pcim_pin_device);
3907 EXPORT_SYMBOL(pci_disable_device);
3908 EXPORT_SYMBOL(pci_find_capability);
3909 EXPORT_SYMBOL(pci_bus_find_capability);
3910 EXPORT_SYMBOL(pci_release_regions);
3911 EXPORT_SYMBOL(pci_request_regions);
3912 EXPORT_SYMBOL(pci_request_regions_exclusive);
3913 EXPORT_SYMBOL(pci_release_region);
3914 EXPORT_SYMBOL(pci_request_region);
3915 EXPORT_SYMBOL(pci_request_region_exclusive);
3916 EXPORT_SYMBOL(pci_release_selected_regions);
3917 EXPORT_SYMBOL(pci_request_selected_regions);
3918 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3919 EXPORT_SYMBOL(pci_set_master);
3920 EXPORT_SYMBOL(pci_clear_master);
3921 EXPORT_SYMBOL(pci_set_mwi);
3922 EXPORT_SYMBOL(pci_try_set_mwi);
3923 EXPORT_SYMBOL(pci_clear_mwi);
3924 EXPORT_SYMBOL_GPL(pci_intx);
3925 EXPORT_SYMBOL(pci_assign_resource);
3926 EXPORT_SYMBOL(pci_find_parent_resource);
3927 EXPORT_SYMBOL(pci_select_bars);
3929 EXPORT_SYMBOL(pci_set_power_state);
3930 EXPORT_SYMBOL(pci_save_state);
3931 EXPORT_SYMBOL(pci_restore_state);
3932 EXPORT_SYMBOL(pci_pme_capable);
3933 EXPORT_SYMBOL(pci_pme_active);
3934 EXPORT_SYMBOL(pci_wake_from_d3);
3935 EXPORT_SYMBOL(pci_target_state);
3936 EXPORT_SYMBOL(pci_prepare_to_sleep);
3937 EXPORT_SYMBOL(pci_back_from_sleep);
3938 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);