drivers/pinctrl/intel/pinctrl-baytrail.c

   1 /*
   2  * Pinctrl GPIO driver for Intel Baytrail
   3  * Copyright (c) 2012-2013, Intel Corporation.
   4  *
   5  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/types.h>
  21 #include <linux/bitops.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/gpio.h>
  24 #include <linux/gpio/driver.h>
  25 #include <linux/acpi.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/io.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/pinctrl/pinctrl.h>
  31 #include <linux/pinctrl/pinmux.h>
  32 #include <linux/pinctrl/pinconf.h>
  33 #include <linux/pinctrl/pinconf-generic.h>
  34
  35 /* memory mapped register offsets */
  36 #define BYT_CONF0_REG           0x000
  37 #define BYT_CONF1_REG           0x004
  38 #define BYT_VAL_REG             0x008
  39 #define BYT_DFT_REG             0x00c
  40 #define BYT_INT_STAT_REG        0x800
  41 #define BYT_DEBOUNCE_REG        0x9d0
  42
  43 /* BYT_CONF0_REG register bits */
  44 #define BYT_IODEN               BIT(31)
  45 #define BYT_DIRECT_IRQ_EN       BIT(27)
  46 #define BYT_TRIG_NEG            BIT(26)
  47 #define BYT_TRIG_POS            BIT(25)
  48 #define BYT_TRIG_LVL            BIT(24)
  49 #define BYT_DEBOUNCE_EN         BIT(20)
  50 #define BYT_PULL_STR_SHIFT      9
  51 #define BYT_PULL_STR_MASK       (3 << BYT_PULL_STR_SHIFT)
  52 #define BYT_PULL_STR_2K         (0 << BYT_PULL_STR_SHIFT)
  53 #define BYT_PULL_STR_10K        (1 << BYT_PULL_STR_SHIFT)
  54 #define BYT_PULL_STR_20K        (2 << BYT_PULL_STR_SHIFT)
  55 #define BYT_PULL_STR_40K        (3 << BYT_PULL_STR_SHIFT)
  56 #define BYT_PULL_ASSIGN_SHIFT   7
  57 #define BYT_PULL_ASSIGN_MASK    (3 << BYT_PULL_ASSIGN_SHIFT)
  58 #define BYT_PULL_ASSIGN_UP      (1 << BYT_PULL_ASSIGN_SHIFT)
  59 #define BYT_PULL_ASSIGN_DOWN    (2 << BYT_PULL_ASSIGN_SHIFT)
  60 #define BYT_PIN_MUX             0x07
  61
  62 /* BYT_VAL_REG register bits */
  63 #define BYT_INPUT_EN            BIT(2)  /* 0: input enabled (active low)*/
  64 #define BYT_OUTPUT_EN           BIT(1)  /* 0: output enabled (active low)*/
  65 #define BYT_LEVEL               BIT(0)
  66
  67 #define BYT_DIR_MASK            (BIT(1) | BIT(2))
  68 #define BYT_TRIG_MASK           (BIT(26) | BIT(25) | BIT(24))
  69
  70 #define BYT_CONF0_RESTORE_MASK  (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
  71                                  BYT_PIN_MUX)
  72 #define BYT_VAL_RESTORE_MASK    (BYT_DIR_MASK | BYT_LEVEL)
  73
  74 /* BYT_DEBOUNCE_REG bits */
  75 #define BYT_DEBOUNCE_PULSE_MASK         0x7
  76 #define BYT_DEBOUNCE_PULSE_375US        1
  77 #define BYT_DEBOUNCE_PULSE_750US        2
  78 #define BYT_DEBOUNCE_PULSE_1500US       3
  79 #define BYT_DEBOUNCE_PULSE_3MS          4
  80 #define BYT_DEBOUNCE_PULSE_6MS          5
  81 #define BYT_DEBOUNCE_PULSE_12MS         6
  82 #define BYT_DEBOUNCE_PULSE_24MS         7
  83
  84 #define BYT_NGPIO_SCORE         102
  85 #define BYT_NGPIO_NCORE         28
  86 #define BYT_NGPIO_SUS           44
  87
  88 #define BYT_SCORE_ACPI_UID      "1"
  89 #define BYT_NCORE_ACPI_UID      "2"
  90 #define BYT_SUS_ACPI_UID        "3"
  91
  92 /*
  93  * This is the function value most pins have for GPIO muxing. If the value
  94  * differs from the default one, it must be explicitly mentioned. Otherwise, the
  95  * pin control implementation will set the muxing value to default GPIO if it
  96  * does not find a match for the requested function.
  97  */
  98 #define BYT_DEFAULT_GPIO_MUX    0
  99
 100 struct byt_gpio_pin_context {
 101         u32 conf0;
 102         u32 val;
 103 };
 104
 105 struct byt_simple_func_mux {
 106         const char *name;
 107         unsigned short func;
 108 };
 109
 110 struct byt_mixed_func_mux {
 111         const char *name;
 112         const unsigned short *func_values;
 113 };
 114
 115 struct byt_pingroup {
 116         const char *name;
 117         const unsigned int *pins;
 118         size_t npins;
 119         unsigned short has_simple_funcs;
 120         union {
 121                 const struct byt_simple_func_mux *simple_funcs;
 122                 const struct byt_mixed_func_mux *mixed_funcs;
 123         };
 124         size_t nfuncs;
 125 };
 126
 127 struct byt_function {
 128         const char *name;
 129         const char * const *groups;
 130         size_t ngroups;
 131 };
 132
 133 struct byt_community {
 134         unsigned int pin_base;
 135         size_t npins;
 136         const unsigned int *pad_map;
 137         void __iomem *reg_base;
 138 };
 139
 140 #define SIMPLE_FUNC(n, f)       \
 141         {                       \
 142                 .name   = (n),  \
 143                 .func   = (f),  \
 144         }
 145 #define MIXED_FUNC(n, f)                \
 146         {                               \
 147                 .name           = (n),  \
 148                 .func_values    = (f),  \
 149         }
 150
 151 #define PIN_GROUP_SIMPLE(n, p, f)                               \
 152         {                                                       \
 153                 .name                   = (n),                  \
 154                 .pins                   = (p),                  \
 155                 .npins                  = ARRAY_SIZE((p)),      \
 156                 .has_simple_funcs       = 1,            \
 157                 .simple_funcs           = (f),                  \
 158                 .nfuncs                 = ARRAY_SIZE((f)),      \
 159         }
 160 #define PIN_GROUP_MIXED(n, p, f)                                \
 161         {                                                       \
 162                 .name                   = (n),                  \
 163                 .pins                   = (p),                  \
 164                 .npins                  = ARRAY_SIZE((p)),      \
 165                 .has_simple_funcs       = 0,                    \
 166                 .mixed_funcs            = (f),                  \
 167                 .nfuncs                 = ARRAY_SIZE((f)),      \
 168         }
 169
 170 #define FUNCTION(n, g)                                  \
 171         {                                               \
 172                 .name           = (n),                  \
 173                 .groups         = (g),                  \
 174                 .ngroups        = ARRAY_SIZE((g)),      \
 175         }
 176
 177 #define COMMUNITY(p, n, map)            \
 178         {                               \
 179                 .pin_base       = (p),  \
 180                 .npins          = (n),  \
 181                 .pad_map        = (map),\
 182         }
 183
 184 struct byt_pinctrl_soc_data {
 185         const char *uid;
 186         const struct pinctrl_pin_desc *pins;
 187         size_t npins;
 188         const struct byt_pingroup *groups;
 189         size_t ngroups;
 190         const struct byt_function *functions;
 191         size_t nfunctions;
 192         const struct byt_community *communities;
 193         size_t ncommunities;
 194 };
 195
 196 struct byt_gpio {
 197         struct gpio_chip chip;
 198         struct platform_device *pdev;
 199         struct pinctrl_dev *pctl_dev;
 200         struct pinctrl_desc pctl_desc;
 201         raw_spinlock_t lock;
 202         const struct byt_pinctrl_soc_data *soc_data;
 203         struct byt_community *communities_copy;
 204         struct byt_gpio_pin_context *saved_context;
 205 };
 206
 207 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
 208 static const struct pinctrl_pin_desc byt_score_pins[] = {
 209         PINCTRL_PIN(0, "SATA_GP0"),
 210         PINCTRL_PIN(1, "SATA_GP1"),
 211         PINCTRL_PIN(2, "SATA_LED#"),
 212         PINCTRL_PIN(3, "PCIE_CLKREQ0"),
 213         PINCTRL_PIN(4, "PCIE_CLKREQ1"),
 214         PINCTRL_PIN(5, "PCIE_CLKREQ2"),
 215         PINCTRL_PIN(6, "PCIE_CLKREQ3"),
 216         PINCTRL_PIN(7, "SD3_WP"),
 217         PINCTRL_PIN(8, "HDA_RST"),
 218         PINCTRL_PIN(9, "HDA_SYNC"),
 219         PINCTRL_PIN(10, "HDA_CLK"),
 220         PINCTRL_PIN(11, "HDA_SDO"),
 221         PINCTRL_PIN(12, "HDA_SDI0"),
 222         PINCTRL_PIN(13, "HDA_SDI1"),
 223         PINCTRL_PIN(14, "GPIO_S0_SC14"),
 224         PINCTRL_PIN(15, "GPIO_S0_SC15"),
 225         PINCTRL_PIN(16, "MMC1_CLK"),
 226         PINCTRL_PIN(17, "MMC1_D0"),
 227         PINCTRL_PIN(18, "MMC1_D1"),
 228         PINCTRL_PIN(19, "MMC1_D2"),
 229         PINCTRL_PIN(20, "MMC1_D3"),
 230         PINCTRL_PIN(21, "MMC1_D4"),
 231         PINCTRL_PIN(22, "MMC1_D5"),
 232         PINCTRL_PIN(23, "MMC1_D6"),
 233         PINCTRL_PIN(24, "MMC1_D7"),
 234         PINCTRL_PIN(25, "MMC1_CMD"),
 235         PINCTRL_PIN(26, "MMC1_RST"),
 236         PINCTRL_PIN(27, "SD2_CLK"),
 237         PINCTRL_PIN(28, "SD2_D0"),
 238         PINCTRL_PIN(29, "SD2_D1"),
 239         PINCTRL_PIN(30, "SD2_D2"),
 240         PINCTRL_PIN(31, "SD2_D3_CD"),
 241         PINCTRL_PIN(32, "SD2_CMD"),
 242         PINCTRL_PIN(33, "SD3_CLK"),
 243         PINCTRL_PIN(34, "SD3_D0"),
 244         PINCTRL_PIN(35, "SD3_D1"),
 245         PINCTRL_PIN(36, "SD3_D2"),
 246         PINCTRL_PIN(37, "SD3_D3"),
 247         PINCTRL_PIN(38, "SD3_CD"),
 248         PINCTRL_PIN(39, "SD3_CMD"),
 249         PINCTRL_PIN(40, "SD3_1P8EN"),
 250         PINCTRL_PIN(41, "SD3_PWREN#"),
 251         PINCTRL_PIN(42, "ILB_LPC_AD0"),
 252         PINCTRL_PIN(43, "ILB_LPC_AD1"),
 253         PINCTRL_PIN(44, "ILB_LPC_AD2"),
 254         PINCTRL_PIN(45, "ILB_LPC_AD3"),
 255         PINCTRL_PIN(46, "ILB_LPC_FRAME"),
 256         PINCTRL_PIN(47, "ILB_LPC_CLK0"),
 257         PINCTRL_PIN(48, "ILB_LPC_CLK1"),
 258         PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
 259         PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
 260         PINCTRL_PIN(51, "PCU_SMB_DATA"),
 261         PINCTRL_PIN(52, "PCU_SMB_CLK"),
 262         PINCTRL_PIN(53, "PCU_SMB_ALERT"),
 263         PINCTRL_PIN(54, "ILB_8254_SPKR"),
 264         PINCTRL_PIN(55, "GPIO_S0_SC55"),
 265         PINCTRL_PIN(56, "GPIO_S0_SC56"),
 266         PINCTRL_PIN(57, "GPIO_S0_SC57"),
 267         PINCTRL_PIN(58, "GPIO_S0_SC58"),
 268         PINCTRL_PIN(59, "GPIO_S0_SC59"),
 269         PINCTRL_PIN(60, "GPIO_S0_SC60"),
 270         PINCTRL_PIN(61, "GPIO_S0_SC61"),
 271         PINCTRL_PIN(62, "LPE_I2S2_CLK"),
 272         PINCTRL_PIN(63, "LPE_I2S2_FRM"),
 273         PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
 274         PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
 275         PINCTRL_PIN(66, "SIO_SPI_CS"),
 276         PINCTRL_PIN(67, "SIO_SPI_MISO"),
 277         PINCTRL_PIN(68, "SIO_SPI_MOSI"),
 278         PINCTRL_PIN(69, "SIO_SPI_CLK"),
 279         PINCTRL_PIN(70, "SIO_UART1_RXD"),
 280         PINCTRL_PIN(71, "SIO_UART1_TXD"),
 281         PINCTRL_PIN(72, "SIO_UART1_RTS"),
 282         PINCTRL_PIN(73, "SIO_UART1_CTS"),
 283         PINCTRL_PIN(74, "SIO_UART2_RXD"),
 284         PINCTRL_PIN(75, "SIO_UART2_TXD"),
 285         PINCTRL_PIN(76, "SIO_UART2_RTS"),
 286         PINCTRL_PIN(77, "SIO_UART2_CTS"),
 287         PINCTRL_PIN(78, "SIO_I2C0_DATA"),
 288         PINCTRL_PIN(79, "SIO_I2C0_CLK"),
 289         PINCTRL_PIN(80, "SIO_I2C1_DATA"),
 290         PINCTRL_PIN(81, "SIO_I2C1_CLK"),
 291         PINCTRL_PIN(82, "SIO_I2C2_DATA"),
 292         PINCTRL_PIN(83, "SIO_I2C2_CLK"),
 293         PINCTRL_PIN(84, "SIO_I2C3_DATA"),
 294         PINCTRL_PIN(85, "SIO_I2C3_CLK"),
 295         PINCTRL_PIN(86, "SIO_I2C4_DATA"),
 296         PINCTRL_PIN(87, "SIO_I2C4_CLK"),
 297         PINCTRL_PIN(88, "SIO_I2C5_DATA"),
 298         PINCTRL_PIN(89, "SIO_I2C5_CLK"),
 299         PINCTRL_PIN(90, "SIO_I2C6_DATA"),
 300         PINCTRL_PIN(91, "SIO_I2C6_CLK"),
 301         PINCTRL_PIN(92, "GPIO_S0_SC92"),
 302         PINCTRL_PIN(93, "GPIO_S0_SC93"),
 303         PINCTRL_PIN(94, "SIO_PWM0"),
 304         PINCTRL_PIN(95, "SIO_PWM1"),
 305         PINCTRL_PIN(96, "PMC_PLT_CLK0"),
 306         PINCTRL_PIN(97, "PMC_PLT_CLK1"),
 307         PINCTRL_PIN(98, "PMC_PLT_CLK2"),
 308         PINCTRL_PIN(99, "PMC_PLT_CLK3"),
 309         PINCTRL_PIN(100, "PMC_PLT_CLK4"),
 310         PINCTRL_PIN(101, "PMC_PLT_CLK5"),
 311 };
 312
 313 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
 314         85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
 315         36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
 316         54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
 317         52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
 318         95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
 319         86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
 320         80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
 321         2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
 322         31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
 323         24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
 324         97, 100,
 325 };
 326
 327 /* SCORE groups */
 328 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
 329 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
 330 static const struct byt_simple_func_mux byt_score_uart_mux[] = {
 331         SIMPLE_FUNC("uart", 1),
 332 };
 333
 334 static const unsigned int byt_score_pwm0_pins[] = { 94 };
 335 static const unsigned int byt_score_pwm1_pins[] = { 95 };
 336 static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
 337         SIMPLE_FUNC("pwm", 1),
 338 };
 339
 340 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
 341 static const struct byt_simple_func_mux byt_score_spi_mux[] = {
 342         SIMPLE_FUNC("spi", 1),
 343 };
 344
 345 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
 346 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
 347 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
 348 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
 349 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
 350 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
 351 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
 352 static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
 353         SIMPLE_FUNC("i2c", 1),
 354 };
 355
 356 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
 357 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
 358 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
 359 static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
 360         SIMPLE_FUNC("ssp", 1),
 361 };
 362
 363 static const unsigned int byt_score_sdcard_pins[] = {
 364         7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
 365 };
 366 static const unsigned short byt_score_sdcard_mux_values[] = {
 367         2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 368 };
 369 static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
 370         MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
 371 };
 372
 373 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
 374 static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
 375         SIMPLE_FUNC("sdio", 1),
 376 };
 377
 378 static const unsigned int byt_score_emmc_pins[] = {
 379         16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 380 };
 381 static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
 382         SIMPLE_FUNC("emmc", 1),
 383 };
 384
 385 static const unsigned int byt_score_ilb_lpc_pins[] = {
 386         42, 43, 44, 45, 46, 47, 48, 49, 50,
 387 };
 388 static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
 389         SIMPLE_FUNC("lpc", 1),
 390 };
 391
 392 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
 393 static const struct byt_simple_func_mux byt_score_sata_mux[] = {
 394         SIMPLE_FUNC("sata", 1),
 395 };
 396
 397 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
 398 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
 399 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
 400 static const unsigned int byt_score_plt_clk4_pins[] = { 99 };
 401 static const unsigned int byt_score_plt_clk5_pins[] = { 100 };
 402 static const unsigned int byt_score_plt_clk3_pins[] = { 101 };
 403 static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
 404         SIMPLE_FUNC("plt_clk", 1),
 405 };
 406
 407 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
 408 static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
 409         SIMPLE_FUNC("smbus", 1),
 410 };
 411
 412 static const struct byt_pingroup byt_score_groups[] = {
 413         PIN_GROUP_SIMPLE("uart1_grp",
 414                          byt_score_uart1_pins, byt_score_uart_mux),
 415         PIN_GROUP_SIMPLE("uart2_grp",
 416                          byt_score_uart2_pins, byt_score_uart_mux),
 417         PIN_GROUP_SIMPLE("pwm0_grp",
 418                          byt_score_pwm0_pins, byt_score_pwm_mux),
 419         PIN_GROUP_SIMPLE("pwm1_grp",
 420                          byt_score_pwm1_pins, byt_score_pwm_mux),
 421         PIN_GROUP_SIMPLE("ssp2_grp",
 422                          byt_score_ssp2_pins, byt_score_pwm_mux),
 423         PIN_GROUP_SIMPLE("sio_spi_grp",
 424                          byt_score_sio_spi_pins, byt_score_spi_mux),
 425         PIN_GROUP_SIMPLE("i2c5_grp",
 426                          byt_score_i2c5_pins, byt_score_i2c_mux),
 427         PIN_GROUP_SIMPLE("i2c6_grp",
 428                          byt_score_i2c6_pins, byt_score_i2c_mux),
 429         PIN_GROUP_SIMPLE("i2c4_grp",
 430                          byt_score_i2c4_pins, byt_score_i2c_mux),
 431         PIN_GROUP_SIMPLE("i2c3_grp",
 432                          byt_score_i2c3_pins, byt_score_i2c_mux),
 433         PIN_GROUP_SIMPLE("i2c2_grp",
 434                          byt_score_i2c2_pins, byt_score_i2c_mux),
 435         PIN_GROUP_SIMPLE("i2c1_grp",
 436                          byt_score_i2c1_pins, byt_score_i2c_mux),
 437         PIN_GROUP_SIMPLE("i2c0_grp",
 438                          byt_score_i2c0_pins, byt_score_i2c_mux),
 439         PIN_GROUP_SIMPLE("ssp0_grp",
 440                          byt_score_ssp0_pins, byt_score_ssp_mux),
 441         PIN_GROUP_SIMPLE("ssp1_grp",
 442                          byt_score_ssp1_pins, byt_score_ssp_mux),
 443         PIN_GROUP_MIXED("sdcard_grp",
 444                         byt_score_sdcard_pins, byt_score_sdcard_mux),
 445         PIN_GROUP_SIMPLE("sdio_grp",
 446                          byt_score_sdio_pins, byt_score_sdio_mux),
 447         PIN_GROUP_SIMPLE("emmc_grp",
 448                          byt_score_emmc_pins, byt_score_emmc_mux),
 449         PIN_GROUP_SIMPLE("lpc_grp",
 450                          byt_score_ilb_lpc_pins, byt_score_lpc_mux),
 451         PIN_GROUP_SIMPLE("sata_grp",
 452                          byt_score_sata_pins, byt_score_sata_mux),
 453         PIN_GROUP_SIMPLE("plt_clk0_grp",
 454                          byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
 455         PIN_GROUP_SIMPLE("plt_clk1_grp",
 456                          byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
 457         PIN_GROUP_SIMPLE("plt_clk2_grp",
 458                          byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
 459         PIN_GROUP_SIMPLE("plt_clk3_grp",
 460                          byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
 461         PIN_GROUP_SIMPLE("plt_clk4_grp",
 462                          byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
 463         PIN_GROUP_SIMPLE("plt_clk5_grp",
 464                          byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
 465         PIN_GROUP_SIMPLE("smbus_grp",
 466                          byt_score_smbus_pins, byt_score_smbus_mux),
 467 };
 468
 469 static const char * const byt_score_uart_groups[] = {
 470         "uart1_grp", "uart2_grp",
 471 };
 472 static const char * const byt_score_pwm_groups[] = {
 473         "pwm0_grp", "pwm1_grp",
 474 };
 475 static const char * const byt_score_ssp_groups[] = {
 476         "ssp0_grp", "ssp1_grp", "ssp2_grp",
 477 };
 478 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
 479 static const char * const byt_score_i2c_groups[] = {
 480         "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
 481         "i2c6_grp",
 482 };
 483 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
 484 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
 485 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
 486 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
 487 static const char * const byt_score_sata_groups[] = { "sata_grp" };
 488 static const char * const byt_score_plt_clk_groups[] = {
 489         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 490         "plt_clk4_grp", "plt_clk5_grp",
 491 };
 492 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
 493 static const char * const byt_score_gpio_groups[] = {
 494         "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
 495         "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
 496         "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
 497         "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
 498         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 499         "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
 500
 501 };
 502
 503 static const struct byt_function byt_score_functions[] = {
 504         FUNCTION("uart", byt_score_uart_groups),
 505         FUNCTION("pwm", byt_score_pwm_groups),
 506         FUNCTION("ssp", byt_score_ssp_groups),
 507         FUNCTION("spi", byt_score_spi_groups),
 508         FUNCTION("i2c", byt_score_i2c_groups),
 509         FUNCTION("sdcard", byt_score_sdcard_groups),
 510         FUNCTION("sdio", byt_score_sdio_groups),
 511         FUNCTION("emmc", byt_score_emmc_groups),
 512         FUNCTION("lpc", byt_score_lpc_groups),
 513         FUNCTION("sata", byt_score_sata_groups),
 514         FUNCTION("plt_clk", byt_score_plt_clk_groups),
 515         FUNCTION("smbus", byt_score_smbus_groups),
 516         FUNCTION("gpio", byt_score_gpio_groups),
 517 };
 518
 519 static const struct byt_community byt_score_communities[] = {
 520         COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
 521 };
 522
 523 static const struct byt_pinctrl_soc_data byt_score_soc_data = {
 524         .uid            = BYT_SCORE_ACPI_UID,
 525         .pins           = byt_score_pins,
 526         .npins          = ARRAY_SIZE(byt_score_pins),
 527         .groups         = byt_score_groups,
 528         .ngroups        = ARRAY_SIZE(byt_score_groups),
 529         .functions      = byt_score_functions,
 530         .nfunctions     = ARRAY_SIZE(byt_score_functions),
 531         .communities    = byt_score_communities,
 532         .ncommunities   = ARRAY_SIZE(byt_score_communities),
 533 };
 534
 535 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>]  */
 536 static const struct pinctrl_pin_desc byt_sus_pins[] = {
 537         PINCTRL_PIN(0, "GPIO_S50"),
 538         PINCTRL_PIN(1, "GPIO_S51"),
 539         PINCTRL_PIN(2, "GPIO_S52"),
 540         PINCTRL_PIN(3, "GPIO_S53"),
 541         PINCTRL_PIN(4, "GPIO_S54"),
 542         PINCTRL_PIN(5, "GPIO_S55"),
 543         PINCTRL_PIN(6, "GPIO_S56"),
 544         PINCTRL_PIN(7, "GPIO_S57"),
 545         PINCTRL_PIN(8, "GPIO_S58"),
 546         PINCTRL_PIN(9, "GPIO_S59"),
 547         PINCTRL_PIN(10, "GPIO_S510"),
 548         PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
 549         PINCTRL_PIN(12, "PMC_SUSCLK0"),
 550         PINCTRL_PIN(13, "GPIO_S513"),
 551         PINCTRL_PIN(14, "USB_ULPI_RST"),
 552         PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
 553         PINCTRL_PIN(16, "PMC_PWRBTN"),
 554         PINCTRL_PIN(17, "GPIO_S517"),
 555         PINCTRL_PIN(18, "PMC_SUS_STAT"),
 556         PINCTRL_PIN(19, "USB_OC0"),
 557         PINCTRL_PIN(20, "USB_OC1"),
 558         PINCTRL_PIN(21, "PCU_SPI_CS1"),
 559         PINCTRL_PIN(22, "GPIO_S522"),
 560         PINCTRL_PIN(23, "GPIO_S523"),
 561         PINCTRL_PIN(24, "GPIO_S524"),
 562         PINCTRL_PIN(25, "GPIO_S525"),
 563         PINCTRL_PIN(26, "GPIO_S526"),
 564         PINCTRL_PIN(27, "GPIO_S527"),
 565         PINCTRL_PIN(28, "GPIO_S528"),
 566         PINCTRL_PIN(29, "GPIO_S529"),
 567         PINCTRL_PIN(30, "GPIO_S530"),
 568         PINCTRL_PIN(31, "USB_ULPI_CLK"),
 569         PINCTRL_PIN(32, "USB_ULPI_DATA0"),
 570         PINCTRL_PIN(33, "USB_ULPI_DATA1"),
 571         PINCTRL_PIN(34, "USB_ULPI_DATA2"),
 572         PINCTRL_PIN(35, "USB_ULPI_DATA3"),
 573         PINCTRL_PIN(36, "USB_ULPI_DATA4"),
 574         PINCTRL_PIN(37, "USB_ULPI_DATA5"),
 575         PINCTRL_PIN(38, "USB_ULPI_DATA6"),
 576         PINCTRL_PIN(39, "USB_ULPI_DATA7"),
 577         PINCTRL_PIN(40, "USB_ULPI_DIR"),
 578         PINCTRL_PIN(41, "USB_ULPI_NXT"),
 579         PINCTRL_PIN(42, "USB_ULPI_STP"),
 580         PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
 581 };
 582
 583 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
 584         29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
 585         18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
 586         0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
 587         26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
 588         52, 53, 59, 40,
 589 };
 590
 591 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
 592 static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
 593         SIMPLE_FUNC("usb", 0),
 594         SIMPLE_FUNC("gpio", 1),
 595 };
 596
 597 static const unsigned int byt_sus_usb_ulpi_pins[] = {
 598         14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 599 };
 600 static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
 601         2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 602 };
 603 static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
 604         1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 605 };
 606 static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
 607         MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
 608         MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
 609 };
 610
 611 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
 612 static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
 613         SIMPLE_FUNC("spi", 0),
 614         SIMPLE_FUNC("gpio", 1),
 615 };
 616
 617 static const struct byt_pingroup byt_sus_groups[] = {
 618         PIN_GROUP_SIMPLE("usb_oc_grp",
 619                         byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
 620         PIN_GROUP_MIXED("usb_ulpi_grp",
 621                         byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
 622         PIN_GROUP_SIMPLE("pcu_spi_grp",
 623                         byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
 624 };
 625
 626 static const char * const byt_sus_usb_groups[] = {
 627         "usb_oc_grp", "usb_ulpi_grp",
 628 };
 629 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
 630 static const char * const byt_sus_gpio_groups[] = {
 631         "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
 632 };
 633
 634 static const struct byt_function byt_sus_functions[] = {
 635         FUNCTION("usb", byt_sus_usb_groups),
 636         FUNCTION("spi", byt_sus_spi_groups),
 637         FUNCTION("gpio", byt_sus_gpio_groups),
 638 };
 639
 640 static const struct byt_community byt_sus_communities[] = {
 641         COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
 642 };
 643
 644 static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
 645         .uid            = BYT_SUS_ACPI_UID,
 646         .pins           = byt_sus_pins,
 647         .npins          = ARRAY_SIZE(byt_sus_pins),
 648         .groups         = byt_sus_groups,
 649         .ngroups        = ARRAY_SIZE(byt_sus_groups),
 650         .functions      = byt_sus_functions,
 651         .nfunctions     = ARRAY_SIZE(byt_sus_functions),
 652         .communities    = byt_sus_communities,
 653         .ncommunities   = ARRAY_SIZE(byt_sus_communities),
 654 };
 655
 656 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
 657         PINCTRL_PIN(0, "GPIO_NCORE0"),
 658         PINCTRL_PIN(1, "GPIO_NCORE1"),
 659         PINCTRL_PIN(2, "GPIO_NCORE2"),
 660         PINCTRL_PIN(3, "GPIO_NCORE3"),
 661         PINCTRL_PIN(4, "GPIO_NCORE4"),
 662         PINCTRL_PIN(5, "GPIO_NCORE5"),
 663         PINCTRL_PIN(6, "GPIO_NCORE6"),
 664         PINCTRL_PIN(7, "GPIO_NCORE7"),
 665         PINCTRL_PIN(8, "GPIO_NCORE8"),
 666         PINCTRL_PIN(9, "GPIO_NCORE9"),
 667         PINCTRL_PIN(10, "GPIO_NCORE10"),
 668         PINCTRL_PIN(11, "GPIO_NCORE11"),
 669         PINCTRL_PIN(12, "GPIO_NCORE12"),
 670         PINCTRL_PIN(13, "GPIO_NCORE13"),
 671         PINCTRL_PIN(14, "GPIO_NCORE14"),
 672         PINCTRL_PIN(15, "GPIO_NCORE15"),
 673         PINCTRL_PIN(16, "GPIO_NCORE16"),
 674         PINCTRL_PIN(17, "GPIO_NCORE17"),
 675         PINCTRL_PIN(18, "GPIO_NCORE18"),
 676         PINCTRL_PIN(19, "GPIO_NCORE19"),
 677         PINCTRL_PIN(20, "GPIO_NCORE20"),
 678         PINCTRL_PIN(21, "GPIO_NCORE21"),
 679         PINCTRL_PIN(22, "GPIO_NCORE22"),
 680         PINCTRL_PIN(23, "GPIO_NCORE23"),
 681         PINCTRL_PIN(24, "GPIO_NCORE24"),
 682         PINCTRL_PIN(25, "GPIO_NCORE25"),
 683         PINCTRL_PIN(26, "GPIO_NCORE26"),
 684         PINCTRL_PIN(27, "GPIO_NCORE27"),
 685 };
 686
 687 static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
 688         19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
 689         14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
 690         3, 6, 10, 13, 2, 5, 9, 7,
 691 };
 692
 693 static const struct byt_community byt_ncore_communities[] = {
 694         COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
 695 };
 696
 697 static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
 698         .uid            = BYT_NCORE_ACPI_UID,
 699         .pins           = byt_ncore_pins,
 700         .npins          = ARRAY_SIZE(byt_ncore_pins),
 701         .communities    = byt_ncore_communities,
 702         .ncommunities   = ARRAY_SIZE(byt_ncore_communities),
 703 };
 704
 705 static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
 706         &byt_score_soc_data,
 707         &byt_sus_soc_data,
 708         &byt_ncore_soc_data,
 709         NULL,
 710 };
 711
 712 static struct byt_community *byt_get_community(struct byt_gpio *vg,
 713                                                unsigned int pin)
 714 {
 715         struct byt_community *comm;
 716         int i;
 717
 718         for (i = 0; i < vg->soc_data->ncommunities; i++) {
 719                 comm = vg->communities_copy + i;
 720                 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
 721                         return comm;
 722         }
 723
 724         return NULL;
 725 }
 726
 727 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
 728                                   int reg)
 729 {
 730         struct byt_community *comm = byt_get_community(vg, offset);
 731         u32 reg_offset = 0;
 732
 733         if (!comm)
 734                 return NULL;
 735
 736         offset -= comm->pin_base;
 737         if (reg == BYT_INT_STAT_REG)
 738                 reg_offset = (offset / 32) * 4;
 739         else
 740                 reg_offset = comm->pad_map[offset] * 16;
 741
 742         return comm->reg_base + reg_offset + reg;
 743 }
 744
 745 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
 746 {
 747         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 748
 749         return vg->soc_data->ngroups;
 750 }
 751
 752 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
 753                                       unsigned int selector)
 754 {
 755         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 756
 757         return vg->soc_data->groups[selector].name;
 758 }
 759
 760 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
 761                               unsigned int selector,
 762                               const unsigned int **pins,
 763                               unsigned int *num_pins)
 764 {
 765         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 766
 767         *pins           = vg->soc_data->groups[selector].pins;
 768         *num_pins       = vg->soc_data->groups[selector].npins;
 769
 770         return 0;
 771 }
 772
 773 static const struct pinctrl_ops byt_pinctrl_ops = {
 774         .get_groups_count       = byt_get_groups_count,
 775         .get_group_name         = byt_get_group_name,
 776         .get_group_pins         = byt_get_group_pins,
 777 };
 778
 779 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
 780 {
 781         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 782
 783         return vg->soc_data->nfunctions;
 784 }
 785
 786 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
 787                                          unsigned int selector)
 788 {
 789         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 790
 791         return vg->soc_data->functions[selector].name;
 792 }
 793
 794 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
 795                                    unsigned int selector,
 796                                    const char * const **groups,
 797                                    unsigned int *num_groups)
 798 {
 799         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 800
 801         *groups         = vg->soc_data->functions[selector].groups;
 802         *num_groups     = vg->soc_data->functions[selector].ngroups;
 803
 804         return 0;
 805 }
 806
 807 static int byt_get_group_simple_mux(const struct byt_pingroup group,
 808                                     const char *func_name,
 809                                     unsigned short *func)
 810 {
 811         int i;
 812
 813         for (i = 0; i < group.nfuncs; i++) {
 814                 if (!strcmp(group.simple_funcs[i].name, func_name)) {
 815                         *func = group.simple_funcs[i].func;
 816                         return 0;
 817                 }
 818         }
 819
 820         return 1;
 821 }
 822
 823 static int byt_get_group_mixed_mux(const struct byt_pingroup group,
 824                                    const char *func_name,
 825                                    const unsigned short **func)
 826 {
 827         int i;
 828
 829         for (i = 0; i < group.nfuncs; i++) {
 830                 if (!strcmp(group.mixed_funcs[i].name, func_name)) {
 831                         *func = group.mixed_funcs[i].func_values;
 832                         return 0;
 833                 }
 834         }
 835
 836         return 1;
 837 }
 838
 839 static void byt_set_group_simple_mux(struct byt_gpio *vg,
 840                                      const struct byt_pingroup group,
 841                                      unsigned short func)
 842 {
 843         unsigned long flags;
 844         int i;
 845
 846         raw_spin_lock_irqsave(&vg->lock, flags);
 847
 848         for (i = 0; i < group.npins; i++) {
 849                 void __iomem *padcfg0;
 850                 u32 value;
 851
 852                 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
 853                 if (!padcfg0) {
 854                         dev_warn(&vg->pdev->dev,
 855                                  "Group %s, pin %i not muxed (no padcfg0)\n",
 856                                  group.name, i);
 857                         continue;
 858                 }
 859
 860                 value = readl(padcfg0);
 861                 value &= ~BYT_PIN_MUX;
 862                 value |= func;
 863                 writel(value, padcfg0);
 864         }
 865
 866         raw_spin_unlock_irqrestore(&vg->lock, flags);
 867 }
 868
 869 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
 870                                     const struct byt_pingroup group,
 871                                     const unsigned short *func)
 872 {
 873         unsigned long flags;
 874         int i;
 875
 876         raw_spin_lock_irqsave(&vg->lock, flags);
 877
 878         for (i = 0; i < group.npins; i++) {
 879                 void __iomem *padcfg0;
 880                 u32 value;
 881
 882                 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
 883                 if (!padcfg0) {
 884                         dev_warn(&vg->pdev->dev,
 885                                  "Group %s, pin %i not muxed (no padcfg0)\n",
 886                                  group.name, i);
 887                         continue;
 888                 }
 889
 890                 value = readl(padcfg0);
 891                 value &= ~BYT_PIN_MUX;
 892                 value |= func[i];
 893                 writel(value, padcfg0);
 894         }
 895
 896         raw_spin_unlock_irqrestore(&vg->lock, flags);
 897 }
 898
 899 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
 900                        unsigned int group_selector)
 901 {
 902         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 903         const struct byt_function func = vg->soc_data->functions[func_selector];
 904         const struct byt_pingroup group = vg->soc_data->groups[group_selector];
 905         const unsigned short *mixed_func;
 906         unsigned short simple_func;
 907         int ret = 1;
 908
 909         if (group.has_simple_funcs)
 910                 ret = byt_get_group_simple_mux(group, func.name, &simple_func);
 911         else
 912                 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
 913
 914         if (ret)
 915                 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
 916         else if (group.has_simple_funcs)
 917                 byt_set_group_simple_mux(vg, group, simple_func);
 918         else
 919                 byt_set_group_mixed_mux(vg, group, mixed_func);
 920
 921         return 0;
 922 }
 923
 924 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
 925 {
 926         /* SCORE pin 92-93 */
 927         if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
 928             offset >= 92 && offset <= 93)
 929                 return 1;
 930
 931         /* SUS pin 11-21 */
 932         if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
 933             offset >= 11 && offset <= 21)
 934                 return 1;
 935
 936         return 0;
 937 }
 938
 939 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
 940 {
 941         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 942         unsigned long flags;
 943         u32 value;
 944
 945         raw_spin_lock_irqsave(&vg->lock, flags);
 946         value = readl(reg);
 947         value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
 948         writel(value, reg);
 949         raw_spin_unlock_irqrestore(&vg->lock, flags);
 950 }
 951
 952 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
 953                                    struct pinctrl_gpio_range *range,
 954                                    unsigned int offset)
 955 {
 956         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
 957         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 958         u32 value, gpio_mux;
 959         unsigned long flags;
 960
 961         raw_spin_lock_irqsave(&vg->lock, flags);
 962
 963         /*
 964          * In most cases, func pin mux 000 means GPIO function.
 965          * But, some pins may have func pin mux 001 represents
 966          * GPIO function.
 967          *
 968          * Because there are devices out there where some pins were not
 969          * configured correctly we allow changing the mux value from
 970          * request (but print out warning about that).
 971          */
 972         value = readl(reg) & BYT_PIN_MUX;
 973         gpio_mux = byt_get_gpio_mux(vg, offset);
 974         if (WARN_ON(gpio_mux != value)) {
 975                 value = readl(reg) & ~BYT_PIN_MUX;
 976                 value |= gpio_mux;
 977                 writel(value, reg);
 978
 979                 dev_warn(&vg->pdev->dev,
 980                          "pin %u forcibly re-configured as GPIO\n", offset);
 981         }
 982
 983         raw_spin_unlock_irqrestore(&vg->lock, flags);
 984
 985         pm_runtime_get(&vg->pdev->dev);
 986
 987         return 0;
 988 }
 989
 990 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
 991                                   struct pinctrl_gpio_range *range,
 992                                   unsigned int offset)
 993 {
 994         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
 995
 996         byt_gpio_clear_triggering(vg, offset);
 997         pm_runtime_put(&vg->pdev->dev);
 998 }
 999
1000 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
1001                                   struct pinctrl_gpio_range *range,
1002                                   unsigned int offset,
1003                                   bool input)
1004 {
1005         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1006         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1007         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1008         unsigned long flags;
1009         u32 value;
1010
1011         raw_spin_lock_irqsave(&vg->lock, flags);
1012
1013         value = readl(val_reg);
1014         value &= ~BYT_DIR_MASK;
1015         if (input)
1016                 value |= BYT_OUTPUT_EN;
1017         else
1018                 /*
1019                  * Before making any direction modifications, do a check if gpio
1020                  * is set for direct IRQ.  On baytrail, setting GPIO to output
1021                  * does not make sense, so let's at least warn the caller before
1022                  * they shoot themselves in the foot.
1023                  */
1024                 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
1025                      "Potential Error: Setting GPIO with direct_irq_en to output");
1026         writel(value, val_reg);
1027
1028         raw_spin_unlock_irqrestore(&vg->lock, flags);
1029
1030         return 0;
1031 }
1032
1033 static const struct pinmux_ops byt_pinmux_ops = {
1034         .get_functions_count    = byt_get_functions_count,
1035         .get_function_name      = byt_get_function_name,
1036         .get_function_groups    = byt_get_function_groups,
1037         .set_mux                = byt_set_mux,
1038         .gpio_request_enable    = byt_gpio_request_enable,
1039         .gpio_disable_free      = byt_gpio_disable_free,
1040         .gpio_set_direction     = byt_gpio_set_direction,
1041 };
1042
1043 static void byt_get_pull_strength(u32 reg, u16 *strength)
1044 {
1045         switch (reg & BYT_PULL_STR_MASK) {
1046         case BYT_PULL_STR_2K:
1047                 *strength = 2000;
1048                 break;
1049         case BYT_PULL_STR_10K:
1050                 *strength = 10000;
1051                 break;
1052         case BYT_PULL_STR_20K:
1053                 *strength = 20000;
1054                 break;
1055         case BYT_PULL_STR_40K:
1056                 *strength = 40000;
1057                 break;
1058         }
1059 }
1060
1061 static int byt_set_pull_strength(u32 *reg, u16 strength)
1062 {
1063         *reg &= ~BYT_PULL_STR_MASK;
1064
1065         switch (strength) {
1066         case 2000:
1067                 *reg |= BYT_PULL_STR_2K;
1068                 break;
1069         case 10000:
1070                 *reg |= BYT_PULL_STR_10K;
1071                 break;
1072         case 20000:
1073                 *reg |= BYT_PULL_STR_20K;
1074                 break;
1075         case 40000:
1076                 *reg |= BYT_PULL_STR_40K;
1077                 break;
1078         default:
1079                 return -EINVAL;
1080         }
1081
1082         return 0;
1083 }
1084
1085 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
1086                               unsigned long *config)
1087 {
1088         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1089         enum pin_config_param param = pinconf_to_config_param(*config);
1090         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1091         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1092         unsigned long flags;
1093         u32 conf, pull, val, debounce;
1094         u16 arg = 0;
1095
1096         raw_spin_lock_irqsave(&vg->lock, flags);
1097         conf = readl(conf_reg);
1098         pull = conf & BYT_PULL_ASSIGN_MASK;
1099         val = readl(val_reg);
1100         raw_spin_unlock_irqrestore(&vg->lock, flags);
1101
1102         switch (param) {
1103         case PIN_CONFIG_BIAS_DISABLE:
1104                 if (pull)
1105                         return -EINVAL;
1106                 break;
1107         case PIN_CONFIG_BIAS_PULL_DOWN:
1108                 /* Pull assignment is only applicable in input mode */
1109                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
1110                         return -EINVAL;
1111
1112                 byt_get_pull_strength(conf, &arg);
1113
1114                 break;
1115         case PIN_CONFIG_BIAS_PULL_UP:
1116                 /* Pull assignment is only applicable in input mode */
1117                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
1118                         return -EINVAL;
1119
1120                 byt_get_pull_strength(conf, &arg);
1121
1122                 break;
1123         case PIN_CONFIG_INPUT_DEBOUNCE:
1124                 if (!(conf & BYT_DEBOUNCE_EN))
1125                         return -EINVAL;
1126
1127                 raw_spin_lock_irqsave(&vg->lock, flags);
1128                 debounce = readl(byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG));
1129                 raw_spin_unlock_irqrestore(&vg->lock, flags);
1130
1131                 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
1132                 case BYT_DEBOUNCE_PULSE_375US:
1133                         arg = 375;
1134                         break;
1135                 case BYT_DEBOUNCE_PULSE_750US:
1136                         arg = 750;
1137                         break;
1138                 case BYT_DEBOUNCE_PULSE_1500US:
1139                         arg = 1500;
1140                         break;
1141                 case BYT_DEBOUNCE_PULSE_3MS:
1142                         arg = 3000;
1143                         break;
1144                 case BYT_DEBOUNCE_PULSE_6MS:
1145                         arg = 6000;
1146                         break;
1147                 case BYT_DEBOUNCE_PULSE_12MS:
1148                         arg = 12000;
1149                         break;
1150                 case BYT_DEBOUNCE_PULSE_24MS:
1151                         arg = 24000;
1152                         break;
1153                 default:
1154                         return -EINVAL;
1155                 }
1156
1157                 break;
1158         default:
1159                 return -ENOTSUPP;
1160         }
1161
1162         *config = pinconf_to_config_packed(param, arg);
1163
1164         return 0;
1165 }
1166
1167 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
1168                               unsigned int offset,
1169                               unsigned long *configs,
1170                               unsigned int num_configs)
1171 {
1172         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1173         unsigned int param, arg;
1174         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1175         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1176         unsigned long flags;
1177         u32 conf, val, debounce;
1178         int i, ret = 0;
1179
1180         raw_spin_lock_irqsave(&vg->lock, flags);
1181
1182         conf = readl(conf_reg);
1183         val = readl(val_reg);
1184
1185         for (i = 0; i < num_configs; i++) {
1186                 param = pinconf_to_config_param(configs[i]);
1187                 arg = pinconf_to_config_argument(configs[i]);
1188
1189                 switch (param) {
1190                 case PIN_CONFIG_BIAS_DISABLE:
1191                         conf &= ~BYT_PULL_ASSIGN_MASK;
1192                         break;
1193                 case PIN_CONFIG_BIAS_PULL_DOWN:
1194                         /* Set default strength value in case none is given */
1195                         if (arg == 1)
1196                                 arg = 2000;
1197
1198                         /*
1199                          * Pull assignment is only applicable in input mode. If
1200                          * chip is not in input mode, set it and warn about it.
1201                          */
1202                         if (val & BYT_INPUT_EN) {
1203                                 val &= ~BYT_INPUT_EN;
1204                                 writel(val, val_reg);
1205                                 dev_warn(&vg->pdev->dev,
1206                                          "pin %u forcibly set to input mode\n",
1207                                          offset);
1208                         }
1209
1210                         conf &= ~BYT_PULL_ASSIGN_MASK;
1211                         conf |= BYT_PULL_ASSIGN_DOWN;
1212                         ret = byt_set_pull_strength(&conf, arg);
1213
1214                         break;
1215                 case PIN_CONFIG_BIAS_PULL_UP:
1216                         /* Set default strength value in case none is given */
1217                         if (arg == 1)
1218                                 arg = 2000;
1219
1220                         /*
1221                          * Pull assignment is only applicable in input mode. If
1222                          * chip is not in input mode, set it and warn about it.
1223                          */
1224                         if (val & BYT_INPUT_EN) {
1225                                 val &= ~BYT_INPUT_EN;
1226                                 writel(val, val_reg);
1227                                 dev_warn(&vg->pdev->dev,
1228                                          "pin %u forcibly set to input mode\n",
1229                                          offset);
1230                         }
1231
1232                         conf &= ~BYT_PULL_ASSIGN_MASK;
1233                         conf |= BYT_PULL_ASSIGN_UP;
1234                         ret = byt_set_pull_strength(&conf, arg);
1235
1236                         break;
1237                 case PIN_CONFIG_INPUT_DEBOUNCE:
1238                         debounce = readl(byt_gpio_reg(vg, offset,
1239                                                       BYT_DEBOUNCE_REG));
1240                         conf &= ~BYT_DEBOUNCE_PULSE_MASK;
1241
1242                         switch (arg) {
1243                         case 375:
1244                                 conf |= BYT_DEBOUNCE_PULSE_375US;
1245                                 break;
1246                         case 750:
1247                                 conf |= BYT_DEBOUNCE_PULSE_750US;
1248                                 break;
1249                         case 1500:
1250                                 conf |= BYT_DEBOUNCE_PULSE_1500US;
1251                                 break;
1252                         case 3000:
1253                                 conf |= BYT_DEBOUNCE_PULSE_3MS;
1254                                 break;
1255                         case 6000:
1256                                 conf |= BYT_DEBOUNCE_PULSE_6MS;
1257                                 break;
1258                         case 12000:
1259                                 conf |= BYT_DEBOUNCE_PULSE_12MS;
1260                                 break;
1261                         case 24000:
1262                                 conf |= BYT_DEBOUNCE_PULSE_24MS;
1263                                 break;
1264                         default:
1265                                 ret = -EINVAL;
1266                         }
1267
1268                         break;
1269                 default:
1270                         ret = -ENOTSUPP;
1271                 }
1272
1273                 if (ret)
1274                         break;
1275         }
1276
1277         if (!ret)
1278                 writel(conf, conf_reg);
1279
1280         raw_spin_unlock_irqrestore(&vg->lock, flags);
1281
1282         return ret;
1283 }
1284
1285 static const struct pinconf_ops byt_pinconf_ops = {
1286         .is_generic     = true,
1287         .pin_config_get = byt_pin_config_get,
1288         .pin_config_set = byt_pin_config_set,
1289 };
1290
1291 static const struct pinctrl_desc byt_pinctrl_desc = {
1292         .pctlops        = &byt_pinctrl_ops,
1293         .pmxops         = &byt_pinmux_ops,
1294         .confops        = &byt_pinconf_ops,
1295         .owner          = THIS_MODULE,
1296 };
1297
1298 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
1299 {
1300         struct byt_gpio *vg = gpiochip_get_data(chip);
1301         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1302         unsigned long flags;
1303         u32 val;
1304
1305         raw_spin_lock_irqsave(&vg->lock, flags);
1306         val = readl(reg);
1307         raw_spin_unlock_irqrestore(&vg->lock, flags);
1308
1309         return !!(val & BYT_LEVEL);
1310 }
1311
1312 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1313 {
1314         struct byt_gpio *vg = gpiochip_get_data(chip);
1315         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1316         unsigned long flags;
1317         u32 old_val;
1318
1319         if (!reg)
1320                 return;
1321
1322         raw_spin_lock_irqsave(&vg->lock, flags);
1323         old_val = readl(reg);
1324         if (value)
1325                 writel(old_val | BYT_LEVEL, reg);
1326         else
1327                 writel(old_val & ~BYT_LEVEL, reg);
1328         raw_spin_unlock_irqrestore(&vg->lock, flags);
1329 }
1330
1331 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1332 {
1333         struct byt_gpio *vg = gpiochip_get_data(chip);
1334         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1335         unsigned long flags;
1336         u32 value;
1337
1338         if (!reg)
1339                 return -EINVAL;
1340
1341         raw_spin_lock_irqsave(&vg->lock, flags);
1342         value = readl(reg);
1343         raw_spin_unlock_irqrestore(&vg->lock, flags);
1344
1345         if (!(value & BYT_OUTPUT_EN))
1346                 return GPIOF_DIR_OUT;
1347         if (!(value & BYT_INPUT_EN))
1348                 return GPIOF_DIR_IN;
1349
1350         return -EINVAL;
1351 }
1352
1353 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1354 {
1355         return pinctrl_gpio_direction_input(chip->base + offset);
1356 }
1357
1358 static int byt_gpio_direction_output(struct gpio_chip *chip,
1359                                      unsigned int offset, int value)
1360 {
1361         int ret = pinctrl_gpio_direction_output(chip->base + offset);
1362
1363         if (ret)
1364                 return ret;
1365
1366         byt_gpio_set(chip, offset, value);
1367
1368         return 0;
1369 }
1370
1371 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1372 {
1373         struct byt_gpio *vg = gpiochip_get_data(chip);
1374         int i;
1375         u32 conf0, val;
1376
1377         for (i = 0; i < vg->soc_data->npins; i++) {
1378                 const struct byt_community *comm;
1379                 const char *pull_str = NULL;
1380                 const char *pull = NULL;
1381                 void __iomem *reg;
1382                 unsigned long flags;
1383                 const char *label;
1384                 unsigned int pin;
1385
1386                 raw_spin_lock_irqsave(&vg->lock, flags);
1387                 pin = vg->soc_data->pins[i].number;
1388                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1389                 if (!reg) {
1390                         seq_printf(s,
1391                                    "Could not retrieve pin %i conf0 reg\n",
1392                                    pin);
1393                         raw_spin_unlock_irqrestore(&vg->lock, flags);
1394                         continue;
1395                 }
1396                 conf0 = readl(reg);
1397
1398                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1399                 if (!reg) {
1400                         seq_printf(s,
1401                                    "Could not retrieve pin %i val reg\n", pin);
1402                         raw_spin_unlock_irqrestore(&vg->lock, flags);
1403                         continue;
1404                 }
1405                 val = readl(reg);
1406                 raw_spin_unlock_irqrestore(&vg->lock, flags);
1407
1408                 comm = byt_get_community(vg, pin);
1409                 if (!comm) {
1410                         seq_printf(s,
1411                                    "Could not get community for pin %i\n", pin);
1412                         continue;
1413                 }
1414                 label = gpiochip_is_requested(chip, i);
1415                 if (!label)
1416                         label = "Unrequested";
1417
1418                 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1419                 case BYT_PULL_ASSIGN_UP:
1420                         pull = "up";
1421                         break;
1422                 case BYT_PULL_ASSIGN_DOWN:
1423                         pull = "down";
1424                         break;
1425                 }
1426
1427                 switch (conf0 & BYT_PULL_STR_MASK) {
1428                 case BYT_PULL_STR_2K:
1429                         pull_str = "2k";
1430                         break;
1431                 case BYT_PULL_STR_10K:
1432                         pull_str = "10k";
1433                         break;
1434                 case BYT_PULL_STR_20K:
1435                         pull_str = "20k";
1436                         break;
1437                 case BYT_PULL_STR_40K:
1438                         pull_str = "40k";
1439                         break;
1440                 }
1441
1442                 seq_printf(s,
1443                            " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1444                            pin,
1445                            label,
1446                            val & BYT_INPUT_EN ? "  " : "in",
1447                            val & BYT_OUTPUT_EN ? "   " : "out",
1448                            val & BYT_LEVEL ? "hi" : "lo",
1449                            comm->pad_map[i], comm->pad_map[i] * 32,
1450                            conf0 & 0x7,
1451                            conf0 & BYT_TRIG_NEG ? " fall" : "     ",
1452                            conf0 & BYT_TRIG_POS ? " rise" : "     ",
1453                            conf0 & BYT_TRIG_LVL ? " level" : "      ");
1454
1455                 if (pull && pull_str)
1456                         seq_printf(s, " %-4s %-3s", pull, pull_str);
1457                 else
1458                         seq_puts(s, "          ");
1459
1460                 if (conf0 & BYT_IODEN)
1461                         seq_puts(s, " open-drain");
1462
1463                 seq_puts(s, "\n");
1464         }
1465 }
1466
1467 static const struct gpio_chip byt_gpio_chip = {
1468         .owner                  = THIS_MODULE,
1469         .request                = gpiochip_generic_request,
1470         .free                   = gpiochip_generic_free,
1471         .get_direction          = byt_gpio_get_direction,
1472         .direction_input        = byt_gpio_direction_input,
1473         .direction_output       = byt_gpio_direction_output,
1474         .get                    = byt_gpio_get,
1475         .set                    = byt_gpio_set,
1476         .dbg_show               = byt_gpio_dbg_show,
1477 };
1478
1479 static void byt_irq_ack(struct irq_data *d)
1480 {
1481         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1482         struct byt_gpio *vg = gpiochip_get_data(gc);
1483         unsigned offset = irqd_to_hwirq(d);
1484         void __iomem *reg;
1485
1486         reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1487         if (!reg)
1488                 return;
1489
1490         raw_spin_lock(&vg->lock);
1491         writel(BIT(offset % 32), reg);
1492         raw_spin_unlock(&vg->lock);
1493 }
1494
1495 static void byt_irq_mask(struct irq_data *d)
1496 {
1497         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1498         struct byt_gpio *vg = gpiochip_get_data(gc);
1499
1500         byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1501 }
1502
1503 static void byt_irq_unmask(struct irq_data *d)
1504 {
1505         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1506         struct byt_gpio *vg = gpiochip_get_data(gc);
1507         unsigned offset = irqd_to_hwirq(d);
1508         unsigned long flags;
1509         void __iomem *reg;
1510         u32 value;
1511
1512         reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1513         if (!reg)
1514                 return;
1515
1516         raw_spin_lock_irqsave(&vg->lock, flags);
1517         value = readl(reg);
1518
1519         switch (irqd_get_trigger_type(d)) {
1520         case IRQ_TYPE_LEVEL_HIGH:
1521                 value |= BYT_TRIG_LVL;
1522         case IRQ_TYPE_EDGE_RISING:
1523                 value |= BYT_TRIG_POS;
1524                 break;
1525         case IRQ_TYPE_LEVEL_LOW:
1526                 value |= BYT_TRIG_LVL;
1527         case IRQ_TYPE_EDGE_FALLING:
1528                 value |= BYT_TRIG_NEG;
1529                 break;
1530         case IRQ_TYPE_EDGE_BOTH:
1531                 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1532                 break;
1533         }
1534
1535         writel(value, reg);
1536
1537         raw_spin_unlock_irqrestore(&vg->lock, flags);
1538 }
1539
1540 static int byt_irq_type(struct irq_data *d, unsigned int type)
1541 {
1542         struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1543         u32 offset = irqd_to_hwirq(d);
1544         u32 value;
1545         unsigned long flags;
1546         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1547
1548         if (!reg || offset >= vg->chip.ngpio)
1549                 return -EINVAL;
1550
1551         raw_spin_lock_irqsave(&vg->lock, flags);
1552         value = readl(reg);
1553
1554         WARN(value & BYT_DIRECT_IRQ_EN,
1555              "Bad pad config for io mode, force direct_irq_en bit clearing");
1556
1557         /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1558          * are used to indicate high and low level triggering
1559          */
1560         value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1561                    BYT_TRIG_LVL);
1562
1563         writel(value, reg);
1564
1565         if (type & IRQ_TYPE_EDGE_BOTH)
1566                 irq_set_handler_locked(d, handle_edge_irq);
1567         else if (type & IRQ_TYPE_LEVEL_MASK)
1568                 irq_set_handler_locked(d, handle_level_irq);
1569
1570         raw_spin_unlock_irqrestore(&vg->lock, flags);
1571
1572         return 0;
1573 }
1574
1575 static struct irq_chip byt_irqchip = {
1576         .name           = "BYT-GPIO",
1577         .irq_ack        = byt_irq_ack,
1578         .irq_mask       = byt_irq_mask,
1579         .irq_unmask     = byt_irq_unmask,
1580         .irq_set_type   = byt_irq_type,
1581         .flags          = IRQCHIP_SKIP_SET_WAKE,
1582 };
1583
1584 static void byt_gpio_irq_handler(struct irq_desc *desc)
1585 {
1586         struct irq_data *data = irq_desc_get_irq_data(desc);
1587         struct byt_gpio *vg = gpiochip_get_data(
1588                                 irq_desc_get_handler_data(desc));
1589         struct irq_chip *chip = irq_data_get_irq_chip(data);
1590         u32 base, pin;
1591         void __iomem *reg;
1592         unsigned long pending;
1593         unsigned int virq;
1594
1595         /* check from GPIO controller which pin triggered the interrupt */
1596         for (base = 0; base < vg->chip.ngpio; base += 32) {
1597                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1598
1599                 if (!reg) {
1600                         dev_warn(&vg->pdev->dev,
1601                                  "Pin %i: could not retrieve interrupt status register\n",
1602                                  base);
1603                         continue;
1604                 }
1605
1606                 pending = readl(reg);
1607                 for_each_set_bit(pin, &pending, 32) {
1608                         virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
1609                         generic_handle_irq(virq);
1610                 }
1611         }
1612         chip->irq_eoi(data);
1613 }
1614
1615 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1616 {
1617         void __iomem *reg;
1618         u32 base, value;
1619         int i;
1620
1621         /*
1622          * Clear interrupt triggers for all pins that are GPIOs and
1623          * do not use direct IRQ mode. This will prevent spurious
1624          * interrupts from misconfigured pins.
1625          */
1626         for (i = 0; i < vg->soc_data->npins; i++) {
1627                 unsigned int pin = vg->soc_data->pins[i].number;
1628
1629                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1630                 if (!reg) {
1631                         dev_warn(&vg->pdev->dev,
1632                                  "Pin %i: could not retrieve conf0 register\n",
1633                                  i);
1634                         continue;
1635                 }
1636
1637                 value = readl(reg);
1638                 if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
1639                     !(value & BYT_DIRECT_IRQ_EN)) {
1640                         byt_gpio_clear_triggering(vg, i);
1641                         dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
1642                 }
1643         }
1644
1645         /* clear interrupt status trigger registers */
1646         for (base = 0; base < vg->soc_data->npins; base += 32) {
1647                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1648
1649                 if (!reg) {
1650                         dev_warn(&vg->pdev->dev,
1651                                  "Pin %i: could not retrieve irq status reg\n",
1652                                  base);
1653                         continue;
1654                 }
1655
1656                 writel(0xffffffff, reg);
1657                 /* make sure trigger bits are cleared, if not then a pin
1658                    might be misconfigured in bios */
1659                 value = readl(reg);
1660                 if (value)
1661                         dev_err(&vg->pdev->dev,
1662                                 "GPIO interrupt error, pins misconfigured\n");
1663         }
1664 }
1665
1666 static int byt_gpio_probe(struct byt_gpio *vg)
1667 {
1668         struct gpio_chip *gc;
1669         struct resource *irq_rc;
1670         int ret;
1671
1672         /* Set up gpio chip */
1673         vg->chip        = byt_gpio_chip;
1674         gc              = &vg->chip;
1675         gc->label       = dev_name(&vg->pdev->dev);
1676         gc->base        = -1;
1677         gc->can_sleep   = false;
1678         gc->parent      = &vg->pdev->dev;
1679         gc->ngpio       = vg->soc_data->npins;
1680
1681 #ifdef CONFIG_PM_SLEEP
1682         vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1683                                        sizeof(*vg->saved_context), GFP_KERNEL);
1684 #endif
1685         ret = gpiochip_add_data(gc, vg);
1686         if (ret) {
1687                 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1688                 return ret;
1689         }
1690
1691         ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1692                                      0, 0, vg->soc_data->npins);
1693         if (ret) {
1694                 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1695                 goto fail;
1696         }
1697
1698         /* set up interrupts  */
1699         irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1700         if (irq_rc && irq_rc->start) {
1701                 byt_gpio_irq_init_hw(vg);
1702                 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1703                                            handle_simple_irq, IRQ_TYPE_NONE);
1704                 if (ret) {
1705                         dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1706                         goto fail;
1707                 }
1708
1709                 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1710                                              (unsigned)irq_rc->start,
1711                                              byt_gpio_irq_handler);
1712         }
1713
1714         return ret;
1715
1716 fail:
1717         gpiochip_remove(&vg->chip);
1718
1719         return ret;
1720 }
1721
1722 static int byt_set_soc_data(struct byt_gpio *vg,
1723                             const struct byt_pinctrl_soc_data *soc_data)
1724 {
1725         int i;
1726
1727         vg->soc_data = soc_data;
1728         vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1729                                             soc_data->ncommunities,
1730                                             sizeof(*vg->communities_copy),
1731                                             GFP_KERNEL);
1732         if (!vg->communities_copy)
1733                 return -ENOMEM;
1734
1735         for (i = 0; i < soc_data->ncommunities; i++) {
1736                 struct byt_community *comm = vg->communities_copy + i;
1737                 struct resource *mem_rc;
1738
1739                 *comm = vg->soc_data->communities[i];
1740
1741                 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
1742                 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
1743                 if (IS_ERR(comm->reg_base))
1744                         return PTR_ERR(comm->reg_base);
1745         }
1746
1747         return 0;
1748 }
1749
1750 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1751         { "INT33B2", (kernel_ulong_t)byt_soc_data },
1752         { "INT33FC", (kernel_ulong_t)byt_soc_data },
1753         { }
1754 };
1755 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
1756
1757 static int byt_pinctrl_probe(struct platform_device *pdev)
1758 {
1759         const struct byt_pinctrl_soc_data *soc_data = NULL;
1760         const struct byt_pinctrl_soc_data **soc_table;
1761         const struct acpi_device_id *acpi_id;
1762         struct acpi_device *acpi_dev;
1763         struct byt_gpio *vg;
1764         int i, ret;
1765
1766         acpi_dev = ACPI_COMPANION(&pdev->dev);
1767         if (!acpi_dev)
1768                 return -ENODEV;
1769
1770         acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
1771         if (!acpi_id)
1772                 return -ENODEV;
1773
1774         soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
1775
1776         for (i = 0; soc_table[i]; i++) {
1777                 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1778                         soc_data = soc_table[i];
1779                         break;
1780                 }
1781         }
1782
1783         if (!soc_data)
1784                 return -ENODEV;
1785
1786         vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1787         if (!vg)
1788                 return -ENOMEM;
1789
1790         vg->pdev = pdev;
1791         ret = byt_set_soc_data(vg, soc_data);
1792         if (ret) {
1793                 dev_err(&pdev->dev, "failed to set soc data\n");
1794                 return ret;
1795         }
1796
1797         vg->pctl_desc           = byt_pinctrl_desc;
1798         vg->pctl_desc.name      = dev_name(&pdev->dev);
1799         vg->pctl_desc.pins      = vg->soc_data->pins;
1800         vg->pctl_desc.npins     = vg->soc_data->npins;
1801
1802         vg->pctl_dev = pinctrl_register(&vg->pctl_desc, &pdev->dev, vg);
1803         if (IS_ERR(vg->pctl_dev)) {
1804                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1805                 return PTR_ERR(vg->pctl_dev);
1806         }
1807
1808         ret = byt_gpio_probe(vg);
1809         if (ret) {
1810                 pinctrl_unregister(vg->pctl_dev);
1811                 return ret;
1812         }
1813
1814         platform_set_drvdata(pdev, vg);
1815         raw_spin_lock_init(&vg->lock);
1816         pm_runtime_enable(&pdev->dev);
1817
1818         return 0;
1819 }
1820
1821 static int byt_pinctrl_remove(struct platform_device *pdev)
1822 {
1823         struct byt_gpio *vg = platform_get_drvdata(pdev);
1824
1825         pm_runtime_disable(&pdev->dev);
1826         gpiochip_remove(&vg->chip);
1827         pinctrl_unregister(vg->pctl_dev);
1828
1829         return 0;
1830 }
1831
1832 #ifdef CONFIG_PM_SLEEP
1833 static int byt_gpio_suspend(struct device *dev)
1834 {
1835         struct platform_device *pdev = to_platform_device(dev);
1836         struct byt_gpio *vg = platform_get_drvdata(pdev);
1837         int i;
1838
1839         for (i = 0; i < vg->soc_data->npins; i++) {
1840                 void __iomem *reg;
1841                 u32 value;
1842                 unsigned int pin = vg->soc_data->pins[i].number;
1843
1844                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1845                 if (!reg) {
1846                         dev_warn(&vg->pdev->dev,
1847                                  "Pin %i: could not retrieve conf0 register\n",
1848                                  i);
1849                         continue;
1850                 }
1851                 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1852                 vg->saved_context[i].conf0 = value;
1853
1854                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1855                 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1856                 vg->saved_context[i].val = value;
1857         }
1858
1859         return 0;
1860 }
1861
1862 static int byt_gpio_resume(struct device *dev)
1863 {
1864         struct platform_device *pdev = to_platform_device(dev);
1865         struct byt_gpio *vg = platform_get_drvdata(pdev);
1866         int i;
1867
1868         for (i = 0; i < vg->soc_data->npins; i++) {
1869                 void __iomem *reg;
1870                 u32 value;
1871                 unsigned int pin = vg->soc_data->pins[i].number;
1872
1873                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1874                 if (!reg) {
1875                         dev_warn(&vg->pdev->dev,
1876                                  "Pin %i: could not retrieve conf0 register\n",
1877                                  i);
1878                         continue;
1879                 }
1880                 value = readl(reg);
1881                 if ((value & BYT_CONF0_RESTORE_MASK) !=
1882                      vg->saved_context[i].conf0) {
1883                         value &= ~BYT_CONF0_RESTORE_MASK;
1884                         value |= vg->saved_context[i].conf0;
1885                         writel(value, reg);
1886                         dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1887                 }
1888
1889                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1890                 value = readl(reg);
1891                 if ((value & BYT_VAL_RESTORE_MASK) !=
1892                      vg->saved_context[i].val) {
1893                         u32 v;
1894
1895                         v = value & ~BYT_VAL_RESTORE_MASK;
1896                         v |= vg->saved_context[i].val;
1897                         if (v != value) {
1898                                 writel(v, reg);
1899                                 dev_dbg(dev, "restored pin %d val %#08x\n",
1900                                         i, v);
1901                         }
1902                 }
1903         }
1904
1905         return 0;
1906 }
1907 #endif
1908
1909 #ifdef CONFIG_PM
1910 static int byt_gpio_runtime_suspend(struct device *dev)
1911 {
1912         return 0;
1913 }
1914
1915 static int byt_gpio_runtime_resume(struct device *dev)
1916 {
1917         return 0;
1918 }
1919 #endif
1920
1921 static const struct dev_pm_ops byt_gpio_pm_ops = {
1922         SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1923         SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1924                            NULL)
1925 };
1926
1927 static struct platform_driver byt_gpio_driver = {
1928         .probe          = byt_pinctrl_probe,
1929         .remove         = byt_pinctrl_remove,
1930         .driver         = {
1931                 .name   = "byt_gpio",
1932                 .pm     = &byt_gpio_pm_ops,
1933                 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1934         },
1935 };
1936
1937 static int __init byt_gpio_init(void)
1938 {
1939         return platform_driver_register(&byt_gpio_driver);
1940 }
1941 subsys_initcall(byt_gpio_init);
1942
1943 static void __exit byt_gpio_exit(void)
1944 {
1945         platform_driver_unregister(&byt_gpio_driver);
1946 }
1947 module_exit(byt_gpio_exit);