2 * Intel pinctrl/GPIO core driver.
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/platform_device.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinconf-generic.h>
22 #include "pinctrl-intel.h"
24 /* Offset from regs */
27 #define GPI_GPE_STS 0x140
28 #define GPI_GPE_EN 0x160
31 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
32 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
33 #define PADOWN_GPP(p) ((p) / 8)
35 /* Offset from pad_regs */
37 #define PADCFG0_RXEVCFG_SHIFT 25
38 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
39 #define PADCFG0_RXEVCFG_LEVEL 0
40 #define PADCFG0_RXEVCFG_EDGE 1
41 #define PADCFG0_RXEVCFG_DISABLED 2
42 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
43 #define PADCFG0_RXINV BIT(23)
44 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
45 #define PADCFG0_GPIROUTSCI BIT(19)
46 #define PADCFG0_GPIROUTSMI BIT(18)
47 #define PADCFG0_GPIROUTNMI BIT(17)
48 #define PADCFG0_PMODE_SHIFT 10
49 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
50 #define PADCFG0_GPIORXDIS BIT(9)
51 #define PADCFG0_GPIOTXDIS BIT(8)
52 #define PADCFG0_GPIORXSTATE BIT(1)
53 #define PADCFG0_GPIOTXSTATE BIT(0)
56 #define PADCFG1_TERM_UP BIT(13)
57 #define PADCFG1_TERM_SHIFT 10
58 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
59 #define PADCFG1_TERM_20K 4
60 #define PADCFG1_TERM_2K 3
61 #define PADCFG1_TERM_5K 2
62 #define PADCFG1_TERM_1K 1
64 struct intel_pad_context {
69 struct intel_community_context {
73 struct intel_pinctrl_context {
74 struct intel_pad_context *pads;
75 struct intel_community_context *communities;
79 * struct intel_pinctrl - Intel pinctrl private structure
80 * @dev: Pointer to the device structure
81 * @lock: Lock to serialize register access
82 * @pctldesc: Pin controller description
83 * @pctldev: Pointer to the pin controller device
84 * @chip: GPIO chip in this pin controller
85 * @soc: SoC/PCH specific pin configuration data
86 * @communities: All communities in this pin controller
87 * @ncommunities: Number of communities in this pin controller
88 * @context: Configuration saved over system sleep
89 * @irq: pinctrl/GPIO chip irq number
91 struct intel_pinctrl {
94 struct pinctrl_desc pctldesc;
95 struct pinctrl_dev *pctldev;
96 struct gpio_chip chip;
97 const struct intel_pinctrl_soc_data *soc;
98 struct intel_community *communities;
100 struct intel_pinctrl_context context;
104 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
106 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
109 struct intel_community *community;
112 for (i = 0; i < pctrl->ncommunities; i++) {
113 community = &pctrl->communities[i];
114 if (pin >= community->pin_base &&
115 pin < community->pin_base + community->npins)
119 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
123 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
126 const struct intel_community *community;
129 community = intel_get_community(pctrl, pin);
133 padno = pin_to_padno(community, pin);
134 return community->pad_regs + reg + padno * 8;
137 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
139 const struct intel_community *community;
140 unsigned padno, gpp, offset, group;
141 void __iomem *padown;
143 community = intel_get_community(pctrl, pin);
146 if (!community->padown_offset)
149 padno = pin_to_padno(community, pin);
150 group = padno / community->gpp_size;
151 gpp = PADOWN_GPP(padno % community->gpp_size);
152 offset = community->padown_offset + 0x10 * group + gpp * 4;
153 padown = community->regs + offset;
155 return !(readl(padown) & PADOWN_MASK(padno));
158 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
160 const struct intel_community *community;
161 unsigned padno, gpp, offset;
162 void __iomem *hostown;
164 community = intel_get_community(pctrl, pin);
167 if (!community->hostown_offset)
170 padno = pin_to_padno(community, pin);
171 gpp = padno / community->gpp_size;
172 offset = community->hostown_offset + gpp * 4;
173 hostown = community->regs + offset;
175 return !(readl(hostown) & BIT(padno % community->gpp_size));
178 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
180 struct intel_community *community;
181 unsigned padno, gpp, offset;
184 community = intel_get_community(pctrl, pin);
187 if (!community->padcfglock_offset)
190 padno = pin_to_padno(community, pin);
191 gpp = padno / community->gpp_size;
194 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
195 * the pad is considered unlocked. Any other case means that it is
196 * either fully or partially locked and we don't touch it.
198 offset = community->padcfglock_offset + gpp * 8;
199 value = readl(community->regs + offset);
200 if (value & BIT(pin % community->gpp_size))
203 offset = community->padcfglock_offset + 4 + gpp * 8;
204 value = readl(community->regs + offset);
205 if (value & BIT(pin % community->gpp_size))
211 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
213 return intel_pad_owned_by_host(pctrl, pin) &&
214 !intel_pad_locked(pctrl, pin);
217 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
219 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
221 return pctrl->soc->ngroups;
224 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
227 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
229 return pctrl->soc->groups[group].name;
232 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
233 const unsigned **pins, unsigned *npins)
235 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
237 *pins = pctrl->soc->groups[group].pins;
238 *npins = pctrl->soc->groups[group].npins;
242 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
245 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
246 u32 cfg0, cfg1, mode;
249 if (!intel_pad_owned_by_host(pctrl, pin)) {
250 seq_puts(s, "not available");
254 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
255 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
257 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
259 seq_puts(s, "GPIO ");
261 seq_printf(s, "mode %d ", mode);
263 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
265 locked = intel_pad_locked(pctrl, pin);
266 acpi = intel_pad_acpi_mode(pctrl, pin);
268 if (locked || acpi) {
271 seq_puts(s, "LOCKED");
281 static const struct pinctrl_ops intel_pinctrl_ops = {
282 .get_groups_count = intel_get_groups_count,
283 .get_group_name = intel_get_group_name,
284 .get_group_pins = intel_get_group_pins,
285 .pin_dbg_show = intel_pin_dbg_show,
288 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
290 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
292 return pctrl->soc->nfunctions;
295 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
298 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
300 return pctrl->soc->functions[function].name;
303 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
305 const char * const **groups,
306 unsigned * const ngroups)
308 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
310 *groups = pctrl->soc->functions[function].groups;
311 *ngroups = pctrl->soc->functions[function].ngroups;
315 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
318 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
319 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
323 raw_spin_lock_irqsave(&pctrl->lock, flags);
326 * All pins in the groups needs to be accessible and writable
327 * before we can enable the mux for this group.
329 for (i = 0; i < grp->npins; i++) {
330 if (!intel_pad_usable(pctrl, grp->pins[i])) {
331 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
336 /* Now enable the mux setting for each pin in the group */
337 for (i = 0; i < grp->npins; i++) {
338 void __iomem *padcfg0;
341 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
342 value = readl(padcfg0);
344 value &= ~PADCFG0_PMODE_MASK;
345 value |= grp->mode << PADCFG0_PMODE_SHIFT;
347 writel(value, padcfg0);
350 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
355 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
356 struct pinctrl_gpio_range *range,
359 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
360 void __iomem *padcfg0;
364 raw_spin_lock_irqsave(&pctrl->lock, flags);
366 if (!intel_pad_usable(pctrl, pin)) {
367 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
371 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
372 /* Put the pad into GPIO mode */
373 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
374 /* Disable SCI/SMI/NMI generation */
375 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
376 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
377 /* Disable TX buffer and enable RX (this will be input) */
378 value &= ~PADCFG0_GPIORXDIS;
379 value |= PADCFG0_GPIOTXDIS;
380 writel(value, padcfg0);
382 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
387 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
388 struct pinctrl_gpio_range *range,
389 unsigned pin, bool input)
391 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
392 void __iomem *padcfg0;
396 raw_spin_lock_irqsave(&pctrl->lock, flags);
398 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
400 value = readl(padcfg0);
402 value |= PADCFG0_GPIOTXDIS;
404 value &= ~PADCFG0_GPIOTXDIS;
405 writel(value, padcfg0);
407 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
412 static const struct pinmux_ops intel_pinmux_ops = {
413 .get_functions_count = intel_get_functions_count,
414 .get_function_name = intel_get_function_name,
415 .get_function_groups = intel_get_function_groups,
416 .set_mux = intel_pinmux_set_mux,
417 .gpio_request_enable = intel_gpio_request_enable,
418 .gpio_set_direction = intel_gpio_set_direction,
421 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
422 unsigned long *config)
424 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
425 enum pin_config_param param = pinconf_to_config_param(*config);
429 if (!intel_pad_owned_by_host(pctrl, pin))
432 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
433 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
436 case PIN_CONFIG_BIAS_DISABLE:
441 case PIN_CONFIG_BIAS_PULL_UP:
442 if (!term || !(value & PADCFG1_TERM_UP))
446 case PADCFG1_TERM_1K:
449 case PADCFG1_TERM_2K:
452 case PADCFG1_TERM_5K:
455 case PADCFG1_TERM_20K:
462 case PIN_CONFIG_BIAS_PULL_DOWN:
463 if (!term || value & PADCFG1_TERM_UP)
467 case PADCFG1_TERM_5K:
470 case PADCFG1_TERM_20K:
481 *config = pinconf_to_config_packed(param, arg);
485 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
486 unsigned long config)
488 unsigned param = pinconf_to_config_param(config);
489 unsigned arg = pinconf_to_config_argument(config);
490 void __iomem *padcfg1;
495 raw_spin_lock_irqsave(&pctrl->lock, flags);
497 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
498 value = readl(padcfg1);
501 case PIN_CONFIG_BIAS_DISABLE:
502 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
505 case PIN_CONFIG_BIAS_PULL_UP:
506 value &= ~PADCFG1_TERM_MASK;
508 value |= PADCFG1_TERM_UP;
512 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
515 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
518 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
521 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
529 case PIN_CONFIG_BIAS_PULL_DOWN:
530 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
534 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
537 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
547 writel(value, padcfg1);
549 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
554 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
555 unsigned long *configs, unsigned nconfigs)
557 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
560 if (!intel_pad_usable(pctrl, pin))
563 for (i = 0; i < nconfigs; i++) {
564 switch (pinconf_to_config_param(configs[i])) {
565 case PIN_CONFIG_BIAS_DISABLE:
566 case PIN_CONFIG_BIAS_PULL_UP:
567 case PIN_CONFIG_BIAS_PULL_DOWN:
568 ret = intel_config_set_pull(pctrl, pin, configs[i]);
581 static const struct pinconf_ops intel_pinconf_ops = {
583 .pin_config_get = intel_config_get,
584 .pin_config_set = intel_config_set,
587 static const struct pinctrl_desc intel_pinctrl_desc = {
588 .pctlops = &intel_pinctrl_ops,
589 .pmxops = &intel_pinmux_ops,
590 .confops = &intel_pinconf_ops,
591 .owner = THIS_MODULE,
594 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
596 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
599 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
603 return !!(readl(reg) & PADCFG0_GPIORXSTATE);
606 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
608 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
611 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
616 raw_spin_lock_irqsave(&pctrl->lock, flags);
617 padcfg0 = readl(reg);
619 padcfg0 |= PADCFG0_GPIOTXSTATE;
621 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
622 writel(padcfg0, reg);
623 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
627 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
629 return pinctrl_gpio_direction_input(chip->base + offset);
632 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
635 intel_gpio_set(chip, offset, value);
636 return pinctrl_gpio_direction_output(chip->base + offset);
639 static const struct gpio_chip intel_gpio_chip = {
640 .owner = THIS_MODULE,
641 .request = gpiochip_generic_request,
642 .free = gpiochip_generic_free,
643 .direction_input = intel_gpio_direction_input,
644 .direction_output = intel_gpio_direction_output,
645 .get = intel_gpio_get,
646 .set = intel_gpio_set,
649 static void intel_gpio_irq_ack(struct irq_data *d)
651 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
652 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
653 const struct intel_community *community;
654 unsigned pin = irqd_to_hwirq(d);
656 raw_spin_lock(&pctrl->lock);
658 community = intel_get_community(pctrl, pin);
660 unsigned padno = pin_to_padno(community, pin);
661 unsigned gpp_offset = padno % community->gpp_size;
662 unsigned gpp = padno / community->gpp_size;
664 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
667 raw_spin_unlock(&pctrl->lock);
670 static void intel_gpio_irq_enable(struct irq_data *d)
672 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
673 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
674 const struct intel_community *community;
675 unsigned pin = irqd_to_hwirq(d);
678 raw_spin_lock_irqsave(&pctrl->lock, flags);
680 community = intel_get_community(pctrl, pin);
682 unsigned padno = pin_to_padno(community, pin);
683 unsigned gpp_size = community->gpp_size;
684 unsigned gpp_offset = padno % gpp_size;
685 unsigned gpp = padno / gpp_size;
688 /* Clear interrupt status first to avoid unexpected interrupt */
689 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
691 value = readl(community->regs + community->ie_offset + gpp * 4);
692 value |= BIT(gpp_offset);
693 writel(value, community->regs + community->ie_offset + gpp * 4);
696 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
699 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
701 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
702 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
703 const struct intel_community *community;
704 unsigned pin = irqd_to_hwirq(d);
707 raw_spin_lock_irqsave(&pctrl->lock, flags);
709 community = intel_get_community(pctrl, pin);
711 unsigned padno = pin_to_padno(community, pin);
712 unsigned gpp_offset = padno % community->gpp_size;
713 unsigned gpp = padno / community->gpp_size;
717 reg = community->regs + community->ie_offset + gpp * 4;
720 value &= ~BIT(gpp_offset);
722 value |= BIT(gpp_offset);
726 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
729 static void intel_gpio_irq_mask(struct irq_data *d)
731 intel_gpio_irq_mask_unmask(d, true);
734 static void intel_gpio_irq_unmask(struct irq_data *d)
736 intel_gpio_irq_mask_unmask(d, false);
739 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
741 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
742 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
743 unsigned pin = irqd_to_hwirq(d);
748 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
753 * If the pin is in ACPI mode it is still usable as a GPIO but it
754 * cannot be used as IRQ because GPI_IS status bit will not be
755 * updated by the host controller hardware.
757 if (intel_pad_acpi_mode(pctrl, pin)) {
758 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
762 raw_spin_lock_irqsave(&pctrl->lock, flags);
766 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
768 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
769 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
770 } else if (type & IRQ_TYPE_EDGE_FALLING) {
771 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
772 value |= PADCFG0_RXINV;
773 } else if (type & IRQ_TYPE_EDGE_RISING) {
774 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
775 } else if (type & IRQ_TYPE_LEVEL_MASK) {
776 if (type & IRQ_TYPE_LEVEL_LOW)
777 value |= PADCFG0_RXINV;
779 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
784 if (type & IRQ_TYPE_EDGE_BOTH)
785 irq_set_handler_locked(d, handle_edge_irq);
786 else if (type & IRQ_TYPE_LEVEL_MASK)
787 irq_set_handler_locked(d, handle_level_irq);
789 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
794 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
796 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
797 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
798 unsigned pin = irqd_to_hwirq(d);
801 enable_irq_wake(pctrl->irq);
803 disable_irq_wake(pctrl->irq);
805 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
809 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
810 const struct intel_community *community)
812 struct gpio_chip *gc = &pctrl->chip;
813 irqreturn_t ret = IRQ_NONE;
816 for (gpp = 0; gpp < community->ngpps; gpp++) {
817 unsigned long pending, enabled, gpp_offset;
819 pending = readl(community->regs + GPI_IS + gpp * 4);
820 enabled = readl(community->regs + community->ie_offset +
823 /* Only interrupts that are enabled */
826 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
830 * The last group in community can have less pins
833 padno = gpp_offset + gpp * community->gpp_size;
834 if (padno >= community->npins)
837 irq = irq_find_mapping(gc->irqdomain,
838 community->pin_base + padno);
839 generic_handle_irq(irq);
848 static irqreturn_t intel_gpio_irq(int irq, void *data)
850 const struct intel_community *community;
851 struct intel_pinctrl *pctrl = data;
852 irqreturn_t ret = IRQ_NONE;
855 /* Need to check all communities for pending interrupts */
856 for (i = 0; i < pctrl->ncommunities; i++) {
857 community = &pctrl->communities[i];
858 ret |= intel_gpio_community_irq_handler(pctrl, community);
864 static struct irq_chip intel_gpio_irqchip = {
865 .name = "intel-gpio",
866 .irq_enable = intel_gpio_irq_enable,
867 .irq_ack = intel_gpio_irq_ack,
868 .irq_mask = intel_gpio_irq_mask,
869 .irq_unmask = intel_gpio_irq_unmask,
870 .irq_set_type = intel_gpio_irq_type,
871 .irq_set_wake = intel_gpio_irq_wake,
874 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
878 pctrl->chip = intel_gpio_chip;
880 pctrl->chip.ngpio = pctrl->soc->npins;
881 pctrl->chip.label = dev_name(pctrl->dev);
882 pctrl->chip.parent = pctrl->dev;
883 pctrl->chip.base = -1;
886 ret = gpiochip_add_data(&pctrl->chip, pctrl);
888 dev_err(pctrl->dev, "failed to register gpiochip\n");
892 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
893 0, 0, pctrl->soc->npins);
895 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
900 * We need to request the interrupt here (instead of providing chip
901 * to the irq directly) because on some platforms several GPIO
902 * controllers share the same interrupt line.
904 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
905 IRQF_SHARED | IRQF_NO_THREAD,
906 dev_name(pctrl->dev), pctrl);
908 dev_err(pctrl->dev, "failed to request interrupt\n");
912 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
913 handle_simple_irq, IRQ_TYPE_NONE);
915 dev_err(pctrl->dev, "failed to add irqchip\n");
919 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
924 gpiochip_remove(&pctrl->chip);
929 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
931 #ifdef CONFIG_PM_SLEEP
932 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
933 struct intel_community_context *communities;
934 struct intel_pad_context *pads;
937 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
941 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
942 sizeof(*communities), GFP_KERNEL);
947 for (i = 0; i < pctrl->ncommunities; i++) {
948 struct intel_community *community = &pctrl->communities[i];
951 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
952 sizeof(*intmask), GFP_KERNEL);
956 communities[i].intmask = intmask;
959 pctrl->context.pads = pads;
960 pctrl->context.communities = communities;
966 int intel_pinctrl_probe(struct platform_device *pdev,
967 const struct intel_pinctrl_soc_data *soc_data)
969 struct intel_pinctrl *pctrl;
975 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
979 pctrl->dev = &pdev->dev;
980 pctrl->soc = soc_data;
981 raw_spin_lock_init(&pctrl->lock);
984 * Make a copy of the communities which we can use to hold pointers
987 pctrl->ncommunities = pctrl->soc->ncommunities;
988 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
989 sizeof(*pctrl->communities), GFP_KERNEL);
990 if (!pctrl->communities)
993 for (i = 0; i < pctrl->ncommunities; i++) {
994 struct intel_community *community = &pctrl->communities[i];
995 struct resource *res;
999 *community = pctrl->soc->communities[i];
1001 res = platform_get_resource(pdev, IORESOURCE_MEM,
1003 regs = devm_ioremap_resource(&pdev->dev, res);
1005 return PTR_ERR(regs);
1007 /* Read offset of the pad configuration registers */
1008 padbar = readl(regs + PADBAR);
1010 community->regs = regs;
1011 community->pad_regs = regs + padbar;
1012 community->ngpps = DIV_ROUND_UP(community->npins,
1013 community->gpp_size);
1016 irq = platform_get_irq(pdev, 0);
1018 dev_err(&pdev->dev, "failed to get interrupt number\n");
1022 ret = intel_pinctrl_pm_init(pctrl);
1026 pctrl->pctldesc = intel_pinctrl_desc;
1027 pctrl->pctldesc.name = dev_name(&pdev->dev);
1028 pctrl->pctldesc.pins = pctrl->soc->pins;
1029 pctrl->pctldesc.npins = pctrl->soc->npins;
1031 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1033 if (IS_ERR(pctrl->pctldev)) {
1034 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1035 return PTR_ERR(pctrl->pctldev);
1038 ret = intel_gpio_probe(pctrl, irq);
1042 platform_set_drvdata(pdev, pctrl);
1046 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1048 int intel_pinctrl_remove(struct platform_device *pdev)
1050 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1052 gpiochip_remove(&pctrl->chip);
1056 EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1058 #ifdef CONFIG_PM_SLEEP
1059 int intel_pinctrl_suspend(struct device *dev)
1061 struct platform_device *pdev = to_platform_device(dev);
1062 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1063 struct intel_community_context *communities;
1064 struct intel_pad_context *pads;
1067 pads = pctrl->context.pads;
1068 for (i = 0; i < pctrl->soc->npins; i++) {
1069 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1072 if (!intel_pad_usable(pctrl, desc->number))
1075 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1076 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1077 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1078 pads[i].padcfg1 = val;
1081 communities = pctrl->context.communities;
1082 for (i = 0; i < pctrl->ncommunities; i++) {
1083 struct intel_community *community = &pctrl->communities[i];
1087 base = community->regs + community->ie_offset;
1088 for (gpp = 0; gpp < community->ngpps; gpp++)
1089 communities[i].intmask[gpp] = readl(base + gpp * 4);
1094 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1096 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1100 for (i = 0; i < pctrl->ncommunities; i++) {
1101 const struct intel_community *community;
1105 community = &pctrl->communities[i];
1106 base = community->regs;
1108 for (gpp = 0; gpp < community->ngpps; gpp++) {
1109 /* Mask and clear all interrupts */
1110 writel(0, base + community->ie_offset + gpp * 4);
1111 writel(0xffff, base + GPI_IS + gpp * 4);
1116 int intel_pinctrl_resume(struct device *dev)
1118 struct platform_device *pdev = to_platform_device(dev);
1119 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1120 const struct intel_community_context *communities;
1121 const struct intel_pad_context *pads;
1124 /* Mask all interrupts */
1125 intel_gpio_irq_init(pctrl);
1127 pads = pctrl->context.pads;
1128 for (i = 0; i < pctrl->soc->npins; i++) {
1129 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1130 void __iomem *padcfg;
1133 if (!intel_pad_usable(pctrl, desc->number))
1136 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1137 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1138 if (val != pads[i].padcfg0) {
1139 writel(pads[i].padcfg0, padcfg);
1140 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1141 desc->number, readl(padcfg));
1144 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1145 val = readl(padcfg);
1146 if (val != pads[i].padcfg1) {
1147 writel(pads[i].padcfg1, padcfg);
1148 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1149 desc->number, readl(padcfg));
1153 communities = pctrl->context.communities;
1154 for (i = 0; i < pctrl->ncommunities; i++) {
1155 struct intel_community *community = &pctrl->communities[i];
1159 base = community->regs + community->ie_offset;
1160 for (gpp = 0; gpp < community->ngpps; gpp++) {
1161 writel(communities[i].intmask[gpp], base + gpp * 4);
1162 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1163 readl(base + gpp * 4));
1169 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1172 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1173 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1174 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1175 MODULE_LICENSE("GPL v2");