2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/gpio.h>
15 #include <linux/module.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
25 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
28 #include "../pinctrl-utils.h"
30 #define PMIC_GPIO_ADDRESS_RANGE 0x100
32 /* type and subtype registers base address offsets */
33 #define PMIC_GPIO_REG_TYPE 0x4
34 #define PMIC_GPIO_REG_SUBTYPE 0x5
36 /* GPIO peripheral type and subtype out_values */
37 #define PMIC_GPIO_TYPE 0x10
38 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
39 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
40 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
41 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
43 #define PMIC_MPP_REG_RT_STS 0x10
44 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
46 /* control register base address offsets */
47 #define PMIC_GPIO_REG_MODE_CTL 0x40
48 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
49 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
50 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
51 #define PMIC_GPIO_REG_EN_CTL 0x46
53 /* PMIC_GPIO_REG_MODE_CTL */
54 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
55 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
56 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
57 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
58 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
60 /* PMIC_GPIO_REG_DIG_VIN_CTL */
61 #define PMIC_GPIO_REG_VIN_SHIFT 0
62 #define PMIC_GPIO_REG_VIN_MASK 0x7
64 /* PMIC_GPIO_REG_DIG_PULL_CTL */
65 #define PMIC_GPIO_REG_PULL_SHIFT 0
66 #define PMIC_GPIO_REG_PULL_MASK 0x7
68 #define PMIC_GPIO_PULL_DOWN 4
69 #define PMIC_GPIO_PULL_DISABLE 5
71 /* PMIC_GPIO_REG_DIG_OUT_CTL */
72 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
73 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
74 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
75 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
78 * Output type - indicates pin should be configured as push-pull,
79 * open drain or open source.
81 #define PMIC_GPIO_OUT_BUF_CMOS 0
82 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
83 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
85 /* PMIC_GPIO_REG_EN_CTL */
86 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
88 #define PMIC_GPIO_PHYSICAL_OFFSET 1
90 /* Qualcomm specific pin configurations */
91 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
92 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
95 * struct pmic_gpio_pad - keep current GPIO settings
96 * @base: Address base in SPMI device.
97 * @irq: IRQ number which this GPIO generate.
98 * @is_enabled: Set to false when GPIO should be put in high Z state.
99 * @out_value: Cached pin output value
100 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
101 * open-drain or open-source mode.
102 * @output_enabled: Set to true if GPIO output logic is enabled.
103 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
104 * @num_sources: Number of power-sources supported by this GPIO.
105 * @power_source: Current power-source used.
106 * @buffer_type: Push-pull, open-drain or open-source.
107 * @pullup: Constant current which flow trough GPIO output buffer.
108 * @strength: No, Low, Medium, High
109 * @function: See pmic_gpio_functions[]
111 struct pmic_gpio_pad {
119 unsigned int num_sources;
120 unsigned int power_source;
121 unsigned int buffer_type;
123 unsigned int strength;
124 unsigned int function;
127 struct pmic_gpio_state {
130 struct pinctrl_dev *ctrl;
131 struct gpio_chip chip;
134 struct pmic_gpio_bindings {
135 const char *property;
139 static struct pmic_gpio_bindings pmic_gpio_bindings[] = {
140 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP},
141 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH},
144 static const char *const pmic_gpio_groups[] = {
145 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
146 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
147 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
148 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
149 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
152 static const char *const pmic_gpio_functions[] = {
153 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
154 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
155 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
156 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
159 static inline struct pmic_gpio_state *to_gpio_state(struct gpio_chip *chip)
161 return container_of(chip, struct pmic_gpio_state, chip);
164 static int pmic_gpio_read(struct pmic_gpio_state *state,
165 struct pmic_gpio_pad *pad, unsigned int addr)
170 ret = regmap_read(state->map, pad->base + addr, &val);
172 dev_err(state->dev, "read 0x%x failed\n", addr);
179 static int pmic_gpio_write(struct pmic_gpio_state *state,
180 struct pmic_gpio_pad *pad, unsigned int addr,
185 ret = regmap_write(state->map, pad->base + addr, val);
187 dev_err(state->dev, "write 0x%x failed\n", addr);
192 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
194 /* Every PIN is a group */
195 return pctldev->desc->npins;
198 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
201 return pctldev->desc->pins[pin].name;
204 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
205 const unsigned **pins, unsigned *num_pins)
207 *pins = &pctldev->desc->pins[pin].number;
212 static int pmic_gpio_parse_dt_config(struct device_node *np,
213 struct pinctrl_dev *pctldev,
214 unsigned long **configs,
215 unsigned int *nconfs)
217 struct pmic_gpio_bindings *par;
222 for (i = 0; i < ARRAY_SIZE(pmic_gpio_bindings); i++) {
223 par = &pmic_gpio_bindings[i];
224 ret = of_property_read_u32(np, par->property, &val);
226 /* property not found */
230 /* use zero as default value */
234 dev_dbg(pctldev->dev, "found %s with value %u\n",
237 cfg = pinconf_to_config_packed(par->param, val);
239 ret = pinctrl_utils_add_config(pctldev, configs, nconfs, cfg);
247 static int pmic_gpio_dt_subnode_to_map(struct pinctrl_dev *pctldev,
248 struct device_node *np,
249 struct pinctrl_map **map,
250 unsigned *reserv, unsigned *nmaps,
251 enum pinctrl_map_type type)
253 unsigned long *configs = NULL;
255 struct property *prop;
259 ret = pmic_gpio_parse_dt_config(np, pctldev, &configs, &nconfs);
266 ret = of_property_count_strings(np, "pins");
270 ret = pinctrl_utils_reserve_map(pctldev, map, reserv, nmaps, ret);
274 of_property_for_each_string(np, "pins", prop, group) {
275 ret = pinctrl_utils_add_map_configs(pctldev, map,
276 reserv, nmaps, group,
277 configs, nconfs, type);
286 static int pmic_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
287 struct device_node *np_config,
288 struct pinctrl_map **map, unsigned *nmaps)
290 enum pinctrl_map_type type;
291 struct device_node *np;
299 type = PIN_MAP_TYPE_CONFIGS_GROUP;
301 for_each_child_of_node(np_config, np) {
302 ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
303 &reserv, nmaps, type);
307 ret = pmic_gpio_dt_subnode_to_map(pctldev, np, map, &reserv,
314 pinctrl_utils_dt_free_map(pctldev, *map, *nmaps);
319 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
320 .get_groups_count = pmic_gpio_get_groups_count,
321 .get_group_name = pmic_gpio_get_group_name,
322 .get_group_pins = pmic_gpio_get_group_pins,
323 .dt_node_to_map = pmic_gpio_dt_node_to_map,
324 .dt_free_map = pinctrl_utils_dt_free_map,
327 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
329 return ARRAY_SIZE(pmic_gpio_functions);
332 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
335 return pmic_gpio_functions[function];
338 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
340 const char *const **groups,
341 unsigned *const num_qgroups)
343 *groups = pmic_gpio_groups;
344 *num_qgroups = pctldev->desc->npins;
348 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
351 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
352 struct pmic_gpio_pad *pad;
356 pad = pctldev->desc->pins[pin].drv_data;
358 pad->function = function;
361 if (pad->output_enabled) {
362 if (pad->input_enabled)
368 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
369 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
371 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
375 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
377 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
380 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
381 .get_functions_count = pmic_gpio_get_functions_count,
382 .get_function_name = pmic_gpio_get_function_name,
383 .get_function_groups = pmic_gpio_get_function_groups,
384 .set_mux = pmic_gpio_set_mux,
387 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
388 unsigned int pin, unsigned long *config)
390 unsigned param = pinconf_to_config_param(*config);
391 struct pmic_gpio_pad *pad;
394 pad = pctldev->desc->pins[pin].drv_data;
397 case PIN_CONFIG_DRIVE_PUSH_PULL:
398 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS;
400 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
401 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
403 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
404 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
406 case PIN_CONFIG_BIAS_PULL_DOWN:
407 arg = pad->pullup == PMIC_GPIO_PULL_DOWN;
409 case PIN_CONFIG_BIAS_DISABLE:
410 arg = pad->pullup = PMIC_GPIO_PULL_DISABLE;
412 case PIN_CONFIG_BIAS_PULL_UP:
413 arg = pad->pullup == PMIC_GPIO_PULL_UP_30;
415 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
416 arg = !pad->is_enabled;
418 case PIN_CONFIG_POWER_SOURCE:
419 arg = pad->power_source;
421 case PIN_CONFIG_INPUT_ENABLE:
422 arg = pad->input_enabled;
424 case PIN_CONFIG_OUTPUT:
425 arg = pad->out_value;
427 case PMIC_GPIO_CONF_PULL_UP:
430 case PMIC_GPIO_CONF_STRENGTH:
437 *config = pinconf_to_config_packed(param, arg);
441 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
442 unsigned long *configs, unsigned nconfs)
444 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
445 struct pmic_gpio_pad *pad;
450 pad = pctldev->desc->pins[pin].drv_data;
452 for (i = 0; i < nconfs; i++) {
453 param = pinconf_to_config_param(configs[i]);
454 arg = pinconf_to_config_argument(configs[i]);
457 case PIN_CONFIG_DRIVE_PUSH_PULL:
458 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
460 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
461 if (!pad->have_buffer)
463 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
465 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
466 if (!pad->have_buffer)
468 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
470 case PIN_CONFIG_BIAS_DISABLE:
471 pad->pullup = PMIC_GPIO_PULL_DISABLE;
473 case PIN_CONFIG_BIAS_PULL_UP:
474 pad->pullup = PMIC_GPIO_PULL_UP_30;
476 case PIN_CONFIG_BIAS_PULL_DOWN:
478 pad->pullup = PMIC_GPIO_PULL_DOWN;
480 pad->pullup = PMIC_GPIO_PULL_DISABLE;
482 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
483 pad->is_enabled = false;
485 case PIN_CONFIG_POWER_SOURCE:
486 if (arg > pad->num_sources)
488 pad->power_source = arg;
490 case PIN_CONFIG_INPUT_ENABLE:
491 pad->input_enabled = arg ? true : false;
493 case PIN_CONFIG_OUTPUT:
494 pad->output_enabled = true;
495 pad->out_value = arg;
497 case PMIC_GPIO_CONF_PULL_UP:
498 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
502 case PMIC_GPIO_CONF_STRENGTH:
503 if (arg > PMIC_GPIO_STRENGTH_LOW)
512 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
514 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
518 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
520 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
524 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
525 val = pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
527 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
532 if (pad->output_enabled) {
533 if (pad->input_enabled)
539 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
540 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
541 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
543 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
546 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
547 struct seq_file *s, unsigned pin)
549 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
550 struct pmic_gpio_pad *pad;
553 static const char *const biases[] = {
554 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
555 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
557 static const char *const buffer_types[] = {
558 "push-pull", "open-drain", "open-source"
560 static const char *const strengths[] = {
561 "no", "high", "medium", "low"
564 pad = pctldev->desc->pins[pin].drv_data;
566 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
568 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
570 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
574 if (!pad->input_enabled) {
575 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
577 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
578 pad->out_value = ret;
582 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
583 seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]);
584 seq_printf(s, " vin-%d", pad->power_source);
585 seq_printf(s, " %-27s", biases[pad->pullup]);
586 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
587 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
588 seq_printf(s, " %-7s", strengths[pad->strength]);
592 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
593 .pin_config_group_get = pmic_gpio_config_get,
594 .pin_config_group_set = pmic_gpio_config_set,
595 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
598 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
600 struct pmic_gpio_state *state = to_gpio_state(chip);
601 unsigned long config;
603 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
605 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
608 static int pmic_gpio_direction_output(struct gpio_chip *chip,
609 unsigned pin, int val)
611 struct pmic_gpio_state *state = to_gpio_state(chip);
612 unsigned long config;
614 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
616 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
619 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
621 struct pmic_gpio_state *state = to_gpio_state(chip);
622 struct pmic_gpio_pad *pad;
625 pad = state->ctrl->desc->pins[pin].drv_data;
627 if (!pad->is_enabled)
630 if (pad->input_enabled) {
631 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
635 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
638 return pad->out_value;
641 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
643 struct pmic_gpio_state *state = to_gpio_state(chip);
644 unsigned long config;
646 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
648 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
651 static int pmic_gpio_request(struct gpio_chip *chip, unsigned base)
653 return pinctrl_request_gpio(chip->base + base);
656 static void pmic_gpio_free(struct gpio_chip *chip, unsigned base)
658 pinctrl_free_gpio(chip->base + base);
661 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
662 const struct of_phandle_args *gpio_desc,
665 if (chip->of_gpio_n_cells < 2)
669 *flags = gpio_desc->args[1];
671 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
674 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
676 struct pmic_gpio_state *state = to_gpio_state(chip);
677 struct pmic_gpio_pad *pad;
679 pad = state->ctrl->desc->pins[pin].drv_data;
684 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
686 struct pmic_gpio_state *state = to_gpio_state(chip);
689 for (i = 0; i < chip->ngpio; i++) {
690 pmic_gpio_config_dbg_show(state->ctrl, s, i);
695 static const struct gpio_chip pmic_gpio_gpio_template = {
696 .direction_input = pmic_gpio_direction_input,
697 .direction_output = pmic_gpio_direction_output,
698 .get = pmic_gpio_get,
699 .set = pmic_gpio_set,
700 .request = pmic_gpio_request,
701 .free = pmic_gpio_free,
702 .of_xlate = pmic_gpio_of_xlate,
703 .to_irq = pmic_gpio_to_irq,
704 .dbg_show = pmic_gpio_dbg_show,
707 static int pmic_gpio_populate(struct pmic_gpio_state *state,
708 struct pmic_gpio_pad *pad)
710 int type, subtype, val, dir;
712 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
716 if (type != PMIC_GPIO_TYPE) {
717 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
722 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
727 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
728 pad->have_buffer = true;
729 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
730 pad->num_sources = 4;
732 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
733 pad->have_buffer = true;
734 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
735 pad->num_sources = 8;
738 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
742 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
746 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
748 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
749 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
752 pad->input_enabled = true;
753 pad->output_enabled = false;
756 pad->input_enabled = false;
757 pad->output_enabled = true;
760 pad->input_enabled = true;
761 pad->output_enabled = true;
764 dev_err(state->dev, "unknown GPIO direction\n");
768 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
769 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
771 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
775 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
776 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
778 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
782 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
783 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
785 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
789 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
790 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
792 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
793 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
795 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
796 pad->is_enabled = true;
800 static int pmic_gpio_probe(struct platform_device *pdev)
802 struct device *dev = &pdev->dev;
803 struct pinctrl_pin_desc *pindesc;
804 struct pinctrl_desc *pctrldesc;
805 struct pmic_gpio_pad *pad, *pads;
806 struct pmic_gpio_state *state;
810 ret = of_property_read_u32_array(dev->of_node, "reg", res, 2);
812 dev_err(dev, "missing base address and/or range");
816 npins = res[1] / PMIC_GPIO_ADDRESS_RANGE;
821 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
823 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
827 platform_set_drvdata(pdev, state);
829 state->dev = &pdev->dev;
830 state->map = dev_get_regmap(dev->parent, NULL);
832 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
836 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
840 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
844 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
845 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
846 pctrldesc->confops = &pmic_gpio_pinconf_ops;
847 pctrldesc->owner = THIS_MODULE;
848 pctrldesc->name = dev_name(dev);
849 pctrldesc->pins = pindesc;
850 pctrldesc->npins = npins;
852 for (i = 0; i < npins; i++, pindesc++) {
854 pindesc->drv_data = pad;
856 pindesc->name = pmic_gpio_groups[i];
858 pad->irq = platform_get_irq(pdev, i);
862 pad->base = res[0] + i * PMIC_GPIO_ADDRESS_RANGE;
864 ret = pmic_gpio_populate(state, pad);
869 state->chip = pmic_gpio_gpio_template;
870 state->chip.dev = dev;
871 state->chip.base = -1;
872 state->chip.ngpio = npins;
873 state->chip.label = dev_name(dev);
874 state->chip.of_gpio_n_cells = 2;
875 state->chip.can_sleep = false;
877 state->ctrl = pinctrl_register(pctrldesc, dev, state);
881 ret = gpiochip_add(&state->chip);
883 dev_err(state->dev, "can't add gpio chip\n");
887 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
889 dev_err(dev, "failed to add pin range\n");
896 gpiochip_remove(&state->chip);
898 pinctrl_unregister(state->ctrl);
902 static int pmic_gpio_remove(struct platform_device *pdev)
904 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
906 gpiochip_remove(&state->chip);
907 pinctrl_unregister(state->ctrl);
911 static const struct of_device_id pmic_gpio_of_match[] = {
912 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
913 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
917 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
919 static struct platform_driver pmic_gpio_driver = {
921 .name = "qcom-spmi-gpio",
922 .of_match_table = pmic_gpio_of_match,
924 .probe = pmic_gpio_probe,
925 .remove = pmic_gpio_remove,
928 module_platform_driver(pmic_gpio_driver);
930 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
931 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
932 MODULE_ALIAS("platform:qcom-spmi-gpio");
933 MODULE_LICENSE("GPL v2");