2 * Copyright (C) Maxime Coquelin 2015
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
6 * Heavily based on Mediatek's pinctrl driver
9 #include <linux/gpio/driver.h>
11 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_irq.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pinctrl/machine.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/platform_device.h>
23 #include <linux/reset.h>
24 #include <linux/slab.h>
27 #include "../pinconf.h"
28 #include "../pinctrl-utils.h"
29 #include "pinctrl-stm32.h"
31 #define STM32_GPIO_MODER 0x00
32 #define STM32_GPIO_TYPER 0x04
33 #define STM32_GPIO_SPEEDR 0x08
34 #define STM32_GPIO_PUPDR 0x0c
35 #define STM32_GPIO_IDR 0x10
36 #define STM32_GPIO_ODR 0x14
37 #define STM32_GPIO_BSRR 0x18
38 #define STM32_GPIO_LCKR 0x1c
39 #define STM32_GPIO_AFRL 0x20
40 #define STM32_GPIO_AFRH 0x24
42 #define STM32_GPIO_PINS_PER_BANK 16
44 #define gpio_range_to_bank(chip) \
45 container_of(chip, struct stm32_gpio_bank, range)
47 static const char * const stm32_gpio_functions[] = {
52 "af11", "af12", "af13",
53 "af14", "af15", "analog",
56 struct stm32_pinctrl_group {
62 struct stm32_gpio_bank {
66 struct gpio_chip gpio_chip;
67 struct pinctrl_gpio_range range;
70 struct stm32_pinctrl {
72 struct pinctrl_dev *pctl_dev;
73 struct pinctrl_desc pctl_desc;
74 struct stm32_pinctrl_group *groups;
76 const char **grp_names;
77 struct stm32_gpio_bank *banks;
79 const struct stm32_pinctrl_match_data *match_data;
82 static inline int stm32_gpio_pin(int gpio)
84 return gpio % STM32_GPIO_PINS_PER_BANK;
87 static inline u32 stm32_gpio_get_mode(u32 function)
92 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
94 case STM32_PIN_ANALOG:
101 static inline u32 stm32_gpio_get_alt(u32 function)
106 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
108 case STM32_PIN_ANALOG:
117 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
118 unsigned offset, int value)
121 offset += STM32_GPIO_PINS_PER_BANK;
123 clk_enable(bank->clk);
125 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
127 clk_disable(bank->clk);
130 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
132 return pinctrl_request_gpio(chip->base + offset);
135 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
137 pinctrl_free_gpio(chip->base + offset);
140 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
142 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
145 clk_enable(bank->clk);
147 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
149 clk_disable(bank->clk);
154 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
156 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
158 __stm32_gpio_set(bank, offset, value);
161 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
163 return pinctrl_gpio_direction_input(chip->base + offset);
166 static int stm32_gpio_direction_output(struct gpio_chip *chip,
167 unsigned offset, int value)
169 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
171 __stm32_gpio_set(bank, offset, value);
172 pinctrl_gpio_direction_output(chip->base + offset);
177 static struct gpio_chip stm32_gpio_template = {
178 .request = stm32_gpio_request,
179 .free = stm32_gpio_free,
180 .get = stm32_gpio_get,
181 .set = stm32_gpio_set,
182 .direction_input = stm32_gpio_direction_input,
183 .direction_output = stm32_gpio_direction_output,
186 /* Pinctrl functions */
188 static struct stm32_pinctrl_group *
189 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
193 for (i = 0; i < pctl->ngroups; i++) {
194 struct stm32_pinctrl_group *grp = pctl->groups + i;
203 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
204 u32 pin_num, u32 fnum)
208 for (i = 0; i < pctl->match_data->npins; i++) {
209 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
210 const struct stm32_desc_function *func = pin->functions;
212 if (pin->pin.number != pin_num)
215 while (func && func->name) {
216 if (func->num == fnum)
227 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
228 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
229 struct pinctrl_map **map, unsigned *reserved_maps,
232 if (*num_maps == *reserved_maps)
235 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
236 (*map)[*num_maps].data.mux.group = grp->name;
238 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
239 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
244 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
250 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
251 struct device_node *node,
252 struct pinctrl_map **map,
253 unsigned *reserved_maps,
256 struct stm32_pinctrl *pctl;
257 struct stm32_pinctrl_group *grp;
258 struct property *pins;
259 u32 pinfunc, pin, func;
260 unsigned long *configs;
261 unsigned int num_configs;
263 unsigned reserve = 0;
264 int num_pins, num_funcs, maps_per_pin, i, err;
266 pctl = pinctrl_dev_get_drvdata(pctldev);
268 pins = of_find_property(node, "pinmux", NULL);
270 dev_err(pctl->dev, "missing pins property in node %s .\n",
275 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
283 num_pins = pins->length / sizeof(u32);
284 num_funcs = num_pins;
288 if (has_config && num_pins >= 1)
291 if (!num_pins || !maps_per_pin)
294 reserve = num_pins * maps_per_pin;
296 err = pinctrl_utils_reserve_map(pctldev, map,
297 reserved_maps, num_maps, reserve);
301 for (i = 0; i < num_pins; i++) {
302 err = of_property_read_u32_index(node, "pinmux",
307 pin = STM32_GET_PIN_NO(pinfunc);
308 func = STM32_GET_PIN_FUNC(pinfunc);
310 if (pin >= pctl->match_data->npins) {
311 dev_err(pctl->dev, "invalid pin number.\n");
315 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
316 dev_err(pctl->dev, "invalid function.\n");
320 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
322 dev_err(pctl->dev, "unable to match pin %d to group\n",
327 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
328 reserved_maps, num_maps);
333 err = pinctrl_utils_add_map_configs(pctldev, map,
334 reserved_maps, num_maps, grp->name,
335 configs, num_configs,
336 PIN_MAP_TYPE_CONFIGS_GROUP);
345 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
346 struct device_node *np_config,
347 struct pinctrl_map **map, unsigned *num_maps)
349 struct device_node *np;
350 unsigned reserved_maps;
357 for_each_child_of_node(np_config, np) {
358 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
359 &reserved_maps, num_maps);
361 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
369 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
371 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
373 return pctl->ngroups;
376 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
379 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
381 return pctl->groups[group].name;
384 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
386 const unsigned **pins,
389 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
391 *pins = (unsigned *)&pctl->groups[group].pin;
397 static const struct pinctrl_ops stm32_pctrl_ops = {
398 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
399 .dt_free_map = pinctrl_utils_dt_free_map,
400 .get_groups_count = stm32_pctrl_get_groups_count,
401 .get_group_name = stm32_pctrl_get_group_name,
402 .get_group_pins = stm32_pctrl_get_group_pins,
406 /* Pinmux functions */
408 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
410 return ARRAY_SIZE(stm32_gpio_functions);
413 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
416 return stm32_gpio_functions[selector];
419 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
421 const char * const **groups,
422 unsigned * const num_groups)
424 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
426 *groups = pctl->grp_names;
427 *num_groups = pctl->ngroups;
432 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
433 int pin, u32 mode, u32 alt)
436 int alt_shift = (pin % 8) * 4;
437 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
440 clk_enable(bank->clk);
441 spin_lock_irqsave(&bank->lock, flags);
443 val = readl_relaxed(bank->base + alt_offset);
444 val &= ~GENMASK(alt_shift + 3, alt_shift);
445 val |= (alt << alt_shift);
446 writel_relaxed(val, bank->base + alt_offset);
448 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
449 val &= ~GENMASK(pin * 2 + 1, pin * 2);
450 val |= mode << (pin * 2);
451 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
453 spin_unlock_irqrestore(&bank->lock, flags);
454 clk_disable(bank->clk);
457 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
462 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
463 struct stm32_pinctrl_group *g = pctl->groups + group;
464 struct pinctrl_gpio_range *range;
465 struct stm32_gpio_bank *bank;
469 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
471 dev_err(pctl->dev, "invalid function %d on group %d .\n",
476 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
477 bank = gpio_range_to_bank(range);
478 pin = stm32_gpio_pin(g->pin);
480 mode = stm32_gpio_get_mode(function);
481 alt = stm32_gpio_get_alt(function);
483 stm32_pmx_set_mode(bank, pin, mode, alt);
488 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
489 struct pinctrl_gpio_range *range, unsigned gpio,
492 struct stm32_gpio_bank *bank = gpio_range_to_bank(range);
493 int pin = stm32_gpio_pin(gpio);
495 stm32_pmx_set_mode(bank, pin, !input, 0);
500 static const struct pinmux_ops stm32_pmx_ops = {
501 .get_functions_count = stm32_pmx_get_funcs_cnt,
502 .get_function_name = stm32_pmx_get_func_name,
503 .get_function_groups = stm32_pmx_get_func_groups,
504 .set_mux = stm32_pmx_set_mux,
505 .gpio_set_direction = stm32_pmx_gpio_set_direction,
508 /* Pinconf functions */
510 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
511 unsigned offset, u32 drive)
516 clk_enable(bank->clk);
517 spin_lock_irqsave(&bank->lock, flags);
519 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
521 val |= drive << offset;
522 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
524 spin_unlock_irqrestore(&bank->lock, flags);
525 clk_disable(bank->clk);
528 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
529 unsigned offset, u32 speed)
534 clk_enable(bank->clk);
535 spin_lock_irqsave(&bank->lock, flags);
537 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
538 val &= ~GENMASK(offset * 2 + 1, offset * 2);
539 val |= speed << (offset * 2);
540 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
542 spin_unlock_irqrestore(&bank->lock, flags);
543 clk_disable(bank->clk);
546 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
547 unsigned offset, u32 bias)
552 clk_enable(bank->clk);
553 spin_lock_irqsave(&bank->lock, flags);
555 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
556 val &= ~GENMASK(offset * 2 + 1, offset * 2);
557 val |= bias << (offset * 2);
558 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
560 spin_unlock_irqrestore(&bank->lock, flags);
561 clk_disable(bank->clk);
564 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
565 unsigned int pin, enum pin_config_param param,
566 enum pin_config_param arg)
568 struct pinctrl_gpio_range *range;
569 struct stm32_gpio_bank *bank;
572 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
573 bank = gpio_range_to_bank(range);
574 offset = stm32_gpio_pin(pin);
577 case PIN_CONFIG_DRIVE_PUSH_PULL:
578 stm32_pconf_set_driving(bank, offset, 0);
580 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
581 stm32_pconf_set_driving(bank, offset, 1);
583 case PIN_CONFIG_SLEW_RATE:
584 stm32_pconf_set_speed(bank, offset, arg);
586 case PIN_CONFIG_BIAS_DISABLE:
587 stm32_pconf_set_bias(bank, offset, 0);
589 case PIN_CONFIG_BIAS_PULL_UP:
590 stm32_pconf_set_bias(bank, offset, 1);
592 case PIN_CONFIG_BIAS_PULL_DOWN:
593 stm32_pconf_set_bias(bank, offset, 2);
595 case PIN_CONFIG_OUTPUT:
596 __stm32_gpio_set(bank, offset, arg);
597 ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false);
606 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
608 unsigned long *config)
610 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
612 *config = pctl->groups[group].config;
617 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
618 unsigned long *configs, unsigned num_configs)
620 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
621 struct stm32_pinctrl_group *g = &pctl->groups[group];
624 for (i = 0; i < num_configs; i++) {
625 ret = stm32_pconf_parse_conf(pctldev, g->pin,
626 pinconf_to_config_param(configs[i]),
627 pinconf_to_config_argument(configs[i]));
631 g->config = configs[i];
637 static const struct pinconf_ops stm32_pconf_ops = {
638 .pin_config_group_get = stm32_pconf_group_get,
639 .pin_config_group_set = stm32_pconf_group_set,
642 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
643 struct device_node *np)
645 int bank_nr = pctl->nbanks;
646 struct stm32_gpio_bank *bank = &pctl->banks[bank_nr];
647 struct pinctrl_gpio_range *range = &bank->range;
648 struct device *dev = pctl->dev;
650 struct reset_control *rstc;
653 rstc = of_reset_control_get(np, NULL);
655 reset_control_deassert(rstc);
657 if (of_address_to_resource(np, 0, &res))
660 bank->base = devm_ioremap_resource(dev, &res);
661 if (IS_ERR(bank->base))
662 return PTR_ERR(bank->base);
664 bank->clk = of_clk_get_by_name(np, NULL);
665 if (IS_ERR(bank->clk)) {
666 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
667 return PTR_ERR(bank->clk);
670 err = clk_prepare(bank->clk);
672 dev_err(dev, "failed to prepare clk (%d)\n", err);
676 npins = pctl->match_data->npins;
677 npins -= bank_nr * STM32_GPIO_PINS_PER_BANK;
680 else if (npins > STM32_GPIO_PINS_PER_BANK)
681 npins = STM32_GPIO_PINS_PER_BANK;
683 bank->gpio_chip = stm32_gpio_template;
684 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
685 bank->gpio_chip.ngpio = npins;
686 bank->gpio_chip.of_node = np;
687 bank->gpio_chip.parent = dev;
688 spin_lock_init(&bank->lock);
690 of_property_read_string(np, "st,bank-name", &range->name);
691 bank->gpio_chip.label = range->name;
694 range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK;
695 range->npins = bank->gpio_chip.ngpio;
696 range->gc = &bank->gpio_chip;
697 err = gpiochip_add_data(&bank->gpio_chip, bank);
699 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
703 dev_info(dev, "%s bank added\n", range->name);
707 static int stm32_pctrl_build_state(struct platform_device *pdev)
709 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
712 pctl->ngroups = pctl->match_data->npins;
714 /* Allocate groups */
715 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
716 sizeof(*pctl->groups), GFP_KERNEL);
720 /* We assume that one pin is one group, use pin name as group name. */
721 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
722 sizeof(*pctl->grp_names), GFP_KERNEL);
723 if (!pctl->grp_names)
726 for (i = 0; i < pctl->match_data->npins; i++) {
727 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
728 struct stm32_pinctrl_group *group = pctl->groups + i;
730 group->name = pin->pin.name;
731 group->pin = pin->pin.number;
733 pctl->grp_names[i] = pin->pin.name;
739 int stm32_pctl_probe(struct platform_device *pdev)
741 struct device_node *np = pdev->dev.of_node;
742 struct device_node *child;
743 const struct of_device_id *match;
744 struct device *dev = &pdev->dev;
745 struct stm32_pinctrl *pctl;
746 struct pinctrl_pin_desc *pins;
747 int i, ret, banks = 0;
752 match = of_match_device(dev->driver->of_match_table, dev);
753 if (!match || !match->data)
756 if (!of_find_property(np, "pins-are-numbered", NULL)) {
757 dev_err(dev, "only support pins-are-numbered format\n");
761 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
765 platform_set_drvdata(pdev, pctl);
768 pctl->match_data = match->data;
769 ret = stm32_pctrl_build_state(pdev);
771 dev_err(dev, "build state failed: %d\n", ret);
775 for_each_child_of_node(np, child)
776 if (of_property_read_bool(child, "gpio-controller"))
780 dev_err(dev, "at least one GPIO bank is required\n");
784 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
789 for_each_child_of_node(np, child) {
790 if (of_property_read_bool(child, "gpio-controller")) {
791 ret = stm32_gpiolib_register_bank(pctl, child);
799 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
804 for (i = 0; i < pctl->match_data->npins; i++)
805 pins[i] = pctl->match_data->pins[i].pin;
807 pctl->pctl_desc.name = dev_name(&pdev->dev);
808 pctl->pctl_desc.owner = THIS_MODULE;
809 pctl->pctl_desc.pins = pins;
810 pctl->pctl_desc.npins = pctl->match_data->npins;
811 pctl->pctl_desc.confops = &stm32_pconf_ops;
812 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
813 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
814 pctl->dev = &pdev->dev;
816 pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
817 if (!pctl->pctl_dev) {
818 dev_err(&pdev->dev, "Failed pinctrl registration\n");
822 for (i = 0; i < pctl->nbanks; i++)
823 pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range);
825 dev_info(dev, "Pinctrl STM32 initialized\n");