2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
31 #define SUNXI_PINCTRL_PIN(bank, pin) \
32 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
34 #define SUNXI_PIN_NAME_MAX_LEN 5
36 #define BANK_MEM_SIZE 0x24
37 #define MUX_REGS_OFFSET 0x0
38 #define DATA_REGS_OFFSET 0x10
39 #define DLEVEL_REGS_OFFSET 0x14
40 #define PULL_REGS_OFFSET 0x1c
42 #define PINS_PER_BANK 32
43 #define MUX_PINS_PER_REG 8
44 #define MUX_PINS_BITS 4
45 #define MUX_PINS_MASK 0x0f
46 #define DATA_PINS_PER_REG 32
47 #define DATA_PINS_BITS 1
48 #define DATA_PINS_MASK 0x01
49 #define DLEVEL_PINS_PER_REG 16
50 #define DLEVEL_PINS_BITS 2
51 #define DLEVEL_PINS_MASK 0x03
52 #define PULL_PINS_PER_REG 16
53 #define PULL_PINS_BITS 2
54 #define PULL_PINS_MASK 0x03
56 #define SUNXI_IRQ_NUMBER 32
58 #define IRQ_CFG_REG 0x200
59 #define IRQ_CFG_IRQ_PER_REG 8
60 #define IRQ_CFG_IRQ_BITS 4
61 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
62 #define IRQ_CTRL_REG 0x210
63 #define IRQ_CTRL_IRQ_PER_REG 32
64 #define IRQ_CTRL_IRQ_BITS 1
65 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
66 #define IRQ_STATUS_REG 0x214
67 #define IRQ_STATUS_IRQ_PER_REG 32
68 #define IRQ_STATUS_IRQ_BITS 1
69 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
71 #define IRQ_EDGE_RISING 0x00
72 #define IRQ_EDGE_FALLING 0x01
73 #define IRQ_LEVEL_HIGH 0x02
74 #define IRQ_LEVEL_LOW 0x03
75 #define IRQ_EDGE_BOTH 0x04
77 struct sunxi_desc_function {
83 struct sunxi_desc_pin {
84 struct pinctrl_pin_desc pin;
85 struct sunxi_desc_function *functions;
88 struct sunxi_pinctrl_desc {
89 const struct sunxi_desc_pin *pins;
94 struct sunxi_pinctrl_function {
100 struct sunxi_pinctrl_group {
102 unsigned long config;
106 struct sunxi_pinctrl {
107 void __iomem *membase;
108 struct gpio_chip *chip;
109 const struct sunxi_pinctrl_desc *desc;
111 struct irq_domain *domain;
112 struct sunxi_pinctrl_function *functions;
114 struct sunxi_pinctrl_group *groups;
117 int irq_array[SUNXI_IRQ_NUMBER];
119 struct pinctrl_dev *pctl_dev;
122 #define SUNXI_PIN(_pin, ...) \
125 .functions = (struct sunxi_desc_function[]){ \
126 __VA_ARGS__, { } }, \
129 #define SUNXI_FUNCTION(_val, _name) \
135 #define SUNXI_FUNCTION_IRQ(_val, _irq) \
143 * The sunXi PIO registers are organized as is:
144 * 0x00 - 0x0c Muxing values.
145 * 8 pins per register, each pin having a 4bits value
147 * 32 bits per register, each pin corresponding to one bit
148 * 0x14 - 0x18 Drive level
149 * 16 pins per register, each pin having a 2bits value
150 * 0x1c - 0x20 Pull-Up values
151 * 16 pins per register, each pin having a 2bits value
153 * This is for the first bank. Each bank will have the same layout,
154 * with an offset being a multiple of 0x24.
156 * The following functions calculate from the pin number the register
157 * and the bit offset that we should access.
159 static inline u32 sunxi_mux_reg(u16 pin)
161 u8 bank = pin / PINS_PER_BANK;
162 u32 offset = bank * BANK_MEM_SIZE;
163 offset += MUX_REGS_OFFSET;
164 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
165 return round_down(offset, 4);
168 static inline u32 sunxi_mux_offset(u16 pin)
170 u32 pin_num = pin % MUX_PINS_PER_REG;
171 return pin_num * MUX_PINS_BITS;
174 static inline u32 sunxi_data_reg(u16 pin)
176 u8 bank = pin / PINS_PER_BANK;
177 u32 offset = bank * BANK_MEM_SIZE;
178 offset += DATA_REGS_OFFSET;
179 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
180 return round_down(offset, 4);
183 static inline u32 sunxi_data_offset(u16 pin)
185 u32 pin_num = pin % DATA_PINS_PER_REG;
186 return pin_num * DATA_PINS_BITS;
189 static inline u32 sunxi_dlevel_reg(u16 pin)
191 u8 bank = pin / PINS_PER_BANK;
192 u32 offset = bank * BANK_MEM_SIZE;
193 offset += DLEVEL_REGS_OFFSET;
194 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
195 return round_down(offset, 4);
198 static inline u32 sunxi_dlevel_offset(u16 pin)
200 u32 pin_num = pin % DLEVEL_PINS_PER_REG;
201 return pin_num * DLEVEL_PINS_BITS;
204 static inline u32 sunxi_pull_reg(u16 pin)
206 u8 bank = pin / PINS_PER_BANK;
207 u32 offset = bank * BANK_MEM_SIZE;
208 offset += PULL_REGS_OFFSET;
209 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
210 return round_down(offset, 4);
213 static inline u32 sunxi_pull_offset(u16 pin)
215 u32 pin_num = pin % PULL_PINS_PER_REG;
216 return pin_num * PULL_PINS_BITS;
219 static inline u32 sunxi_irq_cfg_reg(u16 irq)
221 u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
222 return reg + IRQ_CFG_REG;
225 static inline u32 sunxi_irq_cfg_offset(u16 irq)
227 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
228 return irq_num * IRQ_CFG_IRQ_BITS;
231 static inline u32 sunxi_irq_ctrl_reg(u16 irq)
233 u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
234 return reg + IRQ_CTRL_REG;
237 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
239 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
240 return irq_num * IRQ_CTRL_IRQ_BITS;
243 static inline u32 sunxi_irq_status_reg(u16 irq)
245 u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
246 return reg + IRQ_STATUS_REG;
249 static inline u32 sunxi_irq_status_offset(u16 irq)
251 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
252 return irq_num * IRQ_STATUS_IRQ_BITS;
255 int sunxi_pinctrl_init(struct platform_device *pdev,
256 const struct sunxi_pinctrl_desc *desc);
258 #endif /* __PINCTRL_SUNXI_H */