drivers/pwm/pwm-rockchip.c

   1 /*
   2  * PWM driver for Rockchip SoCs
   3  *
   4  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/time.h>
  20
  21 #define PWM_CTRL_TIMER_EN       (1 << 0)
  22 #define PWM_CTRL_OUTPUT_EN      (1 << 3)
  23
  24 #define PWM_ENABLE              (1 << 0)
  25 #define PWM_CONTINUOUS          (1 << 1)
  26 #define PWM_DUTY_POSITIVE       (1 << 3)
  27 #define PWM_DUTY_NEGATIVE       (0 << 3)
  28 #define PWM_INACTIVE_NEGATIVE   (0 << 4)
  29 #define PWM_INACTIVE_POSITIVE   (1 << 4)
  30 #define PWM_OUTPUT_LEFT         (0 << 5)
  31 #define PWM_LP_DISABLE          (0 << 8)
  32
  33 struct rockchip_pwm_chip {
  34         struct pwm_chip chip;
  35         struct clk *clk;
  36         const struct rockchip_pwm_data *data;
  37         void __iomem *base;
  38 };
  39
  40 struct rockchip_pwm_regs {
  41         unsigned long duty;
  42         unsigned long period;
  43         unsigned long cntr;
  44         unsigned long ctrl;
  45 };
  46
  47 struct rockchip_pwm_data {
  48         struct rockchip_pwm_regs regs;
  49         unsigned int prescaler;
  50         const struct pwm_ops *ops;
  51
  52         void (*set_enable)(struct pwm_chip *chip,
  53                            struct pwm_device *pwm, bool enable);
  54         void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm,
  55                           struct pwm_state *state);
  56 };
  57
  58 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
  59 {
  60         return container_of(c, struct rockchip_pwm_chip, chip);
  61 }
  62
  63 static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip,
  64                                        struct pwm_device *pwm, bool enable)
  65 {
  66         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  67         u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
  68         u32 val;
  69
  70         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  71
  72         if (enable)
  73                 val |= enable_conf;
  74         else
  75                 val &= ~enable_conf;
  76
  77         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
  78 }
  79
  80 static void rockchip_pwm_get_state_v1(struct pwm_chip *chip,
  81                                       struct pwm_device *pwm,
  82                                       struct pwm_state *state)
  83 {
  84         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  85         u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
  86         u32 val;
  87
  88         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  89         if ((val & enable_conf) == enable_conf)
  90                 state->enabled = true;
  91 }
  92
  93 static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip,
  94                                        struct pwm_device *pwm, bool enable)
  95 {
  96         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  97         u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
  98                           PWM_CONTINUOUS;
  99         u32 val;
 100
 101         if (pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED)
 102                 enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
 103         else
 104                 enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
 105
 106         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
 107
 108         if (enable)
 109                 val |= enable_conf;
 110         else
 111                 val &= ~enable_conf;
 112
 113         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
 114 }
 115
 116 static void rockchip_pwm_get_state_v2(struct pwm_chip *chip,
 117                                       struct pwm_device *pwm,
 118                                       struct pwm_state *state)
 119 {
 120         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 121         u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
 122                           PWM_CONTINUOUS;
 123         u32 val;
 124
 125         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
 126         if ((val & enable_conf) != enable_conf)
 127                 return;
 128
 129         state->enabled = true;
 130
 131         if (!(val & PWM_DUTY_POSITIVE))
 132                 state->polarity = PWM_POLARITY_INVERSED;
 133 }
 134
 135 static void rockchip_pwm_get_state(struct pwm_chip *chip,
 136                                    struct pwm_device *pwm,
 137                                    struct pwm_state *state)
 138 {
 139         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 140         unsigned long clk_rate;
 141         u64 tmp;
 142         int ret;
 143
 144         ret = clk_enable(pc->clk);
 145         if (ret)
 146                 return;
 147
 148         clk_rate = clk_get_rate(pc->clk);
 149
 150         tmp = readl_relaxed(pc->base + pc->data->regs.period);
 151         tmp *= pc->data->prescaler * NSEC_PER_SEC;
 152         state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 153
 154         tmp = readl_relaxed(pc->base + pc->data->regs.duty);
 155         tmp *= pc->data->prescaler * NSEC_PER_SEC;
 156         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 157
 158         pc->data->get_state(chip, pwm, state);
 159
 160         clk_disable(pc->clk);
 161 }
 162
 163 static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 164                                int duty_ns, int period_ns)
 165 {
 166         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 167         unsigned long period, duty;
 168         u64 clk_rate, div;
 169         int ret;
 170
 171         clk_rate = clk_get_rate(pc->clk);
 172
 173         /*
 174          * Since period and duty cycle registers have a width of 32
 175          * bits, every possible input period can be obtained using the
 176          * default prescaler value for all practical clock rate values.
 177          */
 178         div = clk_rate * period_ns;
 179         period = DIV_ROUND_CLOSEST_ULL(div,
 180                                        pc->data->prescaler * NSEC_PER_SEC);
 181
 182         div = clk_rate * duty_ns;
 183         duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
 184
 185         ret = clk_enable(pc->clk);
 186         if (ret)
 187                 return ret;
 188
 189         writel(period, pc->base + pc->data->regs.period);
 190         writel(duty, pc->base + pc->data->regs.duty);
 191         writel(0, pc->base + pc->data->regs.cntr);
 192
 193         clk_disable(pc->clk);
 194
 195         return 0;
 196 }
 197
 198 static int rockchip_pwm_set_polarity(struct pwm_chip *chip,
 199                                      struct pwm_device *pwm,
 200                                      enum pwm_polarity polarity)
 201 {
 202         /*
 203          * No action needed here because pwm->polarity will be set by the core
 204          * and the core will only change polarity when the PWM is not enabled.
 205          * We'll handle things in set_enable().
 206          */
 207
 208         return 0;
 209 }
 210
 211 static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 212 {
 213         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 214         int ret;
 215
 216         ret = clk_enable(pc->clk);
 217         if (ret)
 218                 return ret;
 219
 220         pc->data->set_enable(chip, pwm, true);
 221
 222         return 0;
 223 }
 224
 225 static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 226 {
 227         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 228
 229         pc->data->set_enable(chip, pwm, false);
 230
 231         clk_disable(pc->clk);
 232 }
 233
 234 static const struct pwm_ops rockchip_pwm_ops_v1 = {
 235         .get_state = rockchip_pwm_get_state,
 236         .config = rockchip_pwm_config,
 237         .enable = rockchip_pwm_enable,
 238         .disable = rockchip_pwm_disable,
 239         .owner = THIS_MODULE,
 240 };
 241
 242 static const struct pwm_ops rockchip_pwm_ops_v2 = {
 243         .get_state = rockchip_pwm_get_state,
 244         .config = rockchip_pwm_config,
 245         .set_polarity = rockchip_pwm_set_polarity,
 246         .enable = rockchip_pwm_enable,
 247         .disable = rockchip_pwm_disable,
 248         .owner = THIS_MODULE,
 249 };
 250
 251 static const struct rockchip_pwm_data pwm_data_v1 = {
 252         .regs = {
 253                 .duty = 0x04,
 254                 .period = 0x08,
 255                 .cntr = 0x00,
 256                 .ctrl = 0x0c,
 257         },
 258         .prescaler = 2,
 259         .ops = &rockchip_pwm_ops_v1,
 260         .set_enable = rockchip_pwm_set_enable_v1,
 261         .get_state = rockchip_pwm_get_state_v1,
 262 };
 263
 264 static const struct rockchip_pwm_data pwm_data_v2 = {
 265         .regs = {
 266                 .duty = 0x08,
 267                 .period = 0x04,
 268                 .cntr = 0x00,
 269                 .ctrl = 0x0c,
 270         },
 271         .prescaler = 1,
 272         .ops = &rockchip_pwm_ops_v2,
 273         .set_enable = rockchip_pwm_set_enable_v2,
 274         .get_state = rockchip_pwm_get_state_v2,
 275 };
 276
 277 static const struct rockchip_pwm_data pwm_data_vop = {
 278         .regs = {
 279                 .duty = 0x08,
 280                 .period = 0x04,
 281                 .cntr = 0x0c,
 282                 .ctrl = 0x00,
 283         },
 284         .prescaler = 1,
 285         .ops = &rockchip_pwm_ops_v2,
 286         .set_enable = rockchip_pwm_set_enable_v2,
 287         .get_state = rockchip_pwm_get_state_v2,
 288 };
 289
 290 static const struct of_device_id rockchip_pwm_dt_ids[] = {
 291         { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
 292         { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
 293         { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
 294         { /* sentinel */ }
 295 };
 296 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
 297
 298 static int rockchip_pwm_probe(struct platform_device *pdev)
 299 {
 300         const struct of_device_id *id;
 301         struct rockchip_pwm_chip *pc;
 302         struct resource *r;
 303         int ret;
 304
 305         id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
 306         if (!id)
 307                 return -EINVAL;
 308
 309         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 310         if (!pc)
 311                 return -ENOMEM;
 312
 313         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 314         pc->base = devm_ioremap_resource(&pdev->dev, r);
 315         if (IS_ERR(pc->base))
 316                 return PTR_ERR(pc->base);
 317
 318         pc->clk = devm_clk_get(&pdev->dev, NULL);
 319         if (IS_ERR(pc->clk))
 320                 return PTR_ERR(pc->clk);
 321
 322         ret = clk_prepare_enable(pc->clk);
 323         if (ret)
 324                 return ret;
 325
 326         platform_set_drvdata(pdev, pc);
 327
 328         pc->data = id->data;
 329         pc->chip.dev = &pdev->dev;
 330         pc->chip.ops = pc->data->ops;
 331         pc->chip.base = -1;
 332         pc->chip.npwm = 1;
 333
 334         if (pc->data->ops->set_polarity) {
 335                 pc->chip.of_xlate = of_pwm_xlate_with_flags;
 336                 pc->chip.of_pwm_n_cells = 3;
 337         }
 338
 339         ret = pwmchip_add(&pc->chip);
 340         if (ret < 0) {
 341                 clk_unprepare(pc->clk);
 342                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 343         }
 344
 345         /* Keep the PWM clk enabled if the PWM appears to be up and running. */
 346         if (!pwm_is_enabled(pc->chip.pwms))
 347                 clk_disable(pc->clk);
 348
 349         return ret;
 350 }
 351
 352 static int rockchip_pwm_remove(struct platform_device *pdev)
 353 {
 354         struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
 355
 356         /*
 357          * Disable the PWM clk before unpreparing it if the PWM device is still
 358          * running. This should only happen when the last PWM user left it
 359          * enabled, or when nobody requested a PWM that was previously enabled
 360          * by the bootloader.
 361          *
 362          * FIXME: Maybe the core should disable all PWM devices in
 363          * pwmchip_remove(). In this case we'd only have to call
 364          * clk_unprepare() after pwmchip_remove().
 365          *
 366          */
 367         if (pwm_is_enabled(pc->chip.pwms))
 368                 clk_disable(pc->clk);
 369
 370         clk_unprepare(pc->clk);
 371
 372         return pwmchip_remove(&pc->chip);
 373 }
 374
 375 static struct platform_driver rockchip_pwm_driver = {
 376         .driver = {
 377                 .name = "rockchip-pwm",
 378                 .of_match_table = rockchip_pwm_dt_ids,
 379         },
 380         .probe = rockchip_pwm_probe,
 381         .remove = rockchip_pwm_remove,
 382 };
 383 module_platform_driver(rockchip_pwm_driver);
 384
 385 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
 386 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
 387 MODULE_LICENSE("GPL v2");