drivers/rapidio/devices/tsi721.c

   1 /*
   2  * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
   3  *
   4  * Copyright 2011 Integrated Device Technology, Inc.
   5  * Alexandre Bounine <alexandre.bounine@idt.com>
   6  * Chul Kim <chul.kim@idt.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the Free
  10  * Software Foundation; either version 2 of the License, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc., 59
  20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  21  */
  22
  23 #include <linux/io.h>
  24 #include <linux/errno.h>
  25 #include <linux/init.h>
  26 #include <linux/ioport.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <linux/rio.h>
  31 #include <linux/rio_drv.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/kfifo.h>
  35 #include <linux/delay.h>
  36
  37 #include "tsi721.h"
  38
  39 #define DEBUG_PW        /* Inbound Port-Write debugging */
  40
  41 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch);
  42 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch);
  43
  44 /**
  45  * tsi721_lcread - read from local SREP config space
  46  * @mport: RapidIO master port info
  47  * @index: ID of RapdiIO interface
  48  * @offset: Offset into configuration space
  49  * @len: Length (in bytes) of the maintenance transaction
  50  * @data: Value to be read into
  51  *
  52  * Generates a local SREP space read. Returns %0 on
  53  * success or %-EINVAL on failure.
  54  */
  55 static int tsi721_lcread(struct rio_mport *mport, int index, u32 offset,
  56                          int len, u32 *data)
  57 {
  58         struct tsi721_device *priv = mport->priv;
  59
  60         if (len != sizeof(u32))
  61                 return -EINVAL; /* only 32-bit access is supported */
  62
  63         *data = ioread32(priv->regs + offset);
  64
  65         return 0;
  66 }
  67
  68 /**
  69  * tsi721_lcwrite - write into local SREP config space
  70  * @mport: RapidIO master port info
  71  * @index: ID of RapdiIO interface
  72  * @offset: Offset into configuration space
  73  * @len: Length (in bytes) of the maintenance transaction
  74  * @data: Value to be written
  75  *
  76  * Generates a local write into SREP configuration space. Returns %0 on
  77  * success or %-EINVAL on failure.
  78  */
  79 static int tsi721_lcwrite(struct rio_mport *mport, int index, u32 offset,
  80                           int len, u32 data)
  81 {
  82         struct tsi721_device *priv = mport->priv;
  83
  84         if (len != sizeof(u32))
  85                 return -EINVAL; /* only 32-bit access is supported */
  86
  87         iowrite32(data, priv->regs + offset);
  88
  89         return 0;
  90 }
  91
  92 /**
  93  * tsi721_maint_dma - Helper function to generate RapidIO maintenance
  94  *                    transactions using designated Tsi721 DMA channel.
  95  * @priv: pointer to tsi721 private data
  96  * @sys_size: RapdiIO transport system size
  97  * @destid: Destination ID of transaction
  98  * @hopcount: Number of hops to target device
  99  * @offset: Offset into configuration space
 100  * @len: Length (in bytes) of the maintenance transaction
 101  * @data: Location to be read from or write into
 102  * @do_wr: Operation flag (1 == MAINT_WR)
 103  *
 104  * Generates a RapidIO maintenance transaction (Read or Write).
 105  * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
 106  */
 107 static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
 108                         u16 destid, u8 hopcount, u32 offset, int len,
 109                         u32 *data, int do_wr)
 110 {
 111         void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id);
 112         struct tsi721_dma_desc *bd_ptr;
 113         u32 rd_count, swr_ptr, ch_stat;
 114         int i, err = 0;
 115         u32 op = do_wr ? MAINT_WR : MAINT_RD;
 116
 117         if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32)))
 118                 return -EINVAL;
 119
 120         bd_ptr = priv->mdma.bd_base;
 121
 122         rd_count = ioread32(regs + TSI721_DMAC_DRDCNT);
 123
 124         /* Initialize DMA descriptor */
 125         bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid);
 126         bd_ptr[0].bcount = cpu_to_le32((sys_size << 26) | 0x04);
 127         bd_ptr[0].raddr_lo = cpu_to_le32((hopcount << 24) | offset);
 128         bd_ptr[0].raddr_hi = 0;
 129         if (do_wr)
 130                 bd_ptr[0].data[0] = cpu_to_be32p(data);
 131         else
 132                 bd_ptr[0].data[0] = 0xffffffff;
 133
 134         mb();
 135
 136         /* Start DMA operation */
 137         iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT);
 138         ioread32(regs + TSI721_DMAC_DWRCNT);
 139         i = 0;
 140
 141         /* Wait until DMA transfer is finished */
 142         while ((ch_stat = ioread32(regs + TSI721_DMAC_STS))
 143                                                         & TSI721_DMAC_STS_RUN) {
 144                 udelay(1);
 145                 if (++i >= 5000000) {
 146                         dev_dbg(&priv->pdev->dev,
 147                                 "%s : DMA[%d] read timeout ch_status=%x\n",
 148                                 __func__, priv->mdma.ch_id, ch_stat);
 149                         if (!do_wr)
 150                                 *data = 0xffffffff;
 151                         err = -EIO;
 152                         goto err_out;
 153                 }
 154         }
 155
 156         if (ch_stat & TSI721_DMAC_STS_ABORT) {
 157                 /* If DMA operation aborted due to error,
 158                  * reinitialize DMA channel
 159                  */
 160                 dev_dbg(&priv->pdev->dev, "%s : DMA ABORT ch_stat=%x\n",
 161                         __func__, ch_stat);
 162                 dev_dbg(&priv->pdev->dev, "OP=%d : destid=%x hc=%x off=%x\n",
 163                         do_wr ? MAINT_WR : MAINT_RD, destid, hopcount, offset);
 164                 iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
 165                 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
 166                 udelay(10);
 167                 iowrite32(0, regs + TSI721_DMAC_DWRCNT);
 168                 udelay(1);
 169                 if (!do_wr)
 170                         *data = 0xffffffff;
 171                 err = -EIO;
 172                 goto err_out;
 173         }
 174
 175         if (!do_wr)
 176                 *data = be32_to_cpu(bd_ptr[0].data[0]);
 177
 178         /*
 179          * Update descriptor status FIFO RD pointer.
 180          * NOTE: Skipping check and clear FIFO entries because we are waiting
 181          * for transfer to be completed.
 182          */
 183         swr_ptr = ioread32(regs + TSI721_DMAC_DSWP);
 184         iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP);
 185 err_out:
 186
 187         return err;
 188 }
 189
 190 /**
 191  * tsi721_cread_dma - Generate a RapidIO maintenance read transaction
 192  *                    using Tsi721 BDMA engine.
 193  * @mport: RapidIO master port control structure
 194  * @index: ID of RapdiIO interface
 195  * @destid: Destination ID of transaction
 196  * @hopcount: Number of hops to target device
 197  * @offset: Offset into configuration space
 198  * @len: Length (in bytes) of the maintenance transaction
 199  * @val: Location to be read into
 200  *
 201  * Generates a RapidIO maintenance read transaction.
 202  * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
 203  */
 204 static int tsi721_cread_dma(struct rio_mport *mport, int index, u16 destid,
 205                         u8 hopcount, u32 offset, int len, u32 *data)
 206 {
 207         struct tsi721_device *priv = mport->priv;
 208
 209         return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
 210                                 offset, len, data, 0);
 211 }
 212
 213 /**
 214  * tsi721_cwrite_dma - Generate a RapidIO maintenance write transaction
 215  *                     using Tsi721 BDMA engine
 216  * @mport: RapidIO master port control structure
 217  * @index: ID of RapdiIO interface
 218  * @destid: Destination ID of transaction
 219  * @hopcount: Number of hops to target device
 220  * @offset: Offset into configuration space
 221  * @len: Length (in bytes) of the maintenance transaction
 222  * @val: Value to be written
 223  *
 224  * Generates a RapidIO maintenance write transaction.
 225  * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
 226  */
 227 static int tsi721_cwrite_dma(struct rio_mport *mport, int index, u16 destid,
 228                          u8 hopcount, u32 offset, int len, u32 data)
 229 {
 230         struct tsi721_device *priv = mport->priv;
 231         u32 temp = data;
 232
 233         return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
 234                                 offset, len, &temp, 1);
 235 }
 236
 237 /**
 238  * tsi721_pw_handler - Tsi721 inbound port-write interrupt handler
 239  * @priv:  tsi721 device private structure
 240  *
 241  * Handles inbound port-write interrupts. Copies PW message from an internal
 242  * buffer into PW message FIFO and schedules deferred routine to process
 243  * queued messages.
 244  */
 245 static int
 246 tsi721_pw_handler(struct tsi721_device *priv)
 247 {
 248         u32 pw_stat;
 249         u32 pw_buf[TSI721_RIO_PW_MSG_SIZE/sizeof(u32)];
 250
 251
 252         pw_stat = ioread32(priv->regs + TSI721_RIO_PW_RX_STAT);
 253
 254         if (pw_stat & TSI721_RIO_PW_RX_STAT_PW_VAL) {
 255                 pw_buf[0] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(0));
 256                 pw_buf[1] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(1));
 257                 pw_buf[2] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(2));
 258                 pw_buf[3] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(3));
 259
 260                 /* Queue PW message (if there is room in FIFO),
 261                  * otherwise discard it.
 262                  */
 263                 spin_lock(&priv->pw_fifo_lock);
 264                 if (kfifo_avail(&priv->pw_fifo) >= TSI721_RIO_PW_MSG_SIZE)
 265                         kfifo_in(&priv->pw_fifo, pw_buf,
 266                                                 TSI721_RIO_PW_MSG_SIZE);
 267                 else
 268                         priv->pw_discard_count++;
 269                 spin_unlock(&priv->pw_fifo_lock);
 270         }
 271
 272         /* Clear pending PW interrupts */
 273         iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
 274                   priv->regs + TSI721_RIO_PW_RX_STAT);
 275
 276         schedule_work(&priv->pw_work);
 277
 278         return 0;
 279 }
 280
 281 static void tsi721_pw_dpc(struct work_struct *work)
 282 {
 283         struct tsi721_device *priv = container_of(work, struct tsi721_device,
 284                                                     pw_work);
 285         u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; /* Use full size PW message
 286                                                         buffer for RIO layer */
 287
 288         /*
 289          * Process port-write messages
 290          */
 291         while (kfifo_out_spinlocked(&priv->pw_fifo, (unsigned char *)msg_buffer,
 292                          TSI721_RIO_PW_MSG_SIZE, &priv->pw_fifo_lock)) {
 293                 /* Process one message */
 294 #ifdef DEBUG_PW
 295                 {
 296                 u32 i;
 297                 pr_debug("%s : Port-Write Message:", __func__);
 298                 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); ) {
 299                         pr_debug("0x%02x: %08x %08x %08x %08x", i*4,
 300                                 msg_buffer[i], msg_buffer[i + 1],
 301                                 msg_buffer[i + 2], msg_buffer[i + 3]);
 302                         i += 4;
 303                 }
 304                 pr_debug("\n");
 305                 }
 306 #endif
 307                 /* Pass the port-write message to RIO core for processing */
 308                 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
 309         }
 310 }
 311
 312 /**
 313  * tsi721_pw_enable - enable/disable port-write interface init
 314  * @mport: Master port implementing the port write unit
 315  * @enable:    1=enable; 0=disable port-write message handling
 316  */
 317 static int tsi721_pw_enable(struct rio_mport *mport, int enable)
 318 {
 319         struct tsi721_device *priv = mport->priv;
 320         u32 rval;
 321
 322         rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE);
 323
 324         if (enable)
 325                 rval |= TSI721_RIO_EM_INT_ENABLE_PW_RX;
 326         else
 327                 rval &= ~TSI721_RIO_EM_INT_ENABLE_PW_RX;
 328
 329         /* Clear pending PW interrupts */
 330         iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
 331                   priv->regs + TSI721_RIO_PW_RX_STAT);
 332         /* Update enable bits */
 333         iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE);
 334
 335         return 0;
 336 }
 337
 338 /**
 339  * tsi721_dsend - Send a RapidIO doorbell
 340  * @mport: RapidIO master port info
 341  * @index: ID of RapidIO interface
 342  * @destid: Destination ID of target device
 343  * @data: 16-bit info field of RapidIO doorbell
 344  *
 345  * Sends a RapidIO doorbell message. Always returns %0.
 346  */
 347 static int tsi721_dsend(struct rio_mport *mport, int index,
 348                         u16 destid, u16 data)
 349 {
 350         struct tsi721_device *priv = mport->priv;
 351         u32 offset;
 352
 353         offset = (((mport->sys_size) ? RIO_TT_CODE_16 : RIO_TT_CODE_8) << 18) |
 354                  (destid << 2);
 355
 356         dev_dbg(&priv->pdev->dev,
 357                 "Send Doorbell 0x%04x to destID 0x%x\n", data, destid);
 358         iowrite16be(data, priv->odb_base + offset);
 359
 360         return 0;
 361 }
 362
 363 /**
 364  * tsi721_dbell_handler - Tsi721 doorbell interrupt handler
 365  * @priv: tsi721 device-specific data structure
 366  *
 367  * Handles inbound doorbell interrupts. Copies doorbell entry from an internal
 368  * buffer into DB message FIFO and schedules deferred  routine to process
 369  * queued DBs.
 370  */
 371 static int
 372 tsi721_dbell_handler(struct tsi721_device *priv)
 373 {
 374         u32 regval;
 375
 376         /* Disable IDB interrupts */
 377         regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 378         regval &= ~TSI721_SR_CHINT_IDBQRCV;
 379         iowrite32(regval,
 380                 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 381
 382         schedule_work(&priv->idb_work);
 383
 384         return 0;
 385 }
 386
 387 static void tsi721_db_dpc(struct work_struct *work)
 388 {
 389         struct tsi721_device *priv = container_of(work, struct tsi721_device,
 390                                                     idb_work);
 391         struct rio_mport *mport;
 392         struct rio_dbell *dbell;
 393         int found = 0;
 394         u32 wr_ptr, rd_ptr;
 395         u64 *idb_entry;
 396         u32 regval;
 397         union {
 398                 u64 msg;
 399                 u8  bytes[8];
 400         } idb;
 401
 402         /*
 403          * Process queued inbound doorbells
 404          */
 405         mport = &priv->mport;
 406
 407         wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
 408         rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)) % IDB_QSIZE;
 409
 410         while (wr_ptr != rd_ptr) {
 411                 idb_entry = (u64 *)(priv->idb_base +
 412                                         (TSI721_IDB_ENTRY_SIZE * rd_ptr));
 413                 rd_ptr++;
 414                 rd_ptr %= IDB_QSIZE;
 415                 idb.msg = *idb_entry;
 416                 *idb_entry = 0;
 417
 418                 /* Process one doorbell */
 419                 list_for_each_entry(dbell, &mport->dbells, node) {
 420                         if ((dbell->res->start <= DBELL_INF(idb.bytes)) &&
 421                             (dbell->res->end >= DBELL_INF(idb.bytes))) {
 422                                 found = 1;
 423                                 break;
 424                         }
 425                 }
 426
 427                 if (found) {
 428                         dbell->dinb(mport, dbell->dev_id, DBELL_SID(idb.bytes),
 429                                     DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
 430                 } else {
 431                         dev_dbg(&priv->pdev->dev,
 432                                 "spurious inb doorbell, sid %2.2x tid %2.2x"
 433                                 " info %4.4x\n", DBELL_SID(idb.bytes),
 434                                 DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
 435                 }
 436
 437                 wr_ptr = ioread32(priv->regs +
 438                                   TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
 439         }
 440
 441         iowrite32(rd_ptr & (IDB_QSIZE - 1),
 442                 priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
 443
 444         /* Re-enable IDB interrupts */
 445         regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 446         regval |= TSI721_SR_CHINT_IDBQRCV;
 447         iowrite32(regval,
 448                 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 449
 450         wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
 451         if (wr_ptr != rd_ptr)
 452                 schedule_work(&priv->idb_work);
 453 }
 454
 455 /**
 456  * tsi721_irqhandler - Tsi721 interrupt handler
 457  * @irq: Linux interrupt number
 458  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 459  *
 460  * Handles Tsi721 interrupts signaled using MSI and INTA. Checks reported
 461  * interrupt events and calls an event-specific handler(s).
 462  */
 463 static irqreturn_t tsi721_irqhandler(int irq, void *ptr)
 464 {
 465         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 466         u32 dev_int;
 467         u32 dev_ch_int;
 468         u32 intval;
 469         u32 ch_inte;
 470
 471         /* For MSI mode disable all device-level interrupts */
 472         if (priv->flags & TSI721_USING_MSI)
 473                 iowrite32(0, priv->regs + TSI721_DEV_INTE);
 474
 475         dev_int = ioread32(priv->regs + TSI721_DEV_INT);
 476         if (!dev_int)
 477                 return IRQ_NONE;
 478
 479         dev_ch_int = ioread32(priv->regs + TSI721_DEV_CHAN_INT);
 480
 481         if (dev_int & TSI721_DEV_INT_SR2PC_CH) {
 482                 /* Service SR2PC Channel interrupts */
 483                 if (dev_ch_int & TSI721_INT_SR2PC_CHAN(IDB_QUEUE)) {
 484                         /* Service Inbound Doorbell interrupt */
 485                         intval = ioread32(priv->regs +
 486                                                 TSI721_SR_CHINT(IDB_QUEUE));
 487                         if (intval & TSI721_SR_CHINT_IDBQRCV)
 488                                 tsi721_dbell_handler(priv);
 489                         else
 490                                 dev_info(&priv->pdev->dev,
 491                                         "Unsupported SR_CH_INT %x\n", intval);
 492
 493                         /* Clear interrupts */
 494                         iowrite32(intval,
 495                                 priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 496                         ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 497                 }
 498         }
 499
 500         if (dev_int & TSI721_DEV_INT_SMSG_CH) {
 501                 int ch;
 502
 503                 /*
 504                  * Service channel interrupts from Messaging Engine
 505                  */
 506
 507                 if (dev_ch_int & TSI721_INT_IMSG_CHAN_M) { /* Inbound Msg */
 508                         /* Disable signaled OB MSG Channel interrupts */
 509                         ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
 510                         ch_inte &= ~(dev_ch_int & TSI721_INT_IMSG_CHAN_M);
 511                         iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
 512
 513                         /*
 514                          * Process Inbound Message interrupt for each MBOX
 515                          */
 516                         for (ch = 4; ch < RIO_MAX_MBOX + 4; ch++) {
 517                                 if (!(dev_ch_int & TSI721_INT_IMSG_CHAN(ch)))
 518                                         continue;
 519                                 tsi721_imsg_handler(priv, ch);
 520                         }
 521                 }
 522
 523                 if (dev_ch_int & TSI721_INT_OMSG_CHAN_M) { /* Outbound Msg */
 524                         /* Disable signaled OB MSG Channel interrupts */
 525                         ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
 526                         ch_inte &= ~(dev_ch_int & TSI721_INT_OMSG_CHAN_M);
 527                         iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
 528
 529                         /*
 530                          * Process Outbound Message interrupts for each MBOX
 531                          */
 532
 533                         for (ch = 0; ch < RIO_MAX_MBOX; ch++) {
 534                                 if (!(dev_ch_int & TSI721_INT_OMSG_CHAN(ch)))
 535                                         continue;
 536                                 tsi721_omsg_handler(priv, ch);
 537                         }
 538                 }
 539         }
 540
 541         if (dev_int & TSI721_DEV_INT_SRIO) {
 542                 /* Service SRIO MAC interrupts */
 543                 intval = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
 544                 if (intval & TSI721_RIO_EM_INT_STAT_PW_RX)
 545                         tsi721_pw_handler(priv);
 546         }
 547
 548 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
 549         if (dev_int & TSI721_DEV_INT_BDMA_CH) {
 550                 int ch;
 551
 552                 if (dev_ch_int & TSI721_INT_BDMA_CHAN_M) {
 553                         dev_dbg(&priv->pdev->dev,
 554                                 "IRQ from DMA channel 0x%08x\n", dev_ch_int);
 555
 556                         for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) {
 557                                 if (!(dev_ch_int & TSI721_INT_BDMA_CHAN(ch)))
 558                                         continue;
 559                                 tsi721_bdma_handler(&priv->bdma[ch]);
 560                         }
 561                 }
 562         }
 563 #endif
 564
 565         /* For MSI mode re-enable device-level interrupts */
 566         if (priv->flags & TSI721_USING_MSI) {
 567                 dev_int = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
 568                         TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH;
 569                 iowrite32(dev_int, priv->regs + TSI721_DEV_INTE);
 570         }
 571
 572         return IRQ_HANDLED;
 573 }
 574
 575 static void tsi721_interrupts_init(struct tsi721_device *priv)
 576 {
 577         u32 intr;
 578
 579         /* Enable IDB interrupts */
 580         iowrite32(TSI721_SR_CHINT_ALL,
 581                 priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 582         iowrite32(TSI721_SR_CHINT_IDBQRCV,
 583                 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 584
 585         /* Enable SRIO MAC interrupts */
 586         iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
 587                 priv->regs + TSI721_RIO_EM_DEV_INT_EN);
 588
 589         /* Enable interrupts from channels in use */
 590 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
 591         intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE) |
 592                 (TSI721_INT_BDMA_CHAN_M &
 593                  ~TSI721_INT_BDMA_CHAN(TSI721_DMACH_MAINT));
 594 #else
 595         intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE);
 596 #endif
 597         iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE);
 598
 599         if (priv->flags & TSI721_USING_MSIX)
 600                 intr = TSI721_DEV_INT_SRIO;
 601         else
 602                 intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
 603                         TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH;
 604
 605         iowrite32(intr, priv->regs + TSI721_DEV_INTE);
 606         ioread32(priv->regs + TSI721_DEV_INTE);
 607 }
 608
 609 #ifdef CONFIG_PCI_MSI
 610 /**
 611  * tsi721_omsg_msix - MSI-X interrupt handler for outbound messaging
 612  * @irq: Linux interrupt number
 613  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 614  *
 615  * Handles outbound messaging interrupts signaled using MSI-X.
 616  */
 617 static irqreturn_t tsi721_omsg_msix(int irq, void *ptr)
 618 {
 619         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 620         int mbox;
 621
 622         mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX;
 623         tsi721_omsg_handler(priv, mbox);
 624         return IRQ_HANDLED;
 625 }
 626
 627 /**
 628  * tsi721_imsg_msix - MSI-X interrupt handler for inbound messaging
 629  * @irq: Linux interrupt number
 630  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 631  *
 632  * Handles inbound messaging interrupts signaled using MSI-X.
 633  */
 634 static irqreturn_t tsi721_imsg_msix(int irq, void *ptr)
 635 {
 636         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 637         int mbox;
 638
 639         mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX;
 640         tsi721_imsg_handler(priv, mbox + 4);
 641         return IRQ_HANDLED;
 642 }
 643
 644 /**
 645  * tsi721_srio_msix - Tsi721 MSI-X SRIO MAC interrupt handler
 646  * @irq: Linux interrupt number
 647  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 648  *
 649  * Handles Tsi721 interrupts from SRIO MAC.
 650  */
 651 static irqreturn_t tsi721_srio_msix(int irq, void *ptr)
 652 {
 653         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 654         u32 srio_int;
 655
 656         /* Service SRIO MAC interrupts */
 657         srio_int = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
 658         if (srio_int & TSI721_RIO_EM_INT_STAT_PW_RX)
 659                 tsi721_pw_handler(priv);
 660
 661         return IRQ_HANDLED;
 662 }
 663
 664 /**
 665  * tsi721_sr2pc_ch_msix - Tsi721 MSI-X SR2PC Channel interrupt handler
 666  * @irq: Linux interrupt number
 667  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 668  *
 669  * Handles Tsi721 interrupts from SR2PC Channel.
 670  * NOTE: At this moment services only one SR2PC channel associated with inbound
 671  * doorbells.
 672  */
 673 static irqreturn_t tsi721_sr2pc_ch_msix(int irq, void *ptr)
 674 {
 675         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 676         u32 sr_ch_int;
 677
 678         /* Service Inbound DB interrupt from SR2PC channel */
 679         sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 680         if (sr_ch_int & TSI721_SR_CHINT_IDBQRCV)
 681                 tsi721_dbell_handler(priv);
 682
 683         /* Clear interrupts */
 684         iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 685         /* Read back to ensure that interrupt was cleared */
 686         sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 687
 688         return IRQ_HANDLED;
 689 }
 690
 691 /**
 692  * tsi721_request_msix - register interrupt service for MSI-X mode.
 693  * @priv: tsi721 device-specific data structure
 694  *
 695  * Registers MSI-X interrupt service routines for interrupts that are active
 696  * immediately after mport initialization. Messaging interrupt service routines
 697  * should be registered during corresponding open requests.
 698  */
 699 static int tsi721_request_msix(struct tsi721_device *priv)
 700 {
 701         int err = 0;
 702
 703         err = request_irq(priv->msix[TSI721_VECT_IDB].vector,
 704                         tsi721_sr2pc_ch_msix, 0,
 705                         priv->msix[TSI721_VECT_IDB].irq_name, (void *)priv);
 706         if (err)
 707                 return err;
 708
 709         err = request_irq(priv->msix[TSI721_VECT_PWRX].vector,
 710                         tsi721_srio_msix, 0,
 711                         priv->msix[TSI721_VECT_PWRX].irq_name, (void *)priv);
 712         if (err) {
 713                 free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv);
 714                 return err;
 715         }
 716
 717         return 0;
 718 }
 719
 720 /**
 721  * tsi721_enable_msix - Attempts to enable MSI-X support for Tsi721.
 722  * @priv: pointer to tsi721 private data
 723  *
 724  * Configures MSI-X support for Tsi721. Supports only an exact number
 725  * of requested vectors.
 726  */
 727 static int tsi721_enable_msix(struct tsi721_device *priv)
 728 {
 729         struct msix_entry entries[TSI721_VECT_MAX];
 730         int err;
 731         int i;
 732
 733         entries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE);
 734         entries[TSI721_VECT_PWRX].entry = TSI721_MSIX_SRIO_MAC_INT;
 735
 736         /*
 737          * Initialize MSI-X entries for Messaging Engine:
 738          * this driver supports four RIO mailboxes (inbound and outbound)
 739          * NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore
 740          * offset +4 is added to IB MBOX number.
 741          */
 742         for (i = 0; i < RIO_MAX_MBOX; i++) {
 743                 entries[TSI721_VECT_IMB0_RCV + i].entry =
 744                                         TSI721_MSIX_IMSG_DQ_RCV(i + 4);
 745                 entries[TSI721_VECT_IMB0_INT + i].entry =
 746                                         TSI721_MSIX_IMSG_INT(i + 4);
 747                 entries[TSI721_VECT_OMB0_DONE + i].entry =
 748                                         TSI721_MSIX_OMSG_DONE(i);
 749                 entries[TSI721_VECT_OMB0_INT + i].entry =
 750                                         TSI721_MSIX_OMSG_INT(i);
 751         }
 752
 753 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
 754         /*
 755          * Initialize MSI-X entries for Block DMA Engine:
 756          * this driver supports XXX DMA channels
 757          * (one is reserved for SRIO maintenance transactions)
 758          */
 759         for (i = 0; i < TSI721_DMA_CHNUM; i++) {
 760                 entries[TSI721_VECT_DMA0_DONE + i].entry =
 761                                         TSI721_MSIX_DMACH_DONE(i);
 762                 entries[TSI721_VECT_DMA0_INT + i].entry =
 763                                         TSI721_MSIX_DMACH_INT(i);
 764         }
 765 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
 766
 767         err = pci_enable_msix_exact(priv->pdev, entries, ARRAY_SIZE(entries));
 768         if (err) {
 769                 dev_err(&priv->pdev->dev,
 770                         "Failed to enable MSI-X (err=%d)\n", err);
 771                 return err;
 772         }
 773
 774         /*
 775          * Copy MSI-X vector information into tsi721 private structure
 776          */
 777         priv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector;
 778         snprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX,
 779                  DRV_NAME "-idb@pci:%s", pci_name(priv->pdev));
 780         priv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector;
 781         snprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX,
 782                  DRV_NAME "-pwrx@pci:%s", pci_name(priv->pdev));
 783
 784         for (i = 0; i < RIO_MAX_MBOX; i++) {
 785                 priv->msix[TSI721_VECT_IMB0_RCV + i].vector =
 786                                 entries[TSI721_VECT_IMB0_RCV + i].vector;
 787                 snprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name,
 788                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbr%d@pci:%s",
 789                          i, pci_name(priv->pdev));
 790
 791                 priv->msix[TSI721_VECT_IMB0_INT + i].vector =
 792                                 entries[TSI721_VECT_IMB0_INT + i].vector;
 793                 snprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name,
 794                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbi%d@pci:%s",
 795                          i, pci_name(priv->pdev));
 796
 797                 priv->msix[TSI721_VECT_OMB0_DONE + i].vector =
 798                                 entries[TSI721_VECT_OMB0_DONE + i].vector;
 799                 snprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name,
 800                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombd%d@pci:%s",
 801                          i, pci_name(priv->pdev));
 802
 803                 priv->msix[TSI721_VECT_OMB0_INT + i].vector =
 804                                 entries[TSI721_VECT_OMB0_INT + i].vector;
 805                 snprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name,
 806                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombi%d@pci:%s",
 807                          i, pci_name(priv->pdev));
 808         }
 809
 810 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
 811         for (i = 0; i < TSI721_DMA_CHNUM; i++) {
 812                 priv->msix[TSI721_VECT_DMA0_DONE + i].vector =
 813                                 entries[TSI721_VECT_DMA0_DONE + i].vector;
 814                 snprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name,
 815                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmad%d@pci:%s",
 816                          i, pci_name(priv->pdev));
 817
 818                 priv->msix[TSI721_VECT_DMA0_INT + i].vector =
 819                                 entries[TSI721_VECT_DMA0_INT + i].vector;
 820                 snprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name,
 821                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmai%d@pci:%s",
 822                          i, pci_name(priv->pdev));
 823         }
 824 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
 825
 826         return 0;
 827 }
 828 #endif /* CONFIG_PCI_MSI */
 829
 830 static int tsi721_request_irq(struct tsi721_device *priv)
 831 {
 832         int err;
 833
 834 #ifdef CONFIG_PCI_MSI
 835         if (priv->flags & TSI721_USING_MSIX)
 836                 err = tsi721_request_msix(priv);
 837         else
 838 #endif
 839                 err = request_irq(priv->pdev->irq, tsi721_irqhandler,
 840                           (priv->flags & TSI721_USING_MSI) ? 0 : IRQF_SHARED,
 841                           DRV_NAME, (void *)priv);
 842
 843         if (err)
 844                 dev_err(&priv->pdev->dev,
 845                         "Unable to allocate interrupt, Error: %d\n", err);
 846
 847         return err;
 848 }
 849
 850 static void tsi721_free_irq(struct tsi721_device *priv)
 851 {
 852 #ifdef CONFIG_PCI_MSI
 853         if (priv->flags & TSI721_USING_MSIX) {
 854                 free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv);
 855                 free_irq(priv->msix[TSI721_VECT_PWRX].vector, (void *)priv);
 856         } else
 857 #endif
 858         free_irq(priv->pdev->irq, (void *)priv);
 859 }
 860
 861 /**
 862  * tsi721_init_pc2sr_mapping - initializes outbound (PCIe->SRIO)
 863  * translation regions.
 864  * @priv: pointer to tsi721 private data
 865  *
 866  * Disables SREP translation regions.
 867  */
 868 static void tsi721_init_pc2sr_mapping(struct tsi721_device *priv)
 869 {
 870         int i;
 871
 872         /* Disable all PC2SR translation windows */
 873         for (i = 0; i < TSI721_OBWIN_NUM; i++)
 874                 iowrite32(0, priv->regs + TSI721_OBWINLB(i));
 875 }
 876
 877 /**
 878  * tsi721_rio_map_inb_mem -- Mapping inbound memory region.
 879  * @mport: RapidIO master port
 880  * @lstart: Local memory space start address.
 881  * @rstart: RapidIO space start address.
 882  * @size: The mapping region size.
 883  * @flags: Flags for mapping. 0 for using default flags.
 884  *
 885  * Return: 0 -- Success.
 886  *
 887  * This function will create the inbound mapping
 888  * from rstart to lstart.
 889  */
 890 static int tsi721_rio_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
 891                 u64 rstart, u32 size, u32 flags)
 892 {
 893         struct tsi721_device *priv = mport->priv;
 894         int i, avail = -1;
 895         u32 regval;
 896         struct tsi721_ib_win *ib_win;
 897         bool direct = (lstart == rstart);
 898         u64 ibw_size;
 899         dma_addr_t loc_start;
 900         u64 ibw_start;
 901         struct tsi721_ib_win_mapping *map = NULL;
 902         int ret = -EBUSY;
 903
 904         if (direct) {
 905                 dev_dbg(&priv->pdev->dev,
 906                         "Direct (RIO_0x%llx -> PCIe_0x%pad), size=0x%x",
 907                         rstart, &lstart, size);
 908
 909                 /* Calculate minimal acceptable window size and base address */
 910
 911                 ibw_size = roundup_pow_of_two(size);
 912                 ibw_start = lstart & ~(ibw_size - 1);
 913
 914                 while ((lstart + size) > (ibw_start + ibw_size)) {
 915                         ibw_size *= 2;
 916                         ibw_start = lstart & ~(ibw_size - 1);
 917                         if (ibw_size > 0x80000000) { /* Limit max size to 2GB */
 918                                 return -EBUSY;
 919                         }
 920                 }
 921
 922                 loc_start = ibw_start;
 923
 924                 map = kzalloc(sizeof(struct tsi721_ib_win_mapping), GFP_ATOMIC);
 925                 if (map == NULL)
 926                         return -ENOMEM;
 927
 928         } else {
 929                 dev_dbg(&priv->pdev->dev,
 930                         "Translated (RIO_0x%llx -> PCIe_0x%pad), size=0x%x",
 931                         rstart, &lstart, size);
 932
 933                 if (!is_power_of_2(size) || size < 0x1000 ||
 934                     ((u64)lstart & (size - 1)) || (rstart & (size - 1)))
 935                         return -EINVAL;
 936                 if (priv->ibwin_cnt == 0)
 937                         return -EBUSY;
 938                 ibw_start = rstart;
 939                 ibw_size = size;
 940                 loc_start = lstart;
 941         }
 942
 943         /*
 944          * Scan for overlapping with active regions and mark the first available
 945          * IB window at the same time.
 946          */
 947         for (i = 0; i < TSI721_IBWIN_NUM; i++) {
 948                 ib_win = &priv->ib_win[i];
 949
 950                 if (!ib_win->active) {
 951                         if (avail == -1) {
 952                                 avail = i;
 953                                 ret = 0;
 954                         }
 955                 } else if (ibw_start < (ib_win->rstart + ib_win->size) &&
 956                            (ibw_start + ibw_size) > ib_win->rstart) {
 957                         /* Return error if address translation involved */
 958                         if (direct && ib_win->xlat) {
 959                                 ret = -EFAULT;
 960                                 break;
 961                         }
 962
 963                         /*
 964                          * Direct mappings usually are larger than originally
 965                          * requested fragments - check if this new request fits
 966                          * into it.
 967                          */
 968                         if (rstart >= ib_win->rstart &&
 969                             (rstart + size) <= (ib_win->rstart +
 970                                                         ib_win->size)) {
 971                                 /* We are in - no further mapping required */
 972                                 map->lstart = lstart;
 973                                 list_add_tail(&map->node, &ib_win->mappings);
 974                                 return 0;
 975                         }
 976
 977                         ret = -EFAULT;
 978                         break;
 979                 }
 980         }
 981
 982         if (ret)
 983                 goto out;
 984         i = avail;
 985
 986         /* Sanity check: available IB window must be disabled at this point */
 987         regval = ioread32(priv->regs + TSI721_IBWIN_LB(i));
 988         if (WARN_ON(regval & TSI721_IBWIN_LB_WEN)) {
 989                 ret = -EIO;
 990                 goto out;
 991         }
 992
 993         ib_win = &priv->ib_win[i];
 994         ib_win->active = true;
 995         ib_win->rstart = ibw_start;
 996         ib_win->lstart = loc_start;
 997         ib_win->size = ibw_size;
 998         ib_win->xlat = (lstart != rstart);
 999         INIT_LIST_HEAD(&ib_win->mappings);
1000
1001         /*
1002          * When using direct IBW mapping and have larger than requested IBW size
1003          * we can have multiple local memory blocks mapped through the same IBW
1004          * To handle this situation we maintain list of "clients" for such IBWs.
1005          */
1006         if (direct) {
1007                 map->lstart = lstart;
1008                 list_add_tail(&map->node, &ib_win->mappings);
1009         }
1010
1011         iowrite32(TSI721_IBWIN_SIZE(ibw_size) << 8,
1012                         priv->regs + TSI721_IBWIN_SZ(i));
1013
1014         iowrite32(((u64)loc_start >> 32), priv->regs + TSI721_IBWIN_TUA(i));
1015         iowrite32(((u64)loc_start & TSI721_IBWIN_TLA_ADD),
1016                   priv->regs + TSI721_IBWIN_TLA(i));
1017
1018         iowrite32(ibw_start >> 32, priv->regs + TSI721_IBWIN_UB(i));
1019         iowrite32((ibw_start & TSI721_IBWIN_LB_BA) | TSI721_IBWIN_LB_WEN,
1020                 priv->regs + TSI721_IBWIN_LB(i));
1021
1022         priv->ibwin_cnt--;
1023
1024         dev_dbg(&priv->pdev->dev,
1025                 "Configured IBWIN%d (RIO_0x%llx -> PCIe_0x%llx), size=0x%llx\n",
1026                 i, ibw_start, (unsigned long long)loc_start, ibw_size);
1027
1028         return 0;
1029 out:
1030         kfree(map);
1031         return ret;
1032 }
1033
1034 /**
1035  * tsi721_rio_unmap_inb_mem -- Unmapping inbound memory region.
1036  * @mport: RapidIO master port
1037  * @lstart: Local memory space start address.
1038  */
1039 static void tsi721_rio_unmap_inb_mem(struct rio_mport *mport,
1040                                 dma_addr_t lstart)
1041 {
1042         struct tsi721_device *priv = mport->priv;
1043         struct tsi721_ib_win *ib_win;
1044         int i;
1045
1046         dev_dbg(&priv->pdev->dev,
1047                 "Unmap IBW mapped to PCIe_0x%pad", &lstart);
1048
1049         /* Search for matching active inbound translation window */
1050         for (i = 0; i < TSI721_IBWIN_NUM; i++) {
1051                 ib_win = &priv->ib_win[i];
1052
1053                 /* Address translating IBWs must to be an exact march */
1054                 if (!ib_win->active ||
1055                     (ib_win->xlat && lstart != ib_win->lstart))
1056                         continue;
1057
1058                 if (lstart >= ib_win->lstart &&
1059                     lstart < (ib_win->lstart + ib_win->size)) {
1060
1061                         if (!ib_win->xlat) {
1062                                 struct tsi721_ib_win_mapping *map;
1063                                 int found = 0;
1064
1065                                 list_for_each_entry(map,
1066                                                     &ib_win->mappings, node) {
1067                                         if (map->lstart == lstart) {
1068                                                 list_del(&map->node);
1069                                                 kfree(map);
1070                                                 found = 1;
1071                                                 break;
1072                                         }
1073                                 }
1074
1075                                 if (!found)
1076                                         continue;
1077
1078                                 if (!list_empty(&ib_win->mappings))
1079                                         break;
1080                         }
1081
1082                         dev_dbg(&priv->pdev->dev, "Disable IBWIN_%d", i);
1083                         iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1084                         ib_win->active = false;
1085                         priv->ibwin_cnt++;
1086                         break;
1087                 }
1088         }
1089
1090         if (i == TSI721_IBWIN_NUM)
1091                 dev_dbg(&priv->pdev->dev,
1092                         "IB window mapped to %pad not found", &lstart);
1093 }
1094
1095 /**
1096  * tsi721_init_sr2pc_mapping - initializes inbound (SRIO->PCIe)
1097  * translation regions.
1098  * @priv: pointer to tsi721 private data
1099  *
1100  * Disables inbound windows.
1101  */
1102 static void tsi721_init_sr2pc_mapping(struct tsi721_device *priv)
1103 {
1104         int i;
1105
1106         /* Disable all SR2PC inbound windows */
1107         for (i = 0; i < TSI721_IBWIN_NUM; i++)
1108                 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1109         priv->ibwin_cnt = TSI721_IBWIN_NUM;
1110 }
1111
1112 /*
1113  * tsi721_close_sr2pc_mapping - closes all active inbound (SRIO->PCIe)
1114  * translation regions.
1115  * @priv: pointer to tsi721 device private data
1116  */
1117 static void tsi721_close_sr2pc_mapping(struct tsi721_device *priv)
1118 {
1119         struct tsi721_ib_win *ib_win;
1120         int i;
1121
1122         /* Disable all active SR2PC inbound windows */
1123         for (i = 0; i < TSI721_IBWIN_NUM; i++) {
1124                 ib_win = &priv->ib_win[i];
1125                 if (ib_win->active) {
1126                         iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1127                         ib_win->active = false;
1128                 }
1129         }
1130 }
1131
1132 /**
1133  * tsi721_port_write_init - Inbound port write interface init
1134  * @priv: pointer to tsi721 private data
1135  *
1136  * Initializes inbound port write handler.
1137  * Returns %0 on success or %-ENOMEM on failure.
1138  */
1139 static int tsi721_port_write_init(struct tsi721_device *priv)
1140 {
1141         priv->pw_discard_count = 0;
1142         INIT_WORK(&priv->pw_work, tsi721_pw_dpc);
1143         spin_lock_init(&priv->pw_fifo_lock);
1144         if (kfifo_alloc(&priv->pw_fifo,
1145                         TSI721_RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1146                 dev_err(&priv->pdev->dev, "PW FIFO allocation failed\n");
1147                 return -ENOMEM;
1148         }
1149
1150         /* Use reliable port-write capture mode */
1151         iowrite32(TSI721_RIO_PW_CTL_PWC_REL, priv->regs + TSI721_RIO_PW_CTL);
1152         return 0;
1153 }
1154
1155 static void tsi721_port_write_free(struct tsi721_device *priv)
1156 {
1157         kfifo_free(&priv->pw_fifo);
1158 }
1159
1160 static int tsi721_doorbell_init(struct tsi721_device *priv)
1161 {
1162         /* Outbound Doorbells do not require any setup.
1163          * Tsi721 uses dedicated PCI BAR1 to generate doorbells.
1164          * That BAR1 was mapped during the probe routine.
1165          */
1166
1167         /* Initialize Inbound Doorbell processing DPC and queue */
1168         priv->db_discard_count = 0;
1169         INIT_WORK(&priv->idb_work, tsi721_db_dpc);
1170
1171         /* Allocate buffer for inbound doorbells queue */
1172         priv->idb_base = dma_zalloc_coherent(&priv->pdev->dev,
1173                                 IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
1174                                 &priv->idb_dma, GFP_KERNEL);
1175         if (!priv->idb_base)
1176                 return -ENOMEM;
1177
1178         dev_dbg(&priv->pdev->dev, "Allocated IDB buffer @ %p (phys = %llx)\n",
1179                 priv->idb_base, (unsigned long long)priv->idb_dma);
1180
1181         iowrite32(TSI721_IDQ_SIZE_VAL(IDB_QSIZE),
1182                 priv->regs + TSI721_IDQ_SIZE(IDB_QUEUE));
1183         iowrite32(((u64)priv->idb_dma >> 32),
1184                 priv->regs + TSI721_IDQ_BASEU(IDB_QUEUE));
1185         iowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR),
1186                 priv->regs + TSI721_IDQ_BASEL(IDB_QUEUE));
1187         /* Enable accepting all inbound doorbells */
1188         iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE));
1189
1190         iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE));
1191
1192         iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
1193
1194         return 0;
1195 }
1196
1197 static void tsi721_doorbell_free(struct tsi721_device *priv)
1198 {
1199         if (priv->idb_base == NULL)
1200                 return;
1201
1202         /* Free buffer allocated for inbound doorbell queue */
1203         dma_free_coherent(&priv->pdev->dev, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
1204                           priv->idb_base, priv->idb_dma);
1205         priv->idb_base = NULL;
1206 }
1207
1208 /**
1209  * tsi721_bdma_maint_init - Initialize maintenance request BDMA channel.
1210  * @priv: pointer to tsi721 private data
1211  *
1212  * Initialize BDMA channel allocated for RapidIO maintenance read/write
1213  * request generation
1214  * Returns %0 on success or %-ENOMEM on failure.
1215  */
1216 static int tsi721_bdma_maint_init(struct tsi721_device *priv)
1217 {
1218         struct tsi721_dma_desc *bd_ptr;
1219         u64             *sts_ptr;
1220         dma_addr_t      bd_phys, sts_phys;
1221         int             sts_size;
1222         int             bd_num = 2;
1223         void __iomem    *regs;
1224
1225         dev_dbg(&priv->pdev->dev,
1226                 "Init Block DMA Engine for Maintenance requests, CH%d\n",
1227                 TSI721_DMACH_MAINT);
1228
1229         /*
1230          * Initialize DMA channel for maintenance requests
1231          */
1232
1233         priv->mdma.ch_id = TSI721_DMACH_MAINT;
1234         regs = priv->regs + TSI721_DMAC_BASE(TSI721_DMACH_MAINT);
1235
1236         /* Allocate space for DMA descriptors */
1237         bd_ptr = dma_zalloc_coherent(&priv->pdev->dev,
1238                                         bd_num * sizeof(struct tsi721_dma_desc),
1239                                         &bd_phys, GFP_KERNEL);
1240         if (!bd_ptr)
1241                 return -ENOMEM;
1242
1243         priv->mdma.bd_num = bd_num;
1244         priv->mdma.bd_phys = bd_phys;
1245         priv->mdma.bd_base = bd_ptr;
1246
1247         dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n",
1248                 bd_ptr, (unsigned long long)bd_phys);
1249
1250         /* Allocate space for descriptor status FIFO */
1251         sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ?
1252                                         bd_num : TSI721_DMA_MINSTSSZ;
1253         sts_size = roundup_pow_of_two(sts_size);
1254         sts_ptr = dma_zalloc_coherent(&priv->pdev->dev,
1255                                      sts_size * sizeof(struct tsi721_dma_sts),
1256                                      &sts_phys, GFP_KERNEL);
1257         if (!sts_ptr) {
1258                 /* Free space allocated for DMA descriptors */
1259                 dma_free_coherent(&priv->pdev->dev,
1260                                   bd_num * sizeof(struct tsi721_dma_desc),
1261                                   bd_ptr, bd_phys);
1262                 priv->mdma.bd_base = NULL;
1263                 return -ENOMEM;
1264         }
1265
1266         priv->mdma.sts_phys = sts_phys;
1267         priv->mdma.sts_base = sts_ptr;
1268         priv->mdma.sts_size = sts_size;
1269
1270         dev_dbg(&priv->pdev->dev,
1271                 "desc status FIFO @ %p (phys = %llx) size=0x%x\n",
1272                 sts_ptr, (unsigned long long)sts_phys, sts_size);
1273
1274         /* Initialize DMA descriptors ring */
1275         bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29);
1276         bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys &
1277                                                  TSI721_DMAC_DPTRL_MASK);
1278         bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
1279
1280         /* Setup DMA descriptor pointers */
1281         iowrite32(((u64)bd_phys >> 32), regs + TSI721_DMAC_DPTRH);
1282         iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
1283                 regs + TSI721_DMAC_DPTRL);
1284
1285         /* Setup descriptor status FIFO */
1286         iowrite32(((u64)sts_phys >> 32), regs + TSI721_DMAC_DSBH);
1287         iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
1288                 regs + TSI721_DMAC_DSBL);
1289         iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
1290                 regs + TSI721_DMAC_DSSZ);
1291
1292         /* Clear interrupt bits */
1293         iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
1294
1295         ioread32(regs + TSI721_DMAC_INT);
1296
1297         /* Toggle DMA channel initialization */
1298         iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
1299         ioread32(regs + TSI721_DMAC_CTL);
1300         udelay(10);
1301
1302         return 0;
1303 }
1304
1305 static int tsi721_bdma_maint_free(struct tsi721_device *priv)
1306 {
1307         u32 ch_stat;
1308         struct tsi721_bdma_maint *mdma = &priv->mdma;
1309         void __iomem *regs = priv->regs + TSI721_DMAC_BASE(mdma->ch_id);
1310
1311         if (mdma->bd_base == NULL)
1312                 return 0;
1313
1314         /* Check if DMA channel still running */
1315         ch_stat = ioread32(regs + TSI721_DMAC_STS);
1316         if (ch_stat & TSI721_DMAC_STS_RUN)
1317                 return -EFAULT;
1318
1319         /* Put DMA channel into init state */
1320         iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
1321
1322         /* Free space allocated for DMA descriptors */
1323         dma_free_coherent(&priv->pdev->dev,
1324                 mdma->bd_num * sizeof(struct tsi721_dma_desc),
1325                 mdma->bd_base, mdma->bd_phys);
1326         mdma->bd_base = NULL;
1327
1328         /* Free space allocated for status FIFO */
1329         dma_free_coherent(&priv->pdev->dev,
1330                 mdma->sts_size * sizeof(struct tsi721_dma_sts),
1331                 mdma->sts_base, mdma->sts_phys);
1332         mdma->sts_base = NULL;
1333         return 0;
1334 }
1335
1336 /* Enable Inbound Messaging Interrupts */
1337 static void
1338 tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch,
1339                                   u32 inte_mask)
1340 {
1341         u32 rval;
1342
1343         if (!inte_mask)
1344                 return;
1345
1346         /* Clear pending Inbound Messaging interrupts */
1347         iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1348
1349         /* Enable Inbound Messaging interrupts */
1350         rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1351         iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch));
1352
1353         if (priv->flags & TSI721_USING_MSIX)
1354                 return; /* Finished if we are in MSI-X mode */
1355
1356         /*
1357          * For MSI and INTA interrupt signalling we need to enable next levels
1358          */
1359
1360         /* Enable Device Channel Interrupt */
1361         rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1362         iowrite32(rval | TSI721_INT_IMSG_CHAN(ch),
1363                   priv->regs + TSI721_DEV_CHAN_INTE);
1364 }
1365
1366 /* Disable Inbound Messaging Interrupts */
1367 static void
1368 tsi721_imsg_interrupt_disable(struct tsi721_device *priv, int ch,
1369                                    u32 inte_mask)
1370 {
1371         u32 rval;
1372
1373         if (!inte_mask)
1374                 return;
1375
1376         /* Clear pending Inbound Messaging interrupts */
1377         iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1378
1379         /* Disable Inbound Messaging interrupts */
1380         rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1381         rval &= ~inte_mask;
1382         iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch));
1383
1384         if (priv->flags & TSI721_USING_MSIX)
1385                 return; /* Finished if we are in MSI-X mode */
1386
1387         /*
1388          * For MSI and INTA interrupt signalling we need to disable next levels
1389          */
1390
1391         /* Disable Device Channel Interrupt */
1392         rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1393         rval &= ~TSI721_INT_IMSG_CHAN(ch);
1394         iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1395 }
1396
1397 /* Enable Outbound Messaging interrupts */
1398 static void
1399 tsi721_omsg_interrupt_enable(struct tsi721_device *priv, int ch,
1400                                   u32 inte_mask)
1401 {
1402         u32 rval;
1403
1404         if (!inte_mask)
1405                 return;
1406
1407         /* Clear pending Outbound Messaging interrupts */
1408         iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1409
1410         /* Enable Outbound Messaging channel interrupts */
1411         rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1412         iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch));
1413
1414         if (priv->flags & TSI721_USING_MSIX)
1415                 return; /* Finished if we are in MSI-X mode */
1416
1417         /*
1418          * For MSI and INTA interrupt signalling we need to enable next levels
1419          */
1420
1421         /* Enable Device Channel Interrupt */
1422         rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1423         iowrite32(rval | TSI721_INT_OMSG_CHAN(ch),
1424                   priv->regs + TSI721_DEV_CHAN_INTE);
1425 }
1426
1427 /* Disable Outbound Messaging interrupts */
1428 static void
1429 tsi721_omsg_interrupt_disable(struct tsi721_device *priv, int ch,
1430                                    u32 inte_mask)
1431 {
1432         u32 rval;
1433
1434         if (!inte_mask)
1435                 return;
1436
1437         /* Clear pending Outbound Messaging interrupts */
1438         iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1439
1440         /* Disable Outbound Messaging interrupts */
1441         rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1442         rval &= ~inte_mask;
1443         iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch));
1444
1445         if (priv->flags & TSI721_USING_MSIX)
1446                 return; /* Finished if we are in MSI-X mode */
1447
1448         /*
1449          * For MSI and INTA interrupt signalling we need to disable next levels
1450          */
1451
1452         /* Disable Device Channel Interrupt */
1453         rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1454         rval &= ~TSI721_INT_OMSG_CHAN(ch);
1455         iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1456 }
1457
1458 /**
1459  * tsi721_add_outb_message - Add message to the Tsi721 outbound message queue
1460  * @mport: Master port with outbound message queue
1461  * @rdev: Target of outbound message
1462  * @mbox: Outbound mailbox
1463  * @buffer: Message to add to outbound queue
1464  * @len: Length of message
1465  */
1466 static int
1467 tsi721_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
1468                         void *buffer, size_t len)
1469 {
1470         struct tsi721_device *priv = mport->priv;
1471         struct tsi721_omsg_desc *desc;
1472         u32 tx_slot;
1473
1474         if (!priv->omsg_init[mbox] ||
1475             len > TSI721_MSG_MAX_SIZE || len < 8)
1476                 return -EINVAL;
1477
1478         tx_slot = priv->omsg_ring[mbox].tx_slot;
1479
1480         /* Copy copy message into transfer buffer */
1481         memcpy(priv->omsg_ring[mbox].omq_base[tx_slot], buffer, len);
1482
1483         if (len & 0x7)
1484                 len += 8;
1485
1486         /* Build descriptor associated with buffer */
1487         desc = priv->omsg_ring[mbox].omd_base;
1488         desc[tx_slot].type_id = cpu_to_le32((DTYPE4 << 29) | rdev->destid);
1489         if (tx_slot % 4 == 0)
1490                 desc[tx_slot].type_id |= cpu_to_le32(TSI721_OMD_IOF);
1491
1492         desc[tx_slot].msg_info =
1493                 cpu_to_le32((mport->sys_size << 26) | (mbox << 22) |
1494                             (0xe << 12) | (len & 0xff8));
1495         desc[tx_slot].bufptr_lo =
1496                 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] &
1497                             0xffffffff);
1498         desc[tx_slot].bufptr_hi =
1499                 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] >> 32);
1500
1501         priv->omsg_ring[mbox].wr_count++;
1502
1503         /* Go to next descriptor */
1504         if (++priv->omsg_ring[mbox].tx_slot == priv->omsg_ring[mbox].size) {
1505                 priv->omsg_ring[mbox].tx_slot = 0;
1506                 /* Move through the ring link descriptor at the end */
1507                 priv->omsg_ring[mbox].wr_count++;
1508         }
1509
1510         mb();
1511
1512         /* Set new write count value */
1513         iowrite32(priv->omsg_ring[mbox].wr_count,
1514                 priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1515         ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1516
1517         return 0;
1518 }
1519
1520 /**
1521  * tsi721_omsg_handler - Outbound Message Interrupt Handler
1522  * @priv: pointer to tsi721 private data
1523  * @ch:   number of OB MSG channel to service
1524  *
1525  * Services channel interrupts from outbound messaging engine.
1526  */
1527 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch)
1528 {
1529         u32 omsg_int;
1530         struct rio_mport *mport = &priv->mport;
1531
1532         spin_lock(&priv->omsg_ring[ch].lock);
1533
1534         omsg_int = ioread32(priv->regs + TSI721_OBDMAC_INT(ch));
1535
1536         if (omsg_int & TSI721_OBDMAC_INT_ST_FULL)
1537                 dev_info(&priv->pdev->dev,
1538                         "OB MBOX%d: Status FIFO is full\n", ch);
1539
1540         if (omsg_int & (TSI721_OBDMAC_INT_DONE | TSI721_OBDMAC_INT_IOF_DONE)) {
1541                 u32 srd_ptr;
1542                 u64 *sts_ptr, last_ptr = 0, prev_ptr = 0;
1543                 int i, j;
1544                 u32 tx_slot;
1545
1546                 /*
1547                  * Find last successfully processed descriptor
1548                  */
1549
1550                 /* Check and clear descriptor status FIFO entries */
1551                 srd_ptr = priv->omsg_ring[ch].sts_rdptr;
1552                 sts_ptr = priv->omsg_ring[ch].sts_base;
1553                 j = srd_ptr * 8;
1554                 while (sts_ptr[j]) {
1555                         for (i = 0; i < 8 && sts_ptr[j]; i++, j++) {
1556                                 prev_ptr = last_ptr;
1557                                 last_ptr = le64_to_cpu(sts_ptr[j]);
1558                                 sts_ptr[j] = 0;
1559                         }
1560
1561                         ++srd_ptr;
1562                         srd_ptr %= priv->omsg_ring[ch].sts_size;
1563                         j = srd_ptr * 8;
1564                 }
1565
1566                 if (last_ptr == 0)
1567                         goto no_sts_update;
1568
1569                 priv->omsg_ring[ch].sts_rdptr = srd_ptr;
1570                 iowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch));
1571
1572                 if (!mport->outb_msg[ch].mcback)
1573                         goto no_sts_update;
1574
1575                 /* Inform upper layer about transfer completion */
1576
1577                 tx_slot = (last_ptr - (u64)priv->omsg_ring[ch].omd_phys)/
1578                                                 sizeof(struct tsi721_omsg_desc);
1579
1580                 /*
1581                  * Check if this is a Link Descriptor (LD).
1582                  * If yes, ignore LD and use descriptor processed
1583                  * before LD.
1584                  */
1585                 if (tx_slot == priv->omsg_ring[ch].size) {
1586                         if (prev_ptr)
1587                                 tx_slot = (prev_ptr -
1588                                         (u64)priv->omsg_ring[ch].omd_phys)/
1589                                                 sizeof(struct tsi721_omsg_desc);
1590                         else
1591                                 goto no_sts_update;
1592                 }
1593
1594                 /* Move slot index to the next message to be sent */
1595                 ++tx_slot;
1596                 if (tx_slot == priv->omsg_ring[ch].size)
1597                         tx_slot = 0;
1598                 BUG_ON(tx_slot >= priv->omsg_ring[ch].size);
1599                 mport->outb_msg[ch].mcback(mport,
1600                                 priv->omsg_ring[ch].dev_id, ch,
1601                                 tx_slot);
1602         }
1603
1604 no_sts_update:
1605
1606         if (omsg_int & TSI721_OBDMAC_INT_ERROR) {
1607                 /*
1608                 * Outbound message operation aborted due to error,
1609                 * reinitialize OB MSG channel
1610                 */
1611
1612                 dev_dbg(&priv->pdev->dev, "OB MSG ABORT ch_stat=%x\n",
1613                         ioread32(priv->regs + TSI721_OBDMAC_STS(ch)));
1614
1615                 iowrite32(TSI721_OBDMAC_INT_ERROR,
1616                                 priv->regs + TSI721_OBDMAC_INT(ch));
1617                 iowrite32(TSI721_OBDMAC_CTL_INIT,
1618                                 priv->regs + TSI721_OBDMAC_CTL(ch));
1619                 ioread32(priv->regs + TSI721_OBDMAC_CTL(ch));
1620
1621                 /* Inform upper level to clear all pending tx slots */
1622                 if (mport->outb_msg[ch].mcback)
1623                         mport->outb_msg[ch].mcback(mport,
1624                                         priv->omsg_ring[ch].dev_id, ch,
1625                                         priv->omsg_ring[ch].tx_slot);
1626                 /* Synch tx_slot tracking */
1627                 iowrite32(priv->omsg_ring[ch].tx_slot,
1628                         priv->regs + TSI721_OBDMAC_DRDCNT(ch));
1629                 ioread32(priv->regs + TSI721_OBDMAC_DRDCNT(ch));
1630                 priv->omsg_ring[ch].wr_count = priv->omsg_ring[ch].tx_slot;
1631                 priv->omsg_ring[ch].sts_rdptr = 0;
1632         }
1633
1634         /* Clear channel interrupts */
1635         iowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch));
1636
1637         if (!(priv->flags & TSI721_USING_MSIX)) {
1638                 u32 ch_inte;
1639
1640                 /* Re-enable channel interrupts */
1641                 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1642                 ch_inte |= TSI721_INT_OMSG_CHAN(ch);
1643                 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
1644         }
1645
1646         spin_unlock(&priv->omsg_ring[ch].lock);
1647 }
1648
1649 /**
1650  * tsi721_open_outb_mbox - Initialize Tsi721 outbound mailbox
1651  * @mport: Master port implementing Outbound Messaging Engine
1652  * @dev_id: Device specific pointer to pass on event
1653  * @mbox: Mailbox to open
1654  * @entries: Number of entries in the outbound mailbox ring
1655  */
1656 static int tsi721_open_outb_mbox(struct rio_mport *mport, void *dev_id,
1657                                  int mbox, int entries)
1658 {
1659         struct tsi721_device *priv = mport->priv;
1660         struct tsi721_omsg_desc *bd_ptr;
1661         int i, rc = 0;
1662
1663         if ((entries < TSI721_OMSGD_MIN_RING_SIZE) ||
1664             (entries > (TSI721_OMSGD_RING_SIZE)) ||
1665             (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
1666                 rc = -EINVAL;
1667                 goto out;
1668         }
1669
1670         priv->omsg_ring[mbox].dev_id = dev_id;
1671         priv->omsg_ring[mbox].size = entries;
1672         priv->omsg_ring[mbox].sts_rdptr = 0;
1673         spin_lock_init(&priv->omsg_ring[mbox].lock);
1674
1675         /* Outbound Msg Buffer allocation based on
1676            the number of maximum descriptor entries */
1677         for (i = 0; i < entries; i++) {
1678                 priv->omsg_ring[mbox].omq_base[i] =
1679                         dma_alloc_coherent(
1680                                 &priv->pdev->dev, TSI721_MSG_BUFFER_SIZE,
1681                                 &priv->omsg_ring[mbox].omq_phys[i],
1682                                 GFP_KERNEL);
1683                 if (priv->omsg_ring[mbox].omq_base[i] == NULL) {
1684                         dev_dbg(&priv->pdev->dev,
1685                                 "Unable to allocate OB MSG data buffer for"
1686                                 " MBOX%d\n", mbox);
1687                         rc = -ENOMEM;
1688                         goto out_buf;
1689                 }
1690         }
1691
1692         /* Outbound message descriptor allocation */
1693         priv->omsg_ring[mbox].omd_base = dma_alloc_coherent(
1694                                 &priv->pdev->dev,
1695                                 (entries + 1) * sizeof(struct tsi721_omsg_desc),
1696                                 &priv->omsg_ring[mbox].omd_phys, GFP_KERNEL);
1697         if (priv->omsg_ring[mbox].omd_base == NULL) {
1698                 dev_dbg(&priv->pdev->dev,
1699                         "Unable to allocate OB MSG descriptor memory "
1700                         "for MBOX%d\n", mbox);
1701                 rc = -ENOMEM;
1702                 goto out_buf;
1703         }
1704
1705         priv->omsg_ring[mbox].tx_slot = 0;
1706
1707         /* Outbound message descriptor status FIFO allocation */
1708         priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1);
1709         priv->omsg_ring[mbox].sts_base = dma_zalloc_coherent(&priv->pdev->dev,
1710                         priv->omsg_ring[mbox].sts_size *
1711                                                 sizeof(struct tsi721_dma_sts),
1712                         &priv->omsg_ring[mbox].sts_phys, GFP_KERNEL);
1713         if (priv->omsg_ring[mbox].sts_base == NULL) {
1714                 dev_dbg(&priv->pdev->dev,
1715                         "Unable to allocate OB MSG descriptor status FIFO "
1716                         "for MBOX%d\n", mbox);
1717                 rc = -ENOMEM;
1718                 goto out_desc;
1719         }
1720
1721         /*
1722          * Configure Outbound Messaging Engine
1723          */
1724
1725         /* Setup Outbound Message descriptor pointer */
1726         iowrite32(((u64)priv->omsg_ring[mbox].omd_phys >> 32),
1727                         priv->regs + TSI721_OBDMAC_DPTRH(mbox));
1728         iowrite32(((u64)priv->omsg_ring[mbox].omd_phys &
1729                                         TSI721_OBDMAC_DPTRL_MASK),
1730                         priv->regs + TSI721_OBDMAC_DPTRL(mbox));
1731
1732         /* Setup Outbound Message descriptor status FIFO */
1733         iowrite32(((u64)priv->omsg_ring[mbox].sts_phys >> 32),
1734                         priv->regs + TSI721_OBDMAC_DSBH(mbox));
1735         iowrite32(((u64)priv->omsg_ring[mbox].sts_phys &
1736                                         TSI721_OBDMAC_DSBL_MASK),
1737                         priv->regs + TSI721_OBDMAC_DSBL(mbox));
1738         iowrite32(TSI721_DMAC_DSSZ_SIZE(priv->omsg_ring[mbox].sts_size),
1739                 priv->regs + (u32)TSI721_OBDMAC_DSSZ(mbox));
1740
1741         /* Enable interrupts */
1742
1743 #ifdef CONFIG_PCI_MSI
1744         if (priv->flags & TSI721_USING_MSIX) {
1745                 int idx = TSI721_VECT_OMB0_DONE + mbox;
1746
1747                 /* Request interrupt service if we are in MSI-X mode */
1748                 rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0,
1749                                  priv->msix[idx].irq_name, (void *)priv);
1750
1751                 if (rc) {
1752                         dev_dbg(&priv->pdev->dev,
1753                                 "Unable to allocate MSI-X interrupt for "
1754                                 "OBOX%d-DONE\n", mbox);
1755                         goto out_stat;
1756                 }
1757
1758                 idx = TSI721_VECT_OMB0_INT + mbox;
1759                 rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0,
1760                                  priv->msix[idx].irq_name, (void *)priv);
1761
1762                 if (rc) {
1763                         dev_dbg(&priv->pdev->dev,
1764                                 "Unable to allocate MSI-X interrupt for "
1765                                 "MBOX%d-INT\n", mbox);
1766                         idx = TSI721_VECT_OMB0_DONE + mbox;
1767                         free_irq(priv->msix[idx].vector, (void *)priv);
1768                         goto out_stat;
1769                 }
1770         }
1771 #endif /* CONFIG_PCI_MSI */
1772
1773         tsi721_omsg_interrupt_enable(priv, mbox, TSI721_OBDMAC_INT_ALL);
1774
1775         /* Initialize Outbound Message descriptors ring */
1776         bd_ptr = priv->omsg_ring[mbox].omd_base;
1777         bd_ptr[entries].type_id = cpu_to_le32(DTYPE5 << 29);
1778         bd_ptr[entries].msg_info = 0;
1779         bd_ptr[entries].next_lo =
1780                 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys &
1781                 TSI721_OBDMAC_DPTRL_MASK);
1782         bd_ptr[entries].next_hi =
1783                 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys >> 32);
1784         priv->omsg_ring[mbox].wr_count = 0;
1785         mb();
1786
1787         /* Initialize Outbound Message engine */
1788         iowrite32(TSI721_OBDMAC_CTL_INIT, priv->regs + TSI721_OBDMAC_CTL(mbox));
1789         ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1790         udelay(10);
1791
1792         priv->omsg_init[mbox] = 1;
1793
1794         return 0;
1795
1796 #ifdef CONFIG_PCI_MSI
1797 out_stat:
1798         dma_free_coherent(&priv->pdev->dev,
1799                 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
1800                 priv->omsg_ring[mbox].sts_base,
1801                 priv->omsg_ring[mbox].sts_phys);
1802
1803         priv->omsg_ring[mbox].sts_base = NULL;
1804 #endif /* CONFIG_PCI_MSI */
1805
1806 out_desc:
1807         dma_free_coherent(&priv->pdev->dev,
1808                 (entries + 1) * sizeof(struct tsi721_omsg_desc),
1809                 priv->omsg_ring[mbox].omd_base,
1810                 priv->omsg_ring[mbox].omd_phys);
1811
1812         priv->omsg_ring[mbox].omd_base = NULL;
1813
1814 out_buf:
1815         for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
1816                 if (priv->omsg_ring[mbox].omq_base[i]) {
1817                         dma_free_coherent(&priv->pdev->dev,
1818                                 TSI721_MSG_BUFFER_SIZE,
1819                                 priv->omsg_ring[mbox].omq_base[i],
1820                                 priv->omsg_ring[mbox].omq_phys[i]);
1821
1822                         priv->omsg_ring[mbox].omq_base[i] = NULL;
1823                 }
1824         }
1825
1826 out:
1827         return rc;
1828 }
1829
1830 /**
1831  * tsi721_close_outb_mbox - Close Tsi721 outbound mailbox
1832  * @mport: Master port implementing the outbound message unit
1833  * @mbox: Mailbox to close
1834  */
1835 static void tsi721_close_outb_mbox(struct rio_mport *mport, int mbox)
1836 {
1837         struct tsi721_device *priv = mport->priv;
1838         u32 i;
1839
1840         if (!priv->omsg_init[mbox])
1841                 return;
1842         priv->omsg_init[mbox] = 0;
1843
1844         /* Disable Interrupts */
1845
1846         tsi721_omsg_interrupt_disable(priv, mbox, TSI721_OBDMAC_INT_ALL);
1847
1848 #ifdef CONFIG_PCI_MSI
1849         if (priv->flags & TSI721_USING_MSIX) {
1850                 free_irq(priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector,
1851                          (void *)priv);
1852                 free_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector,
1853                          (void *)priv);
1854         }
1855 #endif /* CONFIG_PCI_MSI */
1856
1857         /* Free OMSG Descriptor Status FIFO */
1858         dma_free_coherent(&priv->pdev->dev,
1859                 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
1860                 priv->omsg_ring[mbox].sts_base,
1861                 priv->omsg_ring[mbox].sts_phys);
1862
1863         priv->omsg_ring[mbox].sts_base = NULL;
1864
1865         /* Free OMSG descriptors */
1866         dma_free_coherent(&priv->pdev->dev,
1867                 (priv->omsg_ring[mbox].size + 1) *
1868                         sizeof(struct tsi721_omsg_desc),
1869                 priv->omsg_ring[mbox].omd_base,
1870                 priv->omsg_ring[mbox].omd_phys);
1871
1872         priv->omsg_ring[mbox].omd_base = NULL;
1873
1874         /* Free message buffers */
1875         for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
1876                 if (priv->omsg_ring[mbox].omq_base[i]) {
1877                         dma_free_coherent(&priv->pdev->dev,
1878                                 TSI721_MSG_BUFFER_SIZE,
1879                                 priv->omsg_ring[mbox].omq_base[i],
1880                                 priv->omsg_ring[mbox].omq_phys[i]);
1881
1882                         priv->omsg_ring[mbox].omq_base[i] = NULL;
1883                 }
1884         }
1885 }
1886
1887 /**
1888  * tsi721_imsg_handler - Inbound Message Interrupt Handler
1889  * @priv: pointer to tsi721 private data
1890  * @ch: inbound message channel number to service
1891  *
1892  * Services channel interrupts from inbound messaging engine.
1893  */
1894 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch)
1895 {
1896         u32 mbox = ch - 4;
1897         u32 imsg_int;
1898         struct rio_mport *mport = &priv->mport;
1899
1900         spin_lock(&priv->imsg_ring[mbox].lock);
1901
1902         imsg_int = ioread32(priv->regs + TSI721_IBDMAC_INT(ch));
1903
1904         if (imsg_int & TSI721_IBDMAC_INT_SRTO)
1905                 dev_info(&priv->pdev->dev, "IB MBOX%d SRIO timeout\n",
1906                         mbox);
1907
1908         if (imsg_int & TSI721_IBDMAC_INT_PC_ERROR)
1909                 dev_info(&priv->pdev->dev, "IB MBOX%d PCIe error\n",
1910                         mbox);
1911
1912         if (imsg_int & TSI721_IBDMAC_INT_FQ_LOW)
1913                 dev_info(&priv->pdev->dev,
1914                         "IB MBOX%d IB free queue low\n", mbox);
1915
1916         /* Clear IB channel interrupts */
1917         iowrite32(imsg_int, priv->regs + TSI721_IBDMAC_INT(ch));
1918
1919         /* If an IB Msg is received notify the upper layer */
1920         if (imsg_int & TSI721_IBDMAC_INT_DQ_RCV &&
1921                 mport->inb_msg[mbox].mcback)
1922                 mport->inb_msg[mbox].mcback(mport,
1923                                 priv->imsg_ring[mbox].dev_id, mbox, -1);
1924
1925         if (!(priv->flags & TSI721_USING_MSIX)) {
1926                 u32 ch_inte;
1927
1928                 /* Re-enable channel interrupts */
1929                 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1930                 ch_inte |= TSI721_INT_IMSG_CHAN(ch);
1931                 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
1932         }
1933
1934         spin_unlock(&priv->imsg_ring[mbox].lock);
1935 }
1936
1937 /**
1938  * tsi721_open_inb_mbox - Initialize Tsi721 inbound mailbox
1939  * @mport: Master port implementing the Inbound Messaging Engine
1940  * @dev_id: Device specific pointer to pass on event
1941  * @mbox: Mailbox to open
1942  * @entries: Number of entries in the inbound mailbox ring
1943  */
1944 static int tsi721_open_inb_mbox(struct rio_mport *mport, void *dev_id,
1945                                 int mbox, int entries)
1946 {
1947         struct tsi721_device *priv = mport->priv;
1948         int ch = mbox + 4;
1949         int i;
1950         u64 *free_ptr;
1951         int rc = 0;
1952
1953         if ((entries < TSI721_IMSGD_MIN_RING_SIZE) ||
1954             (entries > TSI721_IMSGD_RING_SIZE) ||
1955             (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
1956                 rc = -EINVAL;
1957                 goto out;
1958         }
1959
1960         /* Initialize IB Messaging Ring */
1961         priv->imsg_ring[mbox].dev_id = dev_id;
1962         priv->imsg_ring[mbox].size = entries;
1963         priv->imsg_ring[mbox].rx_slot = 0;
1964         priv->imsg_ring[mbox].desc_rdptr = 0;
1965         priv->imsg_ring[mbox].fq_wrptr = 0;
1966         for (i = 0; i < priv->imsg_ring[mbox].size; i++)
1967                 priv->imsg_ring[mbox].imq_base[i] = NULL;
1968         spin_lock_init(&priv->imsg_ring[mbox].lock);
1969
1970         /* Allocate buffers for incoming messages */
1971         priv->imsg_ring[mbox].buf_base =
1972                 dma_alloc_coherent(&priv->pdev->dev,
1973                                    entries * TSI721_MSG_BUFFER_SIZE,
1974                                    &priv->imsg_ring[mbox].buf_phys,
1975                                    GFP_KERNEL);
1976
1977         if (priv->imsg_ring[mbox].buf_base == NULL) {
1978                 dev_err(&priv->pdev->dev,
1979                         "Failed to allocate buffers for IB MBOX%d\n", mbox);
1980                 rc = -ENOMEM;
1981                 goto out;
1982         }
1983
1984         /* Allocate memory for circular free list */
1985         priv->imsg_ring[mbox].imfq_base =
1986                 dma_alloc_coherent(&priv->pdev->dev,
1987                                    entries * 8,
1988                                    &priv->imsg_ring[mbox].imfq_phys,
1989                                    GFP_KERNEL);
1990
1991         if (priv->imsg_ring[mbox].imfq_base == NULL) {
1992                 dev_err(&priv->pdev->dev,
1993                         "Failed to allocate free queue for IB MBOX%d\n", mbox);
1994                 rc = -ENOMEM;
1995                 goto out_buf;
1996         }
1997
1998         /* Allocate memory for Inbound message descriptors */
1999         priv->imsg_ring[mbox].imd_base =
2000                 dma_alloc_coherent(&priv->pdev->dev,
2001                                    entries * sizeof(struct tsi721_imsg_desc),
2002                                    &priv->imsg_ring[mbox].imd_phys, GFP_KERNEL);
2003
2004         if (priv->imsg_ring[mbox].imd_base == NULL) {
2005                 dev_err(&priv->pdev->dev,
2006                         "Failed to allocate descriptor memory for IB MBOX%d\n",
2007                         mbox);
2008                 rc = -ENOMEM;
2009                 goto out_dma;
2010         }
2011
2012         /* Fill free buffer pointer list */
2013         free_ptr = priv->imsg_ring[mbox].imfq_base;
2014         for (i = 0; i < entries; i++)
2015                 free_ptr[i] = cpu_to_le64(
2016                                 (u64)(priv->imsg_ring[mbox].buf_phys) +
2017                                 i * 0x1000);
2018
2019         mb();
2020
2021         /*
2022          * For mapping of inbound SRIO Messages into appropriate queues we need
2023          * to set Inbound Device ID register in the messaging engine. We do it
2024          * once when first inbound mailbox is requested.
2025          */
2026         if (!(priv->flags & TSI721_IMSGID_SET)) {
2027                 iowrite32((u32)priv->mport.host_deviceid,
2028                         priv->regs + TSI721_IB_DEVID);
2029                 priv->flags |= TSI721_IMSGID_SET;
2030         }
2031
2032         /*
2033          * Configure Inbound Messaging channel (ch = mbox + 4)
2034          */
2035
2036         /* Setup Inbound Message free queue */
2037         iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys >> 32),
2038                 priv->regs + TSI721_IBDMAC_FQBH(ch));
2039         iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys &
2040                         TSI721_IBDMAC_FQBL_MASK),
2041                 priv->regs+TSI721_IBDMAC_FQBL(ch));
2042         iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
2043                 priv->regs + TSI721_IBDMAC_FQSZ(ch));
2044
2045         /* Setup Inbound Message descriptor queue */
2046         iowrite32(((u64)priv->imsg_ring[mbox].imd_phys >> 32),
2047                 priv->regs + TSI721_IBDMAC_DQBH(ch));
2048         iowrite32(((u32)priv->imsg_ring[mbox].imd_phys &
2049                    (u32)TSI721_IBDMAC_DQBL_MASK),
2050                 priv->regs+TSI721_IBDMAC_DQBL(ch));
2051         iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
2052                 priv->regs + TSI721_IBDMAC_DQSZ(ch));
2053
2054         /* Enable interrupts */
2055
2056 #ifdef CONFIG_PCI_MSI
2057         if (priv->flags & TSI721_USING_MSIX) {
2058                 int idx = TSI721_VECT_IMB0_RCV + mbox;
2059
2060                 /* Request interrupt service if we are in MSI-X mode */
2061                 rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0,
2062                                  priv->msix[idx].irq_name, (void *)priv);
2063
2064                 if (rc) {
2065                         dev_dbg(&priv->pdev->dev,
2066                                 "Unable to allocate MSI-X interrupt for "
2067                                 "IBOX%d-DONE\n", mbox);
2068                         goto out_desc;
2069                 }
2070
2071                 idx = TSI721_VECT_IMB0_INT + mbox;
2072                 rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0,
2073                                  priv->msix[idx].irq_name, (void *)priv);
2074
2075                 if (rc) {
2076                         dev_dbg(&priv->pdev->dev,
2077                                 "Unable to allocate MSI-X interrupt for "
2078                                 "IBOX%d-INT\n", mbox);
2079                         free_irq(
2080                                 priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
2081                                 (void *)priv);
2082                         goto out_desc;
2083                 }
2084         }
2085 #endif /* CONFIG_PCI_MSI */
2086
2087         tsi721_imsg_interrupt_enable(priv, ch, TSI721_IBDMAC_INT_ALL);
2088
2089         /* Initialize Inbound Message Engine */
2090         iowrite32(TSI721_IBDMAC_CTL_INIT, priv->regs + TSI721_IBDMAC_CTL(ch));
2091         ioread32(priv->regs + TSI721_IBDMAC_CTL(ch));
2092         udelay(10);
2093         priv->imsg_ring[mbox].fq_wrptr = entries - 1;
2094         iowrite32(entries - 1, priv->regs + TSI721_IBDMAC_FQWP(ch));
2095
2096         priv->imsg_init[mbox] = 1;
2097         return 0;
2098
2099 #ifdef CONFIG_PCI_MSI
2100 out_desc:
2101         dma_free_coherent(&priv->pdev->dev,
2102                 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2103                 priv->imsg_ring[mbox].imd_base,
2104                 priv->imsg_ring[mbox].imd_phys);
2105
2106         priv->imsg_ring[mbox].imd_base = NULL;
2107 #endif /* CONFIG_PCI_MSI */
2108
2109 out_dma:
2110         dma_free_coherent(&priv->pdev->dev,
2111                 priv->imsg_ring[mbox].size * 8,
2112                 priv->imsg_ring[mbox].imfq_base,
2113                 priv->imsg_ring[mbox].imfq_phys);
2114
2115         priv->imsg_ring[mbox].imfq_base = NULL;
2116
2117 out_buf:
2118         dma_free_coherent(&priv->pdev->dev,
2119                 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2120                 priv->imsg_ring[mbox].buf_base,
2121                 priv->imsg_ring[mbox].buf_phys);
2122
2123         priv->imsg_ring[mbox].buf_base = NULL;
2124
2125 out:
2126         return rc;
2127 }
2128
2129 /**
2130  * tsi721_close_inb_mbox - Shut down Tsi721 inbound mailbox
2131  * @mport: Master port implementing the Inbound Messaging Engine
2132  * @mbox: Mailbox to close
2133  */
2134 static void tsi721_close_inb_mbox(struct rio_mport *mport, int mbox)
2135 {
2136         struct tsi721_device *priv = mport->priv;
2137         u32 rx_slot;
2138         int ch = mbox + 4;
2139
2140         if (!priv->imsg_init[mbox]) /* mbox isn't initialized yet */
2141                 return;
2142         priv->imsg_init[mbox] = 0;
2143
2144         /* Disable Inbound Messaging Engine */
2145
2146         /* Disable Interrupts */
2147         tsi721_imsg_interrupt_disable(priv, ch, TSI721_OBDMAC_INT_MASK);
2148
2149 #ifdef CONFIG_PCI_MSI
2150         if (priv->flags & TSI721_USING_MSIX) {
2151                 free_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
2152                                 (void *)priv);
2153                 free_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector,
2154                                 (void *)priv);
2155         }
2156 #endif /* CONFIG_PCI_MSI */
2157
2158         /* Clear Inbound Buffer Queue */
2159         for (rx_slot = 0; rx_slot < priv->imsg_ring[mbox].size; rx_slot++)
2160                 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
2161
2162         /* Free memory allocated for message buffers */
2163         dma_free_coherent(&priv->pdev->dev,
2164                 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2165                 priv->imsg_ring[mbox].buf_base,
2166                 priv->imsg_ring[mbox].buf_phys);
2167
2168         priv->imsg_ring[mbox].buf_base = NULL;
2169
2170         /* Free memory allocated for free pointr list */
2171         dma_free_coherent(&priv->pdev->dev,
2172                 priv->imsg_ring[mbox].size * 8,
2173                 priv->imsg_ring[mbox].imfq_base,
2174                 priv->imsg_ring[mbox].imfq_phys);
2175
2176         priv->imsg_ring[mbox].imfq_base = NULL;
2177
2178         /* Free memory allocated for RX descriptors */
2179         dma_free_coherent(&priv->pdev->dev,
2180                 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2181                 priv->imsg_ring[mbox].imd_base,
2182                 priv->imsg_ring[mbox].imd_phys);
2183
2184         priv->imsg_ring[mbox].imd_base = NULL;
2185 }
2186
2187 /**
2188  * tsi721_add_inb_buffer - Add buffer to the Tsi721 inbound message queue
2189  * @mport: Master port implementing the Inbound Messaging Engine
2190  * @mbox: Inbound mailbox number
2191  * @buf: Buffer to add to inbound queue
2192  */
2193 static int tsi721_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
2194 {
2195         struct tsi721_device *priv = mport->priv;
2196         u32 rx_slot;
2197         int rc = 0;
2198
2199         rx_slot = priv->imsg_ring[mbox].rx_slot;
2200         if (priv->imsg_ring[mbox].imq_base[rx_slot]) {
2201                 dev_err(&priv->pdev->dev,
2202                         "Error adding inbound buffer %d, buffer exists\n",
2203                         rx_slot);
2204                 rc = -EINVAL;
2205                 goto out;
2206         }
2207
2208         priv->imsg_ring[mbox].imq_base[rx_slot] = buf;
2209
2210         if (++priv->imsg_ring[mbox].rx_slot == priv->imsg_ring[mbox].size)
2211                 priv->imsg_ring[mbox].rx_slot = 0;
2212
2213 out:
2214         return rc;
2215 }
2216
2217 /**
2218  * tsi721_get_inb_message - Fetch inbound message from the Tsi721 MSG Queue
2219  * @mport: Master port implementing the Inbound Messaging Engine
2220  * @mbox: Inbound mailbox number
2221  *
2222  * Returns pointer to the message on success or NULL on failure.
2223  */
2224 static void *tsi721_get_inb_message(struct rio_mport *mport, int mbox)
2225 {
2226         struct tsi721_device *priv = mport->priv;
2227         struct tsi721_imsg_desc *desc;
2228         u32 rx_slot;
2229         void *rx_virt = NULL;
2230         u64 rx_phys;
2231         void *buf = NULL;
2232         u64 *free_ptr;
2233         int ch = mbox + 4;
2234         int msg_size;
2235
2236         if (!priv->imsg_init[mbox])
2237                 return NULL;
2238
2239         desc = priv->imsg_ring[mbox].imd_base;
2240         desc += priv->imsg_ring[mbox].desc_rdptr;
2241
2242         if (!(le32_to_cpu(desc->msg_info) & TSI721_IMD_HO))
2243                 goto out;
2244
2245         rx_slot = priv->imsg_ring[mbox].rx_slot;
2246         while (priv->imsg_ring[mbox].imq_base[rx_slot] == NULL) {
2247                 if (++rx_slot == priv->imsg_ring[mbox].size)
2248                         rx_slot = 0;
2249         }
2250
2251         rx_phys = ((u64)le32_to_cpu(desc->bufptr_hi) << 32) |
2252                         le32_to_cpu(desc->bufptr_lo);
2253
2254         rx_virt = priv->imsg_ring[mbox].buf_base +
2255                   (rx_phys - (u64)priv->imsg_ring[mbox].buf_phys);
2256
2257         buf = priv->imsg_ring[mbox].imq_base[rx_slot];
2258         msg_size = le32_to_cpu(desc->msg_info) & TSI721_IMD_BCOUNT;
2259         if (msg_size == 0)
2260                 msg_size = RIO_MAX_MSG_SIZE;
2261
2262         memcpy(buf, rx_virt, msg_size);
2263         priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
2264
2265         desc->msg_info &= cpu_to_le32(~TSI721_IMD_HO);
2266         if (++priv->imsg_ring[mbox].desc_rdptr == priv->imsg_ring[mbox].size)
2267                 priv->imsg_ring[mbox].desc_rdptr = 0;
2268
2269         iowrite32(priv->imsg_ring[mbox].desc_rdptr,
2270                 priv->regs + TSI721_IBDMAC_DQRP(ch));
2271
2272         /* Return free buffer into the pointer list */
2273         free_ptr = priv->imsg_ring[mbox].imfq_base;
2274         free_ptr[priv->imsg_ring[mbox].fq_wrptr] = cpu_to_le64(rx_phys);
2275
2276         if (++priv->imsg_ring[mbox].fq_wrptr == priv->imsg_ring[mbox].size)
2277                 priv->imsg_ring[mbox].fq_wrptr = 0;
2278
2279         iowrite32(priv->imsg_ring[mbox].fq_wrptr,
2280                 priv->regs + TSI721_IBDMAC_FQWP(ch));
2281 out:
2282         return buf;
2283 }
2284
2285 /**
2286  * tsi721_messages_init - Initialization of Messaging Engine
2287  * @priv: pointer to tsi721 private data
2288  *
2289  * Configures Tsi721 messaging engine.
2290  */
2291 static int tsi721_messages_init(struct tsi721_device *priv)
2292 {
2293         int     ch;
2294
2295         iowrite32(0, priv->regs + TSI721_SMSG_ECC_LOG);
2296         iowrite32(0, priv->regs + TSI721_RETRY_GEN_CNT);
2297         iowrite32(0, priv->regs + TSI721_RETRY_RX_CNT);
2298
2299         /* Set SRIO Message Request/Response Timeout */
2300         iowrite32(TSI721_RQRPTO_VAL, priv->regs + TSI721_RQRPTO);
2301
2302         /* Initialize Inbound Messaging Engine Registers */
2303         for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++) {
2304                 /* Clear interrupt bits */
2305                 iowrite32(TSI721_IBDMAC_INT_MASK,
2306                         priv->regs + TSI721_IBDMAC_INT(ch));
2307                 /* Clear Status */
2308                 iowrite32(0, priv->regs + TSI721_IBDMAC_STS(ch));
2309
2310                 iowrite32(TSI721_SMSG_ECC_COR_LOG_MASK,
2311                                 priv->regs + TSI721_SMSG_ECC_COR_LOG(ch));
2312                 iowrite32(TSI721_SMSG_ECC_NCOR_MASK,
2313                                 priv->regs + TSI721_SMSG_ECC_NCOR(ch));
2314         }
2315
2316         return 0;
2317 }
2318
2319 /**
2320  * tsi721_query_mport - Fetch inbound message from the Tsi721 MSG Queue
2321  * @mport: Master port implementing the Inbound Messaging Engine
2322  * @mbox: Inbound mailbox number
2323  *
2324  * Returns pointer to the message on success or NULL on failure.
2325  */
2326 static int tsi721_query_mport(struct rio_mport *mport,
2327                               struct rio_mport_attr *attr)
2328 {
2329         struct tsi721_device *priv = mport->priv;
2330         u32 rval;
2331
2332         rval = ioread32(priv->regs + (0x100 + RIO_PORT_N_ERR_STS_CSR(0)));
2333         if (rval & RIO_PORT_N_ERR_STS_PORT_OK) {
2334                 rval = ioread32(priv->regs + (0x100 + RIO_PORT_N_CTL2_CSR(0)));
2335                 attr->link_speed = (rval & RIO_PORT_N_CTL2_SEL_BAUD) >> 28;
2336                 rval = ioread32(priv->regs + (0x100 + RIO_PORT_N_CTL_CSR(0)));
2337                 attr->link_width = (rval & RIO_PORT_N_CTL_IPW) >> 27;
2338         } else
2339                 attr->link_speed = RIO_LINK_DOWN;
2340
2341 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
2342         attr->flags = RIO_MPORT_DMA | RIO_MPORT_DMA_SG;
2343         attr->dma_max_sge = 0;
2344         attr->dma_max_size = TSI721_BDMA_MAX_BCOUNT;
2345         attr->dma_align = 0;
2346 #else
2347         attr->flags = 0;
2348 #endif
2349         return 0;
2350 }
2351
2352 /**
2353  * tsi721_disable_ints - disables all device interrupts
2354  * @priv: pointer to tsi721 private data
2355  */
2356 static void tsi721_disable_ints(struct tsi721_device *priv)
2357 {
2358         int ch;
2359
2360         /* Disable all device level interrupts */
2361         iowrite32(0, priv->regs + TSI721_DEV_INTE);
2362
2363         /* Disable all Device Channel interrupts */
2364         iowrite32(0, priv->regs + TSI721_DEV_CHAN_INTE);
2365
2366         /* Disable all Inbound Msg Channel interrupts */
2367         for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++)
2368                 iowrite32(0, priv->regs + TSI721_IBDMAC_INTE(ch));
2369
2370         /* Disable all Outbound Msg Channel interrupts */
2371         for (ch = 0; ch < TSI721_OMSG_CHNUM; ch++)
2372                 iowrite32(0, priv->regs + TSI721_OBDMAC_INTE(ch));
2373
2374         /* Disable all general messaging interrupts */
2375         iowrite32(0, priv->regs + TSI721_SMSG_INTE);
2376
2377         /* Disable all BDMA Channel interrupts */
2378         for (ch = 0; ch < TSI721_DMA_MAXCH; ch++)
2379                 iowrite32(0,
2380                         priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE);
2381
2382         /* Disable all general BDMA interrupts */
2383         iowrite32(0, priv->regs + TSI721_BDMA_INTE);
2384
2385         /* Disable all SRIO Channel interrupts */
2386         for (ch = 0; ch < TSI721_SRIO_MAXCH; ch++)
2387                 iowrite32(0, priv->regs + TSI721_SR_CHINTE(ch));
2388
2389         /* Disable all general SR2PC interrupts */
2390         iowrite32(0, priv->regs + TSI721_SR2PC_GEN_INTE);
2391
2392         /* Disable all PC2SR interrupts */
2393         iowrite32(0, priv->regs + TSI721_PC2SR_INTE);
2394
2395         /* Disable all I2C interrupts */
2396         iowrite32(0, priv->regs + TSI721_I2C_INT_ENABLE);
2397
2398         /* Disable SRIO MAC interrupts */
2399         iowrite32(0, priv->regs + TSI721_RIO_EM_INT_ENABLE);
2400         iowrite32(0, priv->regs + TSI721_RIO_EM_DEV_INT_EN);
2401 }
2402
2403 static struct rio_ops tsi721_rio_ops = {
2404         .lcread                 = tsi721_lcread,
2405         .lcwrite                = tsi721_lcwrite,
2406         .cread                  = tsi721_cread_dma,
2407         .cwrite                 = tsi721_cwrite_dma,
2408         .dsend                  = tsi721_dsend,
2409         .open_inb_mbox          = tsi721_open_inb_mbox,
2410         .close_inb_mbox         = tsi721_close_inb_mbox,
2411         .open_outb_mbox         = tsi721_open_outb_mbox,
2412         .close_outb_mbox        = tsi721_close_outb_mbox,
2413         .add_outb_message       = tsi721_add_outb_message,
2414         .add_inb_buffer         = tsi721_add_inb_buffer,
2415         .get_inb_message        = tsi721_get_inb_message,
2416         .map_inb                = tsi721_rio_map_inb_mem,
2417         .unmap_inb              = tsi721_rio_unmap_inb_mem,
2418         .pwenable               = tsi721_pw_enable,
2419         .query_mport            = tsi721_query_mport,
2420 };
2421
2422 static void tsi721_mport_release(struct device *dev)
2423 {
2424         struct rio_mport *mport = to_rio_mport(dev);
2425
2426         dev_dbg(dev, "RIO: %s %s id=%d\n", __func__, mport->name, mport->id);
2427 }
2428
2429 /**
2430  * tsi721_setup_mport - Setup Tsi721 as RapidIO subsystem master port
2431  * @priv: pointer to tsi721 private data
2432  *
2433  * Configures Tsi721 as RapidIO master port.
2434  */
2435 static int tsi721_setup_mport(struct tsi721_device *priv)
2436 {
2437         struct pci_dev *pdev = priv->pdev;
2438         int err = 0;
2439         struct rio_mport *mport = &priv->mport;
2440
2441         err = rio_mport_initialize(mport);
2442         if (err)
2443                 return err;
2444
2445         mport->ops = &tsi721_rio_ops;
2446         mport->index = 0;
2447         mport->sys_size = 0; /* small system */
2448         mport->phy_type = RIO_PHY_SERIAL;
2449         mport->priv = (void *)priv;
2450         mport->phys_efptr = 0x100;
2451         mport->dev.parent = &pdev->dev;
2452         mport->dev.release = tsi721_mport_release;
2453
2454         INIT_LIST_HEAD(&mport->dbells);
2455
2456         rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
2457         rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 3);
2458         rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 3);
2459         snprintf(mport->name, RIO_MAX_MPORT_NAME, "%s(%s)",
2460                  dev_driver_string(&pdev->dev), dev_name(&pdev->dev));
2461
2462         /* Hook up interrupt handler */
2463
2464 #ifdef CONFIG_PCI_MSI
2465         if (!tsi721_enable_msix(priv))
2466                 priv->flags |= TSI721_USING_MSIX;
2467         else if (!pci_enable_msi(pdev))
2468                 priv->flags |= TSI721_USING_MSI;
2469         else
2470                 dev_info(&pdev->dev,
2471                          "MSI/MSI-X is not available. Using legacy INTx.\n");
2472 #endif /* CONFIG_PCI_MSI */
2473
2474         err = tsi721_request_irq(priv);
2475
2476         if (err) {
2477                 dev_err(&pdev->dev, "Unable to get assigned PCI IRQ "
2478                         "vector %02X err=0x%x\n", pdev->irq, err);
2479                 return err;
2480         }
2481
2482 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
2483         err = tsi721_register_dma(priv);
2484         if (err)
2485                 goto err_exit;
2486 #endif
2487         /* Enable SRIO link */
2488         iowrite32(ioread32(priv->regs + TSI721_DEVCTL) |
2489                   TSI721_DEVCTL_SRBOOT_CMPL,
2490                   priv->regs + TSI721_DEVCTL);
2491
2492         if (mport->host_deviceid >= 0)
2493                 iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER |
2494                           RIO_PORT_GEN_DISCOVERED,
2495                           priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
2496         else
2497                 iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
2498
2499         err = rio_register_mport(mport);
2500         if (err) {
2501                 tsi721_unregister_dma(priv);
2502                 goto err_exit;
2503         }
2504
2505         return 0;
2506
2507 err_exit:
2508         tsi721_free_irq(priv);
2509         return err;
2510 }
2511
2512 static int tsi721_probe(struct pci_dev *pdev,
2513                                   const struct pci_device_id *id)
2514 {
2515         struct tsi721_device *priv;
2516         int err;
2517
2518         priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL);
2519         if (priv == NULL) {
2520                 dev_err(&pdev->dev, "Failed to allocate memory for device\n");
2521                 err = -ENOMEM;
2522                 goto err_exit;
2523         }
2524
2525         err = pci_enable_device(pdev);
2526         if (err) {
2527                 dev_err(&pdev->dev, "Failed to enable PCI device\n");
2528                 goto err_clean;
2529         }
2530
2531         priv->pdev = pdev;
2532
2533 #ifdef DEBUG
2534         {
2535         int i;
2536         for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
2537                 dev_dbg(&pdev->dev, "res[%d] @ 0x%llx (0x%lx, 0x%lx)\n",
2538                         i, (unsigned long long)pci_resource_start(pdev, i),
2539                         (unsigned long)pci_resource_len(pdev, i),
2540                         pci_resource_flags(pdev, i));
2541         }
2542         }
2543 #endif
2544         /*
2545          * Verify BAR configuration
2546          */
2547
2548         /* BAR_0 (registers) must be 512KB+ in 32-bit address space */
2549         if (!(pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM) ||
2550             pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM_64 ||
2551             pci_resource_len(pdev, BAR_0) < TSI721_REG_SPACE_SIZE) {
2552                 dev_err(&pdev->dev,
2553                         "Missing or misconfigured CSR BAR0, aborting.\n");
2554                 err = -ENODEV;
2555                 goto err_disable_pdev;
2556         }
2557
2558         /* BAR_1 (outbound doorbells) must be 16MB+ in 32-bit address space */
2559         if (!(pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM) ||
2560             pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM_64 ||
2561             pci_resource_len(pdev, BAR_1) < TSI721_DB_WIN_SIZE) {
2562                 dev_err(&pdev->dev,
2563                         "Missing or misconfigured Doorbell BAR1, aborting.\n");
2564                 err = -ENODEV;
2565                 goto err_disable_pdev;
2566         }
2567
2568         /*
2569          * BAR_2 and BAR_4 (outbound translation) must be in 64-bit PCIe address
2570          * space.
2571          * NOTE: BAR_2 and BAR_4 are not used by this version of driver.
2572          * It may be a good idea to keep them disabled using HW configuration
2573          * to save PCI memory space.
2574          */
2575         if ((pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM) &&
2576             (pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM_64)) {
2577                 dev_info(&pdev->dev, "Outbound BAR2 is not used but enabled.\n");
2578         }
2579
2580         if ((pci_resource_flags(pdev, BAR_4) & IORESOURCE_MEM) &&
2581             (pci_resource_flags(pdev, BAR_4) & IORESOURCE_MEM_64)) {
2582                 dev_info(&pdev->dev, "Outbound BAR4 is not used but enabled.\n");
2583         }
2584
2585         err = pci_request_regions(pdev, DRV_NAME);
2586         if (err) {
2587                 dev_err(&pdev->dev, "Cannot obtain PCI resources, "
2588                         "aborting.\n");
2589                 goto err_disable_pdev;
2590         }
2591
2592         pci_set_master(pdev);
2593
2594         priv->regs = pci_ioremap_bar(pdev, BAR_0);
2595         if (!priv->regs) {
2596                 dev_err(&pdev->dev,
2597                         "Unable to map device registers space, aborting\n");
2598                 err = -ENOMEM;
2599                 goto err_free_res;
2600         }
2601
2602         priv->odb_base = pci_ioremap_bar(pdev, BAR_1);
2603         if (!priv->odb_base) {
2604                 dev_err(&pdev->dev,
2605                         "Unable to map outbound doorbells space, aborting\n");
2606                 err = -ENOMEM;
2607                 goto err_unmap_bars;
2608         }
2609
2610         /* Configure DMA attributes. */
2611         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2612                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2613                 if (err) {
2614                         dev_info(&pdev->dev, "Unable to set DMA mask\n");
2615                         goto err_unmap_bars;
2616                 }
2617
2618                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2619                         dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
2620         } else {
2621                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2622                 if (err)
2623                         dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
2624         }
2625
2626         BUG_ON(!pci_is_pcie(pdev));
2627
2628         /* Clear "no snoop" and "relaxed ordering" bits. */
2629         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
2630                 PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
2631
2632         /* Adjust PCIe completion timeout. */
2633         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 0xf, 0x2);
2634
2635         /*
2636          * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block
2637          */
2638         pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0x01);
2639         pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXTBL,
2640                                                 TSI721_MSIXTBL_OFFSET);
2641         pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXPBA,
2642                                                 TSI721_MSIXPBA_OFFSET);
2643         pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0);
2644         /* End of FIXUP */
2645
2646         tsi721_disable_ints(priv);
2647
2648         tsi721_init_pc2sr_mapping(priv);
2649         tsi721_init_sr2pc_mapping(priv);
2650
2651         if (tsi721_bdma_maint_init(priv)) {
2652                 dev_err(&pdev->dev, "BDMA initialization failed, aborting\n");
2653                 err = -ENOMEM;
2654                 goto err_unmap_bars;
2655         }
2656
2657         err = tsi721_doorbell_init(priv);
2658         if (err)
2659                 goto err_free_bdma;
2660
2661         tsi721_port_write_init(priv);
2662
2663         err = tsi721_messages_init(priv);
2664         if (err)
2665                 goto err_free_consistent;
2666
2667         err = tsi721_setup_mport(priv);
2668         if (err)
2669                 goto err_free_consistent;
2670
2671         pci_set_drvdata(pdev, priv);
2672         tsi721_interrupts_init(priv);
2673
2674         return 0;
2675
2676 err_free_consistent:
2677         tsi721_port_write_free(priv);
2678         tsi721_doorbell_free(priv);
2679 err_free_bdma:
2680         tsi721_bdma_maint_free(priv);
2681 err_unmap_bars:
2682         if (priv->regs)
2683                 iounmap(priv->regs);
2684         if (priv->odb_base)
2685                 iounmap(priv->odb_base);
2686 err_free_res:
2687         pci_release_regions(pdev);
2688         pci_clear_master(pdev);
2689 err_disable_pdev:
2690         pci_disable_device(pdev);
2691 err_clean:
2692         kfree(priv);
2693 err_exit:
2694         return err;
2695 }
2696
2697 static void tsi721_remove(struct pci_dev *pdev)
2698 {
2699         struct tsi721_device *priv = pci_get_drvdata(pdev);
2700
2701         dev_dbg(&pdev->dev, "%s enter\n", __func__);
2702
2703         tsi721_disable_ints(priv);
2704         tsi721_free_irq(priv);
2705         rio_unregister_mport(&priv->mport);
2706
2707         tsi721_unregister_dma(priv);
2708         tsi721_bdma_maint_free(priv);
2709         tsi721_doorbell_free(priv);
2710         tsi721_port_write_free(priv);
2711         tsi721_close_sr2pc_mapping(priv);
2712
2713         if (priv->regs)
2714                 iounmap(priv->regs);
2715         if (priv->odb_base)
2716                 iounmap(priv->odb_base);
2717 #ifdef CONFIG_PCI_MSI
2718         if (priv->flags & TSI721_USING_MSIX)
2719                 pci_disable_msix(priv->pdev);
2720         else if (priv->flags & TSI721_USING_MSI)
2721                 pci_disable_msi(priv->pdev);
2722 #endif
2723         pci_release_regions(pdev);
2724         pci_clear_master(pdev);
2725         pci_disable_device(pdev);
2726         pci_set_drvdata(pdev, NULL);
2727         kfree(priv);
2728         dev_dbg(&pdev->dev, "%s exit\n", __func__);
2729 }
2730
2731 static void tsi721_shutdown(struct pci_dev *pdev)
2732 {
2733         struct tsi721_device *priv = pci_get_drvdata(pdev);
2734
2735         dev_dbg(&pdev->dev, "RIO: %s\n", __func__);
2736
2737         tsi721_disable_ints(priv);
2738         tsi721_dma_stop_all(priv);
2739         pci_clear_master(pdev);
2740         pci_disable_device(pdev);
2741 }
2742
2743 static const struct pci_device_id tsi721_pci_tbl[] = {
2744         { PCI_DEVICE(PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_TSI721) },
2745         { 0, }  /* terminate list */
2746 };
2747
2748 MODULE_DEVICE_TABLE(pci, tsi721_pci_tbl);
2749
2750 static struct pci_driver tsi721_driver = {
2751         .name           = "tsi721",
2752         .id_table       = tsi721_pci_tbl,
2753         .probe          = tsi721_probe,
2754         .remove         = tsi721_remove,
2755         .shutdown       = tsi721_shutdown,
2756 };
2757
2758 module_pci_driver(tsi721_driver);
2759
2760 MODULE_DESCRIPTION("IDT Tsi721 PCIExpress-to-SRIO bridge driver");
2761 MODULE_AUTHOR("Integrated Device Technology, Inc.");
2762 MODULE_LICENSE("GPL");