2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
13 #define DRV_NAME "hisi_sas_v2_hw"
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_INVLD_DQE_INFO 0x148
59 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
60 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
61 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
62 #define INT_COAL_EN 0x19c
63 #define OQ_INT_COAL_TIME 0x1a0
64 #define OQ_INT_COAL_CNT 0x1a4
65 #define ENT_INT_COAL_TIME 0x1a8
66 #define ENT_INT_COAL_CNT 0x1ac
67 #define OQ_INT_SRC 0x1b0
68 #define OQ_INT_SRC_MSK 0x1b4
69 #define ENT_INT_SRC1 0x1b8
70 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
71 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
72 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
73 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
74 #define ENT_INT_SRC2 0x1bc
75 #define ENT_INT_SRC3 0x1c0
76 #define ENT_INT_SRC3_ITC_INT_OFF 15
77 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78 #define ENT_INT_SRC_MSK1 0x1c4
79 #define ENT_INT_SRC_MSK2 0x1c8
80 #define ENT_INT_SRC_MSK3 0x1cc
81 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
82 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
83 #define SAS_ECC_INTR_MSK 0x1ec
84 #define HGC_ERR_STAT_EN 0x238
85 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
86 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
87 #define DLVRY_Q_0_DEPTH 0x268
88 #define DLVRY_Q_0_WR_PTR 0x26c
89 #define DLVRY_Q_0_RD_PTR 0x270
90 #define HYPER_STREAM_ID_EN_CFG 0xc80
91 #define OQ0_INT_SRC_MSK 0xc90
92 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
93 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
94 #define COMPL_Q_0_DEPTH 0x4e8
95 #define COMPL_Q_0_WR_PTR 0x4ec
96 #define COMPL_Q_0_RD_PTR 0x4f0
98 /* phy registers need init */
99 #define PORT_BASE (0x2000)
101 #define PHY_CFG (PORT_BASE + 0x0)
102 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
103 #define PHY_CFG_ENA_OFF 0
104 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
105 #define PHY_CFG_DC_OPT_OFF 2
106 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
107 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
108 #define PROG_PHY_LINK_RATE_MAX_OFF 0
109 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
110 #define PHY_CTRL (PORT_BASE + 0x14)
111 #define PHY_CTRL_RESET_OFF 0
112 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
113 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
114 #define SL_CFG (PORT_BASE + 0x84)
115 #define PHY_PCN (PORT_BASE + 0x44)
116 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
117 #define SL_CONTROL (PORT_BASE + 0x94)
118 #define SL_CONTROL_NOTIFY_EN_OFF 0
119 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
120 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
121 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
122 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
123 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
124 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
125 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
126 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
127 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
128 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
129 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
130 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
131 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
132 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
133 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
134 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
135 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
136 #define CHL_INT0 (PORT_BASE + 0x1b4)
137 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
138 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
139 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
140 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
141 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
142 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
143 #define CHL_INT0_NOT_RDY_OFF 4
144 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
145 #define CHL_INT0_PHY_RDY_OFF 5
146 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
147 #define CHL_INT1 (PORT_BASE + 0x1b8)
148 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
149 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
150 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
151 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
152 #define CHL_INT2 (PORT_BASE + 0x1bc)
153 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
154 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
155 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
156 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
157 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
158 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
159 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
160 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
161 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
162 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
163 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
164 #define DMA_TX_STATUS_BUSY_OFF 0
165 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
166 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
167 #define DMA_RX_STATUS_BUSY_OFF 0
168 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
170 #define AXI_CFG (0x5100)
171 #define AM_CFG_MAX_TRANS (0x5010)
172 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
174 /* HW dma structures */
175 /* Delivery queue header */
177 #define CMD_HDR_ABORT_FLAG_OFF 0
178 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
179 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
180 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
181 #define CMD_HDR_RESP_REPORT_OFF 5
182 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
183 #define CMD_HDR_TLR_CTRL_OFF 6
184 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
185 #define CMD_HDR_PORT_OFF 18
186 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
187 #define CMD_HDR_PRIORITY_OFF 27
188 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
189 #define CMD_HDR_CMD_OFF 29
190 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
192 #define CMD_HDR_DIR_OFF 5
193 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
194 #define CMD_HDR_RESET_OFF 7
195 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
196 #define CMD_HDR_VDTL_OFF 10
197 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
198 #define CMD_HDR_FRAME_TYPE_OFF 11
199 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
200 #define CMD_HDR_DEV_ID_OFF 16
201 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
203 #define CMD_HDR_CFL_OFF 0
204 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
205 #define CMD_HDR_NCQ_TAG_OFF 10
206 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
207 #define CMD_HDR_MRFL_OFF 15
208 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
209 #define CMD_HDR_SG_MOD_OFF 24
210 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
211 #define CMD_HDR_FIRST_BURST_OFF 26
212 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
214 #define CMD_HDR_IPTT_OFF 0
215 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
217 #define CMD_HDR_DIF_SGL_LEN_OFF 0
218 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
219 #define CMD_HDR_DATA_SGL_LEN_OFF 16
220 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
221 #define CMD_HDR_ABORT_IPTT_OFF 16
222 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
224 /* Completion header */
226 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
227 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
228 #define CMPLT_HDR_ERX_OFF 12
229 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
230 #define CMPLT_HDR_ABORT_STAT_OFF 13
231 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
233 #define STAT_IO_NOT_VALID 0x1
234 #define STAT_IO_NO_DEVICE 0x2
235 #define STAT_IO_COMPLETE 0x3
236 #define STAT_IO_ABORTED 0x4
238 #define CMPLT_HDR_IPTT_OFF 0
239 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
240 #define CMPLT_HDR_DEV_ID_OFF 16
241 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
245 #define ITCT_HDR_DEV_TYPE_OFF 0
246 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
247 #define ITCT_HDR_VALID_OFF 2
248 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
249 #define ITCT_HDR_MCR_OFF 5
250 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
251 #define ITCT_HDR_VLN_OFF 9
252 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
253 #define ITCT_HDR_PORT_ID_OFF 28
254 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
256 #define ITCT_HDR_INLT_OFF 0
257 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
258 #define ITCT_HDR_BITLT_OFF 16
259 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
260 #define ITCT_HDR_MCTLT_OFF 32
261 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
262 #define ITCT_HDR_RTOLT_OFF 48
263 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
265 struct hisi_sas_complete_v2_hdr {
272 struct hisi_sas_err_record_v2 {
274 __le32 trans_tx_fail_type;
277 __le32 trans_rx_fail_type;
280 __le16 dma_tx_err_type;
281 __le16 sipc_rx_err_type;
284 __le32 dma_rx_err_type;
288 HISI_SAS_PHY_PHY_UPDOWN,
289 HISI_SAS_PHY_CHNL_INT,
294 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
295 TRANS_RX_FAIL_BASE = 0x100, /* dw1 */
296 DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */
297 SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/
298 DMA_RX_ERR_BASE = 0x400, /* dw3 */
301 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
302 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
303 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
304 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
305 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
307 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
308 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
309 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
310 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
311 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
312 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
313 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
314 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
315 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
316 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
317 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
318 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
319 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
320 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
321 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
322 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
323 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
324 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
325 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
326 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
327 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
328 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
329 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
330 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
331 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
332 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
333 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
334 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
335 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
338 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */
339 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */
340 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */
341 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */
342 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */
343 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */
344 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */
345 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */
346 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/
347 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */
348 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */
349 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */
350 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */
351 RESERVED1, /* 0x10b */
352 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */
353 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */
354 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */
355 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */
356 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */
357 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */
358 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */
359 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/
360 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */
361 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */
362 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */
363 RESERVED2, /* 0x114 */
364 RESERVED3, /* 0x115 */
365 RESERVED4, /* 0x116 */
366 RESERVED5, /* 0x117 */
367 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */
368 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */
369 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */
370 RESERVED6, /* 0x11b */
371 RESERVED7, /* 0x11c */
372 RESERVED8, /* 0x11d */
373 RESERVED9, /* 0x11e */
374 TRANS_RX_R_ERR, /* 0x11f */
377 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */
378 DMA_TX_DIF_APP_ERR, /* 0x201 */
379 DMA_TX_DIF_RPP_ERR, /* 0x202 */
380 DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */
381 DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */
382 DMA_TX_UNEXP_XFER_ERR, /* 0x205 */
383 DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */
384 DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */
385 DMA_TX_XFER_OFFSET_ERR, /* 0x208 */
386 DMA_TX_RAM_ECC_ERR, /* 0x209 */
387 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */
390 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */
391 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */
392 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */
393 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */
394 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */
395 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */
396 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */
397 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */
398 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */
399 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */
400 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */
403 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */
404 DMA_RX_DIF_APP_ERR, /* 0x401 */
405 DMA_RX_DIF_RPP_ERR, /* 0x402 */
406 DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */
407 DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */
408 DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */
409 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */
410 DMA_RX_DATA_OFFSET_ERR, /* 0x407 */
411 RESERVED10, /* 0x408 */
412 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */
413 DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */
414 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */
415 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */
416 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */
417 DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */
418 DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */
419 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */
420 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */
421 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */
422 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */
423 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */
424 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */
425 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */
426 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */
427 DMA_RX_RAM_ECC_ERR, /* 0x418 */
428 DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */
431 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
433 #define DIR_NO_DATA 0
435 #define DIR_TO_DEVICE 2
436 #define DIR_RESERVED 3
438 #define SATA_PROTOCOL_NONDATA 0x1
439 #define SATA_PROTOCOL_PIO 0x2
440 #define SATA_PROTOCOL_DMA 0x4
441 #define SATA_PROTOCOL_FPDMA 0x8
442 #define SATA_PROTOCOL_ATAPI 0x10
444 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
446 void __iomem *regs = hisi_hba->regs + off;
451 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
453 void __iomem *regs = hisi_hba->regs + off;
455 return readl_relaxed(regs);
458 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
460 void __iomem *regs = hisi_hba->regs + off;
465 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
468 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
473 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
476 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
481 /* This function needs to be protected from pre-emption. */
483 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
484 struct domain_device *device)
486 unsigned int index = 0;
487 void *bitmap = hisi_hba->slot_index_tags;
488 int sata_dev = dev_is_sata(device);
491 index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count,
493 if (index >= hisi_hba->slot_index_count)
494 return -SAS_QUEUE_FULL;
496 * SAS IPTT bit0 should be 1
498 if (sata_dev || (index & 1))
503 set_bit(index, bitmap);
509 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
511 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
512 struct hisi_sas_device *sas_dev = NULL;
513 int i, sata_dev = dev_is_sata(device);
515 spin_lock(&hisi_hba->lock);
516 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
518 * SATA device id bit0 should be 0
520 if (sata_dev && (i & 1))
522 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
523 hisi_hba->devices[i].device_id = i;
524 sas_dev = &hisi_hba->devices[i];
525 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
526 sas_dev->dev_type = device->dev_type;
527 sas_dev->hisi_hba = hisi_hba;
528 sas_dev->sas_device = device;
532 spin_unlock(&hisi_hba->lock);
537 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
539 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
541 cfg &= ~PHY_CFG_DC_OPT_MSK;
542 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
543 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
546 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
548 struct sas_identify_frame identify_frame;
549 u32 *identify_buffer;
551 memset(&identify_frame, 0, sizeof(identify_frame));
552 identify_frame.dev_type = SAS_END_DEVICE;
553 identify_frame.frame_type = 0;
554 identify_frame._un1 = 1;
555 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
556 identify_frame.target_bits = SAS_PROTOCOL_NONE;
557 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
558 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
559 identify_frame.phy_id = phy_no;
560 identify_buffer = (u32 *)(&identify_frame);
562 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
563 __swab32(identify_buffer[0]));
564 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
565 __swab32(identify_buffer[1]));
566 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
567 __swab32(identify_buffer[2]));
568 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
569 __swab32(identify_buffer[3]));
570 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
571 __swab32(identify_buffer[4]));
572 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
573 __swab32(identify_buffer[5]));
576 static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba)
580 for (i = 0; i < hisi_hba->n_phy; i++)
581 config_id_frame_v2_hw(hisi_hba, i);
584 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
585 struct hisi_sas_device *sas_dev)
587 struct domain_device *device = sas_dev->sas_device;
588 struct device *dev = &hisi_hba->pdev->dev;
589 u64 qw0, device_id = sas_dev->device_id;
590 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
591 struct domain_device *parent_dev = device->parent;
592 struct hisi_sas_port *port = device->port->lldd_port;
594 memset(itct, 0, sizeof(*itct));
598 switch (sas_dev->dev_type) {
600 case SAS_EDGE_EXPANDER_DEVICE:
601 case SAS_FANOUT_EXPANDER_DEVICE:
602 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
605 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
606 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
608 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
611 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
615 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
616 (device->linkrate << ITCT_HDR_MCR_OFF) |
617 (1 << ITCT_HDR_VLN_OFF) |
618 (port->id << ITCT_HDR_PORT_ID_OFF));
619 itct->qw0 = cpu_to_le64(qw0);
622 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
623 itct->sas_addr = __swab64(itct->sas_addr);
626 if (!dev_is_sata(device))
627 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) |
628 (0x1ULL << ITCT_HDR_BITLT_OFF) |
629 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
630 (0x1ULL << ITCT_HDR_RTOLT_OFF));
633 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
634 struct hisi_sas_device *sas_dev)
636 u64 qw0, dev_id = sas_dev->device_id;
637 struct device *dev = &hisi_hba->pdev->dev;
638 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
639 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
642 /* clear the itct interrupt state */
643 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
644 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
645 ENT_INT_SRC3_ITC_INT_MSK);
647 /* clear the itct int*/
648 for (i = 0; i < 2; i++) {
649 /* clear the itct table*/
650 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
651 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
652 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
655 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
656 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
657 dev_dbg(dev, "got clear ITCT done interrupt\n");
659 /* invalid the itct state*/
660 qw0 = cpu_to_le64(itct->qw0);
661 qw0 &= ~(1 << ITCT_HDR_VALID_OFF);
662 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
663 ENT_INT_SRC3_ITC_INT_MSK);
664 hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
665 hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
668 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
669 dev_dbg(dev, "clear ITCT ok\n");
675 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
679 unsigned long end_time;
680 struct device *dev = &hisi_hba->pdev->dev;
682 /* The mask needs to be set depending on the number of phys */
683 if (hisi_hba->n_phy == 9)
684 reset_val = 0x1fffff;
688 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
690 /* Disable all of the PHYs */
691 for (i = 0; i < hisi_hba->n_phy; i++) {
692 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
694 phy_cfg &= ~PHY_CTRL_RESET_MSK;
695 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
699 /* Ensure DMA tx & rx idle */
700 for (i = 0; i < hisi_hba->n_phy; i++) {
701 u32 dma_tx_status, dma_rx_status;
703 end_time = jiffies + msecs_to_jiffies(1000);
706 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
708 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
711 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
712 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
716 if (time_after(jiffies, end_time))
721 /* Ensure axi bus idle */
722 end_time = jiffies + msecs_to_jiffies(1000);
725 hisi_sas_read32(hisi_hba, AXI_CFG);
731 if (time_after(jiffies, end_time))
735 if (ACPI_HANDLE(dev)) {
738 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
739 if (ACPI_FAILURE(s)) {
740 dev_err(dev, "Reset failed\n");
743 } else if (hisi_hba->ctrl) {
744 /* reset and disable clock*/
745 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
747 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
750 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
751 if (reset_val != (val & reset_val)) {
752 dev_err(dev, "SAS reset fail.\n");
756 /* De-reset and enable clock*/
757 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
759 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
762 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
764 if (val & reset_val) {
765 dev_err(dev, "SAS de-reset fail.\n");
769 dev_warn(dev, "no reset method\n");
774 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
776 struct device *dev = &hisi_hba->pdev->dev;
779 /* Global registers init */
781 /* Deal with am-max-transmissions quirk */
782 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
783 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
784 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
786 } /* Else, use defaults -> do nothing */
788 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
789 (u32)((1ULL << hisi_hba->queue_count) - 1));
790 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
791 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
792 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
793 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
794 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
795 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
796 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
797 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
798 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
799 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
800 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
801 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
802 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
803 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
804 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
805 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
806 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
807 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
808 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
809 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
810 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
811 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
812 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
813 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
814 for (i = 0; i < hisi_hba->queue_count; i++)
815 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
817 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
818 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
820 for (i = 0; i < hisi_hba->n_phy; i++) {
821 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
822 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
823 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
824 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
825 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
826 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
827 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
828 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
829 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
830 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
831 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
832 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
833 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
834 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
835 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
836 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
837 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
838 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
839 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
842 for (i = 0; i < hisi_hba->queue_count; i++) {
844 hisi_sas_write32(hisi_hba,
845 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
846 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
848 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
849 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
851 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
852 HISI_SAS_QUEUE_SLOTS);
854 /* Completion queue */
855 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
856 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
858 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
859 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
861 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
862 HISI_SAS_QUEUE_SLOTS);
866 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
867 lower_32_bits(hisi_hba->itct_dma));
869 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
870 upper_32_bits(hisi_hba->itct_dma));
873 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
874 lower_32_bits(hisi_hba->iost_dma));
876 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
877 upper_32_bits(hisi_hba->iost_dma));
880 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
881 lower_32_bits(hisi_hba->breakpoint_dma));
883 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
884 upper_32_bits(hisi_hba->breakpoint_dma));
886 /* SATA broken msg */
887 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
888 lower_32_bits(hisi_hba->sata_breakpoint_dma));
890 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
891 upper_32_bits(hisi_hba->sata_breakpoint_dma));
893 /* SATA initial fis */
894 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
895 lower_32_bits(hisi_hba->initial_fis_dma));
897 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
898 upper_32_bits(hisi_hba->initial_fis_dma));
901 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
903 struct device *dev = &hisi_hba->pdev->dev;
906 rc = reset_hw_v2_hw(hisi_hba);
908 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
913 init_reg_v2_hw(hisi_hba);
915 init_id_frame_v2_hw(hisi_hba);
920 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
922 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
924 cfg |= PHY_CFG_ENA_MSK;
925 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
928 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
930 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
932 cfg &= ~PHY_CFG_ENA_MSK;
933 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
936 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
938 config_id_frame_v2_hw(hisi_hba, phy_no);
939 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
940 enable_phy_v2_hw(hisi_hba, phy_no);
943 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
945 disable_phy_v2_hw(hisi_hba, phy_no);
948 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
950 stop_phy_v2_hw(hisi_hba, phy_no);
952 start_phy_v2_hw(hisi_hba, phy_no);
955 static void start_phys_v2_hw(unsigned long data)
957 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
960 for (i = 0; i < hisi_hba->n_phy; i++)
961 start_phy_v2_hw(hisi_hba, i);
964 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
966 struct timer_list *timer = &hisi_hba->timer;
968 setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
969 mod_timer(timer, jiffies + HZ);
972 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
976 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
977 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
978 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
980 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
981 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
982 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
985 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
988 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
989 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
991 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
992 if (phy_state & 1 << i)
993 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
996 if (hisi_hba->n_phy == 9) {
997 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
999 if (phy_state & 1 << 8)
1000 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1001 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1009 * This function allocates across all queues to load balance.
1010 * Slots are allocated from queues in a round-robin fashion.
1012 * The callpath to this function and upto writing the write
1013 * queue pointer should be safe from interruption.
1015 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s)
1017 struct device *dev = &hisi_hba->pdev->dev;
1018 struct hisi_sas_dq *dq;
1020 int queue = hisi_hba->queue;
1023 dq = &hisi_hba->dq[queue];
1025 r = hisi_sas_read32_relaxed(hisi_hba,
1026 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1027 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1028 queue = (queue + 1) % hisi_hba->queue_count;
1029 if (queue == hisi_hba->queue) {
1030 dev_warn(dev, "could not find free slot\n");
1037 hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
1043 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
1045 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
1046 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
1047 struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue];
1049 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1050 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1054 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1055 struct hisi_sas_slot *slot,
1056 struct hisi_sas_cmd_hdr *hdr,
1057 struct scatterlist *scatter,
1060 struct device *dev = &hisi_hba->pdev->dev;
1061 struct scatterlist *sg;
1064 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1065 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1070 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
1071 &slot->sge_page_dma);
1072 if (!slot->sge_page)
1075 for_each_sg(scatter, sg, n_elem, i) {
1076 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
1078 entry->addr = cpu_to_le64(sg_dma_address(sg));
1079 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1080 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1081 entry->data_off = 0;
1084 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
1086 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1091 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1092 struct hisi_sas_slot *slot)
1094 struct sas_task *task = slot->task;
1095 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1096 struct domain_device *device = task->dev;
1097 struct device *dev = &hisi_hba->pdev->dev;
1098 struct hisi_sas_port *port = slot->port;
1099 struct scatterlist *sg_req, *sg_resp;
1100 struct hisi_sas_device *sas_dev = device->lldd_dev;
1101 dma_addr_t req_dma_addr;
1102 unsigned int req_len, resp_len;
1106 * DMA-map SMP request, response buffers
1109 sg_req = &task->smp_task.smp_req;
1110 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1113 req_len = sg_dma_len(sg_req);
1114 req_dma_addr = sg_dma_address(sg_req);
1117 sg_resp = &task->smp_task.smp_resp;
1118 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1123 resp_len = sg_dma_len(sg_resp);
1124 if ((req_len & 0x3) || (resp_len & 0x3)) {
1131 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1132 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1133 (2 << CMD_HDR_CMD_OFF)); /* smp */
1135 /* map itct entry */
1136 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1137 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1138 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1141 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1142 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1145 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1147 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1148 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1153 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1156 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1161 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1162 struct hisi_sas_slot *slot, int is_tmf,
1163 struct hisi_sas_tmf_task *tmf)
1165 struct sas_task *task = slot->task;
1166 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1167 struct domain_device *device = task->dev;
1168 struct hisi_sas_device *sas_dev = device->lldd_dev;
1169 struct hisi_sas_port *port = slot->port;
1170 struct sas_ssp_task *ssp_task = &task->ssp_task;
1171 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1172 int has_data = 0, rc, priority = is_tmf;
1174 u32 dw1 = 0, dw2 = 0;
1176 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1177 (2 << CMD_HDR_TLR_CTRL_OFF) |
1178 (port->id << CMD_HDR_PORT_OFF) |
1179 (priority << CMD_HDR_PRIORITY_OFF) |
1180 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1182 dw1 = 1 << CMD_HDR_VDTL_OFF;
1184 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1185 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1187 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1188 switch (scsi_cmnd->sc_data_direction) {
1191 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1193 case DMA_FROM_DEVICE:
1195 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1198 dw1 &= ~CMD_HDR_DIR_MSK;
1202 /* map itct entry */
1203 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1204 hdr->dw1 = cpu_to_le32(dw1);
1206 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1207 + 3) / 4) << CMD_HDR_CFL_OFF) |
1208 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1209 (2 << CMD_HDR_SG_MOD_OFF);
1210 hdr->dw2 = cpu_to_le32(dw2);
1212 hdr->transfer_tags = cpu_to_le32(slot->idx);
1215 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1221 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1222 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1223 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1225 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
1227 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1229 buf_cmd[9] = task->ssp_task.task_attr |
1230 (task->ssp_task.task_prio << 3);
1231 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1232 task->ssp_task.cmd->cmd_len);
1234 buf_cmd[10] = tmf->tmf;
1236 case TMF_ABORT_TASK:
1237 case TMF_QUERY_TASK:
1239 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1241 tmf->tag_of_task_to_be_managed & 0xff;
1251 static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1252 struct hisi_sas_slot *slot)
1254 struct task_status_struct *ts = &task->task_status;
1255 struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
1256 struct dev_to_host_fis *d2h = slot->status_buffer +
1257 sizeof(struct hisi_sas_err_record);
1259 resp->frame_len = sizeof(struct dev_to_host_fis);
1260 memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
1262 ts->buf_valid_size = sizeof(*resp);
1265 /* by default, task resp is complete */
1266 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
1267 struct sas_task *task,
1268 struct hisi_sas_slot *slot)
1270 struct task_status_struct *ts = &task->task_status;
1271 struct hisi_sas_err_record_v2 *err_record = slot->status_buffer;
1272 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
1273 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
1274 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
1275 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
1276 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
1279 if (dma_rx_err_type) {
1280 error = ffs(dma_rx_err_type)
1281 - 1 + DMA_RX_ERR_BASE;
1282 } else if (sipc_rx_err_type) {
1283 error = ffs(sipc_rx_err_type)
1284 - 1 + SIPC_RX_ERR_BASE;
1285 } else if (dma_tx_err_type) {
1286 error = ffs(dma_tx_err_type)
1287 - 1 + DMA_TX_ERR_BASE;
1288 } else if (trans_rx_fail_type) {
1289 error = ffs(trans_rx_fail_type)
1290 - 1 + TRANS_RX_FAIL_BASE;
1291 } else if (trans_tx_fail_type) {
1292 error = ffs(trans_tx_fail_type)
1293 - 1 + TRANS_TX_FAIL_BASE;
1296 switch (task->task_proto) {
1297 case SAS_PROTOCOL_SSP:
1300 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1302 ts->stat = SAS_OPEN_REJECT;
1303 ts->open_rej_reason = SAS_OREJ_NO_DEST;
1306 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1308 ts->stat = SAS_OPEN_REJECT;
1309 ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED;
1312 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1314 ts->stat = SAS_OPEN_REJECT;
1315 ts->open_rej_reason = SAS_OREJ_EPROTO;
1318 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1320 ts->stat = SAS_OPEN_REJECT;
1321 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1324 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1326 ts->stat = SAS_OPEN_REJECT;
1327 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1330 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1332 ts->stat = SAS_OPEN_REJECT;
1333 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1336 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1338 ts->stat = SAS_OPEN_REJECT;
1339 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1342 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1344 ts->stat = SAS_OPEN_REJECT;
1345 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1348 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1351 ts->stat = SAS_DEV_NO_RESPONSE;
1354 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1356 ts->stat = SAS_PHY_DOWN;
1359 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1361 ts->stat = SAS_OPEN_TO;
1364 case DMA_RX_DATA_LEN_OVERFLOW:
1366 ts->stat = SAS_DATA_OVERRUN;
1370 case DMA_RX_DATA_LEN_UNDERFLOW:
1371 case SIPC_RX_DATA_UNDERFLOW_ERR:
1373 ts->residual = trans_tx_fail_type;
1374 ts->stat = SAS_DATA_UNDERRUN;
1377 case TRANS_TX_ERR_FRAME_TXED:
1379 /* This will request a retry */
1380 ts->stat = SAS_QUEUE_FULL;
1384 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1385 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1386 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1387 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1388 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1389 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1390 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1391 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1392 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1393 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1394 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1395 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1396 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1397 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1398 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
1399 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1400 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
1401 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1402 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1403 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
1404 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
1405 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
1406 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1407 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1408 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1409 case TRANS_RX_ERR_WITH_DATA_LEN0:
1410 case TRANS_RX_ERR_WITH_BAD_HASH:
1411 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1412 case TRANS_RX_SSP_FRM_LEN_ERR:
1413 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
1414 case DMA_TX_UNEXP_XFER_ERR:
1415 case DMA_TX_UNEXP_RETRANS_ERR:
1416 case DMA_TX_XFER_LEN_OVERFLOW:
1417 case DMA_TX_XFER_OFFSET_ERR:
1418 case DMA_RX_DATA_OFFSET_ERR:
1419 case DMA_RX_UNEXP_NORM_RESP_ERR:
1420 case DMA_RX_UNEXP_RDFRAME_ERR:
1421 case DMA_RX_UNKNOWN_FRM_ERR:
1423 ts->stat = SAS_OPEN_REJECT;
1424 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1432 case SAS_PROTOCOL_SMP:
1433 ts->stat = SAM_STAT_CHECK_CONDITION;
1436 case SAS_PROTOCOL_SATA:
1437 case SAS_PROTOCOL_STP:
1438 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1441 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1442 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1443 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1445 ts->resp = SAS_TASK_UNDELIVERED;
1446 ts->stat = SAS_DEV_NO_RESPONSE;
1449 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1450 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1451 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1452 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1453 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1454 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1455 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
1457 ts->stat = SAS_OPEN_REJECT;
1460 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1462 ts->stat = SAS_OPEN_TO;
1465 case DMA_RX_DATA_LEN_OVERFLOW:
1467 ts->stat = SAS_DATA_OVERRUN;
1470 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1471 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1472 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1473 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1474 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1475 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1476 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1477 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1478 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1479 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1480 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1481 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1482 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1483 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1484 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1485 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
1486 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1487 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1488 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
1489 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
1490 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
1491 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
1492 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1493 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1494 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1495 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1496 case TRANS_RX_ERR_WITH_DATA_LEN0:
1497 case TRANS_RX_ERR_WITH_BAD_HASH:
1498 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1499 case TRANS_RX_SSP_FRM_LEN_ERR:
1500 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
1501 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
1502 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
1503 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
1504 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
1505 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
1506 case SIPC_RX_SATA_UNEXP_FIS_ERR:
1507 case DMA_RX_SATA_FRAME_TYPE_ERR:
1508 case DMA_RX_UNEXP_RDFRAME_ERR:
1509 case DMA_RX_PIO_DATA_LEN_ERR:
1510 case DMA_RX_RDSETUP_STATUS_ERR:
1511 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
1512 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
1513 case DMA_RX_RDSETUP_LEN_ODD_ERR:
1514 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
1515 case DMA_RX_RDSETUP_LEN_OVER_ERR:
1516 case DMA_RX_RDSETUP_OFFSET_ERR:
1517 case DMA_RX_RDSETUP_ACTIVE_ERR:
1518 case DMA_RX_RDSETUP_ESTATUS_ERR:
1519 case DMA_RX_UNKNOWN_FRM_ERR:
1521 ts->stat = SAS_OPEN_REJECT;
1526 ts->stat = SAS_PROTO_RESPONSE;
1530 sata_done_v2_hw(hisi_hba, task, slot);
1539 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
1542 struct sas_task *task = slot->task;
1543 struct hisi_sas_device *sas_dev;
1544 struct device *dev = &hisi_hba->pdev->dev;
1545 struct task_status_struct *ts;
1546 struct domain_device *device;
1547 enum exec_status sts;
1548 struct hisi_sas_complete_v2_hdr *complete_queue =
1549 hisi_hba->complete_hdr[slot->cmplt_queue];
1550 struct hisi_sas_complete_v2_hdr *complete_hdr =
1551 &complete_queue[slot->cmplt_queue_slot];
1553 if (unlikely(!task || !task->lldd_task || !task->dev))
1556 ts = &task->task_status;
1558 sas_dev = device->lldd_dev;
1560 task->task_state_flags &=
1561 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1562 task->task_state_flags |= SAS_TASK_STATE_DONE;
1564 memset(ts, 0, sizeof(*ts));
1565 ts->resp = SAS_TASK_COMPLETE;
1567 if (unlikely(!sas_dev || abort)) {
1569 dev_dbg(dev, "slot complete: port has not device\n");
1570 ts->stat = SAS_PHY_DOWN;
1574 /* Use SAS+TMF status codes */
1575 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1576 >> CMPLT_HDR_ABORT_STAT_OFF) {
1577 case STAT_IO_ABORTED:
1578 /* this io has been aborted by abort command */
1579 ts->stat = SAS_ABORTED_TASK;
1581 case STAT_IO_COMPLETE:
1582 /* internal abort command complete */
1583 ts->stat = TMF_RESP_FUNC_COMPLETE;
1585 case STAT_IO_NO_DEVICE:
1586 ts->stat = TMF_RESP_FUNC_COMPLETE;
1588 case STAT_IO_NOT_VALID:
1589 /* abort single io, controller don't find
1590 * the io need to abort
1592 ts->stat = TMF_RESP_FUNC_FAILED;
1598 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
1599 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
1601 slot_err_v2_hw(hisi_hba, task, slot);
1602 if (unlikely(slot->abort)) {
1603 queue_work(hisi_hba->wq, &slot->abort_slot);
1604 /* immediately return and do not complete */
1610 switch (task->task_proto) {
1611 case SAS_PROTOCOL_SSP:
1613 struct ssp_response_iu *iu = slot->status_buffer +
1614 sizeof(struct hisi_sas_err_record);
1616 sas_ssp_task_response(dev, task, iu);
1619 case SAS_PROTOCOL_SMP:
1621 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1624 ts->stat = SAM_STAT_GOOD;
1625 to = kmap_atomic(sg_page(sg_resp));
1627 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1629 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1631 memcpy(to + sg_resp->offset,
1632 slot->status_buffer +
1633 sizeof(struct hisi_sas_err_record),
1634 sg_dma_len(sg_resp));
1638 case SAS_PROTOCOL_SATA:
1639 case SAS_PROTOCOL_STP:
1640 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1642 ts->stat = SAM_STAT_GOOD;
1643 sata_done_v2_hw(hisi_hba, task, slot);
1647 ts->stat = SAM_STAT_CHECK_CONDITION;
1651 if (!slot->port->port_attached) {
1652 dev_err(dev, "slot complete: port %d has removed\n",
1653 slot->port->sas_port.id);
1654 ts->stat = SAS_PHY_DOWN;
1658 if (sas_dev && sas_dev->running_req)
1659 sas_dev->running_req--;
1661 hisi_sas_slot_task_free(hisi_hba, task, slot);
1664 if (task->task_done)
1665 task->task_done(task);
1670 static u8 get_ata_protocol(u8 cmd, int direction)
1673 case ATA_CMD_FPDMA_WRITE:
1674 case ATA_CMD_FPDMA_READ:
1675 case ATA_CMD_FPDMA_RECV:
1676 case ATA_CMD_FPDMA_SEND:
1677 case ATA_CMD_NCQ_NON_DATA:
1678 return SATA_PROTOCOL_FPDMA;
1680 case ATA_CMD_ID_ATA:
1681 case ATA_CMD_PMP_READ:
1682 case ATA_CMD_READ_LOG_EXT:
1683 case ATA_CMD_PIO_READ:
1684 case ATA_CMD_PIO_READ_EXT:
1685 case ATA_CMD_PMP_WRITE:
1686 case ATA_CMD_WRITE_LOG_EXT:
1687 case ATA_CMD_PIO_WRITE:
1688 case ATA_CMD_PIO_WRITE_EXT:
1689 return SATA_PROTOCOL_PIO;
1692 case ATA_CMD_READ_EXT:
1693 case ATA_CMD_READ_LOG_DMA_EXT:
1695 case ATA_CMD_WRITE_EXT:
1696 case ATA_CMD_WRITE_QUEUED:
1697 case ATA_CMD_WRITE_LOG_DMA_EXT:
1698 return SATA_PROTOCOL_DMA;
1700 case ATA_CMD_DOWNLOAD_MICRO:
1701 case ATA_CMD_DEV_RESET:
1702 case ATA_CMD_CHK_POWER:
1704 case ATA_CMD_FLUSH_EXT:
1705 case ATA_CMD_VERIFY:
1706 case ATA_CMD_VERIFY_EXT:
1707 case ATA_CMD_SET_FEATURES:
1708 case ATA_CMD_STANDBY:
1709 case ATA_CMD_STANDBYNOW1:
1710 return SATA_PROTOCOL_NONDATA;
1712 if (direction == DMA_NONE)
1713 return SATA_PROTOCOL_NONDATA;
1714 return SATA_PROTOCOL_PIO;
1718 static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
1720 struct ata_queued_cmd *qc = task->uldd_task;
1723 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
1724 qc->tf.command == ATA_CMD_FPDMA_READ) {
1732 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
1733 struct hisi_sas_slot *slot)
1735 struct sas_task *task = slot->task;
1736 struct domain_device *device = task->dev;
1737 struct domain_device *parent_dev = device->parent;
1738 struct hisi_sas_device *sas_dev = device->lldd_dev;
1739 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1740 struct hisi_sas_port *port = device->port->lldd_port;
1742 int has_data = 0, rc = 0, hdr_tag = 0;
1743 u32 dw1 = 0, dw2 = 0;
1747 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1748 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1749 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1751 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1754 switch (task->data_dir) {
1757 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1759 case DMA_FROM_DEVICE:
1761 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1764 dw1 &= ~CMD_HDR_DIR_MSK;
1767 if (0 == task->ata_task.fis.command)
1768 dw1 |= 1 << CMD_HDR_RESET_OFF;
1770 dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir))
1771 << CMD_HDR_FRAME_TYPE_OFF;
1772 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1773 hdr->dw1 = cpu_to_le32(dw1);
1776 if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
1777 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1778 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1781 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1782 2 << CMD_HDR_SG_MOD_OFF;
1783 hdr->dw2 = cpu_to_le32(dw2);
1786 hdr->transfer_tags = cpu_to_le32(slot->idx);
1789 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1796 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1797 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1798 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1800 buf_cmd = slot->command_table;
1802 if (likely(!task->ata_task.device_control_reg_update))
1803 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1804 /* fill in command FIS */
1805 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1810 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
1811 struct hisi_sas_slot *slot,
1812 int device_id, int abort_flag, int tag_to_abort)
1814 struct sas_task *task = slot->task;
1815 struct domain_device *dev = task->dev;
1816 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1817 struct hisi_sas_port *port = slot->port;
1820 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1821 (port->id << CMD_HDR_PORT_OFF) |
1822 ((dev_is_sata(dev) ? 1:0) <<
1823 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1824 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
1827 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
1830 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1831 hdr->transfer_tags = cpu_to_le32(slot->idx);
1836 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1839 u32 context, port_id, link_rate, hard_phy_linkrate;
1840 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1841 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1842 struct device *dev = &hisi_hba->pdev->dev;
1843 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1844 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1846 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1848 /* Check for SATA dev */
1849 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1850 if (context & (1 << phy_no))
1854 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1856 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1857 PORT_STATE_PHY8_PORT_NUM_OFF;
1858 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1859 PORT_STATE_PHY8_CONN_RATE_OFF;
1861 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1862 port_id = (port_id >> (4 * phy_no)) & 0xf;
1863 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1864 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1867 if (port_id == 0xf) {
1868 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1873 for (i = 0; i < 6; i++) {
1874 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1875 RX_IDAF_DWORD0 + (i * 4));
1876 frame_rcvd[i] = __swab32(idaf);
1879 sas_phy->linkrate = link_rate;
1880 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1882 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1883 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1885 sas_phy->oob_mode = SAS_OOB_MODE;
1886 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
1887 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1888 phy->port_id = port_id;
1889 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1890 phy->phy_type |= PORT_TYPE_SAS;
1891 phy->phy_attached = 1;
1892 phy->identify.device_type = id->dev_type;
1893 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1894 if (phy->identify.device_type == SAS_END_DEVICE)
1895 phy->identify.target_port_protocols =
1897 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1898 phy->identify.target_port_protocols =
1900 queue_work(hisi_hba->wq, &phy->phyup_ws);
1903 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1904 CHL_INT0_SL_PHY_ENABLE_MSK);
1905 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1910 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1913 u32 phy_cfg, phy_state;
1915 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1917 phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1919 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1921 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1923 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1924 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1929 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
1931 struct hisi_hba *hisi_hba = p;
1934 irqreturn_t res = IRQ_HANDLED;
1936 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
1937 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
1940 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1943 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1945 if (phy_up_v2_hw(phy_no, hisi_hba)) {
1950 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1952 if (phy_down_v2_hw(phy_no, hisi_hba)) {
1965 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1967 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1968 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1969 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1971 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1972 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1973 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1974 CHL_INT0_SL_RX_BCST_ACK_MSK);
1975 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1978 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
1980 struct hisi_hba *hisi_hba = p;
1981 struct device *dev = &hisi_hba->pdev->dev;
1982 u32 ent_msk, ent_tmp, irq_msk;
1985 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1987 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1988 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1990 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
1991 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
1994 if (irq_msk & (1 << phy_no)) {
1995 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1997 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1999 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2003 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2004 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2005 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
2006 dev_name(dev), irq_value1);
2008 hisi_sas_phy_write32(hisi_hba, phy_no,
2009 CHL_INT1, irq_value1);
2013 hisi_sas_phy_write32(hisi_hba, phy_no,
2014 CHL_INT2, irq_value2);
2018 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2019 phy_bcast_v2_hw(phy_no, hisi_hba);
2021 hisi_sas_phy_write32(hisi_hba, phy_no,
2022 CHL_INT0, irq_value0
2023 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2024 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2025 & (~CHL_INT0_NOT_RDY_MSK));
2028 irq_msk &= ~(1 << phy_no);
2032 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2037 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
2039 struct hisi_sas_cq *cq = p;
2040 struct hisi_hba *hisi_hba = cq->hisi_hba;
2041 struct hisi_sas_slot *slot;
2042 struct hisi_sas_itct *itct;
2043 struct hisi_sas_complete_v2_hdr *complete_queue;
2044 u32 irq_value, rd_point = cq->rd_point, wr_point, dev_id;
2047 complete_queue = hisi_hba->complete_hdr[queue];
2048 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
2050 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2052 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2055 while (rd_point != wr_point) {
2056 struct hisi_sas_complete_v2_hdr *complete_hdr;
2059 complete_hdr = &complete_queue[rd_point];
2061 /* Check for NCQ completion */
2062 if (complete_hdr->act) {
2063 u32 act_tmp = complete_hdr->act;
2064 int ncq_tag_count = ffs(act_tmp);
2066 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
2067 CMPLT_HDR_DEV_ID_OFF;
2068 itct = &hisi_hba->itct[dev_id];
2070 /* The NCQ tags are held in the itct header */
2071 while (ncq_tag_count) {
2072 __le64 *ncq_tag = &itct->qw4_15[0];
2075 iptt = (ncq_tag[ncq_tag_count / 5]
2076 >> (ncq_tag_count % 5) * 12) & 0xfff;
2078 slot = &hisi_hba->slot_info[iptt];
2079 slot->cmplt_queue_slot = rd_point;
2080 slot->cmplt_queue = queue;
2081 slot_complete_v2_hw(hisi_hba, slot, 0);
2083 act_tmp &= ~(1 << ncq_tag_count);
2084 ncq_tag_count = ffs(act_tmp);
2087 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
2088 slot = &hisi_hba->slot_info[iptt];
2089 slot->cmplt_queue_slot = rd_point;
2090 slot->cmplt_queue = queue;
2091 slot_complete_v2_hw(hisi_hba, slot, 0);
2094 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2098 /* update rd_point */
2099 cq->rd_point = rd_point;
2100 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2104 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
2106 struct hisi_sas_phy *phy = p;
2107 struct hisi_hba *hisi_hba = phy->hisi_hba;
2108 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2109 struct device *dev = &hisi_hba->pdev->dev;
2110 struct hisi_sas_initial_fis *initial_fis;
2111 struct dev_to_host_fis *fis;
2112 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
2113 irqreturn_t res = IRQ_HANDLED;
2114 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
2117 phy_no = sas_phy->id;
2118 initial_fis = &hisi_hba->initial_fis[phy_no];
2119 fis = &initial_fis->fis;
2121 offset = 4 * (phy_no / 4);
2122 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
2123 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
2124 ent_msk | 1 << ((phy_no % 4) * 8));
2126 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
2127 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
2129 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
2130 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
2131 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
2136 if (unlikely(phy_no == 8)) {
2137 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2139 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2140 PORT_STATE_PHY8_PORT_NUM_OFF;
2141 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2142 PORT_STATE_PHY8_CONN_RATE_OFF;
2144 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2145 port_id = (port_id >> (4 * phy_no)) & 0xf;
2146 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2147 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2150 if (port_id == 0xf) {
2151 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
2156 sas_phy->linkrate = link_rate;
2157 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2159 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2160 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2162 sas_phy->oob_mode = SATA_OOB_MODE;
2163 /* Make up some unique SAS address */
2164 attached_sas_addr[0] = 0x50;
2165 attached_sas_addr[7] = phy_no;
2166 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
2167 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
2168 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2169 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2170 phy->port_id = port_id;
2171 phy->phy_type |= PORT_TYPE_SATA;
2172 phy->phy_attached = 1;
2173 phy->identify.device_type = SAS_SATA_DEV;
2174 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2175 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2176 queue_work(hisi_hba->wq, &phy->phyup_ws);
2179 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
2180 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
2185 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
2186 int_phy_updown_v2_hw,
2191 * There is a limitation in the hip06 chipset that we need
2192 * to map in all mbigen interrupts, even if they are not used.
2194 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
2196 struct platform_device *pdev = hisi_hba->pdev;
2197 struct device *dev = &pdev->dev;
2198 int i, irq, rc, irq_map[128];
2201 for (i = 0; i < 128; i++)
2202 irq_map[i] = platform_get_irq(pdev, i);
2204 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
2207 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
2209 dev_err(dev, "irq init: fail map phy interrupt %d\n",
2214 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
2215 DRV_NAME " phy", hisi_hba);
2217 dev_err(dev, "irq init: could not request "
2218 "phy interrupt %d, rc=%d\n",
2224 for (i = 0; i < hisi_hba->n_phy; i++) {
2225 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
2226 int idx = i + 72; /* First SATA interrupt is irq72 */
2230 dev_err(dev, "irq init: fail map phy interrupt %d\n",
2235 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
2236 DRV_NAME " sata", phy);
2238 dev_err(dev, "irq init: could not request "
2239 "sata interrupt %d, rc=%d\n",
2245 for (i = 0; i < hisi_hba->queue_count; i++) {
2246 int idx = i + 96; /* First cq interrupt is irq96 */
2251 "irq init: could not map cq interrupt %d\n",
2255 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
2256 DRV_NAME " cq", &hisi_hba->cq[i]);
2259 "irq init: could not request cq interrupt %d, rc=%d\n",
2268 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
2272 rc = hw_init_v2_hw(hisi_hba);
2276 rc = interrupt_init_v2_hw(hisi_hba);
2280 phys_init_v2_hw(hisi_hba);
2285 static const struct hisi_sas_hw hisi_sas_v2_hw = {
2286 .hw_init = hisi_sas_v2_init,
2287 .setup_itct = setup_itct_v2_hw,
2288 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
2289 .alloc_dev = alloc_dev_quirk_v2_hw,
2290 .sl_notify = sl_notify_v2_hw,
2291 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
2292 .free_device = free_device_v2_hw,
2293 .prep_smp = prep_smp_v2_hw,
2294 .prep_ssp = prep_ssp_v2_hw,
2295 .prep_stp = prep_ata_v2_hw,
2296 .prep_abort = prep_abort_v2_hw,
2297 .get_free_slot = get_free_slot_v2_hw,
2298 .start_delivery = start_delivery_v2_hw,
2299 .slot_complete = slot_complete_v2_hw,
2300 .phy_enable = enable_phy_v2_hw,
2301 .phy_disable = disable_phy_v2_hw,
2302 .phy_hard_reset = phy_hard_reset_v2_hw,
2303 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
2304 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
2307 static int hisi_sas_v2_probe(struct platform_device *pdev)
2309 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
2312 static int hisi_sas_v2_remove(struct platform_device *pdev)
2314 return hisi_sas_remove(pdev);
2317 static const struct of_device_id sas_v2_of_match[] = {
2318 { .compatible = "hisilicon,hip06-sas-v2",},
2321 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
2323 static const struct acpi_device_id sas_v2_acpi_match[] = {
2328 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
2330 static struct platform_driver hisi_sas_v2_driver = {
2331 .probe = hisi_sas_v2_probe,
2332 .remove = hisi_sas_v2_remove,
2335 .of_match_table = sas_v2_of_match,
2336 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
2340 module_platform_driver(hisi_sas_v2_driver);
2342 MODULE_LICENSE("GPL");
2343 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2344 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
2345 MODULE_ALIAS("platform:" DRV_NAME);