4 * Copyright (c) MontaVista Software, Inc. 2008.
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/spinlock.h>
17 #include <linux/err.h>
20 #include <linux/of_gpio.h>
21 #include <linux/gpio/driver.h>
22 /* FIXME: needed for gpio_to_chip() get rid of this */
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/export.h>
26 #include <soc/fsl/qe/qe.h>
29 struct of_mm_gpio_chip mm_gc;
32 unsigned long pin_flags[QE_PIO_PINS];
33 #define QE_PIN_REQUESTED 0
35 /* shadowed data register to clear/set bits safely */
38 /* saved_regs used to restore dedicated functions */
39 struct qe_pio_regs saved_regs;
42 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
44 struct qe_gpio_chip *qe_gc = gpiochip_get_data(&mm_gc->gc);
45 struct qe_pio_regs __iomem *regs = mm_gc->regs;
47 qe_gc->cpdata = in_be32(®s->cpdata);
48 qe_gc->saved_regs.cpdata = qe_gc->cpdata;
49 qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
50 qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
51 qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
52 qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
53 qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
56 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
58 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
59 struct qe_pio_regs __iomem *regs = mm_gc->regs;
60 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
62 return !!(in_be32(®s->cpdata) & pin_mask);
65 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
67 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
68 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
69 struct qe_pio_regs __iomem *regs = mm_gc->regs;
71 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
73 spin_lock_irqsave(&qe_gc->lock, flags);
76 qe_gc->cpdata |= pin_mask;
78 qe_gc->cpdata &= ~pin_mask;
80 out_be32(®s->cpdata, qe_gc->cpdata);
82 spin_unlock_irqrestore(&qe_gc->lock, flags);
85 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
87 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
88 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
91 spin_lock_irqsave(&qe_gc->lock, flags);
93 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
95 spin_unlock_irqrestore(&qe_gc->lock, flags);
100 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
102 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
103 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
106 qe_gpio_set(gc, gpio, val);
108 spin_lock_irqsave(&qe_gc->lock, flags);
110 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
112 spin_unlock_irqrestore(&qe_gc->lock, flags);
119 * The qe_gpio_chip name is unfortunate, we should change that to
120 * something like qe_pio_controller. Someday.
122 struct qe_gpio_chip *controller;
127 * qe_pin_request - Request a QE pin
128 * @np: device node to get a pin from
129 * @index: index of a pin in the device tree
130 * Context: non-atomic
132 * This function return qe_pin so that you could use it with the rest of
133 * the QE Pin Multiplexing API.
135 struct qe_pin *qe_pin_request(struct device_node *np, int index)
137 struct qe_pin *qe_pin;
138 struct gpio_chip *gc;
139 struct of_mm_gpio_chip *mm_gc;
140 struct qe_gpio_chip *qe_gc;
144 qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
146 pr_debug("%s: can't allocate memory\n", __func__);
147 return ERR_PTR(-ENOMEM);
150 err = of_get_gpio(np, index);
153 gc = gpio_to_chip(err);
157 if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
158 pr_debug("%s: tried to get a non-qe pin\n", __func__);
163 mm_gc = to_of_mm_gpio_chip(gc);
164 qe_gc = gpiochip_get_data(gc);
166 spin_lock_irqsave(&qe_gc->lock, flags);
169 if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
170 qe_pin->controller = qe_gc;
177 spin_unlock_irqrestore(&qe_gc->lock, flags);
183 pr_debug("%s failed with status %d\n", __func__, err);
186 EXPORT_SYMBOL(qe_pin_request);
189 * qe_pin_free - Free a pin
190 * @qe_pin: pointer to the qe_pin structure
193 * This function frees the qe_pin structure and makes a pin available
194 * for further qe_pin_request() calls.
196 void qe_pin_free(struct qe_pin *qe_pin)
198 struct qe_gpio_chip *qe_gc = qe_pin->controller;
200 const int pin = qe_pin->num;
202 spin_lock_irqsave(&qe_gc->lock, flags);
203 test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
204 spin_unlock_irqrestore(&qe_gc->lock, flags);
208 EXPORT_SYMBOL(qe_pin_free);
211 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
212 * @qe_pin: pointer to the qe_pin structure
215 * This function resets a pin to a dedicated peripheral function that
216 * has been set up by the firmware.
218 void qe_pin_set_dedicated(struct qe_pin *qe_pin)
220 struct qe_gpio_chip *qe_gc = qe_pin->controller;
221 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
222 struct qe_pio_regs *sregs = &qe_gc->saved_regs;
223 int pin = qe_pin->num;
224 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
225 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
226 bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
229 spin_lock_irqsave(&qe_gc->lock, flags);
232 clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
233 clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
235 clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
236 clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
239 if (sregs->cpdata & mask1)
240 qe_gc->cpdata |= mask1;
242 qe_gc->cpdata &= ~mask1;
244 out_be32(®s->cpdata, qe_gc->cpdata);
245 clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
247 spin_unlock_irqrestore(&qe_gc->lock, flags);
249 EXPORT_SYMBOL(qe_pin_set_dedicated);
252 * qe_pin_set_gpio - Set a pin to the GPIO mode
253 * @qe_pin: pointer to the qe_pin structure
256 * This function sets a pin to the GPIO mode.
258 void qe_pin_set_gpio(struct qe_pin *qe_pin)
260 struct qe_gpio_chip *qe_gc = qe_pin->controller;
261 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
264 spin_lock_irqsave(&qe_gc->lock, flags);
266 /* Let's make it input by default, GPIO API is able to change that. */
267 __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
269 spin_unlock_irqrestore(&qe_gc->lock, flags);
271 EXPORT_SYMBOL(qe_pin_set_gpio);
273 static int __init qe_add_gpiochips(void)
275 struct device_node *np;
277 for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
279 struct qe_gpio_chip *qe_gc;
280 struct of_mm_gpio_chip *mm_gc;
281 struct gpio_chip *gc;
283 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
289 spin_lock_init(&qe_gc->lock);
291 mm_gc = &qe_gc->mm_gc;
294 mm_gc->save_regs = qe_gpio_save_regs;
295 gc->ngpio = QE_PIO_PINS;
296 gc->direction_input = qe_gpio_dir_in;
297 gc->direction_output = qe_gpio_dir_out;
298 gc->get = qe_gpio_get;
299 gc->set = qe_gpio_set;
301 ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
306 pr_err("%s: registration failed with status %d\n",
309 /* try others anyway */
313 arch_initcall(qe_add_gpiochips);