drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/highmem.h>
  24 #include <linux/delay.h>
  25 #include <linux/slab.h>
  26 #include <linux/spi/spi.h>
  27
  28 #include "spi-dw.h"
  29
  30 #ifdef CONFIG_DEBUG_FS
  31 #include <linux/debugfs.h>
  32 #endif
  33
  34 #define START_STATE     ((void *)0)
  35 #define RUNNING_STATE   ((void *)1)
  36 #define DONE_STATE      ((void *)2)
  37 #define ERROR_STATE     ((void *)-1)
  38
  39 #define MRST_SPI_DEASSERT       0
  40 #define MRST_SPI_ASSERT         1
  41
  42 /* Slave spi_dev related */
  43 struct chip_data {
  44         u16 cr0;
  45         u8 cs;                  /* chip select pin */
  46         u8 n_bytes;             /* current is a 1/2/4 byte op */
  47         u8 tmode;               /* TR/TO/RO/EEPROM */
  48         u8 type;                /* SPI/SSP/MicroWire */
  49
  50         u8 poll_mode;           /* 1 means use poll mode */
  51
  52         u32 dma_width;
  53         u32 rx_threshold;
  54         u32 tx_threshold;
  55         u8 enable_dma;
  56         u8 bits_per_word;
  57         u16 clk_div;            /* baud rate divider */
  58         u32 speed_hz;           /* baud rate */
  59         void (*cs_control)(u32 command);
  60 };
  61
  62 #ifdef CONFIG_DEBUG_FS
  63 #define SPI_REGS_BUFSIZE        1024
  64 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  65                                 size_t count, loff_t *ppos)
  66 {
  67         struct dw_spi *dws;
  68         char *buf;
  69         u32 len = 0;
  70         ssize_t ret;
  71
  72         dws = file->private_data;
  73
  74         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  75         if (!buf)
  76                 return 0;
  77
  78         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  79                         "MRST SPI0 registers:\n");
  80         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  81                         "=================================\n");
  82         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  83                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  84         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  85                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  86         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  87                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  88         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  89                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  90         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  91                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  92         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  93                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  94         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  95                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  96         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  97                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  98         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  99                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
 100         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 101                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
 102         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 103                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
 104         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 105                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
 106         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 107                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
 108         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 109                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
 110         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 111                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
 112         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 113                         "=================================\n");
 114
 115         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 116         kfree(buf);
 117         return ret;
 118 }
 119
 120 static const struct file_operations mrst_spi_regs_ops = {
 121         .owner          = THIS_MODULE,
 122         .open           = simple_open,
 123         .read           = spi_show_regs,
 124         .llseek         = default_llseek,
 125 };
 126
 127 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 128 {
 129         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 130         if (!dws->debugfs)
 131                 return -ENOMEM;
 132
 133         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 134                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 135         return 0;
 136 }
 137
 138 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 139 {
 140         if (dws->debugfs)
 141                 debugfs_remove_recursive(dws->debugfs);
 142 }
 143
 144 #else
 145 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 146 {
 147         return 0;
 148 }
 149
 150 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 151 {
 152 }
 153 #endif /* CONFIG_DEBUG_FS */
 154
 155 /* Return the max entries we can fill into tx fifo */
 156 static inline u32 tx_max(struct dw_spi *dws)
 157 {
 158         u32 tx_left, tx_room, rxtx_gap;
 159
 160         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 161         tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
 162
 163         /*
 164          * Another concern is about the tx/rx mismatch, we
 165          * though to use (dws->fifo_len - rxflr - txflr) as
 166          * one maximum value for tx, but it doesn't cover the
 167          * data which is out of tx/rx fifo and inside the
 168          * shift registers. So a control from sw point of
 169          * view is taken.
 170          */
 171         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 172                         / dws->n_bytes;
 173
 174         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 175 }
 176
 177 /* Return the max entries we should read out of rx fifo */
 178 static inline u32 rx_max(struct dw_spi *dws)
 179 {
 180         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 181
 182         return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR));
 183 }
 184
 185 static void dw_writer(struct dw_spi *dws)
 186 {
 187         u32 max = tx_max(dws);
 188         u16 txw = 0;
 189
 190         while (max--) {
 191                 /* Set the tx word if the transfer's original "tx" is not null */
 192                 if (dws->tx_end - dws->len) {
 193                         if (dws->n_bytes == 1)
 194                                 txw = *(u8 *)(dws->tx);
 195                         else
 196                                 txw = *(u16 *)(dws->tx);
 197                 }
 198                 dw_writew(dws, DW_SPI_DR, txw);
 199                 dws->tx += dws->n_bytes;
 200         }
 201 }
 202
 203 static void dw_reader(struct dw_spi *dws)
 204 {
 205         u32 max = rx_max(dws);
 206         u16 rxw;
 207
 208         while (max--) {
 209                 rxw = dw_readw(dws, DW_SPI_DR);
 210                 /* Care rx only if the transfer's original "rx" is not null */
 211                 if (dws->rx_end - dws->len) {
 212                         if (dws->n_bytes == 1)
 213                                 *(u8 *)(dws->rx) = rxw;
 214                         else
 215                                 *(u16 *)(dws->rx) = rxw;
 216                 }
 217                 dws->rx += dws->n_bytes;
 218         }
 219 }
 220
 221 static void *next_transfer(struct dw_spi *dws)
 222 {
 223         struct spi_message *msg = dws->cur_msg;
 224         struct spi_transfer *trans = dws->cur_transfer;
 225
 226         /* Move to next transfer */
 227         if (trans->transfer_list.next != &msg->transfers) {
 228                 dws->cur_transfer =
 229                         list_entry(trans->transfer_list.next,
 230                                         struct spi_transfer,
 231                                         transfer_list);
 232                 return RUNNING_STATE;
 233         } else
 234                 return DONE_STATE;
 235 }
 236
 237 /*
 238  * Note: first step is the protocol driver prepares
 239  * a dma-capable memory, and this func just need translate
 240  * the virt addr to physical
 241  */
 242 static int map_dma_buffers(struct dw_spi *dws)
 243 {
 244         if (!dws->cur_msg->is_dma_mapped
 245                 || !dws->dma_inited
 246                 || !dws->cur_chip->enable_dma
 247                 || !dws->dma_ops)
 248                 return 0;
 249
 250         if (dws->cur_transfer->tx_dma)
 251                 dws->tx_dma = dws->cur_transfer->tx_dma;
 252
 253         if (dws->cur_transfer->rx_dma)
 254                 dws->rx_dma = dws->cur_transfer->rx_dma;
 255
 256         return 1;
 257 }
 258
 259 /* Caller already set message->status; dma and pio irqs are blocked */
 260 static void giveback(struct dw_spi *dws)
 261 {
 262         struct spi_transfer *last_transfer;
 263         struct spi_message *msg;
 264
 265         msg = dws->cur_msg;
 266         dws->cur_msg = NULL;
 267         dws->cur_transfer = NULL;
 268         dws->prev_chip = dws->cur_chip;
 269         dws->cur_chip = NULL;
 270         dws->dma_mapped = 0;
 271
 272         last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
 273                                         transfer_list);
 274
 275         if (!last_transfer->cs_change && dws->cs_control)
 276                 dws->cs_control(MRST_SPI_DEASSERT);
 277
 278         spi_finalize_current_message(dws->master);
 279 }
 280
 281 static void int_error_stop(struct dw_spi *dws, const char *msg)
 282 {
 283         /* Stop the hw */
 284         spi_enable_chip(dws, 0);
 285
 286         dev_err(&dws->master->dev, "%s\n", msg);
 287         dws->cur_msg->state = ERROR_STATE;
 288         tasklet_schedule(&dws->pump_transfers);
 289 }
 290
 291 void dw_spi_xfer_done(struct dw_spi *dws)
 292 {
 293         /* Update total byte transferred return count actual bytes read */
 294         dws->cur_msg->actual_length += dws->len;
 295
 296         /* Move to next transfer */
 297         dws->cur_msg->state = next_transfer(dws);
 298
 299         /* Handle end of message */
 300         if (dws->cur_msg->state == DONE_STATE) {
 301                 dws->cur_msg->status = 0;
 302                 giveback(dws);
 303         } else
 304                 tasklet_schedule(&dws->pump_transfers);
 305 }
 306 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
 307
 308 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 309 {
 310         u16 irq_status = dw_readw(dws, DW_SPI_ISR);
 311
 312         /* Error handling */
 313         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 314                 dw_readw(dws, DW_SPI_TXOICR);
 315                 dw_readw(dws, DW_SPI_RXOICR);
 316                 dw_readw(dws, DW_SPI_RXUICR);
 317                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 318                 return IRQ_HANDLED;
 319         }
 320
 321         dw_reader(dws);
 322         if (dws->rx_end == dws->rx) {
 323                 spi_mask_intr(dws, SPI_INT_TXEI);
 324                 dw_spi_xfer_done(dws);
 325                 return IRQ_HANDLED;
 326         }
 327         if (irq_status & SPI_INT_TXEI) {
 328                 spi_mask_intr(dws, SPI_INT_TXEI);
 329                 dw_writer(dws);
 330                 /* Enable TX irq always, it will be disabled when RX finished */
 331                 spi_umask_intr(dws, SPI_INT_TXEI);
 332         }
 333
 334         return IRQ_HANDLED;
 335 }
 336
 337 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 338 {
 339         struct dw_spi *dws = dev_id;
 340         u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
 341
 342         if (!irq_status)
 343                 return IRQ_NONE;
 344
 345         if (!dws->cur_msg) {
 346                 spi_mask_intr(dws, SPI_INT_TXEI);
 347                 return IRQ_HANDLED;
 348         }
 349
 350         return dws->transfer_handler(dws);
 351 }
 352
 353 /* Must be called inside pump_transfers() */
 354 static void poll_transfer(struct dw_spi *dws)
 355 {
 356         do {
 357                 dw_writer(dws);
 358                 dw_reader(dws);
 359                 cpu_relax();
 360         } while (dws->rx_end > dws->rx);
 361
 362         dw_spi_xfer_done(dws);
 363 }
 364
 365 static void pump_transfers(unsigned long data)
 366 {
 367         struct dw_spi *dws = (struct dw_spi *)data;
 368         struct spi_message *message = NULL;
 369         struct spi_transfer *transfer = NULL;
 370         struct spi_transfer *previous = NULL;
 371         struct spi_device *spi = NULL;
 372         struct chip_data *chip = NULL;
 373         u8 bits = 0;
 374         u8 imask = 0;
 375         u8 cs_change = 0;
 376         u16 txint_level = 0;
 377         u16 clk_div = 0;
 378         u32 speed = 0;
 379         u32 cr0 = 0;
 380
 381         /* Get current state information */
 382         message = dws->cur_msg;
 383         transfer = dws->cur_transfer;
 384         chip = dws->cur_chip;
 385         spi = message->spi;
 386
 387         if (unlikely(!chip->clk_div))
 388                 chip->clk_div = dws->max_freq / chip->speed_hz;
 389
 390         if (message->state == ERROR_STATE) {
 391                 message->status = -EIO;
 392                 goto early_exit;
 393         }
 394
 395         /* Handle end of message */
 396         if (message->state == DONE_STATE) {
 397                 message->status = 0;
 398                 goto early_exit;
 399         }
 400
 401         /* Delay if requested at end of transfer*/
 402         if (message->state == RUNNING_STATE) {
 403                 previous = list_entry(transfer->transfer_list.prev,
 404                                         struct spi_transfer,
 405                                         transfer_list);
 406                 if (previous->delay_usecs)
 407                         udelay(previous->delay_usecs);
 408         }
 409
 410         dws->n_bytes = chip->n_bytes;
 411         dws->dma_width = chip->dma_width;
 412         dws->cs_control = chip->cs_control;
 413
 414         dws->rx_dma = transfer->rx_dma;
 415         dws->tx_dma = transfer->tx_dma;
 416         dws->tx = (void *)transfer->tx_buf;
 417         dws->tx_end = dws->tx + transfer->len;
 418         dws->rx = transfer->rx_buf;
 419         dws->rx_end = dws->rx + transfer->len;
 420         dws->len = dws->cur_transfer->len;
 421         if (chip != dws->prev_chip)
 422                 cs_change = 1;
 423
 424         cr0 = chip->cr0;
 425
 426         /* Handle per transfer options for bpw and speed */
 427         if (transfer->speed_hz) {
 428                 speed = chip->speed_hz;
 429
 430                 if (transfer->speed_hz != speed) {
 431                         speed = transfer->speed_hz;
 432
 433                         /* clk_div doesn't support odd number */
 434                         clk_div = dws->max_freq / speed;
 435                         clk_div = (clk_div + 1) & 0xfffe;
 436
 437                         chip->speed_hz = speed;
 438                         chip->clk_div = clk_div;
 439                 }
 440         }
 441         if (transfer->bits_per_word) {
 442                 bits = transfer->bits_per_word;
 443                 dws->n_bytes = dws->dma_width = bits >> 3;
 444                 cr0 = (bits - 1)
 445                         | (chip->type << SPI_FRF_OFFSET)
 446                         | (spi->mode << SPI_MODE_OFFSET)
 447                         | (chip->tmode << SPI_TMOD_OFFSET);
 448         }
 449         message->state = RUNNING_STATE;
 450
 451         /*
 452          * Adjust transfer mode if necessary. Requires platform dependent
 453          * chipselect mechanism.
 454          */
 455         if (dws->cs_control) {
 456                 if (dws->rx && dws->tx)
 457                         chip->tmode = SPI_TMOD_TR;
 458                 else if (dws->rx)
 459                         chip->tmode = SPI_TMOD_RO;
 460                 else
 461                         chip->tmode = SPI_TMOD_TO;
 462
 463                 cr0 &= ~SPI_TMOD_MASK;
 464                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 465         }
 466
 467         /* Check if current transfer is a DMA transaction */
 468         dws->dma_mapped = map_dma_buffers(dws);
 469
 470         /*
 471          * Interrupt mode
 472          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 473          */
 474         if (!dws->dma_mapped && !chip->poll_mode) {
 475                 int templen = dws->len / dws->n_bytes;
 476                 txint_level = dws->fifo_len / 2;
 477                 txint_level = (templen > txint_level) ? txint_level : templen;
 478
 479                 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
 480                 dws->transfer_handler = interrupt_transfer;
 481         }
 482
 483         /*
 484          * Reprogram registers only if
 485          *      1. chip select changes
 486          *      2. clk_div is changed
 487          *      3. control value changes
 488          */
 489         if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
 490                 spi_enable_chip(dws, 0);
 491
 492                 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
 493                         dw_writew(dws, DW_SPI_CTRL0, cr0);
 494
 495                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 496                 spi_chip_sel(dws, spi->chip_select);
 497
 498                 /* Set the interrupt mask, for poll mode just disable all int */
 499                 spi_mask_intr(dws, 0xff);
 500                 if (imask)
 501                         spi_umask_intr(dws, imask);
 502                 if (txint_level)
 503                         dw_writew(dws, DW_SPI_TXFLTR, txint_level);
 504
 505                 spi_enable_chip(dws, 1);
 506                 if (cs_change)
 507                         dws->prev_chip = chip;
 508         }
 509
 510         if (dws->dma_mapped)
 511                 dws->dma_ops->dma_transfer(dws, cs_change);
 512
 513         if (chip->poll_mode)
 514                 poll_transfer(dws);
 515
 516         return;
 517
 518 early_exit:
 519         giveback(dws);
 520         return;
 521 }
 522
 523 static int dw_spi_transfer_one_message(struct spi_master *master,
 524                 struct spi_message *msg)
 525 {
 526         struct dw_spi *dws = spi_master_get_devdata(master);
 527
 528         dws->cur_msg = msg;
 529         /* Initial message state*/
 530         dws->cur_msg->state = START_STATE;
 531         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 532                                                 struct spi_transfer,
 533                                                 transfer_list);
 534         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 535
 536         /* Launch transfers */
 537         tasklet_schedule(&dws->pump_transfers);
 538
 539         return 0;
 540 }
 541
 542 /* This may be called twice for each spi dev */
 543 static int dw_spi_setup(struct spi_device *spi)
 544 {
 545         struct dw_spi_chip *chip_info = NULL;
 546         struct chip_data *chip;
 547
 548         /* Only alloc on first setup */
 549         chip = spi_get_ctldata(spi);
 550         if (!chip) {
 551                 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
 552                                 GFP_KERNEL);
 553                 if (!chip)
 554                         return -ENOMEM;
 555                 spi_set_ctldata(spi, chip);
 556         }
 557
 558         /*
 559          * Protocol drivers may change the chip settings, so...
 560          * if chip_info exists, use it
 561          */
 562         chip_info = spi->controller_data;
 563
 564         /* chip_info doesn't always exist */
 565         if (chip_info) {
 566                 if (chip_info->cs_control)
 567                         chip->cs_control = chip_info->cs_control;
 568
 569                 chip->poll_mode = chip_info->poll_mode;
 570                 chip->type = chip_info->type;
 571
 572                 chip->rx_threshold = 0;
 573                 chip->tx_threshold = 0;
 574
 575                 chip->enable_dma = chip_info->enable_dma;
 576         }
 577
 578         if (spi->bits_per_word == 8) {
 579                 chip->n_bytes = 1;
 580                 chip->dma_width = 1;
 581         } else if (spi->bits_per_word == 16) {
 582                 chip->n_bytes = 2;
 583                 chip->dma_width = 2;
 584         }
 585         chip->bits_per_word = spi->bits_per_word;
 586
 587         if (!spi->max_speed_hz) {
 588                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 589                 return -EINVAL;
 590         }
 591         chip->speed_hz = spi->max_speed_hz;
 592
 593         chip->tmode = 0; /* Tx & Rx */
 594         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 595         chip->cr0 = (chip->bits_per_word - 1)
 596                         | (chip->type << SPI_FRF_OFFSET)
 597                         | (spi->mode  << SPI_MODE_OFFSET)
 598                         | (chip->tmode << SPI_TMOD_OFFSET);
 599
 600         return 0;
 601 }
 602
 603 static void dw_spi_cleanup(struct spi_device *spi)
 604 {
 605         struct chip_data *chip = spi_get_ctldata(spi);
 606         kfree(chip);
 607 }
 608
 609 /* Restart the controller, disable all interrupts, clean rx fifo */
 610 static void spi_hw_init(struct dw_spi *dws)
 611 {
 612         spi_enable_chip(dws, 0);
 613         spi_mask_intr(dws, 0xff);
 614         spi_enable_chip(dws, 1);
 615
 616         /*
 617          * Try to detect the FIFO depth if not set by interface driver,
 618          * the depth could be from 2 to 256 from HW spec
 619          */
 620         if (!dws->fifo_len) {
 621                 u32 fifo;
 622                 for (fifo = 2; fifo <= 257; fifo++) {
 623                         dw_writew(dws, DW_SPI_TXFLTR, fifo);
 624                         if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
 625                                 break;
 626                 }
 627
 628                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 629                 dw_writew(dws, DW_SPI_TXFLTR, 0);
 630         }
 631 }
 632
 633 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 634 {
 635         struct spi_master *master;
 636         int ret;
 637
 638         BUG_ON(dws == NULL);
 639
 640         master = spi_alloc_master(dev, 0);
 641         if (!master)
 642                 return -ENOMEM;
 643
 644         dws->master = master;
 645         dws->type = SSI_MOTO_SPI;
 646         dws->prev_chip = NULL;
 647         dws->dma_inited = 0;
 648         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 649         snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
 650                         dws->bus_num);
 651
 652         ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
 653                         dws->name, dws);
 654         if (ret < 0) {
 655                 dev_err(&master->dev, "can not get IRQ\n");
 656                 goto err_free_master;
 657         }
 658
 659         master->mode_bits = SPI_CPOL | SPI_CPHA;
 660         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 661         master->bus_num = dws->bus_num;
 662         master->num_chipselect = dws->num_cs;
 663         master->setup = dw_spi_setup;
 664         master->transfer_one_message = dw_spi_transfer_one_message;
 665         master->max_speed_hz = dws->max_freq;
 666
 667         /* Basic HW init */
 668         spi_hw_init(dws);
 669
 670         if (dws->dma_ops && dws->dma_ops->dma_init) {
 671                 ret = dws->dma_ops->dma_init(dws);
 672                 if (ret) {
 673                         dev_warn(&master->dev, "DMA init failed\n");
 674                         dws->dma_inited = 0;
 675                 }
 676         }
 677
 678         tasklet_init(&dws->pump_transfers, pump_transfers, (unsigned long)dws);
 679
 680         spi_master_set_devdata(master, dws);
 681         ret = devm_spi_register_master(dev, master);
 682         if (ret) {
 683                 dev_err(&master->dev, "problem registering spi master\n");
 684                 goto err_dma_exit;
 685         }
 686
 687         mrst_spi_debugfs_init(dws);
 688         return 0;
 689
 690 err_dma_exit:
 691         if (dws->dma_ops && dws->dma_ops->dma_exit)
 692                 dws->dma_ops->dma_exit(dws);
 693         spi_enable_chip(dws, 0);
 694 err_free_master:
 695         spi_master_put(master);
 696         return ret;
 697 }
 698 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 699
 700 void dw_spi_remove_host(struct dw_spi *dws)
 701 {
 702         if (!dws)
 703                 return;
 704         mrst_spi_debugfs_remove(dws);
 705
 706         if (dws->dma_ops && dws->dma_ops->dma_exit)
 707                 dws->dma_ops->dma_exit(dws);
 708         spi_enable_chip(dws, 0);
 709         /* Disable clk */
 710         spi_set_clk(dws, 0);
 711 }
 712 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 713
 714 int dw_spi_suspend_host(struct dw_spi *dws)
 715 {
 716         int ret = 0;
 717
 718         ret = spi_master_suspend(dws->master);
 719         if (ret)
 720                 return ret;
 721         spi_enable_chip(dws, 0);
 722         spi_set_clk(dws, 0);
 723         return ret;
 724 }
 725 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 726
 727 int dw_spi_resume_host(struct dw_spi *dws)
 728 {
 729         int ret;
 730
 731         spi_hw_init(dws);
 732         ret = spi_master_resume(dws->master);
 733         if (ret)
 734                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 735         return ret;
 736 }
 737 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 738
 739 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 740 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 741 MODULE_LICENSE("GPL v2");