drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/of.h>
  31 #include <linux/of_gpio.h>
  32
  33 #include <mach/dma.h>
  34 #include <plat/s3c64xx-spi.h>
  35
  36 #define MAX_SPI_PORTS           3
  37
  38 /* Registers and bit-fields */
  39
  40 #define S3C64XX_SPI_CH_CFG              0x00
  41 #define S3C64XX_SPI_CLK_CFG             0x04
  42 #define S3C64XX_SPI_MODE_CFG    0x08
  43 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  44 #define S3C64XX_SPI_INT_EN              0x10
  45 #define S3C64XX_SPI_STATUS              0x14
  46 #define S3C64XX_SPI_TX_DATA             0x18
  47 #define S3C64XX_SPI_RX_DATA             0x1C
  48 #define S3C64XX_SPI_PACKET_CNT  0x20
  49 #define S3C64XX_SPI_PENDING_CLR 0x24
  50 #define S3C64XX_SPI_SWAP_CFG    0x28
  51 #define S3C64XX_SPI_FB_CLK              0x2C
  52
  53 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  54 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  55 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  56 #define S3C64XX_SPI_CPOL_L              (1<<3)
  57 #define S3C64XX_SPI_CPHA_B              (1<<2)
  58 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  59 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  60
  61 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  62 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  63 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  64 #define S3C64XX_SPI_PSR_MASK            0xff
  65
  66 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  67 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  68 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  69 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  70 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  71 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  72 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  73 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  74 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  75 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  76 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  77
  78 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  79 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  80
  81 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
  82
  83 #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
  84                                         (c)->regs + S3C64XX_SPI_SLAVE_SEL)
  85
  86 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  87 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  88 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  89 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  90 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  91 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  92 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  93
  94 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  95 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  96 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  97 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  98 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  99 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
 100
 101 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
 102
 103 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 104 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 105 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 106 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 107 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 108
 109 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 110 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 111 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 112 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 113 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 114 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 115 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 116 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 117
 118 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 119
 120 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 121 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 122                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 123 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 124 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 125                                         FIFO_LVL_MASK(i))
 126
 127 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 128 #define S3C64XX_SPI_TRAILCNT_OFF        19
 129
 130 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 131
 132 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 133
 134 #define RXBUSY    (1<<2)
 135 #define TXBUSY    (1<<3)
 136
 137 struct s3c64xx_spi_dma_data {
 138         unsigned                ch;
 139         enum dma_data_direction direction;
 140         enum dma_ch     dmach;
 141         struct property         *dma_prop;
 142 };
 143
 144 /**
 145  * struct s3c64xx_spi_info - SPI Controller hardware info
 146  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 147  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 148  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 149  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 150  * @clk_from_cmu: True, if the controller does not include a clock mux and
 151  *      prescaler unit.
 152  *
 153  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 154  * differ in some aspects such as the size of the fifo and spi bus clock
 155  * setup. Such differences are specified to the driver using this structure
 156  * which is provided as driver data to the driver.
 157  */
 158 struct s3c64xx_spi_port_config {
 159         int     fifo_lvl_mask[MAX_SPI_PORTS];
 160         int     rx_lvl_offset;
 161         int     tx_st_done;
 162         bool    high_speed;
 163         bool    clk_from_cmu;
 164 };
 165
 166 /**
 167  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 168  * @clk: Pointer to the spi clock.
 169  * @src_clk: Pointer to the clock used to generate SPI signals.
 170  * @master: Pointer to the SPI Protocol master.
 171  * @cntrlr_info: Platform specific data for the controller this driver manages.
 172  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 173  * @queue: To log SPI xfer requests.
 174  * @lock: Controller specific lock.
 175  * @state: Set of FLAGS to indicate status.
 176  * @rx_dmach: Controller's DMA channel for Rx.
 177  * @tx_dmach: Controller's DMA channel for Tx.
 178  * @sfr_start: BUS address of SPI controller regs.
 179  * @regs: Pointer to ioremap'ed controller registers.
 180  * @irq: interrupt
 181  * @xfer_completion: To indicate completion of xfer task.
 182  * @cur_mode: Stores the active configuration of the controller.
 183  * @cur_bpw: Stores the active bits per word settings.
 184  * @cur_speed: Stores the active xfer clock speed.
 185  */
 186 struct s3c64xx_spi_driver_data {
 187         void __iomem                    *regs;
 188         struct clk                      *clk;
 189         struct clk                      *src_clk;
 190         struct platform_device          *pdev;
 191         struct spi_master               *master;
 192         struct s3c64xx_spi_info  *cntrlr_info;
 193         struct spi_device               *tgl_spi;
 194         struct list_head                queue;
 195         spinlock_t                      lock;
 196         unsigned long                   sfr_start;
 197         struct completion               xfer_completion;
 198         unsigned                        state;
 199         unsigned                        cur_mode, cur_bpw;
 200         unsigned                        cur_speed;
 201         struct s3c64xx_spi_dma_data     rx_dma;
 202         struct s3c64xx_spi_dma_data     tx_dma;
 203         struct samsung_dma_ops          *ops;
 204         struct s3c64xx_spi_port_config  *port_conf;
 205         unsigned int                    port_id;
 206         unsigned long                   gpios[4];
 207 };
 208
 209 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 210         .name = "samsung-spi-dma",
 211 };
 212
 213 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 214 {
 215         void __iomem *regs = sdd->regs;
 216         unsigned long loops;
 217         u32 val;
 218
 219         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 220
 221         val = readl(regs + S3C64XX_SPI_CH_CFG);
 222         val |= S3C64XX_SPI_CH_SW_RST;
 223         val &= ~S3C64XX_SPI_CH_HS_EN;
 224         writel(val, regs + S3C64XX_SPI_CH_CFG);
 225
 226         /* Flush TxFIFO*/
 227         loops = msecs_to_loops(1);
 228         do {
 229                 val = readl(regs + S3C64XX_SPI_STATUS);
 230         } while (TX_FIFO_LVL(val, sdd) && loops--);
 231
 232         if (loops == 0)
 233                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 234
 235         /* Flush RxFIFO*/
 236         loops = msecs_to_loops(1);
 237         do {
 238                 val = readl(regs + S3C64XX_SPI_STATUS);
 239                 if (RX_FIFO_LVL(val, sdd))
 240                         readl(regs + S3C64XX_SPI_RX_DATA);
 241                 else
 242                         break;
 243         } while (loops--);
 244
 245         if (loops == 0)
 246                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 247
 248         val = readl(regs + S3C64XX_SPI_CH_CFG);
 249         val &= ~S3C64XX_SPI_CH_SW_RST;
 250         writel(val, regs + S3C64XX_SPI_CH_CFG);
 251
 252         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 253         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 254         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 255
 256         val = readl(regs + S3C64XX_SPI_CH_CFG);
 257         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 258         writel(val, regs + S3C64XX_SPI_CH_CFG);
 259 }
 260
 261 static void s3c64xx_spi_dmacb(void *data)
 262 {
 263         struct s3c64xx_spi_driver_data *sdd;
 264         struct s3c64xx_spi_dma_data *dma = data;
 265         unsigned long flags;
 266
 267         if (dma->direction == DMA_FROM_DEVICE)
 268                 sdd = container_of(data,
 269                         struct s3c64xx_spi_driver_data, rx_dma);
 270         else
 271                 sdd = container_of(data,
 272                         struct s3c64xx_spi_driver_data, tx_dma);
 273
 274         spin_lock_irqsave(&sdd->lock, flags);
 275
 276         if (dma->direction == DMA_FROM_DEVICE) {
 277                 sdd->state &= ~RXBUSY;
 278                 if (!(sdd->state & TXBUSY))
 279                         complete(&sdd->xfer_completion);
 280         } else {
 281                 sdd->state &= ~TXBUSY;
 282                 if (!(sdd->state & RXBUSY))
 283                         complete(&sdd->xfer_completion);
 284         }
 285
 286         spin_unlock_irqrestore(&sdd->lock, flags);
 287 }
 288
 289 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 290                                         unsigned len, dma_addr_t buf)
 291 {
 292         struct s3c64xx_spi_driver_data *sdd;
 293         struct samsung_dma_prep_info info;
 294
 295         if (dma->direction == DMA_FROM_DEVICE)
 296                 sdd = container_of((void *)dma,
 297                         struct s3c64xx_spi_driver_data, rx_dma);
 298         else
 299                 sdd = container_of((void *)dma,
 300                         struct s3c64xx_spi_driver_data, tx_dma);
 301
 302         info.cap = DMA_SLAVE;
 303         info.len = len;
 304         info.fp = s3c64xx_spi_dmacb;
 305         info.fp_param = dma;
 306         info.direction = dma->direction;
 307         info.buf = buf;
 308
 309         sdd->ops->prepare(dma->ch, &info);
 310         sdd->ops->trigger(dma->ch);
 311 }
 312
 313 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 314 {
 315         struct samsung_dma_info info;
 316
 317         sdd->ops = samsung_dma_get_ops();
 318
 319         info.cap = DMA_SLAVE;
 320         info.client = &s3c64xx_spi_dma_client;
 321         info.width = sdd->cur_bpw / 8;
 322
 323         info.direction = sdd->rx_dma.direction;
 324         info.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 325         info.dt_dmach_prop = sdd->rx_dma.dma_prop;
 326         sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &info);
 327         info.direction =  sdd->tx_dma.direction;
 328         info.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 329         info.dt_dmach_prop = sdd->tx_dma.dma_prop;
 330         sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &info);
 331
 332         return 1;
 333 }
 334
 335 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 336                                 struct spi_device *spi,
 337                                 struct spi_transfer *xfer, int dma_mode)
 338 {
 339         void __iomem *regs = sdd->regs;
 340         u32 modecfg, chcfg;
 341
 342         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 343         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 344
 345         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 346         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 347
 348         if (dma_mode) {
 349                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 350         } else {
 351                 /* Always shift in data in FIFO, even if xfer is Tx only,
 352                  * this helps setting PCKT_CNT value for generating clocks
 353                  * as exactly needed.
 354                  */
 355                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 356                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 357                                         | S3C64XX_SPI_PACKET_CNT_EN,
 358                                         regs + S3C64XX_SPI_PACKET_CNT);
 359         }
 360
 361         if (xfer->tx_buf != NULL) {
 362                 sdd->state |= TXBUSY;
 363                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 364                 if (dma_mode) {
 365                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 366                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 367                 } else {
 368                         switch (sdd->cur_bpw) {
 369                         case 32:
 370                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 371                                         xfer->tx_buf, xfer->len / 4);
 372                                 break;
 373                         case 16:
 374                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 375                                         xfer->tx_buf, xfer->len / 2);
 376                                 break;
 377                         default:
 378                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 379                                         xfer->tx_buf, xfer->len);
 380                                 break;
 381                         }
 382                 }
 383         }
 384
 385         if (xfer->rx_buf != NULL) {
 386                 sdd->state |= RXBUSY;
 387
 388                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 389                                         && !(sdd->cur_mode & SPI_CPHA))
 390                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 391
 392                 if (dma_mode) {
 393                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 394                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 395                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 396                                         | S3C64XX_SPI_PACKET_CNT_EN,
 397                                         regs + S3C64XX_SPI_PACKET_CNT);
 398                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 399                 }
 400         }
 401
 402         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 403         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 404 }
 405
 406 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 407                                                 struct spi_device *spi)
 408 {
 409         struct s3c64xx_spi_csinfo *cs;
 410
 411         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 412                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 413                         /* Deselect the last toggled device */
 414                         cs = sdd->tgl_spi->controller_data;
 415                         gpio_set_value(cs->line,
 416                                 spi->mode & SPI_CS_HIGH ? 0 : 1);
 417                 }
 418                 sdd->tgl_spi = NULL;
 419         }
 420
 421         cs = spi->controller_data;
 422         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 423 }
 424
 425 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 426                                 struct spi_transfer *xfer, int dma_mode)
 427 {
 428         void __iomem *regs = sdd->regs;
 429         unsigned long val;
 430         int ms;
 431
 432         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 433         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 434         ms += 10; /* some tolerance */
 435
 436         if (dma_mode) {
 437                 val = msecs_to_jiffies(ms) + 10;
 438                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 439         } else {
 440                 u32 status;
 441                 val = msecs_to_loops(ms);
 442                 do {
 443                         status = readl(regs + S3C64XX_SPI_STATUS);
 444                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 445         }
 446
 447         if (!val)
 448                 return -EIO;
 449
 450         if (dma_mode) {
 451                 u32 status;
 452
 453                 /*
 454                  * DmaTx returns after simply writing data in the FIFO,
 455                  * w/o waiting for real transmission on the bus to finish.
 456                  * DmaRx returns only after Dma read data from FIFO which
 457                  * needs bus transmission to finish, so we don't worry if
 458                  * Xfer involved Rx(with or without Tx).
 459                  */
 460                 if (xfer->rx_buf == NULL) {
 461                         val = msecs_to_loops(10);
 462                         status = readl(regs + S3C64XX_SPI_STATUS);
 463                         while ((TX_FIFO_LVL(status, sdd)
 464                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 465                                         && --val) {
 466                                 cpu_relax();
 467                                 status = readl(regs + S3C64XX_SPI_STATUS);
 468                         }
 469
 470                         if (!val)
 471                                 return -EIO;
 472                 }
 473         } else {
 474                 /* If it was only Tx */
 475                 if (xfer->rx_buf == NULL) {
 476                         sdd->state &= ~TXBUSY;
 477                         return 0;
 478                 }
 479
 480                 switch (sdd->cur_bpw) {
 481                 case 32:
 482                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 483                                 xfer->rx_buf, xfer->len / 4);
 484                         break;
 485                 case 16:
 486                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 487                                 xfer->rx_buf, xfer->len / 2);
 488                         break;
 489                 default:
 490                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 491                                 xfer->rx_buf, xfer->len);
 492                         break;
 493                 }
 494                 sdd->state &= ~RXBUSY;
 495         }
 496
 497         return 0;
 498 }
 499
 500 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 501                                                 struct spi_device *spi)
 502 {
 503         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 504
 505         if (sdd->tgl_spi == spi)
 506                 sdd->tgl_spi = NULL;
 507
 508         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 509 }
 510
 511 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 512 {
 513         void __iomem *regs = sdd->regs;
 514         u32 val;
 515
 516         /* Disable Clock */
 517         if (sdd->port_conf->clk_from_cmu) {
 518                 clk_disable(sdd->src_clk);
 519         } else {
 520                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 521                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 522                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 523         }
 524
 525         /* Set Polarity and Phase */
 526         val = readl(regs + S3C64XX_SPI_CH_CFG);
 527         val &= ~(S3C64XX_SPI_CH_SLAVE |
 528                         S3C64XX_SPI_CPOL_L |
 529                         S3C64XX_SPI_CPHA_B);
 530
 531         if (sdd->cur_mode & SPI_CPOL)
 532                 val |= S3C64XX_SPI_CPOL_L;
 533
 534         if (sdd->cur_mode & SPI_CPHA)
 535                 val |= S3C64XX_SPI_CPHA_B;
 536
 537         writel(val, regs + S3C64XX_SPI_CH_CFG);
 538
 539         /* Set Channel & DMA Mode */
 540         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 541         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 542                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 543
 544         switch (sdd->cur_bpw) {
 545         case 32:
 546                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 547                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 548                 break;
 549         case 16:
 550                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 551                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 552                 break;
 553         default:
 554                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 555                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 556                 break;
 557         }
 558
 559         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 560
 561         if (sdd->port_conf->clk_from_cmu) {
 562                 /* Configure Clock */
 563                 /* There is half-multiplier before the SPI */
 564                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 565                 /* Enable Clock */
 566                 clk_enable(sdd->src_clk);
 567         } else {
 568                 /* Configure Clock */
 569                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 570                 val &= ~S3C64XX_SPI_PSR_MASK;
 571                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 572                                 & S3C64XX_SPI_PSR_MASK);
 573                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 574
 575                 /* Enable Clock */
 576                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 577                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 578                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 579         }
 580 }
 581
 582 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 583
 584 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 585                                                 struct spi_message *msg)
 586 {
 587         struct device *dev = &sdd->pdev->dev;
 588         struct spi_transfer *xfer;
 589
 590         if (msg->is_dma_mapped)
 591                 return 0;
 592
 593         /* First mark all xfer unmapped */
 594         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 595                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 596                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 597         }
 598
 599         /* Map until end or first fail */
 600         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 601
 602                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 603                         continue;
 604
 605                 if (xfer->tx_buf != NULL) {
 606                         xfer->tx_dma = dma_map_single(dev,
 607                                         (void *)xfer->tx_buf, xfer->len,
 608                                         DMA_TO_DEVICE);
 609                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 610                                 dev_err(dev, "dma_map_single Tx failed\n");
 611                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 612                                 return -ENOMEM;
 613                         }
 614                 }
 615
 616                 if (xfer->rx_buf != NULL) {
 617                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 618                                                 xfer->len, DMA_FROM_DEVICE);
 619                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 620                                 dev_err(dev, "dma_map_single Rx failed\n");
 621                                 dma_unmap_single(dev, xfer->tx_dma,
 622                                                 xfer->len, DMA_TO_DEVICE);
 623                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 624                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 625                                 return -ENOMEM;
 626                         }
 627                 }
 628         }
 629
 630         return 0;
 631 }
 632
 633 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 634                                                 struct spi_message *msg)
 635 {
 636         struct device *dev = &sdd->pdev->dev;
 637         struct spi_transfer *xfer;
 638
 639         if (msg->is_dma_mapped)
 640                 return;
 641
 642         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 643
 644                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 645                         continue;
 646
 647                 if (xfer->rx_buf != NULL
 648                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 649                         dma_unmap_single(dev, xfer->rx_dma,
 650                                                 xfer->len, DMA_FROM_DEVICE);
 651
 652                 if (xfer->tx_buf != NULL
 653                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 654                         dma_unmap_single(dev, xfer->tx_dma,
 655                                                 xfer->len, DMA_TO_DEVICE);
 656         }
 657 }
 658
 659 static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 660                                             struct spi_message *msg)
 661 {
 662         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 663         struct spi_device *spi = msg->spi;
 664         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 665         struct spi_transfer *xfer;
 666         int status = 0, cs_toggle = 0;
 667         u32 speed;
 668         u8 bpw;
 669
 670         /* If Master's(controller) state differs from that needed by Slave */
 671         if (sdd->cur_speed != spi->max_speed_hz
 672                         || sdd->cur_mode != spi->mode
 673                         || sdd->cur_bpw != spi->bits_per_word) {
 674                 sdd->cur_bpw = spi->bits_per_word;
 675                 sdd->cur_speed = spi->max_speed_hz;
 676                 sdd->cur_mode = spi->mode;
 677                 s3c64xx_spi_config(sdd);
 678         }
 679
 680         /* Map all the transfers if needed */
 681         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 682                 dev_err(&spi->dev,
 683                         "Xfer: Unable to map message buffers!\n");
 684                 status = -ENOMEM;
 685                 goto out;
 686         }
 687
 688         /* Configure feedback delay */
 689         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 690
 691         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 692
 693                 unsigned long flags;
 694                 int use_dma;
 695
 696                 INIT_COMPLETION(sdd->xfer_completion);
 697
 698                 /* Only BPW and Speed may change across transfers */
 699                 bpw = xfer->bits_per_word ? : spi->bits_per_word;
 700                 speed = xfer->speed_hz ? : spi->max_speed_hz;
 701
 702                 if (xfer->len % (bpw / 8)) {
 703                         dev_err(&spi->dev,
 704                                 "Xfer length(%u) not a multiple of word size(%u)\n",
 705                                 xfer->len, bpw / 8);
 706                         status = -EIO;
 707                         goto out;
 708                 }
 709
 710                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 711                         sdd->cur_bpw = bpw;
 712                         sdd->cur_speed = speed;
 713                         s3c64xx_spi_config(sdd);
 714                 }
 715
 716                 /* Polling method for xfers not bigger than FIFO capacity */
 717                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 718                         use_dma = 0;
 719                 else
 720                         use_dma = 1;
 721
 722                 spin_lock_irqsave(&sdd->lock, flags);
 723
 724                 /* Pending only which is to be done */
 725                 sdd->state &= ~RXBUSY;
 726                 sdd->state &= ~TXBUSY;
 727
 728                 enable_datapath(sdd, spi, xfer, use_dma);
 729
 730                 /* Slave Select */
 731                 enable_cs(sdd, spi);
 732
 733                 /* Start the signals */
 734                 S3C64XX_SPI_ACT(sdd);
 735
 736                 spin_unlock_irqrestore(&sdd->lock, flags);
 737
 738                 status = wait_for_xfer(sdd, xfer, use_dma);
 739
 740                 /* Quiese the signals */
 741                 S3C64XX_SPI_DEACT(sdd);
 742
 743                 if (status) {
 744                         dev_err(&spi->dev, "I/O Error: "
 745                                 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 746                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 747                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 748                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 749                                 xfer->len);
 750
 751                         if (use_dma) {
 752                                 if (xfer->tx_buf != NULL
 753                                                 && (sdd->state & TXBUSY))
 754                                         sdd->ops->stop(sdd->tx_dma.ch);
 755                                 if (xfer->rx_buf != NULL
 756                                                 && (sdd->state & RXBUSY))
 757                                         sdd->ops->stop(sdd->rx_dma.ch);
 758                         }
 759
 760                         goto out;
 761                 }
 762
 763                 if (xfer->delay_usecs)
 764                         udelay(xfer->delay_usecs);
 765
 766                 if (xfer->cs_change) {
 767                         /* Hint that the next mssg is gonna be
 768                            for the same device */
 769                         if (list_is_last(&xfer->transfer_list,
 770                                                 &msg->transfers))
 771                                 cs_toggle = 1;
 772                         else
 773                                 disable_cs(sdd, spi);
 774                 }
 775
 776                 msg->actual_length += xfer->len;
 777
 778                 flush_fifo(sdd);
 779         }
 780
 781 out:
 782         if (!cs_toggle || status)
 783                 disable_cs(sdd, spi);
 784         else
 785                 sdd->tgl_spi = spi;
 786
 787         s3c64xx_spi_unmap_mssg(sdd, msg);
 788
 789         msg->status = status;
 790
 791         spi_finalize_current_message(master);
 792
 793         return 0;
 794 }
 795
 796 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 797 {
 798         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 799
 800         /* Acquire DMA channels */
 801         while (!acquire_dma(sdd))
 802                 msleep(10);
 803
 804         pm_runtime_get_sync(&sdd->pdev->dev);
 805
 806         return 0;
 807 }
 808
 809 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 810 {
 811         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 812
 813         /* Free DMA channels */
 814         sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
 815         sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
 816
 817         pm_runtime_put(&sdd->pdev->dev);
 818
 819         return 0;
 820 }
 821
 822 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 823                                 struct s3c64xx_spi_driver_data *sdd,
 824                                 struct spi_device *spi)
 825 {
 826         struct s3c64xx_spi_csinfo *cs;
 827         struct device_node *slave_np, *data_np;
 828         u32 fb_delay = 0;
 829
 830         slave_np = spi->dev.of_node;
 831         if (!slave_np) {
 832                 dev_err(&spi->dev, "device node not found\n");
 833                 return ERR_PTR(-EINVAL);
 834         }
 835
 836         for_each_child_of_node(slave_np, data_np)
 837                 if (!strcmp(data_np->name, "controller-data"))
 838                         break;
 839         if (!data_np) {
 840                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 841                 return ERR_PTR(-EINVAL);
 842         }
 843
 844         cs = devm_kzalloc(&sdd->pdev->dev, sizeof(*cs), GFP_KERNEL);
 845         if (!cs) {
 846                 dev_err(&spi->dev, "could not allocate memory for controller"
 847                                         " data\n");
 848                 return ERR_PTR(-ENOMEM);
 849         }
 850
 851         cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
 852         if (!gpio_is_valid(cs->line)) {
 853                 dev_err(&spi->dev, "chip select gpio is invalid\n");
 854                 return ERR_PTR(-EINVAL);
 855         }
 856         if (devm_gpio_request(&sdd->pdev->dev, cs->line, "spi-cs")) {
 857                 dev_err(&spi->dev, "gpio [%d] request failed\n", cs->line);
 858                 return ERR_PTR(-EBUSY);
 859         }
 860
 861         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 862         cs->fb_delay = fb_delay;
 863         return cs;
 864 }
 865
 866 /*
 867  * Here we only check the validity of requested configuration
 868  * and save the configuration in a local data-structure.
 869  * The controller is actually configured only just before we
 870  * get a message to transfer.
 871  */
 872 static int s3c64xx_spi_setup(struct spi_device *spi)
 873 {
 874         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 875         struct s3c64xx_spi_driver_data *sdd;
 876         struct s3c64xx_spi_info *sci;
 877         struct spi_message *msg;
 878         unsigned long flags;
 879         int err = 0;
 880
 881         sdd = spi_master_get_devdata(spi->master);
 882         if (!cs && spi->dev.of_node) {
 883                 cs = s3c64xx_get_slave_ctrldata(sdd, spi);
 884                 spi->controller_data = cs;
 885         }
 886
 887         if (IS_ERR_OR_NULL(cs)) {
 888                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 889                 return -ENODEV;
 890         }
 891
 892         sci = sdd->cntrlr_info;
 893
 894         spin_lock_irqsave(&sdd->lock, flags);
 895
 896         list_for_each_entry(msg, &sdd->queue, queue) {
 897                 /* Is some mssg is already queued for this device */
 898                 if (msg->spi == spi) {
 899                         dev_err(&spi->dev,
 900                                 "setup: attempt while mssg in queue!\n");
 901                         spin_unlock_irqrestore(&sdd->lock, flags);
 902                         return -EBUSY;
 903                 }
 904         }
 905
 906         spin_unlock_irqrestore(&sdd->lock, flags);
 907
 908         if (spi->bits_per_word != 8
 909                         && spi->bits_per_word != 16
 910                         && spi->bits_per_word != 32) {
 911                 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
 912                                                         spi->bits_per_word);
 913                 err = -EINVAL;
 914                 goto setup_exit;
 915         }
 916
 917         pm_runtime_get_sync(&sdd->pdev->dev);
 918
 919         /* Check if we can provide the requested rate */
 920         if (!sdd->port_conf->clk_from_cmu) {
 921                 u32 psr, speed;
 922
 923                 /* Max possible */
 924                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 925
 926                 if (spi->max_speed_hz > speed)
 927                         spi->max_speed_hz = speed;
 928
 929                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 930                 psr &= S3C64XX_SPI_PSR_MASK;
 931                 if (psr == S3C64XX_SPI_PSR_MASK)
 932                         psr--;
 933
 934                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 935                 if (spi->max_speed_hz < speed) {
 936                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 937                                 psr++;
 938                         } else {
 939                                 err = -EINVAL;
 940                                 goto setup_exit;
 941                         }
 942                 }
 943
 944                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 945                 if (spi->max_speed_hz >= speed)
 946                         spi->max_speed_hz = speed;
 947                 else
 948                         err = -EINVAL;
 949         }
 950
 951         pm_runtime_put(&sdd->pdev->dev);
 952
 953 setup_exit:
 954
 955         /* setup() returns with device de-selected */
 956         disable_cs(sdd, spi);
 957
 958         return err;
 959 }
 960
 961 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 962 {
 963         struct s3c64xx_spi_driver_data *sdd = data;
 964         struct spi_master *spi = sdd->master;
 965         unsigned int val;
 966
 967         val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
 968
 969         val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
 970                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
 971                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
 972                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 973
 974         writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 975
 976         if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
 977                 dev_err(&spi->dev, "RX overrun\n");
 978         if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
 979                 dev_err(&spi->dev, "RX underrun\n");
 980         if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
 981                 dev_err(&spi->dev, "TX overrun\n");
 982         if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
 983                 dev_err(&spi->dev, "TX underrun\n");
 984
 985         return IRQ_HANDLED;
 986 }
 987
 988 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
 989 {
 990         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 991         void __iomem *regs = sdd->regs;
 992         unsigned int val;
 993
 994         sdd->cur_speed = 0;
 995
 996         S3C64XX_SPI_DEACT(sdd);
 997
 998         /* Disable Interrupts - we use Polling if not DMA mode */
 999         writel(0, regs + S3C64XX_SPI_INT_EN);
1000
1001         if (!sdd->port_conf->clk_from_cmu)
1002                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1003                                 regs + S3C64XX_SPI_CLK_CFG);
1004         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1005         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1006
1007         /* Clear any irq pending bits */
1008         writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
1009                                 regs + S3C64XX_SPI_PENDING_CLR);
1010
1011         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1012
1013         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1014         val &= ~S3C64XX_SPI_MODE_4BURST;
1015         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1016         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1017         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1018
1019         flush_fifo(sdd);
1020 }
1021
1022 static int __devinit s3c64xx_spi_get_dmares(
1023                         struct s3c64xx_spi_driver_data *sdd, bool tx)
1024 {
1025         struct platform_device *pdev = sdd->pdev;
1026         struct s3c64xx_spi_dma_data *dma_data;
1027         struct property *prop;
1028         struct resource *res;
1029         char prop_name[15], *chan_str;
1030
1031         if (tx) {
1032                 dma_data = &sdd->tx_dma;
1033                 dma_data->direction = DMA_TO_DEVICE;
1034                 chan_str = "tx";
1035         } else {
1036                 dma_data = &sdd->rx_dma;
1037                 dma_data->direction = DMA_FROM_DEVICE;
1038                 chan_str = "rx";
1039         }
1040
1041         if (!sdd->pdev->dev.of_node) {
1042                 res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1);
1043                 if (!res) {
1044                         dev_err(&pdev->dev, "Unable to get SPI-%s dma "
1045                                         "resource\n", chan_str);
1046                         return -ENXIO;
1047                 }
1048                 dma_data->dmach = res->start;
1049                 return 0;
1050         }
1051
1052         sprintf(prop_name, "%s-dma-channel", chan_str);
1053         prop = of_find_property(pdev->dev.of_node, prop_name, NULL);
1054         if (!prop) {
1055                 dev_err(&pdev->dev, "%s dma channel property not specified\n",
1056                                         chan_str);
1057                 return -ENXIO;
1058         }
1059
1060         dma_data->dmach = DMACH_DT_PROP;
1061         dma_data->dma_prop = prop;
1062         return 0;
1063 }
1064
1065 #ifdef CONFIG_OF
1066 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1067 {
1068         struct device *dev = &sdd->pdev->dev;
1069         int idx, gpio, ret;
1070
1071         /* find gpios for mosi, miso and clock lines */
1072         for (idx = 0; idx < 3; idx++) {
1073                 gpio = of_get_gpio(dev->of_node, idx);
1074                 if (!gpio_is_valid(gpio)) {
1075                         dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
1076                         goto free_gpio;
1077                 }
1078                 sdd->gpios[idx] = gpio;
1079                 ret = gpio_request(gpio, "spi-bus");
1080                 if (ret) {
1081                         dev_err(dev, "gpio [%d] request failed\n", gpio);
1082                         goto free_gpio;
1083                 }
1084         }
1085         return 0;
1086
1087 free_gpio:
1088         while (--idx >= 0)
1089                 gpio_free(sdd->gpios[idx]);
1090         return -EINVAL;
1091 }
1092
1093 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1094 {
1095         unsigned int idx;
1096         for (idx = 0; idx < 3; idx++)
1097                 gpio_free(sdd->gpios[idx]);
1098 }
1099
1100 static struct __devinit s3c64xx_spi_info * s3c64xx_spi_parse_dt(
1101                                                 struct device *dev)
1102 {
1103         struct s3c64xx_spi_info *sci;
1104         u32 temp;
1105
1106         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1107         if (!sci) {
1108                 dev_err(dev, "memory allocation for spi_info failed\n");
1109                 return ERR_PTR(-ENOMEM);
1110         }
1111
1112         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1113                 dev_warn(dev, "spi bus clock parent not specified, using "
1114                                 "clock at index 0 as parent\n");
1115                 sci->src_clk_nr = 0;
1116         } else {
1117                 sci->src_clk_nr = temp;
1118         }
1119
1120         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1121                 dev_warn(dev, "number of chip select lines not specified, "
1122                                 "assuming 1 chip select line\n");
1123                 sci->num_cs = 1;
1124         } else {
1125                 sci->num_cs = temp;
1126         }
1127
1128         return sci;
1129 }
1130 #else
1131 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1132 {
1133         return dev->platform_data;
1134 }
1135
1136 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1137 {
1138         return -EINVAL;
1139 }
1140
1141 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1142 {
1143 }
1144 #endif
1145
1146 static const struct of_device_id s3c64xx_spi_dt_match[];
1147
1148 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1149                                                 struct platform_device *pdev)
1150 {
1151 #ifdef CONFIG_OF
1152         if (pdev->dev.of_node) {
1153                 const struct of_device_id *match;
1154                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1155                 return (struct s3c64xx_spi_port_config *)match->data;
1156         }
1157 #endif
1158         return (struct s3c64xx_spi_port_config *)
1159                          platform_get_device_id(pdev)->driver_data;
1160 }
1161
1162 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1163 {
1164         struct resource *mem_res;
1165         struct s3c64xx_spi_driver_data *sdd;
1166         struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
1167         struct spi_master *master;
1168         int ret, irq;
1169         char clk_name[16];
1170
1171         if (!sci && pdev->dev.of_node) {
1172                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1173                 if (IS_ERR(sci))
1174                         return PTR_ERR(sci);
1175         }
1176
1177         if (!sci) {
1178                 dev_err(&pdev->dev, "platform_data missing!\n");
1179                 return -ENODEV;
1180         }
1181
1182         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183         if (mem_res == NULL) {
1184                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1185                 return -ENXIO;
1186         }
1187
1188         irq = platform_get_irq(pdev, 0);
1189         if (irq < 0) {
1190                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1191                 return irq;
1192         }
1193
1194         master = spi_alloc_master(&pdev->dev,
1195                                 sizeof(struct s3c64xx_spi_driver_data));
1196         if (master == NULL) {
1197                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1198                 return -ENOMEM;
1199         }
1200
1201         platform_set_drvdata(pdev, master);
1202
1203         sdd = spi_master_get_devdata(master);
1204         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1205
1206         sdd->master = master;
1207         sdd->cntrlr_info = sci;
1208         sdd->pdev = pdev;
1209         sdd->sfr_start = mem_res->start;
1210         if (pdev->dev.of_node) {
1211                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1212                 if (ret < 0) {
1213                         dev_err(&pdev->dev, "failed to get alias id, "
1214                                                 "errno %d\n", ret);
1215                         goto err0;
1216                 }
1217                 sdd->port_id = ret;
1218         } else {
1219                 sdd->port_id = pdev->id;
1220         }
1221
1222         sdd->cur_bpw = 8;
1223
1224         ret = s3c64xx_spi_get_dmares(sdd, true);
1225         if (ret)
1226                 goto err0;
1227
1228         ret = s3c64xx_spi_get_dmares(sdd, false);
1229         if (ret)
1230                 goto err0;
1231
1232         master->dev.of_node = pdev->dev.of_node;
1233         master->bus_num = sdd->port_id;
1234         master->setup = s3c64xx_spi_setup;
1235         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1236         master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1237         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1238         master->num_chipselect = sci->num_cs;
1239         master->dma_alignment = 8;
1240         /* the spi->mode bits understood by this driver: */
1241         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1242
1243         if (request_mem_region(mem_res->start,
1244                         resource_size(mem_res), pdev->name) == NULL) {
1245                 dev_err(&pdev->dev, "Req mem region failed\n");
1246                 ret = -ENXIO;
1247                 goto err0;
1248         }
1249
1250         sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
1251         if (sdd->regs == NULL) {
1252                 dev_err(&pdev->dev, "Unable to remap IO\n");
1253                 ret = -ENXIO;
1254                 goto err1;
1255         }
1256
1257         if (!sci->cfg_gpio && pdev->dev.of_node) {
1258                 if (s3c64xx_spi_parse_dt_gpio(sdd))
1259                         return -EBUSY;
1260         } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
1261                 dev_err(&pdev->dev, "Unable to config gpio\n");
1262                 ret = -EBUSY;
1263                 goto err2;
1264         }
1265
1266         /* Setup clocks */
1267         sdd->clk = clk_get(&pdev->dev, "spi");
1268         if (IS_ERR(sdd->clk)) {
1269                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1270                 ret = PTR_ERR(sdd->clk);
1271                 goto err3;
1272         }
1273
1274         if (clk_enable(sdd->clk)) {
1275                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1276                 ret = -EBUSY;
1277                 goto err4;
1278         }
1279
1280         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1281         sdd->src_clk = clk_get(&pdev->dev, clk_name);
1282         if (IS_ERR(sdd->src_clk)) {
1283                 dev_err(&pdev->dev,
1284                         "Unable to acquire clock '%s'\n", clk_name);
1285                 ret = PTR_ERR(sdd->src_clk);
1286                 goto err5;
1287         }
1288
1289         if (clk_enable(sdd->src_clk)) {
1290                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1291                 ret = -EBUSY;
1292                 goto err6;
1293         }
1294
1295         /* Setup Deufult Mode */
1296         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1297
1298         spin_lock_init(&sdd->lock);
1299         init_completion(&sdd->xfer_completion);
1300         INIT_LIST_HEAD(&sdd->queue);
1301
1302         ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd);
1303         if (ret != 0) {
1304                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1305                         irq, ret);
1306                 goto err7;
1307         }
1308
1309         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1310                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1311                sdd->regs + S3C64XX_SPI_INT_EN);
1312
1313         if (spi_register_master(master)) {
1314                 dev_err(&pdev->dev, "cannot register SPI master\n");
1315                 ret = -EBUSY;
1316                 goto err8;
1317         }
1318
1319         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1320                                         "with %d Slaves attached\n",
1321                                         sdd->port_id, master->num_chipselect);
1322         dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1323                                         mem_res->end, mem_res->start,
1324                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1325
1326         pm_runtime_enable(&pdev->dev);
1327
1328         return 0;
1329
1330 err8:
1331         free_irq(irq, sdd);
1332 err7:
1333         clk_disable(sdd->src_clk);
1334 err6:
1335         clk_put(sdd->src_clk);
1336 err5:
1337         clk_disable(sdd->clk);
1338 err4:
1339         clk_put(sdd->clk);
1340 err3:
1341         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1342                 s3c64xx_spi_dt_gpio_free(sdd);
1343 err2:
1344         iounmap((void *) sdd->regs);
1345 err1:
1346         release_mem_region(mem_res->start, resource_size(mem_res));
1347 err0:
1348         platform_set_drvdata(pdev, NULL);
1349         spi_master_put(master);
1350
1351         return ret;
1352 }
1353
1354 static int s3c64xx_spi_remove(struct platform_device *pdev)
1355 {
1356         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1357         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1358         struct resource *mem_res;
1359
1360         pm_runtime_disable(&pdev->dev);
1361
1362         spi_unregister_master(master);
1363
1364         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1365
1366         free_irq(platform_get_irq(pdev, 0), sdd);
1367
1368         clk_disable(sdd->src_clk);
1369         clk_put(sdd->src_clk);
1370
1371         clk_disable(sdd->clk);
1372         clk_put(sdd->clk);
1373
1374         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1375                 s3c64xx_spi_dt_gpio_free(sdd);
1376
1377         iounmap((void *) sdd->regs);
1378
1379         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1380         if (mem_res != NULL)
1381                 release_mem_region(mem_res->start, resource_size(mem_res));
1382
1383         platform_set_drvdata(pdev, NULL);
1384         spi_master_put(master);
1385
1386         return 0;
1387 }
1388
1389 #ifdef CONFIG_PM
1390 static int s3c64xx_spi_suspend(struct device *dev)
1391 {
1392         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1393         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1394
1395         spi_master_suspend(master);
1396
1397         /* Disable the clock */
1398         clk_disable(sdd->src_clk);
1399         clk_disable(sdd->clk);
1400
1401         if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
1402                 s3c64xx_spi_dt_gpio_free(sdd);
1403
1404         sdd->cur_speed = 0; /* Output Clock is stopped */
1405
1406         return 0;
1407 }
1408
1409 static int s3c64xx_spi_resume(struct device *dev)
1410 {
1411         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1412         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1413         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1414
1415         if (!sci->cfg_gpio && dev->of_node)
1416                 s3c64xx_spi_parse_dt_gpio(sdd);
1417         else
1418                 sci->cfg_gpio();
1419
1420
1421         /* Enable the clock */
1422         clk_enable(sdd->src_clk);
1423         clk_enable(sdd->clk);
1424
1425         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1426
1427         spi_master_resume(master);
1428
1429         return 0;
1430 }
1431 #endif /* CONFIG_PM */
1432
1433 #ifdef CONFIG_PM_RUNTIME
1434 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1435 {
1436         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1437         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1438
1439         clk_disable(sdd->clk);
1440         clk_disable(sdd->src_clk);
1441
1442         return 0;
1443 }
1444
1445 static int s3c64xx_spi_runtime_resume(struct device *dev)
1446 {
1447         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1448         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1449
1450         clk_enable(sdd->src_clk);
1451         clk_enable(sdd->clk);
1452
1453         return 0;
1454 }
1455 #endif /* CONFIG_PM_RUNTIME */
1456
1457 static const struct dev_pm_ops s3c64xx_spi_pm = {
1458         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1459         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1460                            s3c64xx_spi_runtime_resume, NULL)
1461 };
1462
1463 struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1464         .fifo_lvl_mask  = { 0x7f },
1465         .rx_lvl_offset  = 13,
1466         .tx_st_done     = 21,
1467         .high_speed     = true,
1468 };
1469
1470 struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1471         .fifo_lvl_mask  = { 0x7f, 0x7F },
1472         .rx_lvl_offset  = 13,
1473         .tx_st_done     = 21,
1474 };
1475
1476 struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1477         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1478         .rx_lvl_offset  = 15,
1479         .tx_st_done     = 25,
1480 };
1481
1482 struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1483         .fifo_lvl_mask  = { 0x7f, 0x7F },
1484         .rx_lvl_offset  = 13,
1485         .tx_st_done     = 21,
1486         .high_speed     = true,
1487 };
1488
1489 struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1490         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1491         .rx_lvl_offset  = 15,
1492         .tx_st_done     = 25,
1493         .high_speed     = true,
1494 };
1495
1496 struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1497         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1498         .rx_lvl_offset  = 15,
1499         .tx_st_done     = 25,
1500         .high_speed     = true,
1501         .clk_from_cmu   = true,
1502 };
1503
1504 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1505         {
1506                 .name           = "s3c2443-spi",
1507                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1508         }, {
1509                 .name           = "s3c6410-spi",
1510                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1511         }, {
1512                 .name           = "s5p64x0-spi",
1513                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1514         }, {
1515                 .name           = "s5pc100-spi",
1516                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1517         }, {
1518                 .name           = "s5pv210-spi",
1519                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1520         }, {
1521                 .name           = "exynos4210-spi",
1522                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1523         },
1524         { },
1525 };
1526
1527 #ifdef CONFIG_OF
1528 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1529         { .compatible = "samsung,exynos4210-spi",
1530                         .data = (void *)&exynos4_spi_port_config,
1531         },
1532         { },
1533 };
1534 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1535 #endif /* CONFIG_OF */
1536
1537 static struct platform_driver s3c64xx_spi_driver = {
1538         .driver = {
1539                 .name   = "s3c64xx-spi",
1540                 .owner = THIS_MODULE,
1541                 .pm = &s3c64xx_spi_pm,
1542                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1543         },
1544         .remove = s3c64xx_spi_remove,
1545         .id_table = s3c64xx_spi_driver_ids,
1546 };
1547 MODULE_ALIAS("platform:s3c64xx-spi");
1548
1549 static int __init s3c64xx_spi_init(void)
1550 {
1551         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1552 }
1553 subsys_initcall(s3c64xx_spi_init);
1554
1555 static void __exit s3c64xx_spi_exit(void)
1556 {
1557         platform_driver_unregister(&s3c64xx_spi_driver);
1558 }
1559 module_exit(s3c64xx_spi_exit);
1560
1561 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1562 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1563 MODULE_LICENSE("GPL");