drivers/staging/bcm/nvm.h

   1 /***************************************************************************************
   2  *
   3  * Copyright (c) Beceem Communications Inc.
   4  *
   5  * Module Name:
   6  *      NVM.h
   7  *
   8  * Abstract:
   9  *      This file has the prototypes,preprocessors and definitions various NVM libraries.
  10  *
  11  *
  12  * Revision History:
  13  *      Who             When            What
  14  *      --------        --------        ----------------------------------------------
  15  *      Name            Date            Created/reviewed/modified
  16  *
  17  * Notes:
  18  *
  19  ****************************************************************************************/
  20
  21 #ifndef _NVM_H_
  22 #define _NVM_H_
  23
  24 typedef struct _FLASH_SECTOR_INFO {
  25         unsigned int uiSectorSig;
  26         unsigned int uiSectorSize;
  27 } FLASH_SECTOR_INFO, *PFLASH_SECTOR_INFO;
  28
  29 typedef struct _FLASH_CS_INFO {
  30         u32 MagicNumber;
  31         /* let the magic number be 0xBECE-F1A5 - F1A5 for "flas-h" */
  32         u32 FlashLayoutVersion;
  33         u32 ISOImageVersion;
  34         u32 SCSIFirmwareVersion;
  35         u32 OffsetFromZeroForPart1ISOImage;
  36         u32 OffsetFromZeroForScsiFirmware;
  37         u32 SizeOfScsiFirmware;
  38         u32 OffsetFromZeroForPart2ISOImage;
  39         u32 OffsetFromZeroForCalibrationStart;
  40         u32 OffsetFromZeroForCalibrationEnd;
  41         u32 OffsetFromZeroForVSAStart;
  42         u32 OffsetFromZeroForVSAEnd;
  43         u32 OffsetFromZeroForControlSectionStart;
  44         u32 OffsetFromZeroForControlSectionData;
  45         u32 CDLessInactivityTimeout;
  46         u32 NewImageSignature;
  47         u32 FlashSectorSizeSig;
  48         u32 FlashSectorSize;
  49         u32 FlashWriteSupportSize;
  50         u32 TotalFlashSize;
  51         u32 FlashBaseAddr;
  52         u32 FlashPartMaxSize;
  53         u32 IsCDLessDeviceBootSig;
  54         /* MSC Timeout after reset to switch from MSC to NW Mode */
  55         u32 MassStorageTimeout;
  56 } FLASH_CS_INFO, *PFLASH_CS_INFO;
  57
  58 #define FLASH2X_TOTAL_SIZE      (64 * 1024 * 1024)
  59 #define DEFAULT_SECTOR_SIZE     (64 * 1024)
  60
  61 typedef struct _FLASH_2X_CS_INFO {
  62         /* magic number as 0xBECE-F1A5 - F1A5 for "flas-h" */
  63         u32 MagicNumber;
  64         u32 FlashLayoutVersion;
  65         u32 ISOImageVersion;
  66         u32 SCSIFirmwareVersion;
  67         u32 OffsetFromZeroForPart1ISOImage;
  68         u32 OffsetFromZeroForScsiFirmware;
  69         u32 SizeOfScsiFirmware;
  70         u32 OffsetFromZeroForPart2ISOImage;
  71         u32 OffsetFromZeroForDSDStart;
  72         u32 OffsetFromZeroForDSDEnd;
  73         u32 OffsetFromZeroForVSAStart;
  74         u32 OffsetFromZeroForVSAEnd;
  75         u32 OffsetFromZeroForControlSectionStart;
  76         u32 OffsetFromZeroForControlSectionData;
  77         /* NO Data Activity timeout to switch from MSC to NW Mode */
  78         u32 CDLessInactivityTimeout;
  79         u32 NewImageSignature;
  80         u32 FlashSectorSizeSig;
  81         u32 FlashSectorSize;
  82         u32 FlashWriteSupportSize;
  83         u32 TotalFlashSize;
  84         u32 FlashBaseAddr;
  85         u32 FlashPartMaxSize;
  86         u32 IsCDLessDeviceBootSig;
  87         /* MSC Timeout after reset to switch from MSC to NW Mode */
  88         u32 MassStorageTimeout;
  89         /* Flash Map 2.0 Field */
  90         u32 OffsetISOImage1Part1Start;
  91         u32 OffsetISOImage1Part1End;
  92         u32 OffsetISOImage1Part2Start;
  93         u32 OffsetISOImage1Part2End;
  94         u32 OffsetISOImage1Part3Start;
  95         u32 OffsetISOImage1Part3End;
  96         u32 OffsetISOImage2Part1Start;
  97         u32 OffsetISOImage2Part1End;
  98         u32 OffsetISOImage2Part2Start;
  99         u32 OffsetISOImage2Part2End;
 100         u32 OffsetISOImage2Part3Start;
 101         u32 OffsetISOImage2Part3End;
 102         /* DSD Header offset from start of DSD */
 103         u32 OffsetFromDSDStartForDSDHeader;
 104         u32 OffsetFromZeroForDSD1Start;
 105         u32 OffsetFromZeroForDSD1End;
 106         u32 OffsetFromZeroForDSD2Start;
 107         u32 OffsetFromZeroForDSD2End;
 108         u32 OffsetFromZeroForVSA1Start;
 109         u32 OffsetFromZeroForVSA1End;
 110         u32 OffsetFromZeroForVSA2Start;
 111         u32 OffsetFromZeroForVSA2End;
 112         /*
 113          * ACCESS_BITS_PER_SECTOR       2
 114          * ACCESS_RW                    0
 115          * ACCESS_RO                    1
 116          * ACCESS_RESVD                 2
 117          * ACCESS_RESVD                 3
 118          */
 119         u32 SectorAccessBitMap[FLASH2X_TOTAL_SIZE / (DEFAULT_SECTOR_SIZE * 16)];
 120         /* All expansions to the control data structure should add here */
 121 } FLASH2X_CS_INFO, *PFLASH2X_CS_INFO;
 122
 123 typedef struct _VENDOR_SECTION_INFO {
 124         u32 OffsetFromZeroForSectionStart;
 125         u32 OffsetFromZeroForSectionEnd;
 126         u32 AccessFlags;
 127         u32 Reserved[16];
 128 } VENDOR_SECTION_INFO, *PVENDOR_SECTION_INFO;
 129
 130 typedef struct _FLASH2X_VENDORSPECIFIC_INFO {
 131         VENDOR_SECTION_INFO VendorSection[TOTAL_SECTIONS];
 132         u32 Reserved[16];
 133 } FLASH2X_VENDORSPECIFIC_INFO, *PFLASH2X_VENDORSPECIFIC_INFO;
 134
 135 struct bcm_dsd_header {
 136         u32 DSDImageSize;
 137         u32 DSDImageCRC;
 138         u32 DSDImagePriority;
 139         /* We should not consider right now. Reading reserve is worthless. */
 140         u32 Reserved[252]; /* Resvd for DSD Header */
 141         u32 DSDImageMagicNumber;
 142 };
 143
 144 struct bcm_iso_header {
 145         u32 ISOImageMagicNumber;
 146         u32 ISOImageSize;
 147         u32 ISOImageCRC;
 148         u32 ISOImagePriority;
 149         /* We should not consider right now. Reading reserve is worthless. */
 150         u32 Reserved[60]; /* Resvd for ISO Header extension */
 151 };
 152
 153 #define EEPROM_BEGIN_CIS        (0)
 154 #define EEPROM_BEGIN_NON_CIS    (0x200)
 155 #define EEPROM_END              (0x2000)
 156 #define INIT_PARAMS_SIGNATURE   (0x95a7a597)
 157 #define MAX_INIT_PARAMS_LENGTH  (2048)
 158 #define MAC_ADDRESS_OFFSET      0x200
 159
 160 #define INIT_PARAMS_1_SIGNATURE_ADDRESS         EEPROM_BEGIN_NON_CIS
 161 #define INIT_PARAMS_1_DATA_ADDRESS              (INIT_PARAMS_1_SIGNATURE_ADDRESS+16)
 162 #define INIT_PARAMS_1_MACADDRESS_ADDRESS        (MAC_ADDRESS_OFFSET)
 163 #define INIT_PARAMS_1_LENGTH_ADDRESS            (INIT_PARAMS_1_SIGNATURE_ADDRESS+4)
 164
 165 #define INIT_PARAMS_2_SIGNATURE_ADDRESS         (EEPROM_BEGIN_NON_CIS + 2048 + 16)
 166 #define INIT_PARAMS_2_DATA_ADDRESS              (INIT_PARAMS_2_SIGNATURE_ADDRESS + 16)
 167 #define INIT_PARAMS_2_MACADDRESS_ADDRESS        (INIT_PARAMS_2_SIGNATURE_ADDRESS + 8)
 168 #define INIT_PARAMS_2_LENGTH_ADDRESS            (INIT_PARAMS_2_SIGNATURE_ADDRESS + 4)
 169
 170 #define EEPROM_SPI_DEV_CONFIG_REG               0x0F003000
 171 #define EEPROM_SPI_Q_STATUS1_REG                0x0F003004
 172 #define EEPROM_SPI_Q_STATUS1_MASK_REG           0x0F00300C
 173
 174 #define EEPROM_SPI_Q_STATUS_REG                 0x0F003008
 175 #define EEPROM_CMDQ_SPI_REG                     0x0F003018
 176 #define EEPROM_WRITE_DATAQ_REG                  0x0F00301C
 177 #define EEPROM_READ_DATAQ_REG                   0x0F003020
 178 #define SPI_FLUSH_REG                           0x0F00304C
 179
 180 #define EEPROM_WRITE_ENABLE                     0x06000000
 181 #define EEPROM_READ_STATUS_REGISTER             0x05000000
 182 #define EEPROM_16_BYTE_PAGE_WRITE               0xFA000000
 183 #define EEPROM_WRITE_QUEUE_EMPTY                0x00001000
 184 #define EEPROM_WRITE_QUEUE_AVAIL                0x00002000
 185 #define EEPROM_WRITE_QUEUE_FULL                 0x00004000
 186 #define EEPROM_16_BYTE_PAGE_READ                0xFB000000
 187 #define EEPROM_4_BYTE_PAGE_READ                 0x3B000000
 188
 189 #define EEPROM_CMD_QUEUE_FLUSH                  0x00000001
 190 #define EEPROM_WRITE_QUEUE_FLUSH                0x00000002
 191 #define EEPROM_READ_QUEUE_FLUSH                 0x00000004
 192 #define EEPROM_ETH_QUEUE_FLUSH                  0x00000008
 193 #define EEPROM_ALL_QUEUE_FLUSH                  0x0000000f
 194 #define EEPROM_READ_ENABLE                      0x06000000
 195 #define EEPROM_16_BYTE_PAGE_WRITE               0xFA000000
 196 #define EEPROM_READ_DATA_FULL                   0x00000010
 197 #define EEPROM_READ_DATA_AVAIL                  0x00000020
 198 #define EEPROM_READ_QUEUE_EMPTY                 0x00000002
 199 #define EEPROM_CMD_QUEUE_EMPTY                  0x00000100
 200 #define EEPROM_CMD_QUEUE_AVAIL                  0x00000200
 201 #define EEPROM_CMD_QUEUE_FULL                   0x00000400
 202
 203 /* Most EEPROM status register bit 0 indicates if the EEPROM is busy
 204  * with a write if set 1. See the details of the EEPROM Status Register
 205  * in the EEPROM data sheet.
 206  */
 207 #define EEPROM_STATUS_REG_WRITE_BUSY            0x00000001
 208
 209 /* We will have 1 mSec for every RETRIES_PER_DELAY count and have a max attempts of MAX_EEPROM_RETRIES
 210  * This will give us 80 mSec minimum of delay = 80mSecs
 211  */
 212 #define MAX_EEPROM_RETRIES                      80
 213 #define RETRIES_PER_DELAY                       64
 214 #define MAX_RW_SIZE                             0x10
 215 #define MAX_READ_SIZE                           0x10
 216 #define MAX_SECTOR_SIZE                         (512 * 1024)
 217 #define MIN_SECTOR_SIZE                         (1024)
 218 #define FLASH_SECTOR_SIZE_OFFSET                0xEFFFC
 219 #define FLASH_SECTOR_SIZE_SIG_OFFSET            0xEFFF8
 220 #define FLASH_SECTOR_SIZE_SIG                   0xCAFEBABE
 221 #define FLASH_CS_INFO_START_ADDR                0xFF0000
 222 #define FLASH_CONTROL_STRUCT_SIGNATURE          0xBECEF1A5
 223 #define SCSI_FIRMWARE_MAJOR_VERSION             0x1
 224 #define SCSI_FIRMWARE_MINOR_VERSION             0x5
 225 #define BYTE_WRITE_SUPPORT                      0x1
 226 #define FLASH_AUTO_INIT_BASE_ADDR               0xF00000
 227 #define FLASH_CONTIGIOUS_START_ADDR_AFTER_INIT  0x1C000000
 228 #define FLASH_CONTIGIOUS_START_ADDR_BEFORE_INIT 0x1F000000
 229 #define FLASH_CONTIGIOUS_START_ADDR_BCS350      0x08000000
 230 #define FLASH_CONTIGIOUS_END_ADDR_BCS350        0x08FFFFFF
 231 #define FLASH_SIZE_ADDR                         0xFFFFEC
 232 #define FLASH_SPI_CMDQ_REG                      0xAF003040
 233 #define FLASH_SPI_WRITEQ_REG                    0xAF003044
 234 #define FLASH_SPI_READQ_REG                     0xAF003048
 235 #define FLASH_CONFIG_REG                        0xAF003050
 236 #define FLASH_GPIO_CONFIG_REG                   0xAF000030
 237 #define FLASH_CMD_WRITE_ENABLE                  0x06
 238 #define FLASH_CMD_READ_ENABLE                   0x03
 239 #define FLASH_CMD_RESET_WRITE_ENABLE            0x04
 240 #define FLASH_CMD_STATUS_REG_READ               0x05
 241 #define FLASH_CMD_STATUS_REG_WRITE              0x01
 242 #define FLASH_CMD_READ_ID                       0x9F
 243 #define PAD_SELECT_REGISTER                     0xAF000410
 244 #define FLASH_PART_SST25VF080B                  0xBF258E
 245 #define EEPROM_CAL_DATA_INTERNAL_LOC            0xbFB00008
 246 #define EEPROM_CALPARAM_START                   0x200
 247 #define EEPROM_SIZE_OFFSET                      524
 248
 249 /* As Read/Write time vaires from 1.5 to 3.0 ms.
 250  * so After Ignoring the rdm/wrm time(that is dependent on many factor like interface etc.),
 251  * here time calculated meets the worst case delay, 3.0 ms
 252  */
 253 #define MAX_FLASH_RETRIES               4
 254 #define FLASH_PER_RETRIES_DELAY         16
 255 #define EEPROM_MAX_CAL_AREA_SIZE        0xF0000
 256 #define BECM                            ntohl(0x4245434d)
 257 #define FLASH_2X_MAJOR_NUMBER           0x2
 258 #define DSD_IMAGE_MAGIC_NUMBER          0xBECE0D5D
 259 #define ISO_IMAGE_MAGIC_NUMBER          0xBECE0150
 260 #define NON_CDLESS_DEVICE_BOOT_SIG      0xBECEB007
 261
 262 #define MINOR_VERSION(x) ((x >> 16) & 0xFFFF)
 263 #define MAJOR_VERSION(x) (x & 0xFFFF)
 264
 265 #define CORRUPTED_PATTERN               0x0
 266 #define UNINIT_PTR_IN_CS                0xBBBBDDDD
 267 #define VENDOR_PTR_IN_CS                0xAAAACCCC
 268 #define FLASH2X_SECTION_PRESENT         (1 << 0)
 269 #define FLASH2X_SECTION_VALID           (1 << 1)
 270 #define FLASH2X_SECTION_RO              (1 << 2)
 271 #define FLASH2X_SECTION_ACT             (1 << 3)
 272 #define SECTOR_IS_NOT_WRITABLE          STATUS_FAILURE
 273 #define INVALID_OFFSET                  STATUS_FAILURE
 274 #define INVALID_SECTION                 STATUS_FAILURE
 275 #define SECTOR_1K                       1024
 276 #define SECTOR_64K                      (64 * SECTOR_1K)
 277 #define SECTOR_128K                     (2 * SECTOR_64K)
 278 #define SECTOR_256k                     (2 * SECTOR_128K)
 279 #define SECTOR_512K                     (2 * SECTOR_256k)
 280 #define FLASH_PART_SIZE                 (16 * 1024 * 1024)
 281 #define RESET_CHIP_SELECT               -1
 282 #define CHIP_SELECT_BIT12               12
 283 #define SECTOR_READWRITE_PERMISSION     0
 284 #define SECTOR_READONLY                 1
 285 #define SIGNATURE_SIZE                  4
 286 #define DEFAULT_BUFF_SIZE               0x10000
 287
 288 #define FIELD_OFFSET_IN_HEADER(HeaderPointer, Field) ((u8 *)&((HeaderPointer)(NULL))->Field - (u8 *)(NULL))
 289
 290 #endif
 291