drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31 */
  32
  33 /*
  34  * Driver: cb_pcidas64
  35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  36  *   with the PLX 9080 PCI controller
  37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  38  * Status: works
  39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  49  *
  50  * Configuration options:
  51  *   None.
  52  *
  53  * Manual attachment of PCI cards with the comedi_config utility is not
  54  * supported by this driver; they are attached automatically.
  55  *
  56  * These boards may be autocalibrated with the comedi_calibrate utility.
  57  *
  58  * To select the bnc trigger input on the 4020 (instead of the dio input),
  59  * specify a nonzero channel in the chanspec.  If you wish to use an external
  60  * master clock on the 4020, you may do so by setting the scan_begin_src
  61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  62  * to configure the divisor to use for the external clock.
  63  *
  64  * Some devices are not identified because the PCI device IDs are not yet
  65  * known. If you have such a board, please let the maintainers know.
  66  */
  67
  68 /*
  69
  70 TODO:
  71         make it return error if user attempts an ai command that uses the
  72         external queue, and an ao command simultaneously user counter subdevice
  73         there are a number of boards this driver will support when they are
  74         fully released, but does not yet since the pci device id numbers
  75         are not yet available.
  76
  77         support prescaled 100khz clock for slow pacing (not available on 6000
  78         series?)
  79
  80         make ao fifo size adjustable like ai fifo
  81 */
  82
  83 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  84
  85 #include <linux/module.h>
  86 #include <linux/pci.h>
  87 #include <linux/delay.h>
  88 #include <linux/interrupt.h>
  89
  90 #include "../comedidev.h"
  91
  92 #include "8253.h"
  93 #include "8255.h"
  94 #include "plx9080.h"
  95 #include "comedi_fc.h"
  96
  97 #undef PCIDAS64_DEBUG           /*  disable debugging code */
  98 /* #define PCIDAS64_DEBUG         enable debugging code */
  99
 100 #ifdef PCIDAS64_DEBUG
 101 #define DEBUG_PRINT(format, args...)  pr_debug(format, ## args)
 102 #else
 103 #define DEBUG_PRINT(format, args...)  no_printk(format, ## args)
 104 #endif
 105
 106 #define TIMER_BASE 25           /*  40MHz master clock */
 107 /* 100kHz 'prescaled' clock for slow acquisition,
 108  * maybe I'll support this someday */
 109 #define PRESCALED_TIMER_BASE    10000
 110 #define DMA_BUFFER_SIZE 0x1000
 111
 112 /* maximum value that can be loaded into board's 24-bit counters*/
 113 static const int max_counter_value = 0xffffff;
 114
 115 /* PCI-DAS64xxx base addresses */
 116
 117 /* devpriv->main_iobase registers */
 118 enum write_only_registers {
 119         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 120         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 121         DAQ_SYNC_REG = 0xc,
 122         DAQ_ATRIG_LOW_4020_REG = 0xc,
 123         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 124         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 125         CALIBRATION_REG = 0x14,
 126         /*  lower 16 bits of adc sample interval counter */
 127         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 128         /*  upper 8 bits of adc sample interval counter */
 129         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 130         /*  lower 16 bits of delay interval counter */
 131         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 132         /*  upper 8 bits of delay interval counter */
 133         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 134         /*  lower 16 bits of hardware conversion/scan counter */
 135         ADC_COUNT_LOWER_REG = 0x1e,
 136         /*  upper 8 bits of hardware conversion/scan counter */
 137         ADC_COUNT_UPPER_REG = 0x20,
 138         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 139         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 140         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 141         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 142         ADC_BUFFER_CLEAR_REG = 0x2a,
 143         /*  high channel for internal queue, use adc_chan_bits() inline above */
 144         ADC_QUEUE_HIGH_REG = 0x2c,
 145         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 146         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 147         /*  lower 16 bits of dac sample interval counter */
 148         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 149         /*  upper 8 bits of dac sample interval counter */
 150         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 151         DAC_SELECT_REG = 0x60,
 152         DAC_START_REG = 0x64,
 153         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 154 };
 155
 156 static inline unsigned int dac_convert_reg(unsigned int channel)
 157 {
 158         return 0x70 + (2 * (channel & 0x1));
 159 }
 160
 161 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 162 {
 163         return 0x70 + (4 * (channel & 0x1));
 164 }
 165
 166 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 167 {
 168         return 0x72 + (4 * (channel & 0x1));
 169 }
 170
 171 enum read_only_registers {
 172         /*  hardware status register,
 173          *  reading this apparently clears pending interrupts as well */
 174         HW_STATUS_REG = 0x0,
 175         PIPE1_READ_REG = 0x4,
 176         ADC_READ_PNTR_REG = 0x8,
 177         LOWER_XFER_REG = 0x10,
 178         ADC_WRITE_PNTR_REG = 0xc,
 179         PREPOST_REG = 0x14,
 180 };
 181
 182 enum read_write_registers {
 183         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 184         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 185         ADC_QUEUE_FIFO_REG = 0x100,
 186         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 187         /* dac data fifo, has weird interactions with external channel queue */
 188         DAC_FIFO_REG = 0x300,
 189 };
 190
 191 /* devpriv->dio_counter_iobase registers */
 192 enum dio_counter_registers {
 193         DIO_8255_OFFSET = 0x0,
 194         DO_REG = 0x20,
 195         DI_REG = 0x28,
 196         DIO_DIRECTION_60XX_REG = 0x40,
 197         DIO_DATA_60XX_REG = 0x48,
 198 };
 199
 200 /* bit definitions for write-only registers */
 201
 202 enum intr_enable_contents {
 203         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
 204         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
 205         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 206         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 207         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
 208         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 209         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
 210         DAC_INTR_SRC_MASK = 0x30,
 211         DAC_INTR_QEMPTY_BITS = 0x0,
 212         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 213         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 214         EN_DAC_DONE_INTR_BIT = 0x80,
 215         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 216         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 217         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 218         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 219         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 220 };
 221
 222 enum hw_config_contents {
 223         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
 224         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
 225         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 226         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 227         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
 228         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 229         SLOW_DAC_BIT = 0x400,
 230         /*  bit with unknown function yet given as default value in pci-das64
 231          *  manual */
 232         HW_CONFIG_DUMMY_BITS = 0x2000,
 233         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 234         DMA_CH_SELECT_BIT = 0x8000,
 235         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
 236         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 237         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
 238 };
 239 #define DAC_FIFO_SIZE 0x2000
 240
 241 enum daq_atrig_low_4020_contents {
 242         /*  use trig/ext clk bnc input for analog gate signal */
 243         EXT_AGATE_BNC_BIT = 0x8000,
 244         /*  use trig/ext clk bnc input for external stop trigger signal */
 245         EXT_STOP_TRIG_BNC_BIT = 0x4000,
 246         /*  use trig/ext clk bnc input for external start trigger signal */
 247         EXT_START_TRIG_BNC_BIT = 0x2000,
 248 };
 249
 250 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 251 {
 252         return threshold & 0xfff;
 253 }
 254
 255 enum adc_control0_contents {
 256         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 257         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 258         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 259         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 260         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 261         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 262         ADC_START_TRIG_SOFT_BITS = 0x10,
 263         ADC_START_TRIG_EXT_BITS = 0x20,
 264         ADC_START_TRIG_ANALOG_BITS = 0x30,
 265         ADC_START_TRIG_MASK = 0x30,
 266         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 267         /*  external pacing uses falling edge */
 268         ADC_EXT_CONV_FALLING_BIT = 0x800,
 269         /*  enable hardware scan counter */
 270         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 271         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 272         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 273 };
 274
 275 enum adc_control1_contents {
 276         /*  should be set for boards with > 16 channels */
 277         ADC_QUEUE_CONFIG_BIT = 0x1,
 278         CONVERT_POLARITY_BIT = 0x10,
 279         EOC_POLARITY_BIT = 0x20,
 280         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 281         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 282         RETRIGGER_BIT = 0x800,
 283         ADC_LO_CHANNEL_4020_MASK = 0x300,
 284         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 285         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 286         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
 287         CHANNEL_MODE_4020_MASK = 0x3000,
 288         ADC_MODE_MASK = 0xf000,
 289 };
 290
 291 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 292 {
 293         return (channel & 0x3) << 8;
 294 };
 295
 296 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 297 {
 298         return (channel & 0x3) << 10;
 299 };
 300
 301 static inline uint16_t adc_mode_bits(unsigned int mode)
 302 {
 303         return (mode & 0xf) << 12;
 304 };
 305
 306 enum calibration_contents {
 307         SELECT_8800_BIT = 0x1,
 308         SELECT_8402_64XX_BIT = 0x2,
 309         SELECT_1590_60XX_BIT = 0x2,
 310         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 311         SERIAL_DATA_IN_BIT = 0x80,
 312         SERIAL_CLOCK_BIT = 0x100,
 313         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
 314         CAL_GAIN_BIT = 0x800,
 315 };
 316
 317 /* calibration sources for 6025 are:
 318  *  0 : ground
 319  *  1 : 10V
 320  *  2 : 5V
 321  *  3 : 0.5V
 322  *  4 : 0.05V
 323  *  5 : ground
 324  *  6 : dac channel 0
 325  *  7 : dac channel 1
 326  */
 327
 328 static inline uint16_t adc_src_bits(unsigned int source)
 329 {
 330         return (source & 0xf) << 3;
 331 };
 332
 333 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 334 {
 335         return (channel & 0x3) << 8;
 336 };
 337
 338 enum adc_queue_load_contents {
 339         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 340         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 341         /*  non-referenced single-ended (common-mode input) */
 342         ADC_COMMON_BIT = 0x2000,
 343         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 344         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 345 };
 346
 347 static inline uint16_t adc_chan_bits(unsigned int channel)
 348 {
 349         return channel & 0x3f;
 350 };
 351
 352 enum dac_control0_contents {
 353         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 354         DAC_CYCLIC_STOP_BIT = 0x4000,
 355         DAC_WAVEFORM_MODE_BIT = 0x100,
 356         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 357         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 358         WAVEFORM_TRIG_MASK = 0x30,
 359         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 360         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 361         WAVEFORM_TRIG_EXT_BITS = 0x20,
 362         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 363         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 364         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 365         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 366         WAVEFORM_GATE_SELECT_BIT = 0x1,
 367 };
 368
 369 enum dac_control1_contents {
 370         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 371         DAC1_EXT_REF_BIT = 0x200,
 372         DAC0_EXT_REF_BIT = 0x100,
 373         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 374         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 375         DAC_SW_GATE_BIT = 0x20,
 376         DAC1_UNIPOLAR_BIT = 0x8,
 377         DAC0_UNIPOLAR_BIT = 0x2,
 378 };
 379
 380 /* bit definitions for read-only registers */
 381 enum hw_status_contents {
 382         DAC_UNDERRUN_BIT = 0x1,
 383         ADC_OVERRUN_BIT = 0x2,
 384         DAC_ACTIVE_BIT = 0x4,
 385         ADC_ACTIVE_BIT = 0x8,
 386         DAC_INTR_PENDING_BIT = 0x10,
 387         ADC_INTR_PENDING_BIT = 0x20,
 388         DAC_DONE_BIT = 0x40,
 389         ADC_DONE_BIT = 0x80,
 390         EXT_INTR_PENDING_BIT = 0x100,
 391         ADC_STOP_BIT = 0x200,
 392 };
 393
 394 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 395 {
 396         return (hw_status_bits >> 10) & 0x3;
 397 };
 398
 399 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 400 {
 401         return (prepost_bits >> 6) & 0x3;
 402 }
 403
 404 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 405 {
 406         return (prepost_bits >> 12) & 0x3;
 407 }
 408
 409 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 410 {
 411         return (prepost_bits >> 14) & 0x3;
 412 }
 413
 414 /* I2C addresses for 4020 */
 415 enum i2c_addresses {
 416         RANGE_CAL_I2C_ADDR = 0x20,
 417         CALDAC0_I2C_ADDR = 0xc,
 418         CALDAC1_I2C_ADDR = 0xd,
 419 };
 420
 421 enum range_cal_i2c_contents {
 422         /*  bits that set what source the adc converter measures */
 423         ADC_SRC_4020_MASK = 0x70,
 424         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 425         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 426 };
 427
 428 static inline uint8_t adc_src_4020_bits(unsigned int source)
 429 {
 430         return (source << 4) & ADC_SRC_4020_MASK;
 431 };
 432
 433 static inline uint8_t attenuate_bit(unsigned int channel)
 434 {
 435         /*  attenuate channel (+-5V input range) */
 436         return 1 << (channel & 0x3);
 437 };
 438
 439 /* analog input ranges for 64xx boards */
 440 static const struct comedi_lrange ai_ranges_64xx = {
 441         8,
 442         {
 443          BIP_RANGE(10),
 444          BIP_RANGE(5),
 445          BIP_RANGE(2.5),
 446          BIP_RANGE(1.25),
 447          UNI_RANGE(10),
 448          UNI_RANGE(5),
 449          UNI_RANGE(2.5),
 450          UNI_RANGE(1.25)
 451          }
 452 };
 453
 454 /* analog input ranges for 60xx boards */
 455 static const struct comedi_lrange ai_ranges_60xx = {
 456         4,
 457         {
 458          BIP_RANGE(10),
 459          BIP_RANGE(5),
 460          BIP_RANGE(0.5),
 461          BIP_RANGE(0.05),
 462          }
 463 };
 464
 465 /* analog input ranges for 6030, etc boards */
 466 static const struct comedi_lrange ai_ranges_6030 = {
 467         14,
 468         {
 469          BIP_RANGE(10),
 470          BIP_RANGE(5),
 471          BIP_RANGE(2),
 472          BIP_RANGE(1),
 473          BIP_RANGE(0.5),
 474          BIP_RANGE(0.2),
 475          BIP_RANGE(0.1),
 476          UNI_RANGE(10),
 477          UNI_RANGE(5),
 478          UNI_RANGE(2),
 479          UNI_RANGE(1),
 480          UNI_RANGE(0.5),
 481          UNI_RANGE(0.2),
 482          UNI_RANGE(0.1),
 483          }
 484 };
 485
 486 /* analog input ranges for 6052, etc boards */
 487 static const struct comedi_lrange ai_ranges_6052 = {
 488         15,
 489         {
 490          BIP_RANGE(10),
 491          BIP_RANGE(5),
 492          BIP_RANGE(2.5),
 493          BIP_RANGE(1),
 494          BIP_RANGE(0.5),
 495          BIP_RANGE(0.25),
 496          BIP_RANGE(0.1),
 497          BIP_RANGE(0.05),
 498          UNI_RANGE(10),
 499          UNI_RANGE(5),
 500          UNI_RANGE(2),
 501          UNI_RANGE(1),
 502          UNI_RANGE(0.5),
 503          UNI_RANGE(0.2),
 504          UNI_RANGE(0.1),
 505          }
 506 };
 507
 508 /* analog input ranges for 4020 board */
 509 static const struct comedi_lrange ai_ranges_4020 = {
 510         2,
 511         {
 512          BIP_RANGE(5),
 513          BIP_RANGE(1),
 514          }
 515 };
 516
 517 /* analog output ranges */
 518 static const struct comedi_lrange ao_ranges_64xx = {
 519         4,
 520         {
 521          BIP_RANGE(5),
 522          BIP_RANGE(10),
 523          UNI_RANGE(5),
 524          UNI_RANGE(10),
 525          }
 526 };
 527
 528 static const int ao_range_code_64xx[] = {
 529         0x0,
 530         0x1,
 531         0x2,
 532         0x3,
 533 };
 534
 535 static const int ao_range_code_60xx[] = {
 536         0x0,
 537 };
 538
 539 static const struct comedi_lrange ao_ranges_6030 = {
 540         2,
 541         {
 542          BIP_RANGE(10),
 543          UNI_RANGE(10),
 544          }
 545 };
 546
 547 static const int ao_range_code_6030[] = {
 548         0x0,
 549         0x2,
 550 };
 551
 552 static const struct comedi_lrange ao_ranges_4020 = {
 553         2,
 554         {
 555          BIP_RANGE(5),
 556          BIP_RANGE(10),
 557          }
 558 };
 559
 560 static const int ao_range_code_4020[] = {
 561         0x1,
 562         0x0,
 563 };
 564
 565 enum register_layout {
 566         LAYOUT_60XX,
 567         LAYOUT_64XX,
 568         LAYOUT_4020,
 569 };
 570
 571 struct hw_fifo_info {
 572         unsigned int num_segments;
 573         unsigned int max_segment_length;
 574         unsigned int sample_packing_ratio;
 575         uint16_t fifo_size_reg_mask;
 576 };
 577
 578 enum pcidas64_boardid {
 579         BOARD_PCIDAS6402_16,
 580         BOARD_PCIDAS6402_12,
 581         BOARD_PCIDAS64_M1_16,
 582         BOARD_PCIDAS64_M2_16,
 583         BOARD_PCIDAS64_M3_16,
 584         BOARD_PCIDAS6013,
 585         BOARD_PCIDAS6014,
 586         BOARD_PCIDAS6023,
 587         BOARD_PCIDAS6025,
 588         BOARD_PCIDAS6030,
 589         BOARD_PCIDAS6031,
 590         BOARD_PCIDAS6032,
 591         BOARD_PCIDAS6033,
 592         BOARD_PCIDAS6034,
 593         BOARD_PCIDAS6035,
 594         BOARD_PCIDAS6036,
 595         BOARD_PCIDAS6040,
 596         BOARD_PCIDAS6052,
 597         BOARD_PCIDAS6070,
 598         BOARD_PCIDAS6071,
 599         BOARD_PCIDAS4020_12,
 600         BOARD_PCIDAS6402_16_JR,
 601         BOARD_PCIDAS64_M1_16_JR,
 602         BOARD_PCIDAS64_M2_16_JR,
 603         BOARD_PCIDAS64_M3_16_JR,
 604         BOARD_PCIDAS64_M1_14,
 605         BOARD_PCIDAS64_M2_14,
 606         BOARD_PCIDAS64_M3_14,
 607 };
 608
 609 struct pcidas64_board {
 610         const char *name;
 611         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 612         int ai_bits;            /*  analog input resolution */
 613         int ai_speed;           /*  fastest conversion period in ns */
 614         const struct comedi_lrange *ai_range_table;
 615         int ao_nchan;           /*  number of analog out channels */
 616         int ao_bits;            /*  analog output resolution */
 617         int ao_scan_speed;      /*  analog output scan speed */
 618         const struct comedi_lrange *ao_range_table;
 619         const int *ao_range_code;
 620         const struct hw_fifo_info *const ai_fifo;
 621         /*  different board families have slightly different registers */
 622         enum register_layout layout;
 623         unsigned has_8255:1;
 624 };
 625
 626 static const struct hw_fifo_info ai_fifo_4020 = {
 627         .num_segments = 2,
 628         .max_segment_length = 0x8000,
 629         .sample_packing_ratio = 2,
 630         .fifo_size_reg_mask = 0x7f,
 631 };
 632
 633 static const struct hw_fifo_info ai_fifo_64xx = {
 634         .num_segments = 4,
 635         .max_segment_length = 0x800,
 636         .sample_packing_ratio = 1,
 637         .fifo_size_reg_mask = 0x3f,
 638 };
 639
 640 static const struct hw_fifo_info ai_fifo_60xx = {
 641         .num_segments = 4,
 642         .max_segment_length = 0x800,
 643         .sample_packing_ratio = 1,
 644         .fifo_size_reg_mask = 0x7f,
 645 };
 646
 647 /* maximum number of dma transfers we will chain together into a ring
 648  * (and the maximum number of dma buffers we maintain) */
 649 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 650 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 651 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 652 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 653 {
 654         if (board->layout == LAYOUT_4020)
 655                 return MAX_AI_DMA_RING_COUNT;
 656         else
 657                 return MIN_AI_DMA_RING_COUNT;
 658 }
 659
 660 static const int bytes_in_sample = 2;
 661
 662 static const struct pcidas64_board pcidas64_boards[] = {
 663         [BOARD_PCIDAS6402_16] = {
 664                 .name           = "pci-das6402/16",
 665                 .ai_se_chans    = 64,
 666                 .ai_bits        = 16,
 667                 .ai_speed       = 5000,
 668                 .ao_nchan       = 2,
 669                 .ao_bits        = 16,
 670                 .ao_scan_speed  = 10000,
 671                 .layout         = LAYOUT_64XX,
 672                 .ai_range_table = &ai_ranges_64xx,
 673                 .ao_range_table = &ao_ranges_64xx,
 674                 .ao_range_code  = ao_range_code_64xx,
 675                 .ai_fifo        = &ai_fifo_64xx,
 676                 .has_8255       = 1,
 677         },
 678         [BOARD_PCIDAS6402_12] = {
 679                 .name           = "pci-das6402/12",     /*  XXX check */
 680                 .ai_se_chans    = 64,
 681                 .ai_bits        = 12,
 682                 .ai_speed       = 5000,
 683                 .ao_nchan       = 2,
 684                 .ao_bits        = 12,
 685                 .ao_scan_speed  = 10000,
 686                 .layout         = LAYOUT_64XX,
 687                 .ai_range_table = &ai_ranges_64xx,
 688                 .ao_range_table = &ao_ranges_64xx,
 689                 .ao_range_code  = ao_range_code_64xx,
 690                 .ai_fifo        = &ai_fifo_64xx,
 691                 .has_8255       = 1,
 692         },
 693         [BOARD_PCIDAS64_M1_16] = {
 694                 .name           = "pci-das64/m1/16",
 695                 .ai_se_chans    = 64,
 696                 .ai_bits        = 16,
 697                 .ai_speed       = 1000,
 698                 .ao_nchan       = 2,
 699                 .ao_bits        = 16,
 700                 .ao_scan_speed  = 10000,
 701                 .layout         = LAYOUT_64XX,
 702                 .ai_range_table = &ai_ranges_64xx,
 703                 .ao_range_table = &ao_ranges_64xx,
 704                 .ao_range_code  = ao_range_code_64xx,
 705                 .ai_fifo        = &ai_fifo_64xx,
 706                 .has_8255       = 1,
 707         },
 708         [BOARD_PCIDAS64_M2_16] = {
 709                 .name = "pci-das64/m2/16",
 710                 .ai_se_chans    = 64,
 711                 .ai_bits        = 16,
 712                 .ai_speed       = 500,
 713                 .ao_nchan       = 2,
 714                 .ao_bits        = 16,
 715                 .ao_scan_speed  = 10000,
 716                 .layout         = LAYOUT_64XX,
 717                 .ai_range_table = &ai_ranges_64xx,
 718                 .ao_range_table = &ao_ranges_64xx,
 719                 .ao_range_code  = ao_range_code_64xx,
 720                 .ai_fifo        = &ai_fifo_64xx,
 721                 .has_8255       = 1,
 722         },
 723         [BOARD_PCIDAS64_M3_16] = {
 724                 .name           = "pci-das64/m3/16",
 725                 .ai_se_chans    = 64,
 726                 .ai_bits        = 16,
 727                 .ai_speed       = 333,
 728                 .ao_nchan       = 2,
 729                 .ao_bits        = 16,
 730                 .ao_scan_speed  = 10000,
 731                 .layout         = LAYOUT_64XX,
 732                 .ai_range_table = &ai_ranges_64xx,
 733                 .ao_range_table = &ao_ranges_64xx,
 734                 .ao_range_code  = ao_range_code_64xx,
 735                 .ai_fifo        = &ai_fifo_64xx,
 736                 .has_8255       = 1,
 737         },
 738         [BOARD_PCIDAS6013] = {
 739                 .name           = "pci-das6013",
 740                 .ai_se_chans    = 16,
 741                 .ai_bits        = 16,
 742                 .ai_speed       = 5000,
 743                 .ao_nchan       = 0,
 744                 .ao_bits        = 16,
 745                 .layout         = LAYOUT_60XX,
 746                 .ai_range_table = &ai_ranges_60xx,
 747                 .ao_range_table = &range_bipolar10,
 748                 .ao_range_code  = ao_range_code_60xx,
 749                 .ai_fifo        = &ai_fifo_60xx,
 750                 .has_8255       = 0,
 751         },
 752         [BOARD_PCIDAS6014] = {
 753                 .name           = "pci-das6014",
 754                 .ai_se_chans    = 16,
 755                 .ai_bits        = 16,
 756                 .ai_speed       = 5000,
 757                 .ao_nchan       = 2,
 758                 .ao_bits        = 16,
 759                 .ao_scan_speed  = 100000,
 760                 .layout         = LAYOUT_60XX,
 761                 .ai_range_table = &ai_ranges_60xx,
 762                 .ao_range_table = &range_bipolar10,
 763                 .ao_range_code  = ao_range_code_60xx,
 764                 .ai_fifo        = &ai_fifo_60xx,
 765                 .has_8255       = 0,
 766         },
 767         [BOARD_PCIDAS6023] = {
 768                 .name           = "pci-das6023",
 769                 .ai_se_chans    = 16,
 770                 .ai_bits        = 12,
 771                 .ai_speed       = 5000,
 772                 .ao_nchan       = 0,
 773                 .ao_scan_speed  = 100000,
 774                 .layout         = LAYOUT_60XX,
 775                 .ai_range_table = &ai_ranges_60xx,
 776                 .ao_range_table = &range_bipolar10,
 777                 .ao_range_code  = ao_range_code_60xx,
 778                 .ai_fifo        = &ai_fifo_60xx,
 779                 .has_8255       = 1,
 780         },
 781         [BOARD_PCIDAS6025] = {
 782                 .name           = "pci-das6025",
 783                 .ai_se_chans    = 16,
 784                 .ai_bits        = 12,
 785                 .ai_speed       = 5000,
 786                 .ao_nchan       = 2,
 787                 .ao_bits        = 12,
 788                 .ao_scan_speed  = 100000,
 789                 .layout         = LAYOUT_60XX,
 790                 .ai_range_table = &ai_ranges_60xx,
 791                 .ao_range_table = &range_bipolar10,
 792                 .ao_range_code  = ao_range_code_60xx,
 793                 .ai_fifo        = &ai_fifo_60xx,
 794                 .has_8255       = 1,
 795         },
 796         [BOARD_PCIDAS6030] = {
 797                 .name           = "pci-das6030",
 798                 .ai_se_chans    = 16,
 799                 .ai_bits        = 16,
 800                 .ai_speed       = 10000,
 801                 .ao_nchan       = 2,
 802                 .ao_bits        = 16,
 803                 .ao_scan_speed  = 10000,
 804                 .layout         = LAYOUT_60XX,
 805                 .ai_range_table = &ai_ranges_6030,
 806                 .ao_range_table = &ao_ranges_6030,
 807                 .ao_range_code  = ao_range_code_6030,
 808                 .ai_fifo        = &ai_fifo_60xx,
 809                 .has_8255       = 0,
 810         },
 811         [BOARD_PCIDAS6031] = {
 812                 .name           = "pci-das6031",
 813                 .ai_se_chans    = 64,
 814                 .ai_bits        = 16,
 815                 .ai_speed       = 10000,
 816                 .ao_nchan       = 2,
 817                 .ao_bits        = 16,
 818                 .ao_scan_speed  = 10000,
 819                 .layout         = LAYOUT_60XX,
 820                 .ai_range_table = &ai_ranges_6030,
 821                 .ao_range_table = &ao_ranges_6030,
 822                 .ao_range_code  = ao_range_code_6030,
 823                 .ai_fifo        = &ai_fifo_60xx,
 824                 .has_8255       = 0,
 825         },
 826         [BOARD_PCIDAS6032] = {
 827                 .name           = "pci-das6032",
 828                 .ai_se_chans    = 16,
 829                 .ai_bits        = 16,
 830                 .ai_speed       = 10000,
 831                 .ao_nchan       = 0,
 832                 .layout         = LAYOUT_60XX,
 833                 .ai_range_table = &ai_ranges_6030,
 834                 .ai_fifo        = &ai_fifo_60xx,
 835                 .has_8255       = 0,
 836         },
 837         [BOARD_PCIDAS6033] = {
 838                 .name           = "pci-das6033",
 839                 .ai_se_chans    = 64,
 840                 .ai_bits        = 16,
 841                 .ai_speed       = 10000,
 842                 .ao_nchan       = 0,
 843                 .layout         = LAYOUT_60XX,
 844                 .ai_range_table = &ai_ranges_6030,
 845                 .ai_fifo        = &ai_fifo_60xx,
 846                 .has_8255       = 0,
 847         },
 848         [BOARD_PCIDAS6034] = {
 849                 .name           = "pci-das6034",
 850                 .ai_se_chans    = 16,
 851                 .ai_bits        = 16,
 852                 .ai_speed       = 5000,
 853                 .ao_nchan       = 0,
 854                 .ao_scan_speed  = 0,
 855                 .layout         = LAYOUT_60XX,
 856                 .ai_range_table = &ai_ranges_60xx,
 857                 .ai_fifo        = &ai_fifo_60xx,
 858                 .has_8255       = 0,
 859         },
 860         [BOARD_PCIDAS6035] = {
 861                 .name           = "pci-das6035",
 862                 .ai_se_chans    = 16,
 863                 .ai_bits        = 16,
 864                 .ai_speed       = 5000,
 865                 .ao_nchan       = 2,
 866                 .ao_bits        = 12,
 867                 .ao_scan_speed  = 100000,
 868                 .layout         = LAYOUT_60XX,
 869                 .ai_range_table = &ai_ranges_60xx,
 870                 .ao_range_table = &range_bipolar10,
 871                 .ao_range_code  = ao_range_code_60xx,
 872                 .ai_fifo        = &ai_fifo_60xx,
 873                 .has_8255       = 0,
 874         },
 875         [BOARD_PCIDAS6036] = {
 876                 .name           = "pci-das6036",
 877                 .ai_se_chans    = 16,
 878                 .ai_bits        = 16,
 879                 .ai_speed       = 5000,
 880                 .ao_nchan       = 2,
 881                 .ao_bits        = 16,
 882                 .ao_scan_speed  = 100000,
 883                 .layout         = LAYOUT_60XX,
 884                 .ai_range_table = &ai_ranges_60xx,
 885                 .ao_range_table = &range_bipolar10,
 886                 .ao_range_code  = ao_range_code_60xx,
 887                 .ai_fifo        = &ai_fifo_60xx,
 888                 .has_8255       = 0,
 889         },
 890         [BOARD_PCIDAS6040] = {
 891                 .name           = "pci-das6040",
 892                 .ai_se_chans    = 16,
 893                 .ai_bits        = 12,
 894                 .ai_speed       = 2000,
 895                 .ao_nchan       = 2,
 896                 .ao_bits        = 12,
 897                 .ao_scan_speed  = 1000,
 898                 .layout         = LAYOUT_60XX,
 899                 .ai_range_table = &ai_ranges_6052,
 900                 .ao_range_table = &ao_ranges_6030,
 901                 .ao_range_code  = ao_range_code_6030,
 902                 .ai_fifo        = &ai_fifo_60xx,
 903                 .has_8255       = 0,
 904         },
 905         [BOARD_PCIDAS6052] = {
 906                 .name           = "pci-das6052",
 907                 .ai_se_chans    = 16,
 908                 .ai_bits        = 16,
 909                 .ai_speed       = 3333,
 910                 .ao_nchan       = 2,
 911                 .ao_bits        = 16,
 912                 .ao_scan_speed  = 3333,
 913                 .layout         = LAYOUT_60XX,
 914                 .ai_range_table = &ai_ranges_6052,
 915                 .ao_range_table = &ao_ranges_6030,
 916                 .ao_range_code  = ao_range_code_6030,
 917                 .ai_fifo        = &ai_fifo_60xx,
 918                 .has_8255       = 0,
 919         },
 920         [BOARD_PCIDAS6070] = {
 921                 .name           = "pci-das6070",
 922                 .ai_se_chans    = 16,
 923                 .ai_bits        = 12,
 924                 .ai_speed       = 800,
 925                 .ao_nchan       = 2,
 926                 .ao_bits        = 12,
 927                 .ao_scan_speed  = 1000,
 928                 .layout         = LAYOUT_60XX,
 929                 .ai_range_table = &ai_ranges_6052,
 930                 .ao_range_table = &ao_ranges_6030,
 931                 .ao_range_code  = ao_range_code_6030,
 932                 .ai_fifo        = &ai_fifo_60xx,
 933                 .has_8255       = 0,
 934         },
 935         [BOARD_PCIDAS6071] = {
 936                 .name           = "pci-das6071",
 937                 .ai_se_chans    = 64,
 938                 .ai_bits        = 12,
 939                 .ai_speed       = 800,
 940                 .ao_nchan       = 2,
 941                 .ao_bits        = 12,
 942                 .ao_scan_speed  = 1000,
 943                 .layout         = LAYOUT_60XX,
 944                 .ai_range_table = &ai_ranges_6052,
 945                 .ao_range_table = &ao_ranges_6030,
 946                 .ao_range_code  = ao_range_code_6030,
 947                 .ai_fifo        = &ai_fifo_60xx,
 948                 .has_8255       = 0,
 949         },
 950         [BOARD_PCIDAS4020_12] = {
 951                 .name           = "pci-das4020/12",
 952                 .ai_se_chans    = 4,
 953                 .ai_bits        = 12,
 954                 .ai_speed       = 50,
 955                 .ao_bits        = 12,
 956                 .ao_nchan       = 2,
 957                 .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
 958                 .layout         = LAYOUT_4020,
 959                 .ai_range_table = &ai_ranges_4020,
 960                 .ao_range_table = &ao_ranges_4020,
 961                 .ao_range_code  = ao_range_code_4020,
 962                 .ai_fifo        = &ai_fifo_4020,
 963                 .has_8255       = 1,
 964         },
 965 #if 0
 966         /*
 967          * The device id for these boards is unknown
 968          */
 969
 970         [BOARD_PCIDAS6402_16_JR] = {
 971                 .name           = "pci-das6402/16/jr",
 972                 .ai_se_chans    = 64,
 973                 .ai_bits        = 16,
 974                 .ai_speed       = 5000,
 975                 .ao_nchan       = 0,
 976                 .ao_scan_speed  = 10000,
 977                 .layout         = LAYOUT_64XX,
 978                 .ai_range_table = &ai_ranges_64xx,
 979                 .ai_fifo        = ai_fifo_64xx,
 980                 .has_8255       = 1,
 981         },
 982         [BOARD_PCIDAS64_M1_16_JR] = {
 983                 .name           = "pci-das64/m1/16/jr",
 984                 .ai_se_chans    = 64,
 985                 .ai_bits        = 16,
 986                 .ai_speed       = 1000,
 987                 .ao_nchan       = 0,
 988                 .ao_scan_speed  = 10000,
 989                 .layout         = LAYOUT_64XX,
 990                 .ai_range_table = &ai_ranges_64xx,
 991                 .ai_fifo        = ai_fifo_64xx,
 992                 .has_8255       = 1,
 993         },
 994         [BOARD_PCIDAS64_M2_16_JR] = {
 995                 .name = "pci-das64/m2/16/jr",
 996                 .ai_se_chans    = 64,
 997                 .ai_bits        = 16,
 998                 .ai_speed       = 500,
 999                 .ao_nchan       = 0,
1000                 .ao_scan_speed  = 10000,
1001                 .layout         = LAYOUT_64XX,
1002                 .ai_range_table = &ai_ranges_64xx,
1003                 .ai_fifo        = ai_fifo_64xx,
1004                 .has_8255       = 1,
1005         },
1006         [BOARD_PCIDAS64_M3_16_JR] = {
1007                 .name           = "pci-das64/m3/16/jr",
1008                 .ai_se_chans    = 64,
1009                 .ai_bits        = 16,
1010                 .ai_speed       = 333,
1011                 .ao_nchan       = 0,
1012                 .ao_scan_speed  = 10000,
1013                 .layout         = LAYOUT_64XX,
1014                 .ai_range_table = &ai_ranges_64xx,
1015                 .ai_fifo        = ai_fifo_64xx,
1016                 .has_8255       = 1,
1017         },
1018         [BOARD_PCIDAS64_M1_14] = {
1019                 .name           = "pci-das64/m1/14",
1020                 .ai_se_chans    = 64,
1021                 .ai_bits        = 14,
1022                 .ai_speed       = 1000,
1023                 .ao_nchan       = 2,
1024                 .ao_scan_speed  = 10000,
1025                 .layout         = LAYOUT_64XX,
1026                 .ai_range_table = &ai_ranges_64xx,
1027                 .ai_fifo        = ai_fifo_64xx,
1028                 .has_8255       = 1,
1029         },
1030         [BOARD_PCIDAS64_M2_14] = {
1031                 .name           = "pci-das64/m2/14",
1032                 .ai_se_chans    = 64,
1033                 .ai_bits        = 14,
1034                 .ai_speed       = 500,
1035                 .ao_nchan       = 2,
1036                 .ao_scan_speed  = 10000,
1037                 .layout         = LAYOUT_64XX,
1038                 .ai_range_table = &ai_ranges_64xx,
1039                 .ai_fifo        = ai_fifo_64xx,
1040                 .has_8255       = 1,
1041         },
1042         [BOARD_PCIDAS64_M3_14] = {
1043                 .name           = "pci-das64/m3/14",
1044                 .ai_se_chans    = 64,
1045                 .ai_bits        = 14,
1046                 .ai_speed       = 333,
1047                 .ao_nchan       = 2,
1048                 .ao_scan_speed  = 10000,
1049                 .layout         = LAYOUT_64XX,
1050                 .ai_range_table = &ai_ranges_64xx,
1051                 .ai_fifo        = ai_fifo_64xx,
1052                 .has_8255       = 1,
1053         },
1054 #endif
1055 };
1056
1057 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1058                                               int use_differential)
1059 {
1060         const struct pcidas64_board *thisboard = comedi_board(dev);
1061
1062         if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1063             (thisboard->layout == LAYOUT_60XX && use_differential))
1064                 return ADC_SE_DIFF_BIT;
1065         else
1066                 return 0;
1067 };
1068
1069 struct ext_clock_info {
1070         /*  master clock divisor to use for scans with external master clock */
1071         unsigned int divisor;
1072         /*  chanspec for master clock input when used as scan begin src */
1073         unsigned int chanspec;
1074 };
1075
1076 /* this structure is for data unique to this hardware driver. */
1077 struct pcidas64_private {
1078         /*  base addresses (physical) */
1079         resource_size_t main_phys_iobase;
1080         resource_size_t dio_counter_phys_iobase;
1081         /*  base addresses (ioremapped) */
1082         void __iomem *plx9080_iobase;
1083         void __iomem *main_iobase;
1084         void __iomem *dio_counter_iobase;
1085         /*  local address (used by dma controller) */
1086         uint32_t local0_iobase;
1087         uint32_t local1_iobase;
1088         /*  number of analog input samples remaining */
1089         volatile unsigned int ai_count;
1090         /*  dma buffers for analog input */
1091         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1092         /*  physical addresses of ai dma buffers */
1093         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1094         /*  array of ai dma descriptors read by plx9080,
1095          *  allocated to get proper alignment */
1096         struct plx_dma_desc *ai_dma_desc;
1097         /*  physical address of ai dma descriptor array */
1098         dma_addr_t ai_dma_desc_bus_addr;
1099         /*  index of the ai dma descriptor/buffer
1100          *  that is currently being used */
1101         volatile unsigned int ai_dma_index;
1102         /*  dma buffers for analog output */
1103         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1104         /*  physical addresses of ao dma buffers */
1105         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1106         struct plx_dma_desc *ao_dma_desc;
1107         dma_addr_t ao_dma_desc_bus_addr;
1108         /*  keeps track of buffer where the next ao sample should go */
1109         volatile unsigned int ao_dma_index;
1110         /*  number of analog output samples remaining */
1111         volatile unsigned long ao_count;
1112         /*  remember what the analog outputs are set to, to allow readback */
1113         volatile unsigned int ao_value[2];
1114         unsigned int hw_revision;       /*  stc chip hardware revision number */
1115         /*  last bits sent to INTR_ENABLE_REG register */
1116         volatile unsigned int intr_enable_bits;
1117         /*  last bits sent to ADC_CONTROL1_REG register */
1118         volatile uint16_t adc_control1_bits;
1119         /*  last bits sent to FIFO_SIZE_REG register */
1120         volatile uint16_t fifo_size_bits;
1121         /*  last bits sent to HW_CONFIG_REG register */
1122         volatile uint16_t hw_config_bits;
1123         volatile uint16_t dac_control1_bits;
1124         /*  last bits written to plx9080 control register */
1125         volatile uint32_t plx_control_bits;
1126         /*  last bits written to plx interrupt control and status register */
1127         volatile uint32_t plx_intcsr_bits;
1128         /*  index of calibration source readable through ai ch0 */
1129         volatile int calibration_source;
1130         /*  bits written to i2c calibration/range register */
1131         volatile uint8_t i2c_cal_range_bits;
1132         /*  configure digital triggers to trigger on falling edge */
1133         volatile unsigned int ext_trig_falling;
1134         /*  states of various devices stored to enable read-back */
1135         unsigned int ad8402_state[2];
1136         unsigned int caldac_state[8];
1137         volatile short ai_cmd_running;
1138         unsigned int ai_fifo_segment_length;
1139         struct ext_clock_info ext_clock;
1140         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1141 };
1142
1143 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1144                                        unsigned int range_index)
1145 {
1146         const struct pcidas64_board *thisboard = comedi_board(dev);
1147         const struct comedi_krange *range =
1148                 &thisboard->ai_range_table->range[range_index];
1149         unsigned int bits = 0;
1150
1151         switch (range->max) {
1152         case 10000000:
1153                 bits = 0x000;
1154                 break;
1155         case 5000000:
1156                 bits = 0x100;
1157                 break;
1158         case 2000000:
1159         case 2500000:
1160                 bits = 0x200;
1161                 break;
1162         case 1000000:
1163         case 1250000:
1164                 bits = 0x300;
1165                 break;
1166         case 500000:
1167                 bits = 0x400;
1168                 break;
1169         case 200000:
1170         case 250000:
1171                 bits = 0x500;
1172                 break;
1173         case 100000:
1174                 bits = 0x600;
1175                 break;
1176         case 50000:
1177                 bits = 0x700;
1178                 break;
1179         default:
1180                 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1181                 break;
1182         }
1183         if (range->min == 0)
1184                 bits += 0x900;
1185         return bits;
1186 }
1187
1188 static unsigned int hw_revision(const struct comedi_device *dev,
1189                                 uint16_t hw_status_bits)
1190 {
1191         const struct pcidas64_board *thisboard = comedi_board(dev);
1192
1193         if (thisboard->layout == LAYOUT_4020)
1194                 return (hw_status_bits >> 13) & 0x7;
1195
1196         return (hw_status_bits >> 12) & 0xf;
1197 }
1198
1199 static void set_dac_range_bits(struct comedi_device *dev,
1200                                volatile uint16_t *bits, unsigned int channel,
1201                                unsigned int range)
1202 {
1203         const struct pcidas64_board *thisboard = comedi_board(dev);
1204         unsigned int code = thisboard->ao_range_code[range];
1205
1206         if (channel > 1)
1207                 comedi_error(dev, "bug! bad channel?");
1208         if (code & ~0x3)
1209                 comedi_error(dev, "bug! bad range code?");
1210
1211         *bits &= ~(0x3 << (2 * channel));
1212         *bits |= code << (2 * channel);
1213 };
1214
1215 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1216 {
1217         return board->ao_nchan && board->layout != LAYOUT_4020;
1218 }
1219
1220 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1221 {
1222         struct pcidas64_private *devpriv = dev->private;
1223         unsigned long flags;
1224
1225         /*  spinlock for plx dma control/status reg */
1226         spin_lock_irqsave(&dev->spinlock, flags);
1227
1228         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1229
1230         spin_unlock_irqrestore(&dev->spinlock, flags);
1231 }
1232
1233 static void disable_plx_interrupts(struct comedi_device *dev)
1234 {
1235         struct pcidas64_private *devpriv = dev->private;
1236
1237         devpriv->plx_intcsr_bits = 0;
1238         writel(devpriv->plx_intcsr_bits,
1239                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1240 }
1241
1242 static void disable_ai_interrupts(struct comedi_device *dev)
1243 {
1244         struct pcidas64_private *devpriv = dev->private;
1245         unsigned long flags;
1246
1247         spin_lock_irqsave(&dev->spinlock, flags);
1248         devpriv->intr_enable_bits &=
1249                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1250                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1251                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1252         writew(devpriv->intr_enable_bits,
1253                devpriv->main_iobase + INTR_ENABLE_REG);
1254         spin_unlock_irqrestore(&dev->spinlock, flags);
1255
1256         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1257 }
1258
1259 static void enable_ai_interrupts(struct comedi_device *dev,
1260                                  const struct comedi_cmd *cmd)
1261 {
1262         const struct pcidas64_board *thisboard = comedi_board(dev);
1263         struct pcidas64_private *devpriv = dev->private;
1264         uint32_t bits;
1265         unsigned long flags;
1266
1267         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1268                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1269         /*  Use pio transfer and interrupt on end of conversion
1270          *  if TRIG_WAKE_EOS flag is set. */
1271         if (cmd->flags & TRIG_WAKE_EOS) {
1272                 /*  4020 doesn't support pio transfers except for fifo dregs */
1273                 if (thisboard->layout != LAYOUT_4020)
1274                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1275         }
1276         spin_lock_irqsave(&dev->spinlock, flags);
1277         devpriv->intr_enable_bits |= bits;
1278         writew(devpriv->intr_enable_bits,
1279                devpriv->main_iobase + INTR_ENABLE_REG);
1280         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
1281         spin_unlock_irqrestore(&dev->spinlock, flags);
1282 }
1283
1284 /* initialize plx9080 chip */
1285 static void init_plx9080(struct comedi_device *dev)
1286 {
1287         const struct pcidas64_board *thisboard = comedi_board(dev);
1288         struct pcidas64_private *devpriv = dev->private;
1289         uint32_t bits;
1290         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1291
1292         devpriv->plx_control_bits =
1293                 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1294
1295         /*  plx9080 dump */
1296         DEBUG_PRINT(" plx interrupt status 0x%x\n",
1297                     readl(plx_iobase + PLX_INTRCS_REG));
1298         DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1299         DEBUG_PRINT(" plx control reg 0x%x\n", devpriv->plx_control_bits);
1300         DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1301                     readl(plx_iobase + PLX_MARB_REG));
1302         DEBUG_PRINT(" plx region0 reg 0x%x\n",
1303                     readl(plx_iobase + PLX_REGION0_REG));
1304         DEBUG_PRINT(" plx region1 reg 0x%x\n",
1305                     readl(plx_iobase + PLX_REGION1_REG));
1306
1307         DEBUG_PRINT(" plx revision 0x%x\n",
1308                     readl(plx_iobase + PLX_REVISION_REG));
1309         DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1310                     readl(plx_iobase + PLX_DMA0_MODE_REG));
1311         DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1312                     readl(plx_iobase + PLX_DMA1_MODE_REG));
1313         DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1314                     readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1315         DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1316                     readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1317         DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1318                     readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1319         DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1320                     readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1321         DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1322                     readb(plx_iobase + PLX_DMA0_CS_REG));
1323         DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1324                     readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1325         DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1326
1327 #ifdef __BIG_ENDIAN
1328         bits = BIGEND_DMA0 | BIGEND_DMA1;
1329 #else
1330         bits = 0;
1331 #endif
1332         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1333
1334         disable_plx_interrupts(dev);
1335
1336         abort_dma(dev, 0);
1337         abort_dma(dev, 1);
1338
1339         /*  configure dma0 mode */
1340         bits = 0;
1341         /*  enable ready input, not sure if this is necessary */
1342         bits |= PLX_DMA_EN_READYIN_BIT;
1343         /*  enable bterm, not sure if this is necessary */
1344         bits |= PLX_EN_BTERM_BIT;
1345         /*  enable dma chaining */
1346         bits |= PLX_EN_CHAIN_BIT;
1347         /*  enable interrupt on dma done
1348          *  (probably don't need this, since chain never finishes) */
1349         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1350         /*  don't increment local address during transfers
1351          *  (we are transferring from a fixed fifo register) */
1352         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1353         /*  route dma interrupt to pci bus */
1354         bits |= PLX_DMA_INTR_PCI_BIT;
1355         /*  enable demand mode */
1356         bits |= PLX_DEMAND_MODE_BIT;
1357         /*  enable local burst mode */
1358         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1359         /*  4020 uses 32 bit dma */
1360         if (thisboard->layout == LAYOUT_4020)
1361                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1362         else            /*  localspace0 bus is 16 bits wide */
1363                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1364         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1365         if (ao_cmd_is_supported(thisboard))
1366                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1367
1368         /*  enable interrupts on plx 9080 */
1369         devpriv->plx_intcsr_bits |=
1370             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1371             ICS_DMA0_E | ICS_DMA1_E;
1372         writel(devpriv->plx_intcsr_bits,
1373                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1374 }
1375
1376 static void disable_ai_pacing(struct comedi_device *dev)
1377 {
1378         struct pcidas64_private *devpriv = dev->private;
1379         unsigned long flags;
1380
1381         disable_ai_interrupts(dev);
1382
1383         spin_lock_irqsave(&dev->spinlock, flags);
1384         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1385         writew(devpriv->adc_control1_bits,
1386                devpriv->main_iobase + ADC_CONTROL1_REG);
1387         spin_unlock_irqrestore(&dev->spinlock, flags);
1388
1389         /* disable pacing, triggering, etc */
1390         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1391                devpriv->main_iobase + ADC_CONTROL0_REG);
1392 }
1393
1394 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1395                                       unsigned int num_entries)
1396 {
1397         const struct pcidas64_board *thisboard = comedi_board(dev);
1398         struct pcidas64_private *devpriv = dev->private;
1399         static const int increment_size = 0x100;
1400         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1401         unsigned int num_increments;
1402         uint16_t bits;
1403
1404         if (num_entries < increment_size)
1405                 num_entries = increment_size;
1406         if (num_entries > fifo->max_segment_length)
1407                 num_entries = fifo->max_segment_length;
1408
1409         /*  1 == 256 entries, 2 == 512 entries, etc */
1410         num_increments = (num_entries + increment_size / 2) / increment_size;
1411
1412         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1413         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1414         devpriv->fifo_size_bits |= bits;
1415         writew(devpriv->fifo_size_bits,
1416                devpriv->main_iobase + FIFO_SIZE_REG);
1417
1418         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1419
1420         DEBUG_PRINT("set hardware fifo segment length to %i\n",
1421                     devpriv->ai_fifo_segment_length);
1422
1423         return devpriv->ai_fifo_segment_length;
1424 }
1425
1426 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1427 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1428 {
1429         const struct pcidas64_board *thisboard = comedi_board(dev);
1430         unsigned int num_fifo_entries;
1431         int retval;
1432         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1433
1434         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1435
1436         retval = set_ai_fifo_segment_length(dev,
1437                                             num_fifo_entries /
1438                                             fifo->num_segments);
1439         if (retval < 0)
1440                 return retval;
1441
1442         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1443
1444         DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
1445
1446         return num_samples;
1447 }
1448
1449 /* query length of fifo */
1450 static unsigned int ai_fifo_size(struct comedi_device *dev)
1451 {
1452         const struct pcidas64_board *thisboard = comedi_board(dev);
1453         struct pcidas64_private *devpriv = dev->private;
1454
1455         return devpriv->ai_fifo_segment_length *
1456                thisboard->ai_fifo->num_segments *
1457                thisboard->ai_fifo->sample_packing_ratio;
1458 }
1459
1460 static void init_stc_registers(struct comedi_device *dev)
1461 {
1462         const struct pcidas64_board *thisboard = comedi_board(dev);
1463         struct pcidas64_private *devpriv = dev->private;
1464         uint16_t bits;
1465         unsigned long flags;
1466
1467         spin_lock_irqsave(&dev->spinlock, flags);
1468
1469         /*  bit should be set for 6025,
1470          *  although docs say boards with <= 16 chans should be cleared XXX */
1471         if (1)
1472                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1473         writew(devpriv->adc_control1_bits,
1474                devpriv->main_iobase + ADC_CONTROL1_REG);
1475
1476         /*  6402/16 manual says this register must be initialized to 0xff? */
1477         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1478
1479         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1480         if (thisboard->layout == LAYOUT_4020)
1481                 bits |= INTERNAL_CLOCK_4020_BITS;
1482         devpriv->hw_config_bits |= bits;
1483         writew(devpriv->hw_config_bits,
1484                devpriv->main_iobase + HW_CONFIG_REG);
1485
1486         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1487         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1488
1489         spin_unlock_irqrestore(&dev->spinlock, flags);
1490
1491         /*  set fifos to maximum size */
1492         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1493         set_ai_fifo_segment_length(dev,
1494                                    thisboard->ai_fifo->max_segment_length);
1495
1496         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1497         devpriv->intr_enable_bits =
1498                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1499                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1500         writew(devpriv->intr_enable_bits,
1501                devpriv->main_iobase + INTR_ENABLE_REG);
1502
1503         disable_ai_pacing(dev);
1504 };
1505
1506 static int alloc_and_init_dma_members(struct comedi_device *dev)
1507 {
1508         const struct pcidas64_board *thisboard = comedi_board(dev);
1509         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1510         struct pcidas64_private *devpriv = dev->private;
1511         int i;
1512
1513         /*  allocate pci dma buffers */
1514         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1515                 devpriv->ai_buffer[i] =
1516                         pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1517                                              &devpriv->ai_buffer_bus_addr[i]);
1518                 if (devpriv->ai_buffer[i] == NULL)
1519                         return -ENOMEM;
1520
1521         }
1522         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1523                 if (ao_cmd_is_supported(thisboard)) {
1524                         devpriv->ao_buffer[i] =
1525                                 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1526                                                      &devpriv->
1527                                                       ao_buffer_bus_addr[i]);
1528                         if (devpriv->ao_buffer[i] == NULL)
1529                                 return -ENOMEM;
1530
1531                 }
1532         }
1533         /*  allocate dma descriptors */
1534         devpriv->ai_dma_desc =
1535                 pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1536                                      ai_dma_ring_count(thisboard),
1537                                      &devpriv->ai_dma_desc_bus_addr);
1538         if (devpriv->ai_dma_desc == NULL)
1539                 return -ENOMEM;
1540
1541         DEBUG_PRINT("ai dma descriptors start at bus addr 0x%llx\n",
1542                     (unsigned long long)devpriv->ai_dma_desc_bus_addr);
1543         if (ao_cmd_is_supported(thisboard)) {
1544                 devpriv->ao_dma_desc =
1545                         pci_alloc_consistent(pcidev,
1546                                              sizeof(struct plx_dma_desc) *
1547                                              AO_DMA_RING_COUNT,
1548                                              &devpriv->ao_dma_desc_bus_addr);
1549                 if (devpriv->ao_dma_desc == NULL)
1550                         return -ENOMEM;
1551
1552                 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%llx\n",
1553                             (unsigned long long)devpriv->ao_dma_desc_bus_addr);
1554         }
1555         /*  initialize dma descriptors */
1556         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1557                 devpriv->ai_dma_desc[i].pci_start_addr =
1558                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1559                 if (thisboard->layout == LAYOUT_4020)
1560                         devpriv->ai_dma_desc[i].local_start_addr =
1561                                 cpu_to_le32(devpriv->local1_iobase +
1562                                             ADC_FIFO_REG);
1563                 else
1564                         devpriv->ai_dma_desc[i].local_start_addr =
1565                                 cpu_to_le32(devpriv->local0_iobase +
1566                                             ADC_FIFO_REG);
1567                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1568                 devpriv->ai_dma_desc[i].next =
1569                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1570                                      ((i + 1) % ai_dma_ring_count(thisboard)) *
1571                                      sizeof(devpriv->ai_dma_desc[0])) |
1572                                     PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1573                                     PLX_XFER_LOCAL_TO_PCI);
1574         }
1575         if (ao_cmd_is_supported(thisboard)) {
1576                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1577                         devpriv->ao_dma_desc[i].pci_start_addr =
1578                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1579                         devpriv->ao_dma_desc[i].local_start_addr =
1580                                 cpu_to_le32(devpriv->local0_iobase +
1581                                             DAC_FIFO_REG);
1582                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1583                         devpriv->ao_dma_desc[i].next =
1584                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1585                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1586                                              sizeof(devpriv->ao_dma_desc[0])) |
1587                                             PLX_DESC_IN_PCI_BIT |
1588                                             PLX_INTR_TERM_COUNT);
1589                 }
1590         }
1591         return 0;
1592 }
1593
1594 static inline void warn_external_queue(struct comedi_device *dev)
1595 {
1596         comedi_error(dev,
1597                      "AO command and AI external channel queue cannot be used simultaneously.");
1598         comedi_error(dev,
1599                      "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1600 }
1601
1602 /* Their i2c requires a huge delay on setting clock or data high for some reason */
1603 static const int i2c_high_udelay = 1000;
1604 static const int i2c_low_udelay = 10;
1605
1606 /* set i2c data line high or low */
1607 static void i2c_set_sda(struct comedi_device *dev, int state)
1608 {
1609         struct pcidas64_private *devpriv = dev->private;
1610         static const int data_bit = CTL_EE_W;
1611         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1612                                          PLX_CONTROL_REG;
1613
1614         if (state) {
1615                 /*  set data line high */
1616                 devpriv->plx_control_bits &= ~data_bit;
1617                 writel(devpriv->plx_control_bits, plx_control_addr);
1618                 udelay(i2c_high_udelay);
1619         } else {                /*  set data line low */
1620
1621                 devpriv->plx_control_bits |= data_bit;
1622                 writel(devpriv->plx_control_bits, plx_control_addr);
1623                 udelay(i2c_low_udelay);
1624         }
1625 }
1626
1627 /* set i2c clock line high or low */
1628 static void i2c_set_scl(struct comedi_device *dev, int state)
1629 {
1630         struct pcidas64_private *devpriv = dev->private;
1631         static const int clock_bit = CTL_USERO;
1632         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1633                                          PLX_CONTROL_REG;
1634
1635         if (state) {
1636                 /*  set clock line high */
1637                 devpriv->plx_control_bits &= ~clock_bit;
1638                 writel(devpriv->plx_control_bits, plx_control_addr);
1639                 udelay(i2c_high_udelay);
1640         } else {                /*  set clock line low */
1641
1642                 devpriv->plx_control_bits |= clock_bit;
1643                 writel(devpriv->plx_control_bits, plx_control_addr);
1644                 udelay(i2c_low_udelay);
1645         }
1646 }
1647
1648 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1649 {
1650         uint8_t bit;
1651         unsigned int num_bits = 8;
1652
1653         DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
1654
1655         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1656                 i2c_set_scl(dev, 0);
1657                 if ((byte & bit))
1658                         i2c_set_sda(dev, 1);
1659                 else
1660                         i2c_set_sda(dev, 0);
1661                 i2c_set_scl(dev, 1);
1662         }
1663 }
1664
1665 /* we can't really read the lines, so fake it */
1666 static int i2c_read_ack(struct comedi_device *dev)
1667 {
1668         i2c_set_scl(dev, 0);
1669         i2c_set_sda(dev, 1);
1670         i2c_set_scl(dev, 1);
1671
1672         return 0;               /*  return fake acknowledge bit */
1673 }
1674
1675 /* send start bit */
1676 static void i2c_start(struct comedi_device *dev)
1677 {
1678         i2c_set_scl(dev, 1);
1679         i2c_set_sda(dev, 1);
1680         i2c_set_sda(dev, 0);
1681 }
1682
1683 /* send stop bit */
1684 static void i2c_stop(struct comedi_device *dev)
1685 {
1686         i2c_set_scl(dev, 0);
1687         i2c_set_sda(dev, 0);
1688         i2c_set_scl(dev, 1);
1689         i2c_set_sda(dev, 1);
1690 }
1691
1692 static void i2c_write(struct comedi_device *dev, unsigned int address,
1693                       const uint8_t *data, unsigned int length)
1694 {
1695         struct pcidas64_private *devpriv = dev->private;
1696         unsigned int i;
1697         uint8_t bitstream;
1698         static const int read_bit = 0x1;
1699
1700         /* XXX need mutex to prevent simultaneous attempts to access
1701          * eeprom and i2c bus */
1702
1703         /*  make sure we dont send anything to eeprom */
1704         devpriv->plx_control_bits &= ~CTL_EE_CS;
1705
1706         i2c_stop(dev);
1707         i2c_start(dev);
1708
1709         /*  send address and write bit */
1710         bitstream = (address << 1) & ~read_bit;
1711         i2c_write_byte(dev, bitstream);
1712
1713         /*  get acknowledge */
1714         if (i2c_read_ack(dev) != 0) {
1715                 comedi_error(dev, "i2c write failed: no acknowledge");
1716                 i2c_stop(dev);
1717                 return;
1718         }
1719         /*  write data bytes */
1720         for (i = 0; i < length; i++) {
1721                 i2c_write_byte(dev, data[i]);
1722                 if (i2c_read_ack(dev) != 0) {
1723                         comedi_error(dev, "i2c write failed: no acknowledge");
1724                         i2c_stop(dev);
1725                         return;
1726                 }
1727         }
1728         i2c_stop(dev);
1729 }
1730
1731 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1732                     struct comedi_insn *insn, unsigned int *data)
1733 {
1734         const struct pcidas64_board *thisboard = comedi_board(dev);
1735         struct pcidas64_private *devpriv = dev->private;
1736         unsigned int bits = 0, n, i;
1737         unsigned int channel, range, aref;
1738         unsigned long flags;
1739         static const int timeout = 100;
1740
1741         DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1742         channel = CR_CHAN(insn->chanspec);
1743         range = CR_RANGE(insn->chanspec);
1744         aref = CR_AREF(insn->chanspec);
1745
1746         /*  disable card's analog input interrupt sources and pacing */
1747         /*  4020 generates dac done interrupts even though they are disabled */
1748         disable_ai_pacing(dev);
1749
1750         spin_lock_irqsave(&dev->spinlock, flags);
1751         if (insn->chanspec & CR_ALT_FILTER)
1752                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1753         else
1754                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1755         writew(devpriv->adc_control1_bits,
1756                devpriv->main_iobase + ADC_CONTROL1_REG);
1757         spin_unlock_irqrestore(&dev->spinlock, flags);
1758
1759         if (thisboard->layout != LAYOUT_4020) {
1760                 /*  use internal queue */
1761                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1762                 writew(devpriv->hw_config_bits,
1763                        devpriv->main_iobase + HW_CONFIG_REG);
1764
1765                 /*  ALT_SOURCE is internal calibration reference */
1766                 if (insn->chanspec & CR_ALT_SOURCE) {
1767                         unsigned int cal_en_bit;
1768
1769                         DEBUG_PRINT("reading calibration source\n");
1770                         if (thisboard->layout == LAYOUT_60XX)
1771                                 cal_en_bit = CAL_EN_60XX_BIT;
1772                         else
1773                                 cal_en_bit = CAL_EN_64XX_BIT;
1774                         /*  select internal reference source to connect
1775                          *  to channel 0 */
1776                         writew(cal_en_bit |
1777                                adc_src_bits(devpriv->calibration_source),
1778                                devpriv->main_iobase + CALIBRATION_REG);
1779                 } else {
1780                         /*  make sure internal calibration source
1781                          *  is turned off */
1782                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1783                 }
1784                 /*  load internal queue */
1785                 bits = 0;
1786                 /*  set gain */
1787                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1788                 /*  set single-ended / differential */
1789                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1790                 if (aref == AREF_COMMON)
1791                         bits |= ADC_COMMON_BIT;
1792                 bits |= adc_chan_bits(channel);
1793                 /*  set stop channel */
1794                 writew(adc_chan_bits(channel),
1795                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1796                 /*  set start channel, and rest of settings */
1797                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1798         } else {
1799                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1800
1801                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1802                 if (insn->chanspec & CR_ALT_SOURCE) {
1803                         DEBUG_PRINT("reading calibration source\n");
1804                         devpriv->i2c_cal_range_bits |=
1805                                 adc_src_4020_bits(devpriv->calibration_source);
1806                 } else {        /* select BNC inputs */
1807                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1808                 }
1809                 /*  select range */
1810                 if (range == 0)
1811                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1812                 else
1813                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1814                 /*  update calibration/range i2c register only if necessary,
1815                  *  as it is very slow */
1816                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1817                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1818                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1819                                   sizeof(i2c_data));
1820                 }
1821
1822                 /* 4020 manual asks that sample interval register to be set
1823                  * before writing to convert register.
1824                  * Using somewhat arbitrary setting of 4 master clock ticks
1825                  * = 0.1 usec */
1826                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1827                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1828         }
1829
1830         for (n = 0; n < insn->n; n++) {
1831
1832                 /*  clear adc buffer (inside loop for 4020 sake) */
1833                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1834
1835                 /* trigger conversion, bits sent only matter for 4020 */
1836                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1837                        devpriv->main_iobase + ADC_CONVERT_REG);
1838
1839                 /*  wait for data */
1840                 for (i = 0; i < timeout; i++) {
1841                         bits = readw(devpriv->main_iobase + HW_STATUS_REG);
1842                         DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1843                         if (thisboard->layout == LAYOUT_4020) {
1844                                 if (readw(devpriv->main_iobase +
1845                                           ADC_WRITE_PNTR_REG))
1846                                         break;
1847                         } else {
1848                                 if (pipe_full_bits(bits))
1849                                         break;
1850                         }
1851                         udelay(1);
1852                 }
1853                 DEBUG_PRINT(" looped %i times waiting for data\n", i);
1854                 if (i == timeout) {
1855                         comedi_error(dev, " analog input read insn timed out");
1856                         dev_info(dev->class_dev, "status 0x%x\n", bits);
1857                         return -ETIME;
1858                 }
1859                 if (thisboard->layout == LAYOUT_4020)
1860                         data[n] = readl(devpriv->dio_counter_iobase +
1861                                         ADC_FIFO_REG) & 0xffff;
1862                 else
1863                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1864         }
1865
1866         return n;
1867 }
1868
1869 static int ai_config_calibration_source(struct comedi_device *dev,
1870                                         unsigned int *data)
1871 {
1872         const struct pcidas64_board *thisboard = comedi_board(dev);
1873         struct pcidas64_private *devpriv = dev->private;
1874         unsigned int source = data[1];
1875         int num_calibration_sources;
1876
1877         if (thisboard->layout == LAYOUT_60XX)
1878                 num_calibration_sources = 16;
1879         else
1880                 num_calibration_sources = 8;
1881         if (source >= num_calibration_sources) {
1882                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1883                         source);
1884                 return -EINVAL;
1885         }
1886
1887         DEBUG_PRINT("setting calibration source to %i\n", source);
1888         devpriv->calibration_source = source;
1889
1890         return 2;
1891 }
1892
1893 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1894 {
1895         const struct pcidas64_board *thisboard = comedi_board(dev);
1896         int fifo_size;
1897         const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1898         unsigned int block_size, requested_block_size;
1899         int retval;
1900
1901         requested_block_size = data[1];
1902
1903         if (requested_block_size) {
1904                 fifo_size = requested_block_size * fifo->num_segments /
1905                             bytes_in_sample;
1906
1907                 retval = set_ai_fifo_size(dev, fifo_size);
1908                 if (retval < 0)
1909                         return retval;
1910
1911         }
1912
1913         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1914
1915         data[1] = block_size;
1916
1917         return 2;
1918 }
1919
1920 static int ai_config_master_clock_4020(struct comedi_device *dev,
1921                                        unsigned int *data)
1922 {
1923         struct pcidas64_private *devpriv = dev->private;
1924         unsigned int divisor = data[4];
1925         int retval = 0;
1926
1927         if (divisor < 2) {
1928                 divisor = 2;
1929                 retval = -EAGAIN;
1930         }
1931
1932         switch (data[1]) {
1933         case COMEDI_EV_SCAN_BEGIN:
1934                 devpriv->ext_clock.divisor = divisor;
1935                 devpriv->ext_clock.chanspec = data[2];
1936                 break;
1937         default:
1938                 return -EINVAL;
1939                 break;
1940         }
1941
1942         data[4] = divisor;
1943
1944         return retval ? retval : 5;
1945 }
1946
1947 /* XXX could add support for 60xx series */
1948 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1949 {
1950         const struct pcidas64_board *thisboard = comedi_board(dev);
1951
1952         switch (thisboard->layout) {
1953         case LAYOUT_4020:
1954                 return ai_config_master_clock_4020(dev, data);
1955                 break;
1956         default:
1957                 return -EINVAL;
1958                 break;
1959         }
1960
1961         return -EINVAL;
1962 }
1963
1964 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1965                           struct comedi_insn *insn, unsigned int *data)
1966 {
1967         int id = data[0];
1968
1969         switch (id) {
1970         case INSN_CONFIG_ALT_SOURCE:
1971                 return ai_config_calibration_source(dev, data);
1972                 break;
1973         case INSN_CONFIG_BLOCK_SIZE:
1974                 return ai_config_block_size(dev, data);
1975                 break;
1976         case INSN_CONFIG_TIMER_1:
1977                 return ai_config_master_clock(dev, data);
1978                 break;
1979         default:
1980                 return -EINVAL;
1981                 break;
1982         }
1983         return -EINVAL;
1984 }
1985
1986 /* Gets nearest achievable timing given master clock speed, does not
1987  * take into account possible minimum/maximum divisor values.  Used
1988  * by other timing checking functions. */
1989 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1990 {
1991         unsigned int divisor;
1992
1993         switch (flags & TRIG_ROUND_MASK) {
1994         case TRIG_ROUND_UP:
1995                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
1996                 break;
1997         case TRIG_ROUND_DOWN:
1998                 divisor = ns / TIMER_BASE;
1999                 break;
2000         case TRIG_ROUND_NEAREST:
2001         default:
2002                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
2003                 break;
2004         }
2005         return divisor;
2006 }
2007
2008 /* utility function that rounds desired timing to an achievable time, and
2009  * sets cmd members appropriately.
2010  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
2011  */
2012 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2013 {
2014         const struct pcidas64_board *thisboard = comedi_board(dev);
2015         unsigned int convert_divisor = 0, scan_divisor;
2016         static const int min_convert_divisor = 3;
2017         static const int max_convert_divisor =
2018                 max_counter_value + min_convert_divisor;
2019         static const int min_scan_divisor_4020 = 2;
2020         unsigned long long max_scan_divisor, min_scan_divisor;
2021
2022         if (cmd->convert_src == TRIG_TIMER) {
2023                 if (thisboard->layout == LAYOUT_4020) {
2024                         cmd->convert_arg = 0;
2025                 } else {
2026                         convert_divisor = get_divisor(cmd->convert_arg,
2027                                                       cmd->flags);
2028                         if (convert_divisor > max_convert_divisor)
2029                                 convert_divisor = max_convert_divisor;
2030                         if (convert_divisor < min_convert_divisor)
2031                                 convert_divisor = min_convert_divisor;
2032                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2033                 }
2034         } else if (cmd->convert_src == TRIG_NOW) {
2035                 cmd->convert_arg = 0;
2036         }
2037
2038         if (cmd->scan_begin_src == TRIG_TIMER) {
2039                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2040                 if (cmd->convert_src == TRIG_TIMER) {
2041                         /*  XXX check for integer overflows */
2042                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2043                         max_scan_divisor =
2044                                 (convert_divisor * cmd->chanlist_len - 1) +
2045                                 max_counter_value;
2046                 } else {
2047                         min_scan_divisor = min_scan_divisor_4020;
2048                         max_scan_divisor = max_counter_value + min_scan_divisor;
2049                 }
2050                 if (scan_divisor > max_scan_divisor)
2051                         scan_divisor = max_scan_divisor;
2052                 if (scan_divisor < min_scan_divisor)
2053                         scan_divisor = min_scan_divisor;
2054                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2055         }
2056
2057         return;
2058 }
2059
2060 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2061                       struct comedi_cmd *cmd)
2062 {
2063         const struct pcidas64_board *thisboard = comedi_board(dev);
2064         int err = 0;
2065         unsigned int tmp_arg, tmp_arg2;
2066         int i;
2067         int aref;
2068         unsigned int triggers;
2069
2070         /* Step 1 : check if triggers are trivially valid */
2071
2072         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2073
2074         triggers = TRIG_TIMER;
2075         if (thisboard->layout == LAYOUT_4020)
2076                 triggers |= TRIG_OTHER;
2077         else
2078                 triggers |= TRIG_FOLLOW;
2079         err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2080
2081         triggers = TRIG_TIMER;
2082         if (thisboard->layout == LAYOUT_4020)
2083                 triggers |= TRIG_NOW;
2084         else
2085                 triggers |= TRIG_EXT;
2086         err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2087         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2088         err |= cfc_check_trigger_src(&cmd->stop_src,
2089                                      TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2090
2091         if (err)
2092                 return 1;
2093
2094         /* Step 2a : make sure trigger sources are unique */
2095
2096         err |= cfc_check_trigger_is_unique(cmd->start_src);
2097         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2098         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2099         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2100
2101         /* Step 2b : and mutually compatible */
2102
2103         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2104                 err |= -EINVAL;
2105         if (cmd->stop_src != TRIG_COUNT &&
2106             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2107                 err |= -EINVAL;
2108
2109         if (err)
2110                 return 2;
2111
2112         /* Step 3: check if arguments are trivially valid */
2113
2114         if (cmd->convert_src == TRIG_TIMER) {
2115                 if (thisboard->layout == LAYOUT_4020) {
2116                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2117                 } else {
2118                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2119                                                          thisboard->ai_speed);
2120                         /* if scans are timed faster than conversion rate allows */
2121                         if (cmd->scan_begin_src == TRIG_TIMER)
2122                                 err |= cfc_check_trigger_arg_min(
2123                                                 &cmd->scan_begin_arg,
2124                                                 cmd->convert_arg *
2125                                                 cmd->chanlist_len);
2126                 }
2127         }
2128
2129         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2130         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2131
2132         switch (cmd->stop_src) {
2133         case TRIG_EXT:
2134                 break;
2135         case TRIG_COUNT:
2136                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2137                 break;
2138         case TRIG_NONE:
2139                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2140                 break;
2141         default:
2142                 break;
2143         }
2144
2145         if (err)
2146                 return 3;
2147
2148         /* step 4: fix up any arguments */
2149
2150         if (cmd->convert_src == TRIG_TIMER) {
2151                 tmp_arg = cmd->convert_arg;
2152                 tmp_arg2 = cmd->scan_begin_arg;
2153                 check_adc_timing(dev, cmd);
2154                 if (tmp_arg != cmd->convert_arg)
2155                         err++;
2156                 if (tmp_arg2 != cmd->scan_begin_arg)
2157                         err++;
2158         }
2159
2160         if (err)
2161                 return 4;
2162
2163         /*  make sure user is doesn't change analog reference mid chanlist */
2164         if (cmd->chanlist) {
2165                 aref = CR_AREF(cmd->chanlist[0]);
2166                 for (i = 1; i < cmd->chanlist_len; i++) {
2167                         if (aref != CR_AREF(cmd->chanlist[i])) {
2168                                 comedi_error(dev,
2169                                              "all elements in chanlist must use the same analog reference");
2170                                 err++;
2171                                 break;
2172                         }
2173                 }
2174                 /*  check 4020 chanlist */
2175                 if (thisboard->layout == LAYOUT_4020) {
2176                         unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2177                         for (i = 1; i < cmd->chanlist_len; i++) {
2178                                 if (CR_CHAN(cmd->chanlist[i]) !=
2179                                     first_channel + i) {
2180                                         comedi_error(dev,
2181                                                      "chanlist must use consecutive channels");
2182                                         err++;
2183                                         break;
2184                                 }
2185                         }
2186                         if (cmd->chanlist_len == 3) {
2187                                 comedi_error(dev,
2188                                              "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2189                                 err++;
2190                         }
2191                 }
2192         }
2193
2194         if (err)
2195                 return 5;
2196
2197         return 0;
2198 }
2199
2200 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2201 {
2202 /* disable for now until I work out a race */
2203         return 0;
2204
2205         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2206                 return 1;
2207         else
2208                 return 0;
2209 }
2210
2211 static void setup_sample_counters(struct comedi_device *dev,
2212                                   struct comedi_cmd *cmd)
2213 {
2214         struct pcidas64_private *devpriv = dev->private;
2215
2216         if (cmd->stop_src == TRIG_COUNT) {
2217                 /*  set software count */
2218                 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2219         }
2220         /*  load hardware conversion counter */
2221         if (use_hw_sample_counter(cmd)) {
2222                 writew(cmd->stop_arg & 0xffff,
2223                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2224                 writew((cmd->stop_arg >> 16) & 0xff,
2225                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2226         } else {
2227                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2228         }
2229 }
2230
2231 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2232 {
2233         const struct pcidas64_board *thisboard = comedi_board(dev);
2234         struct pcidas64_private *devpriv = dev->private;
2235         unsigned int num_samples;
2236
2237         num_samples = devpriv->ai_fifo_segment_length *
2238                       thisboard->ai_fifo->sample_packing_ratio;
2239         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2240                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2241
2242         return num_samples;
2243 }
2244
2245 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2246                                         const struct comedi_cmd *cmd)
2247 {
2248         /*  supposed to load counter with desired divisor minus 3 */
2249         return cmd->convert_arg / TIMER_BASE - 3;
2250 }
2251
2252 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2253                                      struct comedi_cmd *cmd)
2254 {
2255         uint32_t count;
2256
2257         /*  figure out how long we need to delay at end of scan */
2258         switch (cmd->scan_begin_src) {
2259         case TRIG_TIMER:
2260                 count = (cmd->scan_begin_arg -
2261                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2262                         TIMER_BASE;
2263                 break;
2264         case TRIG_FOLLOW:
2265                 count = cmd->convert_arg / TIMER_BASE;
2266                 break;
2267         default:
2268                 return 0;
2269                 break;
2270         }
2271         return count - 3;
2272 }
2273
2274 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2275                                         struct comedi_cmd *cmd)
2276 {
2277         struct pcidas64_private *devpriv = dev->private;
2278         unsigned int divisor;
2279
2280         switch (cmd->scan_begin_src) {
2281         case TRIG_TIMER:
2282                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2283                 break;
2284         case TRIG_OTHER:
2285                 divisor = devpriv->ext_clock.divisor;
2286                 break;
2287         default:                /*  should never happen */
2288                 comedi_error(dev, "bug! failed to set ai pacing!");
2289                 divisor = 1000;
2290                 break;
2291         }
2292
2293         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2294         return divisor - 2;
2295 }
2296
2297 static void select_master_clock_4020(struct comedi_device *dev,
2298                                      const struct comedi_cmd *cmd)
2299 {
2300         struct pcidas64_private *devpriv = dev->private;
2301
2302         /*  select internal/external master clock */
2303         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2304         if (cmd->scan_begin_src == TRIG_OTHER) {
2305                 int chanspec = devpriv->ext_clock.chanspec;
2306
2307                 if (CR_CHAN(chanspec))
2308                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2309                 else
2310                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2311         } else {
2312                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2313         }
2314         writew(devpriv->hw_config_bits,
2315                devpriv->main_iobase + HW_CONFIG_REG);
2316 }
2317
2318 static void select_master_clock(struct comedi_device *dev,
2319                                 const struct comedi_cmd *cmd)
2320 {
2321         const struct pcidas64_board *thisboard = comedi_board(dev);
2322
2323         switch (thisboard->layout) {
2324         case LAYOUT_4020:
2325                 select_master_clock_4020(dev, cmd);
2326                 break;
2327         default:
2328                 break;
2329         }
2330 }
2331
2332 static inline void dma_start_sync(struct comedi_device *dev,
2333                                   unsigned int channel)
2334 {
2335         struct pcidas64_private *devpriv = dev->private;
2336         unsigned long flags;
2337
2338         /*  spinlock for plx dma control/status reg */
2339         spin_lock_irqsave(&dev->spinlock, flags);
2340         if (channel)
2341                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2342                        PLX_CLEAR_DMA_INTR_BIT,
2343                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2344         else
2345                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2346                        PLX_CLEAR_DMA_INTR_BIT,
2347                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2348         spin_unlock_irqrestore(&dev->spinlock, flags);
2349 }
2350
2351 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2352 {
2353         const struct pcidas64_board *thisboard = comedi_board(dev);
2354         struct pcidas64_private *devpriv = dev->private;
2355         uint32_t convert_counter = 0, scan_counter = 0;
2356
2357         check_adc_timing(dev, cmd);
2358
2359         select_master_clock(dev, cmd);
2360
2361         if (thisboard->layout == LAYOUT_4020) {
2362                 convert_counter = ai_convert_counter_4020(dev, cmd);
2363         } else {
2364                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2365                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2366         }
2367
2368         /*  load lower 16 bits of convert interval */
2369         writew(convert_counter & 0xffff,
2370                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2371         DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2372         /*  load upper 8 bits of convert interval */
2373         writew((convert_counter >> 16) & 0xff,
2374                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2375         /*  load lower 16 bits of scan delay */
2376         writew(scan_counter & 0xffff,
2377                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2378         /*  load upper 8 bits of scan delay */
2379         writew((scan_counter >> 16) & 0xff,
2380                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2381         DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2382 }
2383
2384 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2385 {
2386         int i;
2387
2388         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2389                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2390                     CR_CHAN(cmd->chanlist[i]) + 1)
2391                         return 0;
2392                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2393                     CR_RANGE(cmd->chanlist[i]))
2394                         return 0;
2395                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2396                         return 0;
2397         }
2398         return 1;
2399 }
2400
2401 static int setup_channel_queue(struct comedi_device *dev,
2402                                const struct comedi_cmd *cmd)
2403 {
2404         const struct pcidas64_board *thisboard = comedi_board(dev);
2405         struct pcidas64_private *devpriv = dev->private;
2406         unsigned short bits;
2407         int i;
2408
2409         if (thisboard->layout != LAYOUT_4020) {
2410                 if (use_internal_queue_6xxx(cmd)) {
2411                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2412                         writew(devpriv->hw_config_bits,
2413                                devpriv->main_iobase + HW_CONFIG_REG);
2414                         bits = 0;
2415                         /*  set channel */
2416                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2417                         /*  set gain */
2418                         bits |= ai_range_bits_6xxx(dev,
2419                                                    CR_RANGE(cmd->chanlist[0]));
2420                         /*  set single-ended / differential */
2421                         bits |= se_diff_bit_6xxx(dev,
2422                                                  CR_AREF(cmd->chanlist[0]) ==
2423                                                  AREF_DIFF);
2424                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2425                                 bits |= ADC_COMMON_BIT;
2426                         /*  set stop channel */
2427                         writew(adc_chan_bits
2428                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2429                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2430                         /*  set start channel, and rest of settings */
2431                         writew(bits,
2432                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2433                 } else {
2434                         /*  use external queue */
2435                         if (dev->write_subdev && dev->write_subdev->busy) {
2436                                 warn_external_queue(dev);
2437                                 return -EBUSY;
2438                         }
2439                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2440                         writew(devpriv->hw_config_bits,
2441                                devpriv->main_iobase + HW_CONFIG_REG);
2442                         /*  clear DAC buffer to prevent weird interactions */
2443                         writew(0,
2444                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2445                         /*  clear queue pointer */
2446                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2447                         /*  load external queue */
2448                         for (i = 0; i < cmd->chanlist_len; i++) {
2449                                 bits = 0;
2450                                 /*  set channel */
2451                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2452                                                               chanlist[i]));
2453                                 /*  set gain */
2454                                 bits |= ai_range_bits_6xxx(dev,
2455                                                            CR_RANGE(cmd->
2456                                                                     chanlist
2457                                                                     [i]));
2458                                 /*  set single-ended / differential */
2459                                 bits |= se_diff_bit_6xxx(dev,
2460                                                          CR_AREF(cmd->
2461                                                                  chanlist[i]) ==
2462                                                          AREF_DIFF);
2463                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2464                                         bits |= ADC_COMMON_BIT;
2465                                 /*  mark end of queue */
2466                                 if (i == cmd->chanlist_len - 1)
2467                                         bits |= QUEUE_EOSCAN_BIT |
2468                                                 QUEUE_EOSEQ_BIT;
2469                                 writew(bits,
2470                                        devpriv->main_iobase +
2471                                        ADC_QUEUE_FIFO_REG);
2472                                 DEBUG_PRINT(
2473                                             "wrote 0x%x to external channel queue\n",
2474                                             bits);
2475                         }
2476                         /* doing a queue clear is not specified in board docs,
2477                          * but required for reliable operation */
2478                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2479                         /*  prime queue holding register */
2480                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2481                 }
2482         } else {
2483                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2484
2485                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2486                 /* select BNC inputs */
2487                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2488                 /*  select ranges */
2489                 for (i = 0; i < cmd->chanlist_len; i++) {
2490                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2491                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2492
2493                         if (range == 0)
2494                                 devpriv->i2c_cal_range_bits |=
2495                                         attenuate_bit(channel);
2496                         else
2497                                 devpriv->i2c_cal_range_bits &=
2498                                         ~attenuate_bit(channel);
2499                 }
2500                 /*  update calibration/range i2c register only if necessary,
2501                  *  as it is very slow */
2502                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2503                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2504                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2505                                   sizeof(i2c_data));
2506                 }
2507         }
2508         return 0;
2509 }
2510
2511 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2512                                              unsigned int dma_channel,
2513                                              unsigned int descriptor_bits)
2514 {
2515         struct pcidas64_private *devpriv = dev->private;
2516
2517         /* The transfer size, pci address, and local address registers
2518          * are supposedly unused during chained dma,
2519          * but I have found that left over values from last operation
2520          * occasionally cause problems with transfer of first dma
2521          * block.  Initializing them to zero seems to fix the problem. */
2522         if (dma_channel) {
2523                 writel(0,
2524                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2525                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2526                 writel(0,
2527                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2528                 writel(descriptor_bits,
2529                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2530         } else {
2531                 writel(0,
2532                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2533                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2534                 writel(0,
2535                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2536                 writel(descriptor_bits,
2537                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2538         }
2539 }
2540
2541 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2542 {
2543         const struct pcidas64_board *thisboard = comedi_board(dev);
2544         struct pcidas64_private *devpriv = dev->private;
2545         struct comedi_async *async = s->async;
2546         struct comedi_cmd *cmd = &async->cmd;
2547         uint32_t bits;
2548         unsigned int i;
2549         unsigned long flags;
2550         int retval;
2551
2552         disable_ai_pacing(dev);
2553         abort_dma(dev, 1);
2554
2555         retval = setup_channel_queue(dev, cmd);
2556         if (retval < 0)
2557                 return retval;
2558
2559         /*  make sure internal calibration source is turned off */
2560         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2561
2562         set_ai_pacing(dev, cmd);
2563
2564         setup_sample_counters(dev, cmd);
2565
2566         enable_ai_interrupts(dev, cmd);
2567
2568         spin_lock_irqsave(&dev->spinlock, flags);
2569         /* set mode, allow conversions through software gate */
2570         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2571         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2572         if (thisboard->layout != LAYOUT_4020) {
2573                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2574                 if (cmd->convert_src == TRIG_EXT)
2575                         /*  good old mode 13 */
2576                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2577                 else
2578                         /*  mode 8.  What else could you need? */
2579                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2580         } else {
2581                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2582                 if (cmd->chanlist_len == 4)
2583                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2584                 else if (cmd->chanlist_len == 2)
2585                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2586                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2587                 devpriv->adc_control1_bits |=
2588                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2589                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2590                 devpriv->adc_control1_bits |=
2591                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2592                                                       [cmd->chanlist_len - 1]));
2593         }
2594         writew(devpriv->adc_control1_bits,
2595                devpriv->main_iobase + ADC_CONTROL1_REG);
2596         DEBUG_PRINT("control1 bits 0x%x\n", devpriv->adc_control1_bits);
2597         spin_unlock_irqrestore(&dev->spinlock, flags);
2598
2599         /*  clear adc buffer */
2600         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2601
2602         if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2603             thisboard->layout == LAYOUT_4020) {
2604                 devpriv->ai_dma_index = 0;
2605
2606                 /*  set dma transfer size */
2607                 for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2608                         devpriv->ai_dma_desc[i].transfer_size =
2609                                 cpu_to_le32(dma_transfer_size(dev) *
2610                                             sizeof(uint16_t));
2611
2612                 /*  give location of first dma descriptor */
2613                 load_first_dma_descriptor(dev, 1,
2614                                           devpriv->ai_dma_desc_bus_addr |
2615                                           PLX_DESC_IN_PCI_BIT |
2616                                           PLX_INTR_TERM_COUNT |
2617                                           PLX_XFER_LOCAL_TO_PCI);
2618
2619                 dma_start_sync(dev, 1);
2620         }
2621
2622         if (thisboard->layout == LAYOUT_4020) {
2623                 /* set source for external triggers */
2624                 bits = 0;
2625                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2626                         bits |= EXT_START_TRIG_BNC_BIT;
2627                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2628                         bits |= EXT_STOP_TRIG_BNC_BIT;
2629                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2630         }
2631
2632         spin_lock_irqsave(&dev->spinlock, flags);
2633
2634         /* enable pacing, triggering, etc */
2635         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2636         if (cmd->flags & TRIG_WAKE_EOS)
2637                 bits |= ADC_DMA_DISABLE_BIT;
2638         /*  set start trigger */
2639         if (cmd->start_src == TRIG_EXT) {
2640                 bits |= ADC_START_TRIG_EXT_BITS;
2641                 if (cmd->start_arg & CR_INVERT)
2642                         bits |= ADC_START_TRIG_FALLING_BIT;
2643         } else if (cmd->start_src == TRIG_NOW)
2644                 bits |= ADC_START_TRIG_SOFT_BITS;
2645         if (use_hw_sample_counter(cmd))
2646                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2647         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2648         DEBUG_PRINT("control0 bits 0x%x\n", bits);
2649
2650         devpriv->ai_cmd_running = 1;
2651
2652         spin_unlock_irqrestore(&dev->spinlock, flags);
2653
2654         /*  start acquisition */
2655         if (cmd->start_src == TRIG_NOW) {
2656                 writew(0, devpriv->main_iobase + ADC_START_REG);
2657                 DEBUG_PRINT("soft trig\n");
2658         }
2659
2660         return 0;
2661 }
2662
2663 /* read num_samples from 16 bit wide ai fifo */
2664 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2665 {
2666         struct pcidas64_private *devpriv = dev->private;
2667         struct comedi_subdevice *s = dev->read_subdev;
2668         struct comedi_async *async = s->async;
2669         struct comedi_cmd *cmd = &async->cmd;
2670         unsigned int i;
2671         uint16_t prepost_bits;
2672         int read_segment, read_index, write_segment, write_index;
2673         int num_samples;
2674
2675         do {
2676                 /*  get least significant 15 bits */
2677                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2678                              0x7fff;
2679                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2680                               0x7fff;
2681                 /* Get most significant bits (grey code).
2682                  * Different boards use different code so use a scheme
2683                  * that doesn't depend on encoding.  This read must
2684                  * occur after reading least significant 15 bits to avoid race
2685                  * with fifo switching to next segment. */
2686                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2687
2688                 /* if read and write pointers are not on the same fifo segment,
2689                  * read to the end of the read segment */
2690                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2691                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2692
2693                 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2694                             read_segment, write_segment, read_index,
2695                             write_index);
2696
2697                 if (read_segment != write_segment)
2698                         num_samples =
2699                                 devpriv->ai_fifo_segment_length - read_index;
2700                 else
2701                         num_samples = write_index - read_index;
2702
2703                 if (cmd->stop_src == TRIG_COUNT) {
2704                         if (devpriv->ai_count == 0)
2705                                 break;
2706                         if (num_samples > devpriv->ai_count)
2707                                 num_samples = devpriv->ai_count;
2708
2709                         devpriv->ai_count -= num_samples;
2710                 }
2711
2712                 if (num_samples < 0) {
2713                         dev_err(dev->class_dev,
2714                                 "cb_pcidas64: bug! num_samples < 0\n");
2715                         break;
2716                 }
2717
2718                 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2719
2720                 for (i = 0; i < num_samples; i++) {
2721                         cfc_write_to_buffer(s,
2722                                             readw(devpriv->main_iobase +
2723                                                   ADC_FIFO_REG));
2724                 }
2725
2726         } while (read_segment != write_segment);
2727 }
2728
2729 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2730  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2731  * supports the use of pio for draining the last remaining points from the
2732  * fifo when a data acquisition operation has completed).
2733  */
2734 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2735 {
2736         struct pcidas64_private *devpriv = dev->private;
2737         struct comedi_subdevice *s = dev->read_subdev;
2738         struct comedi_async *async = s->async;
2739         struct comedi_cmd *cmd = &async->cmd;
2740         unsigned int i;
2741         unsigned int max_transfer = 100000;
2742         uint32_t fifo_data;
2743         int write_code =
2744                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2745         int read_code =
2746                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2747
2748         if (cmd->stop_src == TRIG_COUNT) {
2749                 if (max_transfer > devpriv->ai_count)
2750                         max_transfer = devpriv->ai_count;
2751
2752         }
2753         for (i = 0; read_code != write_code && i < max_transfer;) {
2754                 fifo_data = readl(devpriv->dio_counter_iobase + ADC_FIFO_REG);
2755                 cfc_write_to_buffer(s, fifo_data & 0xffff);
2756                 i++;
2757                 if (i < max_transfer) {
2758                         cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2759                         i++;
2760                 }
2761                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2762                             0x7fff;
2763         }
2764         devpriv->ai_count -= i;
2765 }
2766
2767 /* empty fifo */
2768 static void pio_drain_ai_fifo(struct comedi_device *dev)
2769 {
2770         const struct pcidas64_board *thisboard = comedi_board(dev);
2771
2772         if (thisboard->layout == LAYOUT_4020)
2773                 pio_drain_ai_fifo_32(dev);
2774         else
2775                 pio_drain_ai_fifo_16(dev);
2776 }
2777
2778 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2779 {
2780         const struct pcidas64_board *thisboard = comedi_board(dev);
2781         struct pcidas64_private *devpriv = dev->private;
2782         struct comedi_async *async = dev->read_subdev->async;
2783         uint32_t next_transfer_addr;
2784         int j;
2785         int num_samples = 0;
2786         void __iomem *pci_addr_reg;
2787
2788         if (channel)
2789                 pci_addr_reg =
2790                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2791         else
2792                 pci_addr_reg =
2793                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2794
2795         /*  loop until we have read all the full buffers */
2796         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2797              (next_transfer_addr <
2798               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2799               next_transfer_addr >=
2800               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2801               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2802                 /*  transfer data from dma buffer to comedi buffer */
2803                 num_samples = dma_transfer_size(dev);
2804                 if (async->cmd.stop_src == TRIG_COUNT) {
2805                         if (num_samples > devpriv->ai_count)
2806                                 num_samples = devpriv->ai_count;
2807                         devpriv->ai_count -= num_samples;
2808                 }
2809                 cfc_write_array_to_buffer(dev->read_subdev,
2810                                           devpriv->ai_buffer[devpriv->
2811                                                              ai_dma_index],
2812                                           num_samples * sizeof(uint16_t));
2813                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2814                                         ai_dma_ring_count(thisboard);
2815
2816                 DEBUG_PRINT("next buffer addr 0x%lx\n",
2817                             (unsigned long)devpriv->
2818                             ai_buffer_bus_addr[devpriv->ai_dma_index]);
2819                 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2820         }
2821         /* XXX check for dma ring buffer overrun
2822          * (use end-of-chain bit to mark last unused buffer) */
2823 }
2824
2825 static void handle_ai_interrupt(struct comedi_device *dev,
2826                                 unsigned short status,
2827                                 unsigned int plx_status)
2828 {
2829         const struct pcidas64_board *thisboard = comedi_board(dev);
2830         struct pcidas64_private *devpriv = dev->private;
2831         struct comedi_subdevice *s = dev->read_subdev;
2832         struct comedi_async *async = s->async;
2833         struct comedi_cmd *cmd = &async->cmd;
2834         uint8_t dma1_status;
2835         unsigned long flags;
2836
2837         /*  check for fifo overrun */
2838         if (status & ADC_OVERRUN_BIT) {
2839                 comedi_error(dev, "fifo overrun");
2840                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2841         }
2842         /*  spin lock makes sure no one else changes plx dma control reg */
2843         spin_lock_irqsave(&dev->spinlock, flags);
2844         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2845         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2846                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2847                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2848                 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2849
2850                 if (dma1_status & PLX_DMA_EN_BIT)
2851                         drain_dma_buffers(dev, 1);
2852
2853                 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2854         }
2855         spin_unlock_irqrestore(&dev->spinlock, flags);
2856
2857         if (status & ADC_DONE_BIT)
2858                 DEBUG_PRINT("adc done interrupt\n");
2859
2860         /*  drain fifo with pio */
2861         if ((status & ADC_DONE_BIT) ||
2862             ((cmd->flags & TRIG_WAKE_EOS) &&
2863              (status & ADC_INTR_PENDING_BIT) &&
2864              (thisboard->layout != LAYOUT_4020))) {
2865                 DEBUG_PRINT("pio fifo drain\n");
2866                 spin_lock_irqsave(&dev->spinlock, flags);
2867                 if (devpriv->ai_cmd_running) {
2868                         spin_unlock_irqrestore(&dev->spinlock, flags);
2869                         pio_drain_ai_fifo(dev);
2870                 } else
2871                         spin_unlock_irqrestore(&dev->spinlock, flags);
2872         }
2873         /*  if we are have all the data, then quit */
2874         if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2875             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2876                 async->events |= COMEDI_CB_EOA;
2877         }
2878
2879         cfc_handle_events(dev, s);
2880 }
2881
2882 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2883 {
2884         struct pcidas64_private *devpriv = dev->private;
2885         unsigned int buffer_index;
2886
2887         if (devpriv->ao_dma_index == 0)
2888                 buffer_index = AO_DMA_RING_COUNT - 1;
2889         else
2890                 buffer_index = devpriv->ao_dma_index - 1;
2891         return buffer_index;
2892 }
2893
2894 static int last_ao_dma_load_completed(struct comedi_device *dev)
2895 {
2896         struct pcidas64_private *devpriv = dev->private;
2897         unsigned int buffer_index;
2898         unsigned int transfer_address;
2899         unsigned short dma_status;
2900
2901         buffer_index = prev_ao_dma_index(dev);
2902         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2903         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2904                 return 0;
2905
2906         transfer_address =
2907                 readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2908         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2909                 return 0;
2910
2911         return 1;
2912 }
2913
2914 static int ao_stopped_by_error(struct comedi_device *dev,
2915                                const struct comedi_cmd *cmd)
2916 {
2917         struct pcidas64_private *devpriv = dev->private;
2918
2919         if (cmd->stop_src == TRIG_NONE)
2920                 return 1;
2921         if (cmd->stop_src == TRIG_COUNT) {
2922                 if (devpriv->ao_count)
2923                         return 1;
2924                 if (last_ao_dma_load_completed(dev) == 0)
2925                         return 1;
2926         }
2927         return 0;
2928 }
2929
2930 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2931                                        unsigned short dma_status)
2932 {
2933         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2934             (dma_status & PLX_DMA_EN_BIT) == 0)
2935                 return 0;
2936         if (last_ao_dma_load_completed(dev))
2937                 return 0;
2938
2939         return 1;
2940 }
2941
2942 static void restart_ao_dma(struct comedi_device *dev)
2943 {
2944         struct pcidas64_private *devpriv = dev->private;
2945         unsigned int dma_desc_bits;
2946
2947         dma_desc_bits =
2948                 readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2949         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2950         DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
2951         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2952
2953         dma_start_sync(dev, 0);
2954 }
2955
2956 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2957                                        const struct comedi_cmd *cmd)
2958 {
2959         struct pcidas64_private *devpriv = dev->private;
2960         unsigned int num_bytes, buffer_index, prev_buffer_index;
2961         unsigned int next_bits;
2962
2963         buffer_index = devpriv->ao_dma_index;
2964         prev_buffer_index = prev_ao_dma_index(dev);
2965
2966         DEBUG_PRINT("attempting to load ao buffer %i (0x%llx)\n", buffer_index,
2967                     (unsigned long long)devpriv->ao_buffer_bus_addr[
2968                                                                 buffer_index]);
2969
2970         num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
2971         if (num_bytes > DMA_BUFFER_SIZE)
2972                 num_bytes = DMA_BUFFER_SIZE;
2973         if (cmd->stop_src == TRIG_COUNT && num_bytes > devpriv->ao_count)
2974                 num_bytes = devpriv->ao_count;
2975         num_bytes -= num_bytes % bytes_in_sample;
2976
2977         if (num_bytes == 0)
2978                 return 0;
2979
2980         DEBUG_PRINT("loading %i bytes\n", num_bytes);
2981
2982         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
2983                                                devpriv->
2984                                                ao_buffer[buffer_index],
2985                                                num_bytes);
2986         devpriv->ao_dma_desc[buffer_index].transfer_size =
2987                 cpu_to_le32(num_bytes);
2988         /* set end of chain bit so we catch underruns */
2989         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2990         next_bits |= PLX_END_OF_CHAIN_BIT;
2991         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2992         /* clear end of chain bit on previous buffer now that we have set it
2993          * for the last buffer */
2994         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2995         next_bits &= ~PLX_END_OF_CHAIN_BIT;
2996         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2997
2998         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2999         devpriv->ao_count -= num_bytes;
3000
3001         return num_bytes;
3002 }
3003
3004 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3005 {
3006         struct pcidas64_private *devpriv = dev->private;
3007         unsigned int num_bytes;
3008         unsigned int next_transfer_addr;
3009         void __iomem *pci_addr_reg =
3010                 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3011         unsigned int buffer_index;
3012
3013         do {
3014                 buffer_index = devpriv->ao_dma_index;
3015                 /* don't overwrite data that hasn't been transferred yet */
3016                 next_transfer_addr = readl(pci_addr_reg);
3017                 if (next_transfer_addr >=
3018                     devpriv->ao_buffer_bus_addr[buffer_index] &&
3019                     next_transfer_addr <
3020                     devpriv->ao_buffer_bus_addr[buffer_index] +
3021                     DMA_BUFFER_SIZE)
3022                         return;
3023                 num_bytes = load_ao_dma_buffer(dev, cmd);
3024         } while (num_bytes >= DMA_BUFFER_SIZE);
3025 }
3026
3027 static void handle_ao_interrupt(struct comedi_device *dev,
3028                                 unsigned short status, unsigned int plx_status)
3029 {
3030         struct pcidas64_private *devpriv = dev->private;
3031         struct comedi_subdevice *s = dev->write_subdev;
3032         struct comedi_async *async;
3033         struct comedi_cmd *cmd;
3034         uint8_t dma0_status;
3035         unsigned long flags;
3036
3037         /* board might not support ao, in which case write_subdev is NULL */
3038         if (s == NULL)
3039                 return;
3040         async = s->async;
3041         cmd = &async->cmd;
3042
3043         /*  spin lock makes sure no one else changes plx dma control reg */
3044         spin_lock_irqsave(&dev->spinlock, flags);
3045         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3046         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
3047                 if ((dma0_status & PLX_DMA_EN_BIT) &&
3048                     !(dma0_status & PLX_DMA_DONE_BIT))
3049                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3050                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3051                 else
3052                         writeb(PLX_CLEAR_DMA_INTR_BIT,
3053                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3054                 spin_unlock_irqrestore(&dev->spinlock, flags);
3055                 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3056                 if (dma0_status & PLX_DMA_EN_BIT) {
3057                         load_ao_dma(dev, cmd);
3058                         /* try to recover from dma end-of-chain event */
3059                         if (ao_dma_needs_restart(dev, dma0_status))
3060                                 restart_ao_dma(dev);
3061                 }
3062                 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3063         } else {
3064                 spin_unlock_irqrestore(&dev->spinlock, flags);
3065         }
3066
3067         if ((status & DAC_DONE_BIT)) {
3068                 async->events |= COMEDI_CB_EOA;
3069                 if (ao_stopped_by_error(dev, cmd))
3070                         async->events |= COMEDI_CB_ERROR;
3071                 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3072                             readl(devpriv->plx9080_iobase +
3073                                   PLX_DMA0_DESCRIPTOR_REG));
3074                 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3075                             readl(devpriv->plx9080_iobase +
3076                                   PLX_DMA0_PCI_ADDRESS_REG));
3077         }
3078         cfc_handle_events(dev, s);
3079 }
3080
3081 static irqreturn_t handle_interrupt(int irq, void *d)
3082 {
3083         struct comedi_device *dev = d;
3084         struct pcidas64_private *devpriv = dev->private;
3085         unsigned short status;
3086         uint32_t plx_status;
3087         uint32_t plx_bits;
3088
3089         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3090         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3091
3092         DEBUG_PRINT("hw status 0x%x, plx status 0x%x\n", status, plx_status);
3093
3094         /* an interrupt before all the postconfig stuff gets done could
3095          * cause a NULL dereference if we continue through the
3096          * interrupt handler */
3097         if (!dev->attached) {
3098                 DEBUG_PRINT("premature interrupt, ignoring\n");
3099                 return IRQ_HANDLED;
3100         }
3101         handle_ai_interrupt(dev, status, plx_status);
3102         handle_ao_interrupt(dev, status, plx_status);
3103
3104         /*  clear possible plx9080 interrupt sources */
3105         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3106                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3107                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3108                 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3109         }
3110
3111         DEBUG_PRINT("exiting handler\n");
3112
3113         return IRQ_HANDLED;
3114 }
3115
3116 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3117 {
3118         struct pcidas64_private *devpriv = dev->private;
3119         unsigned long flags;
3120
3121         spin_lock_irqsave(&dev->spinlock, flags);
3122         if (devpriv->ai_cmd_running == 0) {
3123                 spin_unlock_irqrestore(&dev->spinlock, flags);
3124                 return 0;
3125         }
3126         devpriv->ai_cmd_running = 0;
3127         spin_unlock_irqrestore(&dev->spinlock, flags);
3128
3129         disable_ai_pacing(dev);
3130
3131         abort_dma(dev, 1);
3132
3133         DEBUG_PRINT("ai canceled\n");
3134         return 0;
3135 }
3136
3137 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3138                     struct comedi_insn *insn, unsigned int *data)
3139 {
3140         const struct pcidas64_board *thisboard = comedi_board(dev);
3141         struct pcidas64_private *devpriv = dev->private;
3142         int chan = CR_CHAN(insn->chanspec);
3143         int range = CR_RANGE(insn->chanspec);
3144
3145         /*  do some initializing */
3146         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3147
3148         /*  set range */
3149         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3150         writew(devpriv->dac_control1_bits,
3151                devpriv->main_iobase + DAC_CONTROL1_REG);
3152
3153         /*  write to channel */
3154         if (thisboard->layout == LAYOUT_4020) {
3155                 writew(data[0] & 0xff,
3156                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3157                 writew((data[0] >> 8) & 0xf,
3158                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3159         } else {
3160                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3161         }
3162
3163         /*  remember output value */
3164         devpriv->ao_value[chan] = data[0];
3165
3166         return 1;
3167 }
3168
3169 static int ao_readback_insn(struct comedi_device *dev,
3170                             struct comedi_subdevice *s,
3171                             struct comedi_insn *insn, unsigned int *data)
3172 {
3173         struct pcidas64_private *devpriv = dev->private;
3174
3175         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
3176
3177         return 1;
3178 }
3179
3180 static void set_dac_control0_reg(struct comedi_device *dev,
3181                                  const struct comedi_cmd *cmd)
3182 {
3183         struct pcidas64_private *devpriv = dev->private;
3184         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3185                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3186
3187         if (cmd->start_src == TRIG_EXT) {
3188                 bits |= WAVEFORM_TRIG_EXT_BITS;
3189                 if (cmd->start_arg & CR_INVERT)
3190                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3191         } else {
3192                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3193         }
3194         if (cmd->scan_begin_src == TRIG_EXT) {
3195                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3196                 if (cmd->scan_begin_arg & CR_INVERT)
3197                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3198         }
3199         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3200 }
3201
3202 static void set_dac_control1_reg(struct comedi_device *dev,
3203                                  const struct comedi_cmd *cmd)
3204 {
3205         struct pcidas64_private *devpriv = dev->private;
3206         int i;
3207
3208         for (i = 0; i < cmd->chanlist_len; i++) {
3209                 int channel, range;
3210
3211                 channel = CR_CHAN(cmd->chanlist[i]);
3212                 range = CR_RANGE(cmd->chanlist[i]);
3213                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3214                                    range);
3215         }
3216         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3217         writew(devpriv->dac_control1_bits,
3218                devpriv->main_iobase + DAC_CONTROL1_REG);
3219 }
3220
3221 static void set_dac_select_reg(struct comedi_device *dev,
3222                                const struct comedi_cmd *cmd)
3223 {
3224         struct pcidas64_private *devpriv = dev->private;
3225         uint16_t bits;
3226         unsigned int first_channel, last_channel;
3227
3228         first_channel = CR_CHAN(cmd->chanlist[0]);
3229         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3230         if (last_channel < first_channel)
3231                 comedi_error(dev, "bug! last ao channel < first ao channel");
3232
3233         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3234
3235         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3236 }
3237
3238 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3239 {
3240         return get_divisor(ns, flags) - 2;
3241 }
3242
3243 static void set_dac_interval_regs(struct comedi_device *dev,
3244                                   const struct comedi_cmd *cmd)
3245 {
3246         struct pcidas64_private *devpriv = dev->private;
3247         unsigned int divisor;
3248
3249         if (cmd->scan_begin_src != TRIG_TIMER)
3250                 return;
3251
3252         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3253         if (divisor > max_counter_value) {
3254                 comedi_error(dev, "bug! ao divisor too big");
3255                 divisor = max_counter_value;
3256         }
3257         writew(divisor & 0xffff,
3258                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3259         writew((divisor >> 16) & 0xff,
3260                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3261 }
3262
3263 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3264 {
3265         struct pcidas64_private *devpriv = dev->private;
3266         unsigned int num_bytes;
3267         int i;
3268
3269         /* clear queue pointer too, since external queue has
3270          * weird interactions with ao fifo */
3271         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3272         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3273
3274         num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3275         if (cmd->stop_src == TRIG_COUNT &&
3276             num_bytes / bytes_in_sample > devpriv->ao_count)
3277                 num_bytes = devpriv->ao_count * bytes_in_sample;
3278         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3279                                                devpriv->ao_bounce_buffer,
3280                                                num_bytes);
3281         for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3282                 writew(devpriv->ao_bounce_buffer[i],
3283                        devpriv->main_iobase + DAC_FIFO_REG);
3284         }
3285         devpriv->ao_count -= num_bytes / bytes_in_sample;
3286         if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3287                 return 0;
3288         num_bytes = load_ao_dma_buffer(dev, cmd);
3289         if (num_bytes == 0)
3290                 return -1;
3291         load_ao_dma(dev, cmd);
3292
3293         dma_start_sync(dev, 0);
3294
3295         return 0;
3296 }
3297
3298 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3299 {
3300         const struct pcidas64_board *thisboard = comedi_board(dev);
3301
3302         if (dev->read_subdev->busy)
3303                 return 0;
3304         if (thisboard->layout == LAYOUT_4020)
3305                 return 0;
3306         else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3307                 return 0;
3308         return 1;
3309 }
3310
3311 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3312                       unsigned int trig_num)
3313 {
3314         struct pcidas64_private *devpriv = dev->private;
3315         struct comedi_cmd *cmd = &s->async->cmd;
3316         int retval;
3317
3318         if (trig_num != 0)
3319                 return -EINVAL;
3320
3321         retval = prep_ao_dma(dev, cmd);
3322         if (retval < 0)
3323                 return -EPIPE;
3324
3325         set_dac_control0_reg(dev, cmd);
3326
3327         if (cmd->start_src == TRIG_INT)
3328                 writew(0, devpriv->main_iobase + DAC_START_REG);
3329
3330         s->async->inttrig = NULL;
3331
3332         return 0;
3333 }
3334
3335 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3336 {
3337         struct pcidas64_private *devpriv = dev->private;
3338         struct comedi_cmd *cmd = &s->async->cmd;
3339
3340         if (external_ai_queue_in_use(dev)) {
3341                 warn_external_queue(dev);
3342                 return -EBUSY;
3343         }
3344         /* disable analog output system during setup */
3345         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3346
3347         devpriv->ao_dma_index = 0;
3348         devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3349
3350         set_dac_select_reg(dev, cmd);
3351         set_dac_interval_regs(dev, cmd);
3352         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3353                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3354
3355         set_dac_control1_reg(dev, cmd);
3356         s->async->inttrig = ao_inttrig;
3357
3358         return 0;
3359 }
3360
3361 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3362                       struct comedi_cmd *cmd)
3363 {
3364         const struct pcidas64_board *thisboard = comedi_board(dev);
3365         int err = 0;
3366         unsigned int tmp_arg;
3367         int i;
3368
3369         /* Step 1 : check if triggers are trivially valid */
3370
3371         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3372         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3373                                      TRIG_TIMER | TRIG_EXT);
3374         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3375         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3376         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3377
3378         if (err)
3379                 return 1;
3380
3381         /* Step 2a : make sure trigger sources are unique */
3382
3383         err |= cfc_check_trigger_is_unique(cmd->start_src);
3384         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3385
3386         /* Step 2b : and mutually compatible */
3387
3388         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3389                 err |= -EINVAL;
3390         if (cmd->stop_src != TRIG_COUNT &&
3391             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3392                 err |= -EINVAL;
3393
3394         if (err)
3395                 return 2;
3396
3397         /* Step 3: check if arguments are trivially valid */
3398
3399         if (cmd->scan_begin_src == TRIG_TIMER) {
3400                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3401                                                  thisboard->ao_scan_speed);
3402                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3403                     max_counter_value) {
3404                         cmd->scan_begin_arg = (max_counter_value + 2) *
3405                                               TIMER_BASE;
3406                         err |= -EINVAL;
3407                 }
3408         }
3409
3410         err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3411         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3412
3413         if (err)
3414                 return 3;
3415
3416         /* step 4: fix up any arguments */
3417
3418         if (cmd->scan_begin_src == TRIG_TIMER) {
3419                 tmp_arg = cmd->scan_begin_arg;
3420                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3421                                                   cmd->flags) * TIMER_BASE;
3422                 if (tmp_arg != cmd->scan_begin_arg)
3423                         err++;
3424         }
3425
3426         if (err)
3427                 return 4;
3428
3429         if (cmd->chanlist) {
3430                 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3431                 for (i = 1; i < cmd->chanlist_len; i++) {
3432                         if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3433                                 comedi_error(dev,
3434                                              "chanlist must use consecutive channels");
3435                                 err++;
3436                                 break;
3437                         }
3438                 }
3439         }
3440
3441         if (err)
3442                 return 5;
3443
3444         return 0;
3445 }
3446
3447 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3448 {
3449         struct pcidas64_private *devpriv = dev->private;
3450
3451         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3452         abort_dma(dev, 0);
3453         return 0;
3454 }
3455
3456 static int dio_callback(int dir, int port, int data, unsigned long arg)
3457 {
3458         void __iomem *iobase = (void __iomem *)arg;
3459         if (dir) {
3460                 writeb(data, iobase + port);
3461                 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3462                 return 0;
3463         } else {
3464                 return readb(iobase + port);
3465         }
3466 }
3467
3468 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3469 {
3470         void __iomem *iobase = (void __iomem *)arg;
3471         if (dir) {
3472                 writew(data, iobase + 2 * port);
3473                 return 0;
3474         } else {
3475                 return readw(iobase + 2 * port);
3476         }
3477 }
3478
3479 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3480                     struct comedi_insn *insn, unsigned int *data)
3481 {
3482         struct pcidas64_private *devpriv = dev->private;
3483         unsigned int bits;
3484
3485         bits = readb(devpriv->dio_counter_iobase + DI_REG);
3486         bits &= 0xf;
3487         data[1] = bits;
3488         data[0] = 0;
3489
3490         return insn->n;
3491 }
3492
3493 static int do_wbits(struct comedi_device *dev,
3494                     struct comedi_subdevice *s,
3495                     struct comedi_insn *insn,
3496                     unsigned int *data)
3497 {
3498         struct pcidas64_private *devpriv = dev->private;
3499
3500         if (comedi_dio_update_state(s, data))
3501                 writeb(s->state, devpriv->dio_counter_iobase + DO_REG);
3502
3503         data[1] = s->state;
3504
3505         return insn->n;
3506 }
3507
3508 static int dio_60xx_config_insn(struct comedi_device *dev,
3509                                 struct comedi_subdevice *s,
3510                                 struct comedi_insn *insn,
3511                                 unsigned int *data)
3512 {
3513         struct pcidas64_private *devpriv = dev->private;
3514         int ret;
3515
3516         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3517         if (ret)
3518                 return ret;
3519
3520         writeb(s->io_bits,
3521                devpriv->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3522
3523         return insn->n;
3524 }
3525
3526 static int dio_60xx_wbits(struct comedi_device *dev,
3527                           struct comedi_subdevice *s,
3528                           struct comedi_insn *insn,
3529                           unsigned int *data)
3530 {
3531         struct pcidas64_private *devpriv = dev->private;
3532
3533         if (comedi_dio_update_state(s, data)) {
3534                 writeb(s->state,
3535                        devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3536         }
3537
3538         data[1] = readb(devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3539
3540         return insn->n;
3541 }
3542
3543 /* pci-6025 8800 caldac:
3544  * address 0 == dac channel 0 offset
3545  * address 1 == dac channel 0 gain
3546  * address 2 == dac channel 1 offset
3547  * address 3 == dac channel 1 gain
3548  * address 4 == fine adc offset
3549  * address 5 == coarse adc offset
3550  * address 6 == coarse adc gain
3551  * address 7 == fine adc gain
3552  */
3553 /* pci-6402/16 uses all 8 channels for dac:
3554  * address 0 == dac channel 0 fine gain
3555  * address 1 == dac channel 0 coarse gain
3556  * address 2 == dac channel 0 coarse offset
3557  * address 3 == dac channel 1 coarse offset
3558  * address 4 == dac channel 1 fine gain
3559  * address 5 == dac channel 1 coarse gain
3560  * address 6 == dac channel 0 fine offset
3561  * address 7 == dac channel 1 fine offset
3562 */
3563
3564 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3565                              uint8_t value)
3566 {
3567         struct pcidas64_private *devpriv = dev->private;
3568         static const int num_caldac_channels = 8;
3569         static const int bitstream_length = 11;
3570         unsigned int bitstream = ((address & 0x7) << 8) | value;
3571         unsigned int bit, register_bits;
3572         static const int caldac_8800_udelay = 1;
3573
3574         if (address >= num_caldac_channels) {
3575                 comedi_error(dev, "illegal caldac channel");
3576                 return -1;
3577         }
3578         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3579                 register_bits = 0;
3580                 if (bitstream & bit)
3581                         register_bits |= SERIAL_DATA_IN_BIT;
3582                 udelay(caldac_8800_udelay);
3583                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3584                 register_bits |= SERIAL_CLOCK_BIT;
3585                 udelay(caldac_8800_udelay);
3586                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3587         }
3588         udelay(caldac_8800_udelay);
3589         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3590         udelay(caldac_8800_udelay);
3591         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3592         udelay(caldac_8800_udelay);
3593         return 0;
3594 }
3595
3596 /* 4020 caldacs */
3597 static int caldac_i2c_write(struct comedi_device *dev,
3598                             unsigned int caldac_channel, unsigned int value)
3599 {
3600         uint8_t serial_bytes[3];
3601         uint8_t i2c_addr;
3602         enum pointer_bits {
3603                 /*  manual has gain and offset bits switched */
3604                 OFFSET_0_2 = 0x1,
3605                 GAIN_0_2 = 0x2,
3606                 OFFSET_1_3 = 0x4,
3607                 GAIN_1_3 = 0x8,
3608         };
3609         enum data_bits {
3610                 NOT_CLEAR_REGISTERS = 0x20,
3611         };
3612
3613         switch (caldac_channel) {
3614         case 0:         /*  chan 0 offset */
3615                 i2c_addr = CALDAC0_I2C_ADDR;
3616                 serial_bytes[0] = OFFSET_0_2;
3617                 break;
3618         case 1:         /*  chan 1 offset */
3619                 i2c_addr = CALDAC0_I2C_ADDR;
3620                 serial_bytes[0] = OFFSET_1_3;
3621                 break;
3622         case 2:         /*  chan 2 offset */
3623                 i2c_addr = CALDAC1_I2C_ADDR;
3624                 serial_bytes[0] = OFFSET_0_2;
3625                 break;
3626         case 3:         /*  chan 3 offset */
3627                 i2c_addr = CALDAC1_I2C_ADDR;
3628                 serial_bytes[0] = OFFSET_1_3;
3629                 break;
3630         case 4:         /*  chan 0 gain */
3631                 i2c_addr = CALDAC0_I2C_ADDR;
3632                 serial_bytes[0] = GAIN_0_2;
3633                 break;
3634         case 5:         /*  chan 1 gain */
3635                 i2c_addr = CALDAC0_I2C_ADDR;
3636                 serial_bytes[0] = GAIN_1_3;
3637                 break;
3638         case 6:         /*  chan 2 gain */
3639                 i2c_addr = CALDAC1_I2C_ADDR;
3640                 serial_bytes[0] = GAIN_0_2;
3641                 break;
3642         case 7:         /*  chan 3 gain */
3643                 i2c_addr = CALDAC1_I2C_ADDR;
3644                 serial_bytes[0] = GAIN_1_3;
3645                 break;
3646         default:
3647                 comedi_error(dev, "invalid caldac channel\n");
3648                 return -1;
3649                 break;
3650         }
3651         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3652         serial_bytes[2] = value & 0xff;
3653         i2c_write(dev, i2c_addr, serial_bytes, 3);
3654         return 0;
3655 }
3656
3657 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3658                          unsigned int value)
3659 {
3660         const struct pcidas64_board *thisboard = comedi_board(dev);
3661         struct pcidas64_private *devpriv = dev->private;
3662
3663         devpriv->caldac_state[channel] = value;
3664
3665         switch (thisboard->layout) {
3666         case LAYOUT_60XX:
3667         case LAYOUT_64XX:
3668                 caldac_8800_write(dev, channel, value);
3669                 break;
3670         case LAYOUT_4020:
3671                 caldac_i2c_write(dev, channel, value);
3672                 break;
3673         default:
3674                 break;
3675         }
3676 }
3677
3678 static int calib_write_insn(struct comedi_device *dev,
3679                             struct comedi_subdevice *s,
3680                             struct comedi_insn *insn, unsigned int *data)
3681 {
3682         struct pcidas64_private *devpriv = dev->private;
3683         int channel = CR_CHAN(insn->chanspec);
3684
3685         /* return immediately if setting hasn't changed, since
3686          * programming these things is slow */
3687         if (devpriv->caldac_state[channel] == data[0])
3688                 return 1;
3689
3690         caldac_write(dev, channel, data[0]);
3691
3692         return 1;
3693 }
3694
3695 static int calib_read_insn(struct comedi_device *dev,
3696                            struct comedi_subdevice *s, struct comedi_insn *insn,
3697                            unsigned int *data)
3698 {
3699         struct pcidas64_private *devpriv = dev->private;
3700         unsigned int channel = CR_CHAN(insn->chanspec);
3701
3702         data[0] = devpriv->caldac_state[channel];
3703
3704         return 1;
3705 }
3706
3707 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3708                          unsigned int value)
3709 {
3710         struct pcidas64_private *devpriv = dev->private;
3711         static const int bitstream_length = 10;
3712         unsigned int bit, register_bits;
3713         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3714         static const int ad8402_udelay = 1;
3715
3716         devpriv->ad8402_state[channel] = value;
3717
3718         register_bits = SELECT_8402_64XX_BIT;
3719         udelay(ad8402_udelay);
3720         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3721
3722         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3723                 if (bitstream & bit)
3724                         register_bits |= SERIAL_DATA_IN_BIT;
3725                 else
3726                         register_bits &= ~SERIAL_DATA_IN_BIT;
3727                 udelay(ad8402_udelay);
3728                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3729                 udelay(ad8402_udelay);
3730                 writew(register_bits | SERIAL_CLOCK_BIT,
3731                        devpriv->main_iobase + CALIBRATION_REG);
3732         }
3733
3734         udelay(ad8402_udelay);
3735         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3736 }
3737
3738 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3739 static int ad8402_write_insn(struct comedi_device *dev,
3740                              struct comedi_subdevice *s,
3741                              struct comedi_insn *insn, unsigned int *data)
3742 {
3743         struct pcidas64_private *devpriv = dev->private;
3744         int channel = CR_CHAN(insn->chanspec);
3745
3746         /* return immediately if setting hasn't changed, since
3747          * programming these things is slow */
3748         if (devpriv->ad8402_state[channel] == data[0])
3749                 return 1;
3750
3751         devpriv->ad8402_state[channel] = data[0];
3752
3753         ad8402_write(dev, channel, data[0]);
3754
3755         return 1;
3756 }
3757
3758 static int ad8402_read_insn(struct comedi_device *dev,
3759                             struct comedi_subdevice *s,
3760                             struct comedi_insn *insn, unsigned int *data)
3761 {
3762         struct pcidas64_private *devpriv = dev->private;
3763         unsigned int channel = CR_CHAN(insn->chanspec);
3764
3765         data[0] = devpriv->ad8402_state[channel];
3766
3767         return 1;
3768 }
3769
3770 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3771 {
3772         struct pcidas64_private *devpriv = dev->private;
3773         static const int bitstream_length = 11;
3774         static const int read_command = 0x6;
3775         unsigned int bitstream = (read_command << 8) | address;
3776         unsigned int bit;
3777         void __iomem * const plx_control_addr =
3778                 devpriv->plx9080_iobase + PLX_CONTROL_REG;
3779         uint16_t value;
3780         static const int value_length = 16;
3781         static const int eeprom_udelay = 1;
3782
3783         udelay(eeprom_udelay);
3784         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3785         /*  make sure we don't send anything to the i2c bus on 4020 */
3786         devpriv->plx_control_bits |= CTL_USERO;
3787         writel(devpriv->plx_control_bits, plx_control_addr);
3788         /*  activate serial eeprom */
3789         udelay(eeprom_udelay);
3790         devpriv->plx_control_bits |= CTL_EE_CS;
3791         writel(devpriv->plx_control_bits, plx_control_addr);
3792
3793         /*  write read command and desired memory address */
3794         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3795                 /*  set bit to be written */
3796                 udelay(eeprom_udelay);
3797                 if (bitstream & bit)
3798                         devpriv->plx_control_bits |= CTL_EE_W;
3799                 else
3800                         devpriv->plx_control_bits &= ~CTL_EE_W;
3801                 writel(devpriv->plx_control_bits, plx_control_addr);
3802                 /*  clock in bit */
3803                 udelay(eeprom_udelay);
3804                 devpriv->plx_control_bits |= CTL_EE_CLK;
3805                 writel(devpriv->plx_control_bits, plx_control_addr);
3806                 udelay(eeprom_udelay);
3807                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3808                 writel(devpriv->plx_control_bits, plx_control_addr);
3809         }
3810         /*  read back value from eeprom memory location */
3811         value = 0;
3812         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3813                 /*  clock out bit */
3814                 udelay(eeprom_udelay);
3815                 devpriv->plx_control_bits |= CTL_EE_CLK;
3816                 writel(devpriv->plx_control_bits, plx_control_addr);
3817                 udelay(eeprom_udelay);
3818                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3819                 writel(devpriv->plx_control_bits, plx_control_addr);
3820                 udelay(eeprom_udelay);
3821                 if (readl(plx_control_addr) & CTL_EE_R)
3822                         value |= bit;
3823         }
3824
3825         /*  deactivate eeprom serial input */
3826         udelay(eeprom_udelay);
3827         devpriv->plx_control_bits &= ~CTL_EE_CS;
3828         writel(devpriv->plx_control_bits, plx_control_addr);
3829
3830         return value;
3831 }
3832
3833 static int eeprom_read_insn(struct comedi_device *dev,
3834                             struct comedi_subdevice *s,
3835                             struct comedi_insn *insn, unsigned int *data)
3836 {
3837         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3838
3839         return 1;
3840 }
3841
3842 /* Allocate and initialize the subdevice structures.
3843  */
3844 static int setup_subdevices(struct comedi_device *dev)
3845 {
3846         const struct pcidas64_board *thisboard = comedi_board(dev);
3847         struct pcidas64_private *devpriv = dev->private;
3848         struct comedi_subdevice *s;
3849         void __iomem *dio_8255_iobase;
3850         int i;
3851         int ret;
3852
3853         ret = comedi_alloc_subdevices(dev, 10);
3854         if (ret)
3855                 return ret;
3856
3857         s = &dev->subdevices[0];
3858         /* analog input subdevice */
3859         dev->read_subdev = s;
3860         s->type = COMEDI_SUBD_AI;
3861         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3862         if (thisboard->layout == LAYOUT_60XX)
3863                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3864         else if (thisboard->layout == LAYOUT_64XX)
3865                 s->subdev_flags |= SDF_DIFF;
3866         /* XXX Number of inputs in differential mode is ignored */
3867         s->n_chan = thisboard->ai_se_chans;
3868         s->len_chanlist = 0x2000;
3869         s->maxdata = (1 << thisboard->ai_bits) - 1;
3870         s->range_table = thisboard->ai_range_table;
3871         s->insn_read = ai_rinsn;
3872         s->insn_config = ai_config_insn;
3873         s->do_cmd = ai_cmd;
3874         s->do_cmdtest = ai_cmdtest;
3875         s->cancel = ai_cancel;
3876         if (thisboard->layout == LAYOUT_4020) {
3877                 uint8_t data;
3878                 /*  set adc to read from inputs
3879                  *  (not internal calibration sources) */
3880                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3881                 /*  set channels to +-5 volt input ranges */
3882                 for (i = 0; i < s->n_chan; i++)
3883                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3884                 data = devpriv->i2c_cal_range_bits;
3885                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3886         }
3887
3888         /* analog output subdevice */
3889         s = &dev->subdevices[1];
3890         if (thisboard->ao_nchan) {
3891                 s->type = COMEDI_SUBD_AO;
3892                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3893                                   SDF_GROUND | SDF_CMD_WRITE;
3894                 s->n_chan = thisboard->ao_nchan;
3895                 s->maxdata = (1 << thisboard->ao_bits) - 1;
3896                 s->range_table = thisboard->ao_range_table;
3897                 s->insn_read = ao_readback_insn;
3898                 s->insn_write = ao_winsn;
3899                 if (ao_cmd_is_supported(thisboard)) {
3900                         dev->write_subdev = s;
3901                         s->do_cmdtest = ao_cmdtest;
3902                         s->do_cmd = ao_cmd;
3903                         s->len_chanlist = thisboard->ao_nchan;
3904                         s->cancel = ao_cancel;
3905                 }
3906         } else {
3907                 s->type = COMEDI_SUBD_UNUSED;
3908         }
3909
3910         /*  digital input */
3911         s = &dev->subdevices[2];
3912         if (thisboard->layout == LAYOUT_64XX) {
3913                 s->type = COMEDI_SUBD_DI;
3914                 s->subdev_flags = SDF_READABLE;
3915                 s->n_chan = 4;
3916                 s->maxdata = 1;
3917                 s->range_table = &range_digital;
3918                 s->insn_bits = di_rbits;
3919         } else
3920                 s->type = COMEDI_SUBD_UNUSED;
3921
3922         /*  digital output */
3923         if (thisboard->layout == LAYOUT_64XX) {
3924                 s = &dev->subdevices[3];
3925                 s->type = COMEDI_SUBD_DO;
3926                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3927                 s->n_chan = 4;
3928                 s->maxdata = 1;
3929                 s->range_table = &range_digital;
3930                 s->insn_bits = do_wbits;
3931         } else
3932                 s->type = COMEDI_SUBD_UNUSED;
3933
3934         /* 8255 */
3935         s = &dev->subdevices[4];
3936         if (thisboard->has_8255) {
3937                 if (thisboard->layout == LAYOUT_4020) {
3938                         dio_8255_iobase = devpriv->main_iobase + I8255_4020_REG;
3939                         subdev_8255_init(dev, s, dio_callback_4020,
3940                                          (unsigned long)dio_8255_iobase);
3941                 } else {
3942                         dio_8255_iobase =
3943                                 devpriv->dio_counter_iobase + DIO_8255_OFFSET;
3944                         subdev_8255_init(dev, s, dio_callback,
3945                                          (unsigned long)dio_8255_iobase);
3946                 }
3947         } else
3948                 s->type = COMEDI_SUBD_UNUSED;
3949
3950         /*  8 channel dio for 60xx */
3951         s = &dev->subdevices[5];
3952         if (thisboard->layout == LAYOUT_60XX) {
3953                 s->type = COMEDI_SUBD_DIO;
3954                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3955                 s->n_chan = 8;
3956                 s->maxdata = 1;
3957                 s->range_table = &range_digital;
3958                 s->insn_config = dio_60xx_config_insn;
3959                 s->insn_bits = dio_60xx_wbits;
3960         } else
3961                 s->type = COMEDI_SUBD_UNUSED;
3962
3963         /*  caldac */
3964         s = &dev->subdevices[6];
3965         s->type = COMEDI_SUBD_CALIB;
3966         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3967         s->n_chan = 8;
3968         if (thisboard->layout == LAYOUT_4020)
3969                 s->maxdata = 0xfff;
3970         else
3971                 s->maxdata = 0xff;
3972         s->insn_read = calib_read_insn;
3973         s->insn_write = calib_write_insn;
3974         for (i = 0; i < s->n_chan; i++)
3975                 caldac_write(dev, i, s->maxdata / 2);
3976
3977         /*  2 channel ad8402 potentiometer */
3978         s = &dev->subdevices[7];
3979         if (thisboard->layout == LAYOUT_64XX) {
3980                 s->type = COMEDI_SUBD_CALIB;
3981                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3982                 s->n_chan = 2;
3983                 s->insn_read = ad8402_read_insn;
3984                 s->insn_write = ad8402_write_insn;
3985                 s->maxdata = 0xff;
3986                 for (i = 0; i < s->n_chan; i++)
3987                         ad8402_write(dev, i, s->maxdata / 2);
3988         } else
3989                 s->type = COMEDI_SUBD_UNUSED;
3990
3991         /* serial EEPROM, if present */
3992         s = &dev->subdevices[8];
3993         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
3994                 s->type = COMEDI_SUBD_MEMORY;
3995                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3996                 s->n_chan = 128;
3997                 s->maxdata = 0xffff;
3998                 s->insn_read = eeprom_read_insn;
3999         } else
4000                 s->type = COMEDI_SUBD_UNUSED;
4001
4002         /*  user counter subd XXX */
4003         s = &dev->subdevices[9];
4004         s->type = COMEDI_SUBD_UNUSED;
4005
4006         return 0;
4007 }
4008
4009 static int auto_attach(struct comedi_device *dev,
4010                        unsigned long context)
4011 {
4012         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4013         const struct pcidas64_board *thisboard = NULL;
4014         struct pcidas64_private *devpriv;
4015         uint32_t local_range, local_decode;
4016         int retval;
4017
4018         if (context < ARRAY_SIZE(pcidas64_boards))
4019                 thisboard = &pcidas64_boards[context];
4020         if (!thisboard)
4021                 return -ENODEV;
4022         dev->board_ptr = thisboard;
4023
4024         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
4025         if (!devpriv)
4026                 return -ENOMEM;
4027
4028         retval = comedi_pci_enable(dev);
4029         if (retval)
4030                 return retval;
4031         pci_set_master(pcidev);
4032
4033         /* Initialize dev->board_name */
4034         dev->board_name = thisboard->name;
4035
4036         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
4037         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
4038
4039         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4040         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4041         devpriv->dio_counter_iobase = pci_ioremap_bar(pcidev, 3);
4042
4043         if (!devpriv->plx9080_iobase || !devpriv->main_iobase
4044             || !devpriv->dio_counter_iobase) {
4045                 dev_warn(dev->class_dev, "failed to remap io memory\n");
4046                 return -ENOMEM;
4047         }
4048
4049         DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
4050         DEBUG_PRINT(" main remapped to 0x%p\n", devpriv->main_iobase);
4051         DEBUG_PRINT(" diocounter remapped to 0x%p\n",
4052                     devpriv->dio_counter_iobase);
4053
4054         /*  figure out what local addresses are */
4055         local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
4056                       LRNG_MEM_MASK;
4057         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
4058                        local_range & LMAP_MEM_MASK;
4059         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4060                                   ~local_range) | local_decode;
4061         local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
4062                       LRNG_MEM_MASK;
4063         local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
4064                        local_range & LMAP_MEM_MASK;
4065         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4066                                   ~local_range) | local_decode;
4067
4068         DEBUG_PRINT(" local 0 io addr 0x%x\n", devpriv->local0_iobase);
4069         DEBUG_PRINT(" local 1 io addr 0x%x\n", devpriv->local1_iobase);
4070
4071         retval = alloc_and_init_dma_members(dev);
4072         if (retval < 0)
4073                 return retval;
4074
4075         devpriv->hw_revision =
4076                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4077         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4078                 devpriv->hw_revision);
4079         init_plx9080(dev);
4080         init_stc_registers(dev);
4081         /*  get irq */
4082         if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4083                         "cb_pcidas64", dev)) {
4084                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4085                         pcidev->irq);
4086                 return -EINVAL;
4087         }
4088         dev->irq = pcidev->irq;
4089         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4090
4091         retval = setup_subdevices(dev);
4092         if (retval < 0)
4093                 return retval;
4094
4095         return 0;
4096 }
4097
4098 static void detach(struct comedi_device *dev)
4099 {
4100         const struct pcidas64_board *thisboard = comedi_board(dev);
4101         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4102         struct pcidas64_private *devpriv = dev->private;
4103         unsigned int i;
4104
4105         if (dev->irq)
4106                 free_irq(dev->irq, dev);
4107         if (devpriv) {
4108                 if (pcidev) {
4109                         if (devpriv->plx9080_iobase) {
4110                                 disable_plx_interrupts(dev);
4111                                 iounmap(devpriv->plx9080_iobase);
4112                         }
4113                         if (devpriv->main_iobase)
4114                                 iounmap(devpriv->main_iobase);
4115                         if (devpriv->dio_counter_iobase)
4116                                 iounmap(devpriv->dio_counter_iobase);
4117                         /*  free pci dma buffers */
4118                         for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
4119                                 if (devpriv->ai_buffer[i])
4120                                         pci_free_consistent(pcidev,
4121                                                 DMA_BUFFER_SIZE,
4122                                                 devpriv->ai_buffer[i],
4123                                                 devpriv->ai_buffer_bus_addr[i]);
4124                         }
4125                         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
4126                                 if (devpriv->ao_buffer[i])
4127                                         pci_free_consistent(pcidev,
4128                                                 DMA_BUFFER_SIZE,
4129                                                 devpriv->ao_buffer[i],
4130                                                 devpriv->ao_buffer_bus_addr[i]);
4131                         }
4132                         /*  free dma descriptors */
4133                         if (devpriv->ai_dma_desc)
4134                                 pci_free_consistent(pcidev,
4135                                         sizeof(struct plx_dma_desc) *
4136                                         ai_dma_ring_count(thisboard),
4137                                         devpriv->ai_dma_desc,
4138                                         devpriv->ai_dma_desc_bus_addr);
4139                         if (devpriv->ao_dma_desc)
4140                                 pci_free_consistent(pcidev,
4141                                         sizeof(struct plx_dma_desc) *
4142                                         AO_DMA_RING_COUNT,
4143                                         devpriv->ao_dma_desc,
4144                                         devpriv->ao_dma_desc_bus_addr);
4145                 }
4146         }
4147         comedi_pci_disable(dev);
4148 }
4149
4150 static struct comedi_driver cb_pcidas64_driver = {
4151         .driver_name    = "cb_pcidas64",
4152         .module         = THIS_MODULE,
4153         .auto_attach    = auto_attach,
4154         .detach         = detach,
4155 };
4156
4157 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4158                                  const struct pci_device_id *id)
4159 {
4160         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4161                                       id->driver_data);
4162 }
4163
4164 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4165         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4166         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4167         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4168         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4169         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4170         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4171         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4172         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4173         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4174         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4175         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4176         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4177         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4178         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4179         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4180         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4181         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4182         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4183         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4184         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4185         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4186         { 0 }
4187 };
4188 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4189
4190 static struct pci_driver cb_pcidas64_pci_driver = {
4191         .name           = "cb_pcidas64",
4192         .id_table       = cb_pcidas64_pci_table,
4193         .probe          = cb_pcidas64_pci_probe,
4194         .remove         = comedi_pci_auto_unconfig,
4195 };
4196 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4197
4198 MODULE_AUTHOR("Comedi http://www.comedi.org");
4199 MODULE_DESCRIPTION("Comedi low-level driver");
4200 MODULE_LICENSE("GPL");