2 comedi/drivers/dmm32at.c
3 Diamond Systems mm32at code for a Comedi driver
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: Diamond Systems mm32at driver.
22 Author: Perry J. Piplani <perry.j.piplani@nasa.gov>
23 Updated: Fri Jun 4 09:13:24 CDT 2004
26 This driver is for the Diamond Systems MM-32-AT board
27 http://www.diamondsystems.com/products/diamondmm32at It is being used
28 on serveral projects inside NASA, without problems so far. For analog
29 input commands, TRIG_EXT is not yet supported at all..
31 Configuration Options:
32 comedi_config /dev/comedi0 dmm32at baseaddr,irq
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/interrupt.h>
38 #include "../comedidev.h"
40 #include "comedi_fc.h"
42 /* Board register addresses */
44 #define DMM32AT_MEMSIZE 0x10
46 #define DMM32AT_CONV 0x00
47 #define DMM32AT_AILSB 0x00
48 #define DMM32AT_AUXDOUT 0x01
49 #define DMM32AT_AIMSB 0x01
50 #define DMM32AT_AILOW 0x02
51 #define DMM32AT_AIHIGH 0x03
53 #define DMM32AT_DACLSB 0x04
54 #define DMM32AT_DACSTAT 0x04
55 #define DMM32AT_DACMSB 0x05
57 #define DMM32AT_FIFOCNTRL 0x07
58 #define DMM32AT_FIFOSTAT 0x07
60 #define DMM32AT_CNTRL 0x08
61 #define DMM32AT_AISTAT 0x08
63 #define DMM32AT_INTCLOCK 0x09
65 #define DMM32AT_CNTRDIO 0x0a
67 #define DMM32AT_AICONF 0x0b
68 #define DMM32AT_AIRBACK 0x0b
70 #define DMM32AT_CLK1 0x0d
71 #define DMM32AT_CLK2 0x0e
72 #define DMM32AT_CLKCT 0x0f
74 #define DMM32AT_DIOA 0x0c
75 #define DMM32AT_DIOB 0x0d
76 #define DMM32AT_DIOC 0x0e
77 #define DMM32AT_DIOCONF 0x0f
79 /* Board register values. */
81 /* DMM32AT_DACSTAT 0x04 */
82 #define DMM32AT_DACBUSY 0x80
84 /* DMM32AT_FIFOCNTRL 0x07 */
85 #define DMM32AT_FIFORESET 0x02
86 #define DMM32AT_SCANENABLE 0x04
88 /* DMM32AT_CNTRL 0x08 */
89 #define DMM32AT_RESET 0x20
90 #define DMM32AT_INTRESET 0x08
91 #define DMM32AT_CLKACC 0x00
92 #define DMM32AT_DIOACC 0x01
94 /* DMM32AT_AISTAT 0x08 */
95 #define DMM32AT_STATUS 0x80
97 /* DMM32AT_INTCLOCK 0x09 */
98 #define DMM32AT_ADINT 0x80
99 #define DMM32AT_CLKSEL 0x03
101 /* DMM32AT_CNTRDIO 0x0a */
102 #define DMM32AT_FREQ12 0x80
104 /* DMM32AT_AICONF 0x0b */
105 #define DMM32AT_RANGE_U10 0x0c
106 #define DMM32AT_RANGE_U5 0x0d
107 #define DMM32AT_RANGE_B10 0x08
108 #define DMM32AT_RANGE_B5 0x00
109 #define DMM32AT_SCINT_20 0x00
110 #define DMM32AT_SCINT_15 0x10
111 #define DMM32AT_SCINT_10 0x20
112 #define DMM32AT_SCINT_5 0x30
114 /* DMM32AT_CLKCT 0x0f */
115 #define DMM32AT_CLKCT1 0x56 /* mode3 counter 1 - write low byte only */
116 #define DMM32AT_CLKCT2 0xb6 /* mode3 counter 2 - write high and low byte */
118 /* DMM32AT_DIOCONF 0x0f */
119 #define DMM32AT_DIENABLE 0x80
120 #define DMM32AT_DIRA 0x10
121 #define DMM32AT_DIRB 0x02
122 #define DMM32AT_DIRCL 0x01
123 #define DMM32AT_DIRCH 0x08
125 /* board AI ranges in comedi structure */
126 static const struct comedi_lrange dmm32at_airanges = {
135 /* register values for above ranges */
136 static const unsigned char dmm32at_rangebits[] = {
143 /* only one of these ranges is valid, as set by a jumper on the
144 * board. The application should only use the range set by the jumper
146 static const struct comedi_lrange dmm32at_aoranges = {
155 struct dmm32at_private {
159 unsigned int ai_scans_left;
161 /* Used for AO readback */
162 unsigned int ao_readback[4];
163 unsigned char dio_config;
167 static int dmm32at_ai_status(struct comedi_device *dev,
168 struct comedi_subdevice *s,
169 struct comedi_insn *insn,
170 unsigned long context)
172 unsigned char status;
174 status = inb(dev->iobase + context);
175 if ((status & DMM32AT_STATUS) == 0)
180 static int dmm32at_ai_rinsn(struct comedi_device *dev,
181 struct comedi_subdevice *s,
182 struct comedi_insn *insn, unsigned int *data)
186 unsigned short msb, lsb;
191 /* get the channel and range number */
193 chan = CR_CHAN(insn->chanspec) & (s->n_chan - 1);
194 range = CR_RANGE(insn->chanspec);
196 /* zero scan and fifo control and reset fifo */
197 outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL);
199 /* write the ai channel range regs */
200 outb(chan, dev->iobase + DMM32AT_AILOW);
201 outb(chan, dev->iobase + DMM32AT_AIHIGH);
202 /* set the range bits */
203 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF);
205 /* wait for circuit to settle */
206 ret = comedi_timeout(dev, s, insn, dmm32at_ai_status, DMM32AT_AIRBACK);
210 /* convert n samples */
211 for (n = 0; n < insn->n; n++) {
212 /* trigger conversion */
213 outb(0xff, dev->iobase + DMM32AT_CONV);
215 /* wait for conversion to end */
216 ret = comedi_timeout(dev, s, insn, dmm32at_ai_status,
222 lsb = inb(dev->iobase + DMM32AT_AILSB);
223 msb = inb(dev->iobase + DMM32AT_AIMSB);
225 /* invert sign bit to make range unsigned, this is an
226 idiosyncrasy of the diamond board, it return
227 conversions as a signed value, i.e. -32768 to
228 32767, flipping the bit and interpreting it as
229 signed gives you a range of 0 to 65535 which is
231 d = ((msb ^ 0x0080) << 8) + lsb;
236 /* return the number of samples read/written */
240 static int dmm32at_ns_to_timer(unsigned int *ns, unsigned int flags)
246 static int dmm32at_ai_check_chanlist(struct comedi_device *dev,
247 struct comedi_subdevice *s,
248 struct comedi_cmd *cmd)
250 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
251 unsigned int range0 = CR_RANGE(cmd->chanlist[0]);
254 for (i = 1; i < cmd->chanlist_len; i++) {
255 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
256 unsigned int range = CR_RANGE(cmd->chanlist[i]);
258 if (chan != (chan0 + i) % s->n_chan) {
259 dev_dbg(dev->class_dev,
260 "entries in chanlist must be consecutive channels, counting upwards\n");
263 if (range != range0) {
264 dev_dbg(dev->class_dev,
265 "entries in chanlist must all have the same gain\n");
273 static int dmm32at_ai_cmdtest(struct comedi_device *dev,
274 struct comedi_subdevice *s,
275 struct comedi_cmd *cmd)
280 /* Step 1 : check if triggers are trivially valid */
282 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
283 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
284 TRIG_TIMER /*| TRIG_EXT */);
285 err |= cfc_check_trigger_src(&cmd->convert_src,
286 TRIG_TIMER /*| TRIG_EXT */);
287 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
288 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
293 /* Step 2a : make sure trigger sources are unique */
295 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
296 err |= cfc_check_trigger_is_unique(cmd->convert_src);
297 err |= cfc_check_trigger_is_unique(cmd->stop_src);
299 /* Step 2b : and mutually compatible */
304 /* Step 3: check if arguments are trivially valid */
306 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
308 #define MAX_SCAN_SPEED 1000000 /* in nanoseconds */
309 #define MIN_SCAN_SPEED 1000000000 /* in nanoseconds */
311 if (cmd->scan_begin_src == TRIG_TIMER) {
312 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
314 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
317 /* external trigger */
318 /* should be level/edge, hi/lo specification here */
319 /* should specify multiple external triggers */
320 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
323 if (cmd->convert_src == TRIG_TIMER) {
324 if (cmd->convert_arg >= 17500)
325 cmd->convert_arg = 20000;
326 else if (cmd->convert_arg >= 12500)
327 cmd->convert_arg = 15000;
328 else if (cmd->convert_arg >= 7500)
329 cmd->convert_arg = 10000;
331 cmd->convert_arg = 5000;
333 /* external trigger */
335 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9);
338 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
340 if (cmd->stop_src == TRIG_COUNT) {
341 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0xfffffff0);
342 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
345 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
351 /* step 4: fix up any arguments */
353 if (cmd->scan_begin_src == TRIG_TIMER) {
354 arg = cmd->scan_begin_arg;
355 dmm32at_ns_to_timer(&arg, cmd->flags);
356 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
358 if (cmd->convert_src == TRIG_TIMER) {
359 arg = cmd->convert_arg;
360 dmm32at_ns_to_timer(&arg, cmd->flags);
361 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
363 if (cmd->scan_begin_src == TRIG_TIMER) {
364 arg = cmd->convert_arg * cmd->scan_end_arg;
365 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
373 /* Step 5: check channel list if it exists */
374 if (cmd->chanlist && cmd->chanlist_len > 0)
375 err |= dmm32at_ai_check_chanlist(dev, s, cmd);
383 static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec)
385 unsigned char lo1, lo2, hi2;
386 unsigned short both2;
388 /* based on 10mhz clock */
390 both2 = nansec / 20000;
391 hi2 = (both2 & 0xff00) >> 8;
392 lo2 = both2 & 0x00ff;
394 /* set the counter frequency to 10mhz */
395 outb(0, dev->iobase + DMM32AT_CNTRDIO);
397 /* get access to the clock regs */
398 outb(DMM32AT_CLKACC, dev->iobase + DMM32AT_CNTRL);
400 /* write the counter 1 control word and low byte to counter */
401 outb(DMM32AT_CLKCT1, dev->iobase + DMM32AT_CLKCT);
402 outb(lo1, dev->iobase + DMM32AT_CLK1);
404 /* write the counter 2 control word and low byte then to counter */
405 outb(DMM32AT_CLKCT2, dev->iobase + DMM32AT_CLKCT);
406 outb(lo2, dev->iobase + DMM32AT_CLK2);
407 outb(hi2, dev->iobase + DMM32AT_CLK2);
409 /* enable the ai conversion interrupt and the clock to start scans */
410 outb(DMM32AT_ADINT | DMM32AT_CLKSEL, dev->iobase + DMM32AT_INTCLOCK);
413 static int dmm32at_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
415 struct dmm32at_private *devpriv = dev->private;
416 struct comedi_cmd *cmd = &s->async->cmd;
418 unsigned char chanlo, chanhi;
424 /* get the channel list and range */
425 chanlo = CR_CHAN(cmd->chanlist[0]) & (s->n_chan - 1);
426 chanhi = chanlo + cmd->chanlist_len - 1;
427 if (chanhi >= s->n_chan)
429 range = CR_RANGE(cmd->chanlist[0]);
432 outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL);
434 /* set scan enable */
435 outb(DMM32AT_SCANENABLE, dev->iobase + DMM32AT_FIFOCNTRL);
437 /* write the ai channel range regs */
438 outb(chanlo, dev->iobase + DMM32AT_AILOW);
439 outb(chanhi, dev->iobase + DMM32AT_AIHIGH);
441 /* set the range bits */
442 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF);
444 /* reset the interrupt just in case */
445 outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL);
447 if (cmd->stop_src == TRIG_COUNT)
448 devpriv->ai_scans_left = cmd->stop_arg;
449 else { /* TRIG_NONE */
450 devpriv->ai_scans_left = 0xffffffff; /* indicates TRIG_NONE to
455 * wait for circuit to settle
456 * we don't have the 'insn' here but it's not needed
458 ret = comedi_timeout(dev, s, NULL, dmm32at_ai_status, DMM32AT_AIRBACK);
462 if (devpriv->ai_scans_left > 1) {
463 /* start the clock and enable the interrupts */
464 dmm32at_setaitimer(dev, cmd->scan_begin_arg);
466 /* start the interrups and initiate a single scan */
467 outb(DMM32AT_ADINT, dev->iobase + DMM32AT_INTCLOCK);
468 outb(0xff, dev->iobase + DMM32AT_CONV);
475 static int dmm32at_ai_cancel(struct comedi_device *dev,
476 struct comedi_subdevice *s)
478 struct dmm32at_private *devpriv = dev->private;
480 devpriv->ai_scans_left = 1;
484 static irqreturn_t dmm32at_isr(int irq, void *d)
486 struct comedi_device *dev = d;
487 struct dmm32at_private *devpriv = dev->private;
488 unsigned char intstat;
490 unsigned short msb, lsb;
493 if (!dev->attached) {
494 dev_err(dev->class_dev, "spurious interrupt\n");
498 intstat = inb(dev->iobase + DMM32AT_INTCLOCK);
500 if (intstat & DMM32AT_ADINT) {
501 struct comedi_subdevice *s = dev->read_subdev;
502 struct comedi_cmd *cmd = &s->async->cmd;
504 for (i = 0; i < cmd->chanlist_len; i++) {
506 lsb = inb(dev->iobase + DMM32AT_AILSB);
507 msb = inb(dev->iobase + DMM32AT_AIMSB);
509 /* invert sign bit to make range unsigned */
510 samp = ((msb ^ 0x0080) << 8) + lsb;
511 comedi_buf_put(s, samp);
514 if (devpriv->ai_scans_left != 0xffffffff) { /* TRIG_COUNT */
515 devpriv->ai_scans_left--;
516 if (devpriv->ai_scans_left == 0) {
517 /* disable further interrupts and clocks */
518 outb(0x0, dev->iobase + DMM32AT_INTCLOCK);
519 /* set the buffer to be flushed with an EOF */
520 s->async->events |= COMEDI_CB_EOA;
524 /* flush the buffer */
525 comedi_event(dev, s);
528 /* reset the interrupt */
529 outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL);
533 static int dmm32at_ao_eoc(struct comedi_device *dev,
534 struct comedi_subdevice *s,
535 struct comedi_insn *insn,
536 unsigned long context)
538 unsigned char status;
540 status = inb(dev->iobase + DMM32AT_DACSTAT);
541 if ((status & DMM32AT_DACBUSY) == 0)
546 static int dmm32at_ao_winsn(struct comedi_device *dev,
547 struct comedi_subdevice *s,
548 struct comedi_insn *insn, unsigned int *data)
550 struct dmm32at_private *devpriv = dev->private;
552 int chan = CR_CHAN(insn->chanspec);
553 unsigned char hi, lo, status;
556 /* Writing a list of values to an AO channel is probably not
557 * very useful, but that's how the interface is defined. */
558 for (i = 0; i < insn->n; i++) {
560 devpriv->ao_readback[chan] = data[i];
562 /* get the low byte */
563 lo = data[i] & 0x00ff;
564 /* high byte also contains channel number */
565 hi = (data[i] >> 8) + chan * (1 << 6);
566 /* write the low and high values to the board */
567 outb(lo, dev->iobase + DMM32AT_DACLSB);
568 outb(hi, dev->iobase + DMM32AT_DACMSB);
570 /* wait for circuit to settle */
571 ret = comedi_timeout(dev, s, insn, dmm32at_ao_eoc, 0);
575 /* dummy read to update trigger the output */
576 status = inb(dev->iobase + DMM32AT_DACMSB);
580 /* return the number of samples read/written */
584 static int dmm32at_ao_rinsn(struct comedi_device *dev,
585 struct comedi_subdevice *s,
586 struct comedi_insn *insn, unsigned int *data)
588 struct dmm32at_private *devpriv = dev->private;
590 int chan = CR_CHAN(insn->chanspec);
592 for (i = 0; i < insn->n; i++)
593 data[i] = devpriv->ao_readback[chan];
598 static int dmm32at_dio_insn_bits(struct comedi_device *dev,
599 struct comedi_subdevice *s,
600 struct comedi_insn *insn,
603 struct dmm32at_private *devpriv = dev->private;
607 mask = comedi_dio_update_state(s, data);
609 /* get access to the DIO regs */
610 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
612 /* if either part of dio is set for output */
613 if (((devpriv->dio_config & DMM32AT_DIRCL) == 0) ||
614 ((devpriv->dio_config & DMM32AT_DIRCH) == 0)) {
615 val = (s->state & 0x00ff0000) >> 16;
616 outb(val, dev->iobase + DMM32AT_DIOC);
618 if ((devpriv->dio_config & DMM32AT_DIRB) == 0) {
619 val = (s->state & 0x0000ff00) >> 8;
620 outb(val, dev->iobase + DMM32AT_DIOB);
622 if ((devpriv->dio_config & DMM32AT_DIRA) == 0) {
623 val = (s->state & 0x000000ff);
624 outb(val, dev->iobase + DMM32AT_DIOA);
628 val = inb(dev->iobase + DMM32AT_DIOA);
629 val |= inb(dev->iobase + DMM32AT_DIOB) << 8;
630 val |= inb(dev->iobase + DMM32AT_DIOC) << 16;
638 static int dmm32at_dio_insn_config(struct comedi_device *dev,
639 struct comedi_subdevice *s,
640 struct comedi_insn *insn,
643 struct dmm32at_private *devpriv = dev->private;
644 unsigned int chan = CR_CHAN(insn->chanspec);
646 unsigned char chanbit;
651 chanbit = DMM32AT_DIRA;
652 } else if (chan < 16) {
654 chanbit = DMM32AT_DIRB;
655 } else if (chan < 20) {
657 chanbit = DMM32AT_DIRCL;
660 chanbit = DMM32AT_DIRCH;
663 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
667 if (data[0] == INSN_CONFIG_DIO_OUTPUT)
668 devpriv->dio_config &= ~chanbit;
670 devpriv->dio_config |= chanbit;
671 /* get access to the DIO regs */
672 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
673 /* set the DIO's to the new configuration setting */
674 outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF);
679 static int dmm32at_attach(struct comedi_device *dev,
680 struct comedi_devconfig *it)
682 struct dmm32at_private *devpriv;
684 struct comedi_subdevice *s;
685 unsigned char aihi, ailo, fifostat, aistat, intstat, airback;
687 ret = comedi_request_region(dev, it->options[0], DMM32AT_MEMSIZE);
691 /* the following just makes sure the board is there and gets
692 it to a known state */
694 /* reset the board */
695 outb(DMM32AT_RESET, dev->iobase + DMM32AT_CNTRL);
697 /* allow a millisecond to reset */
700 /* zero scan and fifo control */
701 outb(0x0, dev->iobase + DMM32AT_FIFOCNTRL);
703 /* zero interrupt and clock control */
704 outb(0x0, dev->iobase + DMM32AT_INTCLOCK);
706 /* write a test channel range, the high 3 bits should drop */
707 outb(0x80, dev->iobase + DMM32AT_AILOW);
708 outb(0xff, dev->iobase + DMM32AT_AIHIGH);
710 /* set the range at 10v unipolar */
711 outb(DMM32AT_RANGE_U10, dev->iobase + DMM32AT_AICONF);
713 /* should take 10 us to settle, here's a hundred */
716 /* read back the values */
717 ailo = inb(dev->iobase + DMM32AT_AILOW);
718 aihi = inb(dev->iobase + DMM32AT_AIHIGH);
719 fifostat = inb(dev->iobase + DMM32AT_FIFOSTAT);
720 aistat = inb(dev->iobase + DMM32AT_AISTAT);
721 intstat = inb(dev->iobase + DMM32AT_INTCLOCK);
722 airback = inb(dev->iobase + DMM32AT_AIRBACK);
724 if ((ailo != 0x00) || (aihi != 0x1f) || (fifostat != 0x80) ||
725 (aistat != 0x60 || (intstat != 0x00) || airback != 0x0c)) {
726 dev_err(dev->class_dev, "board detection failed\n");
730 if (it->options[1]) {
731 ret = request_irq(it->options[1], dmm32at_isr, 0,
732 dev->board_name, dev);
734 dev->irq = it->options[1];
737 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
741 ret = comedi_alloc_subdevices(dev, 3);
745 s = &dev->subdevices[0];
746 /* analog input subdevice */
747 s->type = COMEDI_SUBD_AI;
748 /* we support single-ended (ground) and differential */
749 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF;
752 s->range_table = &dmm32at_airanges;
753 s->insn_read = dmm32at_ai_rinsn;
755 dev->read_subdev = s;
756 s->subdev_flags |= SDF_CMD_READ;
757 s->len_chanlist = 32;
758 s->do_cmd = dmm32at_ai_cmd;
759 s->do_cmdtest = dmm32at_ai_cmdtest;
760 s->cancel = dmm32at_ai_cancel;
763 s = &dev->subdevices[1];
764 /* analog output subdevice */
765 s->type = COMEDI_SUBD_AO;
766 s->subdev_flags = SDF_WRITABLE;
769 s->range_table = &dmm32at_aoranges;
770 s->insn_write = dmm32at_ao_winsn;
771 s->insn_read = dmm32at_ao_rinsn;
773 s = &dev->subdevices[2];
774 /* digital i/o subdevice */
776 /* get access to the DIO regs */
777 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
778 /* set the DIO's to the defualt input setting */
779 devpriv->dio_config = DMM32AT_DIRA | DMM32AT_DIRB |
780 DMM32AT_DIRCL | DMM32AT_DIRCH | DMM32AT_DIENABLE;
781 outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF);
783 /* set up the subdevice */
784 s->type = COMEDI_SUBD_DIO;
785 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
789 s->range_table = &range_digital;
790 s->insn_bits = dmm32at_dio_insn_bits;
791 s->insn_config = dmm32at_dio_insn_config;
796 static struct comedi_driver dmm32at_driver = {
797 .driver_name = "dmm32at",
798 .module = THIS_MODULE,
799 .attach = dmm32at_attach,
800 .detach = comedi_legacy_detach,
802 module_comedi_driver(dmm32at_driver);
804 MODULE_AUTHOR("Comedi http://www.comedi.org");
805 MODULE_DESCRIPTION("Comedi low-level driver");
806 MODULE_LICENSE("GPL");