drivers/staging/comedi/drivers/ni_pcidio.c

   1 /*
   2     comedi/drivers/ni_pcidio.c
   3     driver for National Instruments PCI-DIO-32HS
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18 /*
  19 Driver: ni_pcidio
  20 Description: National Instruments PCI-DIO32HS, PCI-6533
  21 Author: ds
  22 Status: works
  23 Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
  24          [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
  25          [National Instruments] PCI-6534 (pci-6534)
  26 Updated: Mon, 09 Jan 2012 14:27:23 +0000
  27
  28 The DIO32HS board appears as one subdevice, with 32 channels.
  29 Each channel is individually I/O configurable.  The channel order
  30 is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0.  The driver only
  31 supports simple digital I/O; no handshaking is supported.
  32
  33 DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
  34
  35 The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
  36 scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
  37 scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
  38 trailing edge.
  39
  40 This driver could be easily modified to support AT-MIO32HS and
  41 AT-MIO96.
  42
  43 The PCI-6534 requires a firmware upload after power-up to work, the
  44 firmware data and instructions for loading it with comedi_config
  45 it are contained in the
  46 comedi_nonfree_firmware tarball available from http://www.comedi.org
  47 */
  48
  49 #define USE_DMA
  50
  51 #include <linux/module.h>
  52 #include <linux/delay.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/sched.h>
  55
  56 #include "../comedidev.h"
  57
  58 #include "comedi_fc.h"
  59 #include "mite.h"
  60
  61 /* defines for the PCI-DIO-32HS */
  62
  63 #define Window_Address                  4       /* W */
  64 #define Interrupt_And_Window_Status     4       /* R */
  65 #define IntStatus1                              (1<<0)
  66 #define IntStatus2                              (1<<1)
  67 #define WindowAddressStatus_mask                0x7c
  68
  69 #define Master_DMA_And_Interrupt_Control 5      /* W */
  70 #define InterruptLine(x)                        ((x)&3)
  71 #define OpenInt                         (1<<2)
  72 #define Group_Status                    5       /* R */
  73 #define DataLeft                                (1<<0)
  74 #define Req                                     (1<<2)
  75 #define StopTrig                                (1<<3)
  76
  77 #define Group_1_Flags                   6       /* R */
  78 #define Group_2_Flags                   7       /* R */
  79 #define TransferReady                           (1<<0)
  80 #define CountExpired                            (1<<1)
  81 #define Waited                          (1<<5)
  82 #define PrimaryTC                               (1<<6)
  83 #define SecondaryTC                             (1<<7)
  84   /* #define SerialRose */
  85   /* #define ReqRose */
  86   /* #define Paused */
  87
  88 #define Group_1_First_Clear             6       /* W */
  89 #define Group_2_First_Clear             7       /* W */
  90 #define ClearWaited                             (1<<3)
  91 #define ClearPrimaryTC                  (1<<4)
  92 #define ClearSecondaryTC                        (1<<5)
  93 #define DMAReset                                (1<<6)
  94 #define FIFOReset                               (1<<7)
  95 #define ClearAll                                0xf8
  96
  97 #define Group_1_FIFO                    8       /* W */
  98 #define Group_2_FIFO                    12      /* W */
  99
 100 #define Transfer_Count                  20
 101 #define Chip_ID_D                       24
 102 #define Chip_ID_I                       25
 103 #define Chip_ID_O                       26
 104 #define Chip_Version                    27
 105 #define Port_IO(x)                      (28+(x))
 106 #define Port_Pin_Directions(x)          (32+(x))
 107 #define Port_Pin_Mask(x)                (36+(x))
 108 #define Port_Pin_Polarities(x)          (40+(x))
 109
 110 #define Master_Clock_Routing            45
 111 #define RTSIClocking(x)                 (((x)&3)<<4)
 112
 113 #define Group_1_Second_Clear            46      /* W */
 114 #define Group_2_Second_Clear            47      /* W */
 115 #define ClearExpired                            (1<<0)
 116
 117 #define Port_Pattern(x)                 (48+(x))
 118
 119 #define Data_Path                       64
 120 #define FIFOEnableA             (1<<0)
 121 #define FIFOEnableB             (1<<1)
 122 #define FIFOEnableC             (1<<2)
 123 #define FIFOEnableD             (1<<3)
 124 #define Funneling(x)            (((x)&3)<<4)
 125 #define GroupDirection  (1<<7)
 126
 127 #define Protocol_Register_1             65
 128 #define OpMode                          Protocol_Register_1
 129 #define RunMode(x)              ((x)&7)
 130 #define Numbered                (1<<3)
 131
 132 #define Protocol_Register_2             66
 133 #define ClockReg                        Protocol_Register_2
 134 #define ClockLine(x)            (((x)&3)<<5)
 135 #define InvertStopTrig  (1<<7)
 136 #define DataLatching(x)       (((x)&3)<<5)
 137
 138 #define Protocol_Register_3             67
 139 #define Sequence                        Protocol_Register_3
 140
 141 #define Protocol_Register_14            68      /* 16 bit */
 142 #define ClockSpeed                      Protocol_Register_14
 143
 144 #define Protocol_Register_4             70
 145 #define ReqReg                          Protocol_Register_4
 146 #define ReqConditioning(x)      (((x)&7)<<3)
 147
 148 #define Protocol_Register_5             71
 149 #define BlockMode                       Protocol_Register_5
 150
 151 #define FIFO_Control                    72
 152 #define ReadyLevel(x)           ((x)&7)
 153
 154 #define Protocol_Register_6             73
 155 #define LinePolarities                  Protocol_Register_6
 156 #define InvertAck               (1<<0)
 157 #define InvertReq               (1<<1)
 158 #define InvertClock             (1<<2)
 159 #define InvertSerial            (1<<3)
 160 #define OpenAck         (1<<4)
 161 #define OpenClock               (1<<5)
 162
 163 #define Protocol_Register_7             74
 164 #define AckSer                          Protocol_Register_7
 165 #define AckLine(x)              (((x)&3)<<2)
 166 #define ExchangePins            (1<<7)
 167
 168 #define Interrupt_Control               75
 169   /* bits same as flags */
 170
 171 #define DMA_Line_Control_Group1         76
 172 #define DMA_Line_Control_Group2         108
 173 /* channel zero is none */
 174 static inline unsigned primary_DMAChannel_bits(unsigned channel)
 175 {
 176         return channel & 0x3;
 177 }
 178
 179 static inline unsigned secondary_DMAChannel_bits(unsigned channel)
 180 {
 181         return (channel << 2) & 0xc;
 182 }
 183
 184 #define Transfer_Size_Control           77
 185 #define TransferWidth(x)        ((x)&3)
 186 #define TransferLength(x)       (((x)&3)<<3)
 187 #define RequireRLevel           (1<<5)
 188
 189 #define Protocol_Register_15            79
 190 #define DAQOptions                      Protocol_Register_15
 191 #define StartSource(x)                  ((x)&0x3)
 192 #define InvertStart                             (1<<2)
 193 #define StopSource(x)                           (((x)&0x3)<<3)
 194 #define ReqStart                                (1<<6)
 195 #define PreStart                                (1<<7)
 196
 197 #define Pattern_Detection               81
 198 #define DetectionMethod                 (1<<0)
 199 #define InvertMatch                             (1<<1)
 200 #define IE_Pattern_Detection                    (1<<2)
 201
 202 #define Protocol_Register_9             82
 203 #define ReqDelay                        Protocol_Register_9
 204
 205 #define Protocol_Register_10            83
 206 #define ReqNotDelay                     Protocol_Register_10
 207
 208 #define Protocol_Register_11            84
 209 #define AckDelay                        Protocol_Register_11
 210
 211 #define Protocol_Register_12            85
 212 #define AckNotDelay                     Protocol_Register_12
 213
 214 #define Protocol_Register_13            86
 215 #define Data1Delay                      Protocol_Register_13
 216
 217 #define Protocol_Register_8             88      /* 32 bit */
 218 #define StartDelay                      Protocol_Register_8
 219
 220 /* Firmware files for PCI-6524 */
 221 #define FW_PCI_6534_MAIN                "ni6534a.bin"
 222 #define FW_PCI_6534_SCARAB_DI           "niscrb01.bin"
 223 #define FW_PCI_6534_SCARAB_DO           "niscrb02.bin"
 224 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
 225 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
 226 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
 227
 228 enum pci_6534_firmware_registers {      /* 16 bit */
 229         Firmware_Control_Register = 0x100,
 230         Firmware_Status_Register = 0x104,
 231         Firmware_Data_Register = 0x108,
 232         Firmware_Mask_Register = 0x10c,
 233         Firmware_Debug_Register = 0x110,
 234 };
 235 /* main fpga registers (32 bit)*/
 236 enum pci_6534_fpga_registers {
 237         FPGA_Control1_Register = 0x200,
 238         FPGA_Control2_Register = 0x204,
 239         FPGA_Irq_Mask_Register = 0x208,
 240         FPGA_Status_Register = 0x20c,
 241         FPGA_Signature_Register = 0x210,
 242         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
 243         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
 244         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
 245         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
 246         FPGA_Temp_Control_Register = 0x2a0,
 247         FPGA_DAR_Register = 0x2a8,
 248         FPGA_ELC_Read_Register = 0x2b8,
 249         FPGA_ELC_Write_Register = 0x2bc,
 250 };
 251 enum FPGA_Control_Bits {
 252         FPGA_Enable_Bit = 0x8000,
 253 };
 254
 255 #define TIMER_BASE 50           /* nanoseconds */
 256
 257 #ifdef USE_DMA
 258 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
 259 #else
 260 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
 261 #endif
 262
 263 enum nidio_boardid {
 264         BOARD_PCIDIO_32HS,
 265         BOARD_PXI6533,
 266         BOARD_PCI6534,
 267 };
 268
 269 struct nidio_board {
 270         const char *name;
 271         unsigned int uses_firmware:1;
 272 };
 273
 274 static const struct nidio_board nidio_boards[] = {
 275         [BOARD_PCIDIO_32HS] = {
 276                 .name           = "pci-dio-32hs",
 277         },
 278         [BOARD_PXI6533] = {
 279                 .name           = "pxi-6533",
 280         },
 281         [BOARD_PCI6534] = {
 282                 .name           = "pci-6534",
 283                 .uses_firmware  = 1,
 284         },
 285 };
 286
 287 struct nidio96_private {
 288         struct mite_struct *mite;
 289         int boardtype;
 290         int dio;
 291         unsigned short OpModeBits;
 292         struct mite_channel *di_mite_chan;
 293         struct mite_dma_descriptor_ring *di_mite_ring;
 294         spinlock_t mite_channel_lock;
 295 };
 296
 297 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
 298 {
 299         struct nidio96_private *devpriv = dev->private;
 300         unsigned long flags;
 301
 302         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 303         BUG_ON(devpriv->di_mite_chan);
 304         devpriv->di_mite_chan =
 305             mite_request_channel_in_range(devpriv->mite,
 306                                           devpriv->di_mite_ring, 1, 2);
 307         if (devpriv->di_mite_chan == NULL) {
 308                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 309                 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
 310                 return -EBUSY;
 311         }
 312         devpriv->di_mite_chan->dir = COMEDI_INPUT;
 313         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
 314                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
 315                devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 316         mmiowb();
 317         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 318         return 0;
 319 }
 320
 321 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
 322 {
 323         struct nidio96_private *devpriv = dev->private;
 324         unsigned long flags;
 325
 326         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 327         if (devpriv->di_mite_chan) {
 328                 mite_dma_disarm(devpriv->di_mite_chan);
 329                 mite_dma_reset(devpriv->di_mite_chan);
 330                 mite_release_channel(devpriv->di_mite_chan);
 331                 devpriv->di_mite_chan = NULL;
 332                 writeb(primary_DMAChannel_bits(0) |
 333                        secondary_DMAChannel_bits(0),
 334                        devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 335                 mmiowb();
 336         }
 337         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 338 }
 339
 340 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
 341 {
 342         struct nidio96_private *devpriv = dev->private;
 343         int retval;
 344         unsigned long flags;
 345
 346         retval = ni_pcidio_request_di_mite_channel(dev);
 347         if (retval)
 348                 return retval;
 349
 350         /* write alloc the entire buffer */
 351         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
 352
 353         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 354         if (devpriv->di_mite_chan) {
 355                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
 356                 mite_dma_arm(devpriv->di_mite_chan);
 357         } else
 358                 retval = -EIO;
 359         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 360
 361         return retval;
 362 }
 363
 364 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
 365 {
 366         struct nidio96_private *devpriv = dev->private;
 367         unsigned long irq_flags;
 368         int count;
 369
 370         spin_lock_irqsave(&dev->spinlock, irq_flags);
 371         spin_lock(&devpriv->mite_channel_lock);
 372         if (devpriv->di_mite_chan)
 373                 mite_sync_input_dma(devpriv->di_mite_chan, s);
 374         spin_unlock(&devpriv->mite_channel_lock);
 375         count = comedi_buf_n_bytes_ready(s);
 376         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
 377         return count;
 378 }
 379
 380 static irqreturn_t nidio_interrupt(int irq, void *d)
 381 {
 382         struct comedi_device *dev = d;
 383         struct nidio96_private *devpriv = dev->private;
 384         struct comedi_subdevice *s = dev->read_subdev;
 385         struct comedi_async *async = s->async;
 386         struct mite_struct *mite = devpriv->mite;
 387
 388         /* int i, j; */
 389         unsigned int auxdata = 0;
 390         unsigned short data1 = 0;
 391         unsigned short data2 = 0;
 392         int flags;
 393         int status;
 394         int work = 0;
 395         unsigned int m_status = 0;
 396
 397         /* interrupcions parasites */
 398         if (!dev->attached) {
 399                 /* assume it's from another card */
 400                 return IRQ_NONE;
 401         }
 402
 403         /* Lock to avoid race with comedi_poll */
 404         spin_lock(&dev->spinlock);
 405
 406         status = readb(devpriv->mite->daq_io_addr +
 407                        Interrupt_And_Window_Status);
 408         flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 409
 410         spin_lock(&devpriv->mite_channel_lock);
 411         if (devpriv->di_mite_chan)
 412                 m_status = mite_get_status(devpriv->di_mite_chan);
 413
 414         if (m_status & CHSR_INT) {
 415                 if (m_status & CHSR_LINKC) {
 416                         writel(CHOR_CLRLC,
 417                                mite->mite_io_addr +
 418                                MITE_CHOR(devpriv->di_mite_chan->channel));
 419                         mite_sync_input_dma(devpriv->di_mite_chan, s);
 420                         /* XXX need to byteswap */
 421                 }
 422                 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY |
 423                                  CHSR_DRQ1 | CHSR_MRDY)) {
 424                         dev_dbg(dev->class_dev,
 425                                 "unknown mite interrupt, disabling IRQ\n");
 426                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 427                         disable_irq(dev->irq);
 428                 }
 429         }
 430         spin_unlock(&devpriv->mite_channel_lock);
 431
 432         while (status & DataLeft) {
 433                 work++;
 434                 if (work > 20) {
 435                         dev_dbg(dev->class_dev, "too much work in interrupt\n");
 436                         writeb(0x00,
 437                                devpriv->mite->daq_io_addr +
 438                                Master_DMA_And_Interrupt_Control);
 439                         break;
 440                 }
 441
 442                 flags &= IntEn;
 443
 444                 if (flags & TransferReady) {
 445                         while (flags & TransferReady) {
 446                                 work++;
 447                                 if (work > 100) {
 448                                         dev_dbg(dev->class_dev,
 449                                                 "too much work in interrupt\n");
 450                                         writeb(0x00,
 451                                                devpriv->mite->daq_io_addr +
 452                                                Master_DMA_And_Interrupt_Control
 453                                               );
 454                                         goto out;
 455                                 }
 456                                 auxdata =
 457                                     readl(devpriv->mite->daq_io_addr +
 458                                           Group_1_FIFO);
 459                                 data1 = auxdata & 0xffff;
 460                                 data2 = (auxdata & 0xffff0000) >> 16;
 461                                 comedi_buf_put(s, data1);
 462                                 comedi_buf_put(s, data2);
 463                                 flags = readb(devpriv->mite->daq_io_addr +
 464                                               Group_1_Flags);
 465                         }
 466                         async->events |= COMEDI_CB_BLOCK;
 467                 }
 468
 469                 if (flags & CountExpired) {
 470                         writeb(ClearExpired,
 471                                devpriv->mite->daq_io_addr +
 472                                Group_1_Second_Clear);
 473                         async->events |= COMEDI_CB_EOA;
 474
 475                         writeb(0x00, devpriv->mite->daq_io_addr + OpMode);
 476                         break;
 477                 } else if (flags & Waited) {
 478                         writeb(ClearWaited,
 479                                devpriv->mite->daq_io_addr +
 480                                Group_1_First_Clear);
 481                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 482                         break;
 483                 } else if (flags & PrimaryTC) {
 484                         writeb(ClearPrimaryTC,
 485                                devpriv->mite->daq_io_addr +
 486                                Group_1_First_Clear);
 487                         async->events |= COMEDI_CB_EOA;
 488                 } else if (flags & SecondaryTC) {
 489                         writeb(ClearSecondaryTC,
 490                                devpriv->mite->daq_io_addr +
 491                                Group_1_First_Clear);
 492                         async->events |= COMEDI_CB_EOA;
 493                 }
 494
 495                 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 496                 status = readb(devpriv->mite->daq_io_addr +
 497                                Interrupt_And_Window_Status);
 498         }
 499
 500 out:
 501         cfc_handle_events(dev, s);
 502 #if 0
 503         if (!tag) {
 504                 writeb(0x03,
 505                        devpriv->mite->daq_io_addr +
 506                        Master_DMA_And_Interrupt_Control);
 507         }
 508 #endif
 509
 510         spin_unlock(&dev->spinlock);
 511         return IRQ_HANDLED;
 512 }
 513
 514 static int ni_pcidio_insn_config(struct comedi_device *dev,
 515                                  struct comedi_subdevice *s,
 516                                  struct comedi_insn *insn,
 517                                  unsigned int *data)
 518 {
 519         struct nidio96_private *devpriv = dev->private;
 520         int ret;
 521
 522         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
 523         if (ret)
 524                 return ret;
 525
 526         writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
 527
 528         return insn->n;
 529 }
 530
 531 static int ni_pcidio_insn_bits(struct comedi_device *dev,
 532                                struct comedi_subdevice *s,
 533                                struct comedi_insn *insn,
 534                                unsigned int *data)
 535 {
 536         struct nidio96_private *devpriv = dev->private;
 537
 538         if (comedi_dio_update_state(s, data))
 539                 writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0));
 540
 541         data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0));
 542
 543         return insn->n;
 544 }
 545
 546 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
 547 {
 548         int divider, base;
 549
 550         base = TIMER_BASE;
 551
 552         switch (flags & TRIG_ROUND_MASK) {
 553         case TRIG_ROUND_NEAREST:
 554         default:
 555                 divider = (*nanosec + base / 2) / base;
 556                 break;
 557         case TRIG_ROUND_DOWN:
 558                 divider = (*nanosec) / base;
 559                 break;
 560         case TRIG_ROUND_UP:
 561                 divider = (*nanosec + base - 1) / base;
 562                 break;
 563         }
 564
 565         *nanosec = base * divider;
 566         return divider;
 567 }
 568
 569 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 570                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
 571 {
 572         int err = 0;
 573         unsigned int arg;
 574
 575         /* Step 1 : check if triggers are trivially valid */
 576
 577         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
 578         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
 579                                         TRIG_TIMER | TRIG_EXT);
 580         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
 581         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 582         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
 583
 584         if (err)
 585                 return 1;
 586
 587         /* Step 2a : make sure trigger sources are unique */
 588
 589         err |= cfc_check_trigger_is_unique(cmd->start_src);
 590         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
 591         err |= cfc_check_trigger_is_unique(cmd->stop_src);
 592
 593         /* Step 2b : and mutually compatible */
 594
 595         if (err)
 596                 return 2;
 597
 598         /* Step 3: check if arguments are trivially valid */
 599
 600         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
 601
 602 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
 603
 604         if (cmd->scan_begin_src == TRIG_TIMER) {
 605                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
 606                                                  MAX_SPEED);
 607                 /* no minimum speed */
 608         } else {
 609                 /* TRIG_EXT */
 610                 /* should be level/edge, hi/lo specification here */
 611                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
 612                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 613                         err |= -EINVAL;
 614                 }
 615         }
 616
 617         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
 618         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
 619
 620         if (cmd->stop_src == TRIG_COUNT) {
 621                 /* no limit */
 622         } else {        /* TRIG_NONE */
 623                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
 624         }
 625
 626         if (err)
 627                 return 3;
 628
 629         /* step 4: fix up any arguments */
 630
 631         if (cmd->scan_begin_src == TRIG_TIMER) {
 632                 arg = cmd->scan_begin_arg;
 633                 ni_pcidio_ns_to_timer(&arg, cmd->flags);
 634                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
 635         }
 636
 637         if (err)
 638                 return 4;
 639
 640         return 0;
 641 }
 642
 643 static int ni_pcidio_inttrig(struct comedi_device *dev,
 644                              struct comedi_subdevice *s,
 645                              unsigned int trig_num)
 646 {
 647         struct nidio96_private *devpriv = dev->private;
 648         struct comedi_cmd *cmd = &s->async->cmd;
 649
 650         if (trig_num != cmd->start_arg)
 651                 return -EINVAL;
 652
 653         writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode);
 654         s->async->inttrig = NULL;
 655
 656         return 1;
 657 }
 658
 659 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 660 {
 661         struct nidio96_private *devpriv = dev->private;
 662         struct comedi_cmd *cmd = &s->async->cmd;
 663
 664         /* XXX configure ports for input */
 665         writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
 666
 667         if (1) {
 668                 /* enable fifos A B C D */
 669                 writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path);
 670
 671                 /* set transfer width a 32 bits */
 672                 writeb(TransferWidth(0) | TransferLength(0),
 673                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
 674         } else {
 675                 writeb(0x03, devpriv->mite->daq_io_addr + Data_Path);
 676                 writeb(TransferWidth(3) | TransferLength(0),
 677                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
 678         }
 679
 680         /* protocol configuration */
 681         if (cmd->scan_begin_src == TRIG_TIMER) {
 682                 /* page 4-5, "input with internal REQs" */
 683                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
 684                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
 685                 writeb(1, devpriv->mite->daq_io_addr + Sequence);
 686                 writeb(0x04, devpriv->mite->daq_io_addr + ReqReg);
 687                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
 688                 writeb(3, devpriv->mite->daq_io_addr + LinePolarities);
 689                 writeb(0xc0, devpriv->mite->daq_io_addr + AckSer);
 690                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 691                                              TRIG_ROUND_NEAREST),
 692                        devpriv->mite->daq_io_addr + StartDelay);
 693                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
 694                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
 695                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
 696                 writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay);
 697                 writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay);
 698                 /* manual, page 4-5: ClockSpeed comment is incorrectly listed
 699                  * on DAQOptions */
 700                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
 701                 writeb(0, devpriv->mite->daq_io_addr + DAQOptions);
 702         } else {
 703                 /* TRIG_EXT */
 704                 /* page 4-5, "input with external REQs" */
 705                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
 706                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
 707                 writeb(0, devpriv->mite->daq_io_addr + Sequence);
 708                 writeb(0x00, devpriv->mite->daq_io_addr + ReqReg);
 709                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
 710                 if (!(cmd->scan_begin_arg & CR_INVERT)) {
 711                         /* Leading Edge pulse mode */
 712                         writeb(0, devpriv->mite->daq_io_addr + LinePolarities);
 713                 } else {
 714                         /* Trailing Edge pulse mode */
 715                         writeb(2, devpriv->mite->daq_io_addr + LinePolarities);
 716                 }
 717                 writeb(0x00, devpriv->mite->daq_io_addr + AckSer);
 718                 writel(1, devpriv->mite->daq_io_addr + StartDelay);
 719                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
 720                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
 721                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
 722                 writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay);
 723                 writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay);
 724                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
 725                 writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions);
 726         }
 727
 728         if (cmd->stop_src == TRIG_COUNT) {
 729                 writel(cmd->stop_arg,
 730                        devpriv->mite->daq_io_addr + Transfer_Count);
 731         } else {
 732                 /* XXX */
 733         }
 734
 735 #ifdef USE_DMA
 736         writeb(ClearPrimaryTC | ClearSecondaryTC,
 737                devpriv->mite->daq_io_addr + Group_1_First_Clear);
 738
 739         {
 740                 int retval = setup_mite_dma(dev, s);
 741
 742                 if (retval)
 743                         return retval;
 744         }
 745 #else
 746         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 747 #endif
 748         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2);
 749
 750         /* clear and enable interrupts */
 751         writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear);
 752         /* writeb(ClearExpired,
 753                devpriv->mite->daq_io_addr+Group_1_Second_Clear); */
 754
 755         writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control);
 756         writeb(0x03,
 757                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
 758
 759         if (cmd->stop_src == TRIG_NONE) {
 760                 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
 761         } else {                /* TRIG_TIMER */
 762                 devpriv->OpModeBits = Numbered | RunMode(7);
 763         }
 764         if (cmd->start_src == TRIG_NOW) {
 765                 /* start */
 766                 writeb(devpriv->OpModeBits,
 767                        devpriv->mite->daq_io_addr + OpMode);
 768                 s->async->inttrig = NULL;
 769         } else {
 770                 /* TRIG_INT */
 771                 s->async->inttrig = ni_pcidio_inttrig;
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int ni_pcidio_cancel(struct comedi_device *dev,
 778                             struct comedi_subdevice *s)
 779 {
 780         struct nidio96_private *devpriv = dev->private;
 781
 782         writeb(0x00,
 783                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
 784         ni_pcidio_release_di_mite_channel(dev);
 785
 786         return 0;
 787 }
 788
 789 static int ni_pcidio_change(struct comedi_device *dev,
 790                             struct comedi_subdevice *s)
 791 {
 792         struct nidio96_private *devpriv = dev->private;
 793         int ret;
 794
 795         ret = mite_buf_change(devpriv->di_mite_ring, s);
 796         if (ret < 0)
 797                 return ret;
 798
 799         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
 800
 801         return 0;
 802 }
 803
 804 static int pci_6534_load_fpga(struct comedi_device *dev,
 805                               const u8 *data, size_t data_len,
 806                               unsigned long context)
 807 {
 808         struct nidio96_private *devpriv = dev->private;
 809         static const int timeout = 1000;
 810         int fpga_index = context;
 811         int i;
 812         size_t j;
 813
 814         writew(0x80 | fpga_index,
 815                devpriv->mite->daq_io_addr + Firmware_Control_Register);
 816         writew(0xc0 | fpga_index,
 817                devpriv->mite->daq_io_addr + Firmware_Control_Register);
 818         for (i = 0;
 819              (readw(devpriv->mite->daq_io_addr +
 820                     Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i) {
 821                 udelay(1);
 822         }
 823         if (i == timeout) {
 824                 dev_warn(dev->class_dev,
 825                          "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
 826                          fpga_index);
 827                 return -EIO;
 828         }
 829         writew(0x80 | fpga_index,
 830                devpriv->mite->daq_io_addr + Firmware_Control_Register);
 831         for (i = 0;
 832              readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) !=
 833              0x3 && i < timeout; ++i) {
 834                 udelay(1);
 835         }
 836         if (i == timeout) {
 837                 dev_warn(dev->class_dev,
 838                          "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
 839                          fpga_index);
 840                 return -EIO;
 841         }
 842         for (j = 0; j + 1 < data_len;) {
 843                 unsigned int value = data[j++];
 844
 845                 value |= data[j++] << 8;
 846                 writew(value,
 847                        devpriv->mite->daq_io_addr + Firmware_Data_Register);
 848                 for (i = 0;
 849                      (readw(devpriv->mite->daq_io_addr +
 850                             Firmware_Status_Register) & 0x2) == 0
 851                      && i < timeout; ++i) {
 852                         udelay(1);
 853                 }
 854                 if (i == timeout) {
 855                         dev_warn(dev->class_dev,
 856                                  "ni_pcidio: failed to load word into fpga %i\n",
 857                                  fpga_index);
 858                         return -EIO;
 859                 }
 860                 if (need_resched())
 861                         schedule();
 862         }
 863         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
 864         return 0;
 865 }
 866
 867 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
 868 {
 869         return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
 870 }
 871
 872 static int pci_6534_reset_fpgas(struct comedi_device *dev)
 873 {
 874         struct nidio96_private *devpriv = dev->private;
 875         int ret;
 876         int i;
 877
 878         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
 879         for (i = 0; i < 3; ++i) {
 880                 ret = pci_6534_reset_fpga(dev, i);
 881                 if (ret < 0)
 882                         break;
 883         }
 884         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register);
 885         return ret;
 886 }
 887
 888 static void pci_6534_init_main_fpga(struct comedi_device *dev)
 889 {
 890         struct nidio96_private *devpriv = dev->private;
 891
 892         writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register);
 893         writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register);
 894         writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register);
 895         writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register);
 896         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register);
 897         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register);
 898 }
 899
 900 static int pci_6534_upload_firmware(struct comedi_device *dev)
 901 {
 902         struct nidio96_private *devpriv = dev->private;
 903         static const char *const fw_file[3] = {
 904                 FW_PCI_6534_SCARAB_DI,  /* loaded into scarab A for DI */
 905                 FW_PCI_6534_SCARAB_DO,  /* loaded into scarab B for DO */
 906                 FW_PCI_6534_MAIN,       /* loaded into main FPGA */
 907         };
 908         int ret;
 909         int n;
 910
 911         ret = pci_6534_reset_fpgas(dev);
 912         if (ret < 0)
 913                 return ret;
 914         /* load main FPGA first, then the two scarabs */
 915         for (n = 2; n >= 0; n--) {
 916                 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
 917                                            fw_file[n],
 918                                            pci_6534_load_fpga, n);
 919                 if (ret == 0 && n == 2)
 920                         pci_6534_init_main_fpga(dev);
 921                 if (ret < 0)
 922                         break;
 923         }
 924         return ret;
 925 }
 926
 927 static void nidio_reset_board(struct comedi_device *dev)
 928 {
 929         struct nidio96_private *devpriv = dev->private;
 930         void __iomem *daq_mmio = devpriv->mite->daq_io_addr;
 931
 932         writel(0, daq_mmio + Port_IO(0));
 933         writel(0, daq_mmio + Port_Pin_Directions(0));
 934         writel(0, daq_mmio + Port_Pin_Mask(0));
 935
 936         /* disable interrupts on board */
 937         writeb(0, daq_mmio + Master_DMA_And_Interrupt_Control);
 938 }
 939
 940 static int nidio_auto_attach(struct comedi_device *dev,
 941                              unsigned long context)
 942 {
 943         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 944         const struct nidio_board *board = NULL;
 945         struct nidio96_private *devpriv;
 946         struct comedi_subdevice *s;
 947         int ret;
 948         unsigned int irq;
 949
 950         if (context < ARRAY_SIZE(nidio_boards))
 951                 board = &nidio_boards[context];
 952         if (!board)
 953                 return -ENODEV;
 954         dev->board_ptr = board;
 955         dev->board_name = board->name;
 956
 957         ret = comedi_pci_enable(dev);
 958         if (ret)
 959                 return ret;
 960
 961         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 962         if (!devpriv)
 963                 return -ENOMEM;
 964
 965         spin_lock_init(&devpriv->mite_channel_lock);
 966
 967         devpriv->mite = mite_alloc(pcidev);
 968         if (!devpriv->mite)
 969                 return -ENOMEM;
 970
 971         ret = mite_setup(dev, devpriv->mite);
 972         if (ret < 0)
 973                 return ret;
 974
 975         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
 976         if (devpriv->di_mite_ring == NULL)
 977                 return -ENOMEM;
 978
 979         if (board->uses_firmware) {
 980                 ret = pci_6534_upload_firmware(dev);
 981                 if (ret < 0)
 982                         return ret;
 983         }
 984
 985         nidio_reset_board(dev);
 986
 987         ret = comedi_alloc_subdevices(dev, 1);
 988         if (ret)
 989                 return ret;
 990
 991         dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
 992                  readb(devpriv->mite->daq_io_addr + Chip_Version));
 993
 994         s = &dev->subdevices[0];
 995
 996         dev->read_subdev = s;
 997         s->type = COMEDI_SUBD_DIO;
 998         s->subdev_flags =
 999                 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
1000                 SDF_CMD_READ;
1001         s->n_chan = 32;
1002         s->range_table = &range_digital;
1003         s->maxdata = 1;
1004         s->insn_config = &ni_pcidio_insn_config;
1005         s->insn_bits = &ni_pcidio_insn_bits;
1006         s->do_cmd = &ni_pcidio_cmd;
1007         s->do_cmdtest = &ni_pcidio_cmdtest;
1008         s->cancel = &ni_pcidio_cancel;
1009         s->len_chanlist = 32;   /* XXX */
1010         s->buf_change = &ni_pcidio_change;
1011         s->async_dma_dir = DMA_BIDIRECTIONAL;
1012         s->poll = &ni_pcidio_poll;
1013
1014         irq = pcidev->irq;
1015         if (irq) {
1016                 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
1017                                   dev->board_name, dev);
1018                 if (ret == 0)
1019                         dev->irq = irq;
1020         }
1021
1022         return 0;
1023 }
1024
1025 static void nidio_detach(struct comedi_device *dev)
1026 {
1027         struct nidio96_private *devpriv = dev->private;
1028
1029         if (dev->irq)
1030                 free_irq(dev->irq, dev);
1031         if (devpriv) {
1032                 if (devpriv->di_mite_ring) {
1033                         mite_free_ring(devpriv->di_mite_ring);
1034                         devpriv->di_mite_ring = NULL;
1035                 }
1036                 mite_detach(devpriv->mite);
1037         }
1038         comedi_pci_disable(dev);
1039 }
1040
1041 static struct comedi_driver ni_pcidio_driver = {
1042         .driver_name    = "ni_pcidio",
1043         .module         = THIS_MODULE,
1044         .auto_attach    = nidio_auto_attach,
1045         .detach         = nidio_detach,
1046 };
1047
1048 static int ni_pcidio_pci_probe(struct pci_dev *dev,
1049                                const struct pci_device_id *id)
1050 {
1051         return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
1052 }
1053
1054 static const struct pci_device_id ni_pcidio_pci_table[] = {
1055         { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
1056         { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
1057         { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
1058         { 0 }
1059 };
1060 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1061
1062 static struct pci_driver ni_pcidio_pci_driver = {
1063         .name           = "ni_pcidio",
1064         .id_table       = ni_pcidio_pci_table,
1065         .probe          = ni_pcidio_pci_probe,
1066         .remove         = comedi_pci_auto_unconfig,
1067 };
1068 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1069
1070 MODULE_AUTHOR("Comedi http://www.comedi.org");
1071 MODULE_DESCRIPTION("Comedi low-level driver");
1072 MODULE_LICENSE("GPL");