2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: National Instruments PCI-MIO-E series and M series (all boards)
21 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
22 Herman Bruyninckx, Terry Barnaby
24 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
25 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
26 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
27 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
28 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
29 PCI-6225, PXI-6225, PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PXIe-6251,
30 PCI-6254, PCI-6259, PCIe-6259,
31 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
32 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
33 PXI-6071E, PCI-6070E, PXI-6070E,
34 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
36 Updated: Mon, 09 Jan 2012 14:52:48 +0000
38 These boards are almost identical to the AT-MIO E series, except that
39 they use the PCI bus instead of ISA (i.e., AT). See the notes for
40 the ni_atmio.o driver for additional information about these boards.
42 Autocalibration is supported on many of the devices, using the
43 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
44 M-Series boards do analog input and analog output calibration entirely
45 in software. The software calibration corrects
46 the analog input for offset, gain and
47 nonlinearity. The analog outputs are corrected for offset and gain.
48 See the comedilib documentation on comedi_get_softcal_converter() for
51 By default, the driver uses DMA to transfer analog input data to
52 memory. When DMA is enabled, not all triggering features are
55 Digital I/O may not work on 673x.
57 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
58 With this board all of the convertors perform one simultaineous sample during
59 a scan interval. The period for a scan is used for the convert time in a
60 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
62 The RTSI trigger bus is supported on these cards on
63 subdevice 10. See the comedilib documentation for details.
65 Information (number of channels, bits, etc.) for some devices may be
66 incorrect. Please check this and submit a bug if there are problems
69 SCXI is probably broken for m-series boards.
72 - When DMA is enabled, COMEDI_EV_CONVERT does
77 The PCI-MIO E series driver was originally written by
78 Tomasz Motylewski <...>, and ported to comedi by ds.
82 341079b.pdf PCI E Series Register-Level Programmer Manual
83 340934b.pdf DAQ-STC reference manual
85 322080b.pdf 6711/6713/6715 User Manual
87 320945c.pdf PCI E Series User Manual
88 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
92 need to deal with external reference for DAC, and other DAC
93 properties in board properties
95 deal with at-mio-16de-10 revision D to N changes, etc.
97 need to add other CALDAC type
99 need to slow down DAC loading. I don't trust NI's claim that
100 two writes to the PCI bus slows IO enough. I would prefer to
101 use udelay(). Timing specs: (clock)
109 #include <linux/module.h>
110 #include <linux/delay.h>
112 #include "../comedidev.h"
114 #include <asm/byteorder.h>
124 #define MAX_N_CALDACS (16+16+2)
126 #define DRV_NAME "ni_pcimio"
128 /* These are not all the possible ao ranges for 628x boards.
129 They can do OFFSET +- REFERENCE where OFFSET can be
130 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
131 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
132 63 different possibilities. An AO channel
133 can not act as it's own OFFSET or REFERENCE.
135 static const struct comedi_lrange range_ni_M_628x_ao = {
149 static const struct comedi_lrange range_ni_M_625x_ao = {
157 enum ni_pcimio_boardid {
158 BOARD_PCIMIO_16XE_50,
159 BOARD_PCIMIO_16XE_10,
217 static const struct ni_board_struct ni_boards[] = {
218 [BOARD_PCIMIO_16XE_50] = {
219 .name = "pci-mio-16xe-50",
222 .ai_fifo_depth = 2048,
224 .gainlkup = ai_gain_8,
228 .ao_range_table = &range_bipolar10,
230 .num_p0_dio_channels = 8,
231 .caldac = { dac8800, dac8043 },
233 [BOARD_PCIMIO_16XE_10] = {
234 .name = "pci-mio-16xe-10", /* aka pci-6030E */
237 .ai_fifo_depth = 512,
239 .gainlkup = ai_gain_14,
243 .ao_fifo_depth = 2048,
244 .ao_range_table = &range_ni_E_ao_ext,
247 .num_p0_dio_channels = 8,
248 .caldac = { dac8800, dac8043, ad8522 },
254 .ai_fifo_depth = 512,
256 .gainlkup = ai_gain_4,
260 .ao_range_table = &range_bipolar10,
262 .num_p0_dio_channels = 8,
263 .caldac = { ad8804_debug },
269 .ai_fifo_depth = 512,
271 .gainlkup = ai_gain_14,
275 .ao_fifo_depth = 2048,
276 .ao_range_table = &range_ni_E_ao_ext,
279 .num_p0_dio_channels = 8,
280 .caldac = { dac8800, dac8043, ad8522 },
282 [BOARD_PCIMIO_16E_1] = {
283 .name = "pci-mio-16e-1", /* aka pci-6070e */
286 .ai_fifo_depth = 512,
287 .gainlkup = ai_gain_16,
291 .ao_fifo_depth = 2048,
292 .ao_range_table = &range_ni_E_ao_ext,
295 .num_p0_dio_channels = 8,
296 .caldac = { mb88341 },
298 [BOARD_PCIMIO_16E_4] = {
299 .name = "pci-mio-16e-4", /* aka pci-6040e */
302 .ai_fifo_depth = 512,
303 .gainlkup = ai_gain_16,
305 * there have been reported problems with
306 * full speed on this board
311 .ao_fifo_depth = 512,
312 .ao_range_table = &range_ni_E_ao_ext,
315 .num_p0_dio_channels = 8,
316 .caldac = { ad8804_debug }, /* doc says mb88341 */
322 .ai_fifo_depth = 512,
323 .gainlkup = ai_gain_16,
327 .ao_fifo_depth = 512,
328 .ao_range_table = &range_ni_E_ao_ext,
331 .num_p0_dio_channels = 8,
332 .caldac = { mb88341 },
338 .ai_fifo_depth = 512,
340 .gainlkup = ai_gain_14,
344 .ao_fifo_depth = 2048,
345 .ao_range_table = &range_ni_E_ao_ext,
348 .num_p0_dio_channels = 8,
349 .caldac = { dac8800, dac8043, ad8522 },
355 .ai_fifo_depth = 512,
357 .gainlkup = ai_gain_14,
359 .num_p0_dio_channels = 8,
360 .caldac = { dac8800, dac8043, ad8522 },
366 .ai_fifo_depth = 512,
368 .gainlkup = ai_gain_14,
370 .num_p0_dio_channels = 8,
371 .caldac = { dac8800, dac8043, ad8522 },
377 .ai_fifo_depth = 512,
379 .gainlkup = ai_gain_16,
383 .ao_fifo_depth = 2048,
384 .ao_range_table = &range_ni_E_ao_ext,
387 .num_p0_dio_channels = 8,
388 .caldac = { ad8804_debug },
394 .ai_fifo_depth = 512,
395 .gainlkup = ai_gain_4,
397 .num_p0_dio_channels = 8,
398 .caldac = { ad8804_debug }, /* manual is wrong */
404 .ai_fifo_depth = 512,
405 .gainlkup = ai_gain_4,
409 .ao_range_table = &range_bipolar10,
411 .num_p0_dio_channels = 8,
412 .caldac = { ad8804_debug }, /* manual is wrong */
418 .ai_fifo_depth = 512,
419 .gainlkup = ai_gain_4,
423 .ao_range_table = &range_bipolar10,
425 .num_p0_dio_channels = 8,
426 .caldac = { ad8804_debug }, /* manual is wrong */
433 .ai_fifo_depth = 512,
434 .gainlkup = ai_gain_4,
438 .ao_range_table = &range_ni_E_ao_ext,
441 .num_p0_dio_channels = 8,
442 .caldac = { ad8804_debug }, /* manual is wrong */
449 .ai_fifo_depth = 512,
451 .gainlkup = ai_gain_4,
453 .num_p0_dio_channels = 8,
454 .caldac = { ad8804_debug },
460 .ai_fifo_depth = 512,
462 .gainlkup = ai_gain_4,
466 .ao_range_table = &range_bipolar10,
468 .num_p0_dio_channels = 8,
469 .caldac = { ad8804_debug },
475 .ai_fifo_depth = 512,
477 .gainlkup = ai_gain_16,
482 .ao_fifo_depth = 2048,
483 .ao_range_table = &range_ni_E_ao_ext,
485 .num_p0_dio_channels = 8,
486 /* manual is wrong */
487 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
493 .ai_fifo_depth = 8192,
495 .gainlkup = ai_gain_611x,
499 .reg_type = ni_reg_611x,
500 .ao_range_table = &range_bipolar10,
501 .ao_fifo_depth = 2048,
503 .num_p0_dio_channels = 8,
504 .caldac = { ad8804, ad8804 },
510 .ai_fifo_depth = 8192,
511 .gainlkup = ai_gain_611x,
515 .reg_type = ni_reg_611x,
516 .ao_range_table = &range_bipolar10,
517 .ao_fifo_depth = 2048,
519 .num_p0_dio_channels = 8,
520 .caldac = { ad8804, ad8804 },
523 /* The 6115 boards probably need their own driver */
524 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
528 .ai_fifo_depth = 8192,
529 .gainlkup = ai_gain_611x,
534 .ao_fifo_depth = 2048,
536 .num_p0_dio_channels = 8,
539 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
543 [BOARD_PXI6115] = { /* .device_id = ????, */
547 .ai_fifo_depth = 8192,
548 .gainlkup = ai_gain_611x,
553 .ao_fifo_depth = 2048,
556 .num_p0_dio_channels = 8,
558 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
565 /* data sheet says 8192, but fifo really holds 16384 samples */
566 .ao_fifo_depth = 16384,
567 .ao_range_table = &range_bipolar10,
569 .num_p0_dio_channels = 8,
570 .reg_type = ni_reg_6711,
571 .caldac = { ad8804_debug },
577 .ao_fifo_depth = 16384,
578 .ao_range_table = &range_bipolar10,
580 .num_p0_dio_channels = 8,
581 .reg_type = ni_reg_6711,
582 .caldac = { ad8804_debug },
588 .ao_fifo_depth = 16384,
589 .ao_range_table = &range_bipolar10,
591 .num_p0_dio_channels = 8,
592 .reg_type = ni_reg_6713,
593 .caldac = { ad8804_debug, ad8804_debug },
599 .ao_fifo_depth = 16384,
600 .ao_range_table = &range_bipolar10,
602 .num_p0_dio_channels = 8,
603 .reg_type = ni_reg_6713,
604 .caldac = { ad8804_debug, ad8804_debug },
610 .ao_fifo_depth = 8192,
611 .ao_range_table = &range_bipolar10,
613 .num_p0_dio_channels = 8,
614 .reg_type = ni_reg_6711,
615 .caldac = { ad8804_debug },
618 [BOARD_PXI6731] = { /* .device_id = ????, */
622 .ao_fifo_depth = 8192,
623 .ao_range_table = &range_bipolar10,
624 .num_p0_dio_channels = 8,
625 .reg_type = ni_reg_6711,
626 .caldac = { ad8804_debug },
633 .ao_fifo_depth = 16384,
634 .ao_range_table = &range_bipolar10,
636 .num_p0_dio_channels = 8,
637 .reg_type = ni_reg_6713,
638 .caldac = { ad8804_debug, ad8804_debug },
644 .ao_fifo_depth = 16384,
645 .ao_range_table = &range_bipolar10,
647 .num_p0_dio_channels = 8,
648 .reg_type = ni_reg_6713,
649 .caldac = { ad8804_debug, ad8804_debug },
655 .ai_fifo_depth = 512,
657 .gainlkup = ai_gain_16,
661 .ao_fifo_depth = 2048,
662 .ao_range_table = &range_ni_E_ao_ext,
665 .num_p0_dio_channels = 8,
666 .caldac = { ad8804_debug },
672 .ai_fifo_depth = 512,
674 .gainlkup = ai_gain_16,
678 .ao_fifo_depth = 2048,
679 .ao_range_table = &range_ni_E_ao_ext,
682 .num_p0_dio_channels = 8,
683 .caldac = { ad8804_debug },
689 .ai_fifo_depth = 512,
691 .gainlkup = ai_gain_16,
696 .ao_fifo_depth = 2048,
697 .ao_range_table = &range_ni_E_ao_ext,
699 .num_p0_dio_channels = 8,
700 .caldac = { mb88341, mb88341, ad8522 },
706 .ai_fifo_depth = 512,
708 .gainlkup = ai_gain_14,
712 .ao_fifo_depth = 2048,
713 .ao_range_table = &range_ni_E_ao_ext,
716 .num_p0_dio_channels = 8,
717 .caldac = { dac8800, dac8043, ad8522 },
723 .ai_fifo_depth = 512,
725 .gainlkup = ai_gain_4,
729 .ao_range_table = &range_bipolar10,
731 .num_p0_dio_channels = 8,
732 .caldac = { ad8804_debug },
738 .ai_fifo_depth = 512, /* FIXME: guess */
739 .gainlkup = ai_gain_622x,
741 .num_p0_dio_channels = 8,
742 .reg_type = ni_reg_622x,
743 .caldac = { caldac_none },
749 .ai_fifo_depth = 4095,
750 .gainlkup = ai_gain_622x,
754 .ao_fifo_depth = 8191,
755 .ao_range_table = &range_bipolar10,
756 .reg_type = ni_reg_622x,
758 .num_p0_dio_channels = 8,
759 .caldac = { caldac_none },
761 [BOARD_PCI6221_37PIN] = {
762 .name = "pci-6221_37pin",
765 .ai_fifo_depth = 4095,
766 .gainlkup = ai_gain_622x,
770 .ao_fifo_depth = 8191,
771 .ao_range_table = &range_bipolar10,
772 .reg_type = ni_reg_622x,
774 .num_p0_dio_channels = 8,
775 .caldac = { caldac_none },
781 .ai_fifo_depth = 4095,
782 .gainlkup = ai_gain_622x,
784 .reg_type = ni_reg_622x,
785 .num_p0_dio_channels = 32,
786 .caldac = { caldac_none },
792 .ai_fifo_depth = 4095,
793 .gainlkup = ai_gain_622x,
795 .reg_type = ni_reg_622x,
796 .num_p0_dio_channels = 32,
797 .caldac = { caldac_none },
803 .ai_fifo_depth = 4095,
804 .gainlkup = ai_gain_622x,
808 .ao_fifo_depth = 8191,
809 .ao_range_table = &range_bipolar10,
810 .reg_type = ni_reg_622x,
812 .num_p0_dio_channels = 32,
813 .caldac = { caldac_none },
819 .ai_fifo_depth = 4095,
820 .gainlkup = ai_gain_622x,
824 .ao_fifo_depth = 8191,
825 .ao_range_table = &range_bipolar10,
826 .reg_type = ni_reg_622x,
828 .num_p0_dio_channels = 32,
829 .caldac = { caldac_none },
835 .ai_fifo_depth = 4095,
836 .gainlkup = ai_gain_622x,
840 .ao_fifo_depth = 8191,
841 .ao_range_table = &range_bipolar10,
842 .reg_type = ni_reg_622x,
844 .num_p0_dio_channels = 32,
845 .caldac = { caldac_none },
851 .ai_fifo_depth = 4095,
852 .gainlkup = ai_gain_628x,
854 .reg_type = ni_reg_625x,
855 .num_p0_dio_channels = 8,
856 .caldac = { caldac_none },
862 .ai_fifo_depth = 4095,
863 .gainlkup = ai_gain_628x,
867 .ao_fifo_depth = 8191,
868 .ao_range_table = &range_ni_M_625x_ao,
869 .reg_type = ni_reg_625x,
871 .num_p0_dio_channels = 8,
872 .caldac = { caldac_none },
878 .ai_fifo_depth = 4095,
879 .gainlkup = ai_gain_628x,
883 .ao_fifo_depth = 8191,
884 .ao_range_table = &range_ni_M_625x_ao,
885 .reg_type = ni_reg_625x,
887 .num_p0_dio_channels = 8,
888 .caldac = { caldac_none },
894 .ai_fifo_depth = 4095,
895 .gainlkup = ai_gain_628x,
899 .ao_fifo_depth = 8191,
900 .ao_range_table = &range_ni_M_625x_ao,
901 .reg_type = ni_reg_625x,
903 .num_p0_dio_channels = 8,
904 .caldac = { caldac_none },
910 .ai_fifo_depth = 4095,
911 .gainlkup = ai_gain_628x,
913 .reg_type = ni_reg_625x,
914 .num_p0_dio_channels = 32,
915 .caldac = { caldac_none },
921 .ai_fifo_depth = 4095,
922 .gainlkup = ai_gain_628x,
926 .ao_fifo_depth = 8191,
927 .ao_range_table = &range_ni_M_625x_ao,
928 .reg_type = ni_reg_625x,
930 .num_p0_dio_channels = 32,
931 .caldac = { caldac_none },
937 .ai_fifo_depth = 4095,
938 .gainlkup = ai_gain_628x,
942 .ao_fifo_depth = 8191,
943 .ao_range_table = &range_ni_M_625x_ao,
944 .reg_type = ni_reg_625x,
946 .num_p0_dio_channels = 32,
947 .caldac = { caldac_none },
953 .ai_fifo_depth = 2047,
954 .gainlkup = ai_gain_628x,
956 .ao_fifo_depth = 8191,
957 .reg_type = ni_reg_628x,
958 .num_p0_dio_channels = 8,
959 .caldac = { caldac_none },
965 .ai_fifo_depth = 2047,
966 .gainlkup = ai_gain_628x,
970 .ao_fifo_depth = 8191,
971 .ao_range_table = &range_ni_M_628x_ao,
972 .reg_type = ni_reg_628x,
975 .num_p0_dio_channels = 8,
976 .caldac = { caldac_none },
982 .ai_fifo_depth = 2047,
983 .gainlkup = ai_gain_628x,
987 .ao_fifo_depth = 8191,
988 .ao_range_table = &range_ni_M_628x_ao,
989 .reg_type = ni_reg_628x,
992 .num_p0_dio_channels = 8,
993 .caldac = { caldac_none },
999 .ai_fifo_depth = 2047,
1000 .gainlkup = ai_gain_628x,
1002 .reg_type = ni_reg_628x,
1003 .num_p0_dio_channels = 32,
1004 .caldac = { caldac_none },
1010 .ai_fifo_depth = 2047,
1011 .gainlkup = ai_gain_628x,
1015 .ao_fifo_depth = 8191,
1016 .ao_range_table = &range_ni_M_628x_ao,
1017 .reg_type = ni_reg_628x,
1020 .num_p0_dio_channels = 32,
1021 .caldac = { caldac_none },
1027 .ai_fifo_depth = 1024,
1028 .gainlkup = ai_gain_6143,
1030 .reg_type = ni_reg_6143,
1031 .num_p0_dio_channels = 8,
1032 .caldac = { ad8804_debug, ad8804_debug },
1038 .ai_fifo_depth = 1024,
1039 .gainlkup = ai_gain_6143,
1041 .reg_type = ni_reg_6143,
1042 .num_p0_dio_channels = 8,
1043 .caldac = { ad8804_debug, ad8804_debug },
1050 /* How we access registers */
1052 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1053 #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1054 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1055 #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1056 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1057 #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1059 /* How we access STC registers */
1061 /* We automatically take advantage of STC registers that can be
1062 * read/written directly in the I/O space of the board. Most
1063 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1064 * The 611x devices map the write registers to iobase+addr*2, and
1065 * the read registers to iobase+(addr-1)*2. */
1066 /* However, the 611x boards still aren't working, so I'm disabling
1067 * non-windowed STC access temporarily */
1069 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1071 struct ni_private *devpriv = dev->private;
1072 unsigned long flags;
1074 spin_lock_irqsave(&devpriv->window_lock, flags);
1075 ni_writew(reg, Window_Address);
1076 ni_writew(data, Window_Data);
1077 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1080 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1082 struct ni_private *devpriv = dev->private;
1083 unsigned long flags;
1086 spin_lock_irqsave(&devpriv->window_lock, flags);
1087 ni_writew(reg, Window_Address);
1088 ret = ni_readw(Window_Data);
1089 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1094 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1097 struct ni_private *devpriv = dev->private;
1101 case ADC_FIFO_Clear:
1102 offset = M_Offset_AI_FIFO_Clear;
1104 case AI_Command_1_Register:
1105 offset = M_Offset_AI_Command_1;
1107 case AI_Command_2_Register:
1108 offset = M_Offset_AI_Command_2;
1110 case AI_Mode_1_Register:
1111 offset = M_Offset_AI_Mode_1;
1113 case AI_Mode_2_Register:
1114 offset = M_Offset_AI_Mode_2;
1116 case AI_Mode_3_Register:
1117 offset = M_Offset_AI_Mode_3;
1119 case AI_Output_Control_Register:
1120 offset = M_Offset_AI_Output_Control;
1122 case AI_Personal_Register:
1123 offset = M_Offset_AI_Personal;
1125 case AI_SI2_Load_A_Register:
1126 /* this is actually a 32 bit register on m series boards */
1127 ni_writel(data, M_Offset_AI_SI2_Load_A);
1130 case AI_SI2_Load_B_Register:
1131 /* this is actually a 32 bit register on m series boards */
1132 ni_writel(data, M_Offset_AI_SI2_Load_B);
1135 case AI_START_STOP_Select_Register:
1136 offset = M_Offset_AI_START_STOP_Select;
1138 case AI_Trigger_Select_Register:
1139 offset = M_Offset_AI_Trigger_Select;
1141 case Analog_Trigger_Etc_Register:
1142 offset = M_Offset_Analog_Trigger_Etc;
1144 case AO_Command_1_Register:
1145 offset = M_Offset_AO_Command_1;
1147 case AO_Command_2_Register:
1148 offset = M_Offset_AO_Command_2;
1150 case AO_Mode_1_Register:
1151 offset = M_Offset_AO_Mode_1;
1153 case AO_Mode_2_Register:
1154 offset = M_Offset_AO_Mode_2;
1156 case AO_Mode_3_Register:
1157 offset = M_Offset_AO_Mode_3;
1159 case AO_Output_Control_Register:
1160 offset = M_Offset_AO_Output_Control;
1162 case AO_Personal_Register:
1163 offset = M_Offset_AO_Personal;
1165 case AO_Start_Select_Register:
1166 offset = M_Offset_AO_Start_Select;
1168 case AO_Trigger_Select_Register:
1169 offset = M_Offset_AO_Trigger_Select;
1171 case Clock_and_FOUT_Register:
1172 offset = M_Offset_Clock_and_FOUT;
1174 case Configuration_Memory_Clear:
1175 offset = M_Offset_Configuration_Memory_Clear;
1177 case DAC_FIFO_Clear:
1178 offset = M_Offset_AO_FIFO_Clear;
1180 case DIO_Control_Register:
1181 dev_dbg(dev->class_dev,
1182 "%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1186 case G_Autoincrement_Register(0):
1187 offset = M_Offset_G0_Autoincrement;
1189 case G_Autoincrement_Register(1):
1190 offset = M_Offset_G1_Autoincrement;
1192 case G_Command_Register(0):
1193 offset = M_Offset_G0_Command;
1195 case G_Command_Register(1):
1196 offset = M_Offset_G1_Command;
1198 case G_Input_Select_Register(0):
1199 offset = M_Offset_G0_Input_Select;
1201 case G_Input_Select_Register(1):
1202 offset = M_Offset_G1_Input_Select;
1204 case G_Mode_Register(0):
1205 offset = M_Offset_G0_Mode;
1207 case G_Mode_Register(1):
1208 offset = M_Offset_G1_Mode;
1210 case Interrupt_A_Ack_Register:
1211 offset = M_Offset_Interrupt_A_Ack;
1213 case Interrupt_A_Enable_Register:
1214 offset = M_Offset_Interrupt_A_Enable;
1216 case Interrupt_B_Ack_Register:
1217 offset = M_Offset_Interrupt_B_Ack;
1219 case Interrupt_B_Enable_Register:
1220 offset = M_Offset_Interrupt_B_Enable;
1222 case Interrupt_Control_Register:
1223 offset = M_Offset_Interrupt_Control;
1225 case IO_Bidirection_Pin_Register:
1226 offset = M_Offset_IO_Bidirection_Pin;
1228 case Joint_Reset_Register:
1229 offset = M_Offset_Joint_Reset;
1231 case RTSI_Trig_A_Output_Register:
1232 offset = M_Offset_RTSI_Trig_A_Output;
1234 case RTSI_Trig_B_Output_Register:
1235 offset = M_Offset_RTSI_Trig_B_Output;
1237 case RTSI_Trig_Direction_Register:
1238 offset = M_Offset_RTSI_Trig_Direction;
1240 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1241 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1243 dev_warn(dev->class_dev,
1244 "%s: bug! unhandled register=0x%x in switch.\n",
1250 ni_writew(data, offset);
1253 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1255 struct ni_private *devpriv = dev->private;
1259 case AI_Status_1_Register:
1260 offset = M_Offset_AI_Status_1;
1262 case AO_Status_1_Register:
1263 offset = M_Offset_AO_Status_1;
1265 case AO_Status_2_Register:
1266 offset = M_Offset_AO_Status_2;
1268 case DIO_Serial_Input_Register:
1269 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1271 case Joint_Status_1_Register:
1272 offset = M_Offset_Joint_Status_1;
1274 case Joint_Status_2_Register:
1275 offset = M_Offset_Joint_Status_2;
1277 case G_Status_Register:
1278 offset = M_Offset_G01_Status;
1281 dev_warn(dev->class_dev,
1282 "%s: bug! unhandled register=0x%x in switch.\n",
1288 return ni_readw(offset);
1291 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1294 struct ni_private *devpriv = dev->private;
1298 case AI_SC_Load_A_Registers:
1299 offset = M_Offset_AI_SC_Load_A;
1301 case AI_SI_Load_A_Registers:
1302 offset = M_Offset_AI_SI_Load_A;
1304 case AO_BC_Load_A_Register:
1305 offset = M_Offset_AO_BC_Load_A;
1307 case AO_UC_Load_A_Register:
1308 offset = M_Offset_AO_UC_Load_A;
1310 case AO_UI_Load_A_Register:
1311 offset = M_Offset_AO_UI_Load_A;
1313 case G_Load_A_Register(0):
1314 offset = M_Offset_G0_Load_A;
1316 case G_Load_A_Register(1):
1317 offset = M_Offset_G1_Load_A;
1319 case G_Load_B_Register(0):
1320 offset = M_Offset_G0_Load_B;
1322 case G_Load_B_Register(1):
1323 offset = M_Offset_G1_Load_B;
1326 dev_warn(dev->class_dev,
1327 "%s: bug! unhandled register=0x%x in switch.\n",
1333 ni_writel(data, offset);
1336 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1338 struct ni_private *devpriv = dev->private;
1342 case G_HW_Save_Register(0):
1343 offset = M_Offset_G0_HW_Save;
1345 case G_HW_Save_Register(1):
1346 offset = M_Offset_G1_HW_Save;
1348 case G_Save_Register(0):
1349 offset = M_Offset_G0_Save;
1351 case G_Save_Register(1):
1352 offset = M_Offset_G1_Save;
1355 dev_warn(dev->class_dev,
1356 "%s: bug! unhandled register=0x%x in switch.\n",
1362 return ni_readl(offset);
1365 #define interrupt_pin(a) 0
1366 #define IRQ_POLARITY 1
1368 #define NI_E_IRQ_FLAGS IRQF_SHARED
1370 #include "ni_mio_common.c"
1372 static int pcimio_ai_change(struct comedi_device *dev,
1373 struct comedi_subdevice *s, unsigned long new_size);
1374 static int pcimio_ao_change(struct comedi_device *dev,
1375 struct comedi_subdevice *s, unsigned long new_size);
1376 static int pcimio_gpct0_change(struct comedi_device *dev,
1377 struct comedi_subdevice *s,
1378 unsigned long new_size);
1379 static int pcimio_gpct1_change(struct comedi_device *dev,
1380 struct comedi_subdevice *s,
1381 unsigned long new_size);
1382 static int pcimio_dio_change(struct comedi_device *dev,
1383 struct comedi_subdevice *s,
1384 unsigned long new_size);
1386 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1388 struct ni_private *devpriv = dev->private;
1389 static const int Start_Cal_EEPROM = 0x400;
1390 static const unsigned window_size = 10;
1391 static const int serial_number_eeprom_offset = 0x4;
1392 static const int serial_number_eeprom_length = 0x4;
1393 unsigned old_iodwbsr_bits;
1394 unsigned old_iodwbsr1_bits;
1395 unsigned old_iodwcr1_bits;
1398 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1399 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1400 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1401 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1402 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1403 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1404 writel(0x1 | old_iodwcr1_bits,
1405 devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1406 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1408 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1409 for (i = 0; i < serial_number_eeprom_length; ++i) {
1410 char *byte_ptr = (char *)&devpriv->serial_number + i;
1411 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1413 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1415 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1416 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1418 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1419 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1420 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1421 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1424 static void init_6143(struct comedi_device *dev)
1426 const struct ni_board_struct *board = comedi_board(dev);
1427 struct ni_private *devpriv = dev->private;
1429 /* Disable interrupts */
1430 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1432 /* Initialise 6143 AI specific bits */
1433 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */
1434 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */
1435 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */
1437 /* Set the FIFO half full level */
1438 ni_writel(board->ai_fifo_depth / 2, AIFIFO_Flag_6143);
1440 /* Strobe Relay disable bit */
1441 devpriv->ai_calib_source_enabled = 0;
1442 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1443 Calibration_Channel_6143);
1444 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1447 static void pcimio_detach(struct comedi_device *dev)
1449 struct ni_private *devpriv = dev->private;
1451 mio_common_detach(dev);
1453 free_irq(dev->irq, dev);
1455 mite_free_ring(devpriv->ai_mite_ring);
1456 mite_free_ring(devpriv->ao_mite_ring);
1457 mite_free_ring(devpriv->cdo_mite_ring);
1458 mite_free_ring(devpriv->gpct_mite_ring[0]);
1459 mite_free_ring(devpriv->gpct_mite_ring[1]);
1460 if (devpriv->mite) {
1461 mite_unsetup(devpriv->mite);
1462 mite_free(devpriv->mite);
1465 comedi_pci_disable(dev);
1468 static int pcimio_auto_attach(struct comedi_device *dev,
1469 unsigned long context)
1471 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1472 const struct ni_board_struct *board = NULL;
1473 struct ni_private *devpriv;
1477 if (context < ARRAY_SIZE(ni_boards))
1478 board = &ni_boards[context];
1481 dev->board_ptr = board;
1482 dev->board_name = board->name;
1484 ret = comedi_pci_enable(dev);
1488 ret = ni_alloc_private(dev);
1491 devpriv = dev->private;
1493 devpriv->mite = mite_alloc(pcidev);
1497 if (board->reg_type & ni_reg_m_series_mask) {
1498 devpriv->stc_writew = &m_series_stc_writew;
1499 devpriv->stc_readw = &m_series_stc_readw;
1500 devpriv->stc_writel = &m_series_stc_writel;
1501 devpriv->stc_readl = &m_series_stc_readl;
1503 devpriv->stc_writew = &e_series_win_out;
1504 devpriv->stc_readw = &e_series_win_in;
1505 devpriv->stc_writel = &win_out2;
1506 devpriv->stc_readl = &win_in2;
1509 ret = mite_setup(devpriv->mite);
1511 pr_warn("error setting up mite\n");
1515 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1516 if (devpriv->ai_mite_ring == NULL)
1518 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1519 if (devpriv->ao_mite_ring == NULL)
1521 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1522 if (devpriv->cdo_mite_ring == NULL)
1524 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1525 if (devpriv->gpct_mite_ring[0] == NULL)
1527 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1528 if (devpriv->gpct_mite_ring[1] == NULL)
1531 if (board->reg_type & ni_reg_m_series_mask)
1532 m_series_init_eeprom_buffer(dev);
1533 if (board->reg_type == ni_reg_6143)
1536 irq = mite_irq(devpriv->mite);
1538 ret = request_irq(irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1539 dev->board_name, dev);
1544 ret = ni_E_init(dev);
1548 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1549 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1550 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1551 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1552 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1557 static int pcimio_ai_change(struct comedi_device *dev,
1558 struct comedi_subdevice *s, unsigned long new_size)
1560 struct ni_private *devpriv = dev->private;
1563 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1570 static int pcimio_ao_change(struct comedi_device *dev,
1571 struct comedi_subdevice *s, unsigned long new_size)
1573 struct ni_private *devpriv = dev->private;
1576 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1583 static int pcimio_gpct0_change(struct comedi_device *dev,
1584 struct comedi_subdevice *s,
1585 unsigned long new_size)
1587 struct ni_private *devpriv = dev->private;
1590 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1597 static int pcimio_gpct1_change(struct comedi_device *dev,
1598 struct comedi_subdevice *s,
1599 unsigned long new_size)
1601 struct ni_private *devpriv = dev->private;
1604 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1611 static int pcimio_dio_change(struct comedi_device *dev,
1612 struct comedi_subdevice *s, unsigned long new_size)
1614 struct ni_private *devpriv = dev->private;
1617 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1624 static struct comedi_driver ni_pcimio_driver = {
1625 .driver_name = "ni_pcimio",
1626 .module = THIS_MODULE,
1627 .auto_attach = pcimio_auto_attach,
1628 .detach = pcimio_detach,
1631 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1632 const struct pci_device_id *id)
1634 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1637 static const struct pci_device_id ni_pcimio_pci_table[] = {
1638 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1639 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1640 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1641 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1642 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1643 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1644 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1645 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1646 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1647 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1648 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1649 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1650 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1651 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1652 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1653 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1654 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1655 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1656 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1657 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1658 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1659 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1660 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1661 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1662 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1663 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1664 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1665 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1666 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1667 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1668 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1669 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1670 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1671 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1672 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1673 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1674 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1675 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1676 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1677 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1678 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1679 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1680 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1681 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1682 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1683 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1684 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1685 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1686 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1687 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1688 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1689 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1690 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1691 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1694 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1696 static struct pci_driver ni_pcimio_pci_driver = {
1697 .name = "ni_pcimio",
1698 .id_table = ni_pcimio_pci_table,
1699 .probe = ni_pcimio_pci_probe,
1700 .remove = comedi_pci_auto_unconfig,
1702 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1704 MODULE_AUTHOR("Comedi http://www.comedi.org");
1705 MODULE_DESCRIPTION("Comedi low-level driver");
1706 MODULE_LICENSE("GPL");