2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
19 #include "dgnc_types.h"
22 /************************************************************************
23 * Per channel/port Classic UART structure *
24 ************************************************************************
25 * Base Structure Entries Usage Meanings to Host *
27 * W = read write R = read only *
29 ************************************************************************/
32 * txrx : WR RHR/THR - Holding reg
33 * ier : WR IER - Interrupt Enable Reg
34 * isr_fcr : WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg
35 * lcr : WR LCR - Line Control Reg
36 * mcr : WR MCR - Modem Control Reg
37 * lsr : WR LSR - Line Status Reg
38 * msr : WR MSG - Modem Status Reg
39 * spr : WR SPR - Scratch pad Reg
41 struct cls_uart_struct {
52 /* Where to read the interrupt register (8bits) */
53 #define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
55 #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
57 #define UART_16654_FCR_TXTRIGGER_8 0x0
58 #define UART_16654_FCR_TXTRIGGER_16 0x10
59 #define UART_16654_FCR_TXTRIGGER_32 0x20
60 #define UART_16654_FCR_TXTRIGGER_56 0x30
62 #define UART_16654_FCR_RXTRIGGER_8 0x0
63 #define UART_16654_FCR_RXTRIGGER_16 0x40
64 #define UART_16654_FCR_RXTRIGGER_56 0x80
65 #define UART_16654_FCR_RXTRIGGER_60 0xC0
67 /* Received CTS/RTS change of state */
68 #define UART_IIR_CTSRTS 0x20
70 /* Receiver data TIMEOUT */
71 #define UART_IIR_RDI_TIMEOUT 0x0C
74 * These are the EXTENDED definitions for the Exar 654's Interrupt
77 #define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
78 #define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
79 #define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
80 #define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
81 #define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
83 /* Indicates whether chip saw an incoming XOFF char */
84 #define UART_EXAR654_XOFF_DETECT 0x1
86 /* Indicates whether chip saw an incoming XON char */
87 #define UART_EXAR654_XON_DETECT 0x2
89 #define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
90 #define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
91 #define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
94 * Our Global Variables
96 extern struct board_ops dgnc_cls_ops;