2 tristate "DesignWare USB2 DRD Core Support"
7 Say Y or M here if your system has a Dual Role HighSpeed
8 USB controller based on the DesignWare HSOTG IP Core.
10 If you choose to build this driver as dynamically linked
11 modules, the core module will be called dwc2.ko, and the
12 PCI bus interface module (if you have a PCI bus system)
13 will be called dwc2_pci.ko.
15 NOTE: This driver at present only implements the Host mode
16 of the controller. The existing s3c-hsotg driver supports
17 Peripheral mode, but only for the Samsung S3C platforms.
18 There are plans to merge the s3c-hsotg driver with this
19 driver in the near future to create a dual-role driver.
24 bool "Enable Debugging Messages"
26 Say Y here to enable debugging messages in the DWC2 Driver.
28 config USB_DWC2_VERBOSE
29 bool "Enable Verbose Debugging Messages"
30 depends on USB_DWC2_DEBUG
32 Say Y here to enable verbose debugging messages in the DWC2 Driver.
33 WARNING: Enabling this will quickly fill your message log.
36 config USB_DWC2_TRACK_MISSED_SOFS
37 bool "Enable Missed SOF Tracking"
39 Say Y here to enable logging of missed SOF events to the dmesg log.
42 config USB_DWC2_DEBUG_PERIODIC
43 bool "Enable Debugging Messages For Periodic Transfers"
44 depends on USB_DWC2_DEBUG || USB_DWC2_VERBOSE
47 Say N here to disable (verbose) debugging messages to be
48 logged for periodic transfers. This allows better debugging of
49 non-periodic transfers, but of course the debug logs will be
50 incomplete. Note that this also disables some debug messages
51 for which the transfer type cannot be deduced.