drivers/staging/media/dt3155v4l/dt3155v4l.c

   1 /***************************************************************************
   2  *   Copyright (C) 2006-2010 by Marin Mitov                                *
   3  *   mitov@issp.bas.bg                                                     *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 #include <linux/module.h>
  22 #include <linux/stringify.h>
  23 #include <linux/delay.h>
  24 #include <linux/kthread.h>
  25 #include <linux/slab.h>
  26 #include <media/v4l2-dev.h>
  27 #include <media/v4l2-ioctl.h>
  28 #include <media/v4l2-common.h>
  29 #include <media/videobuf2-dma-contig.h>
  30
  31 #include "dt3155v4l.h"
  32
  33 #define DT3155_DEVICE_ID 0x1223
  34
  35 /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
  36 #define DT3155_CHUNK_SIZE (1U << 22)
  37
  38 #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
  39
  40 #define DT3155_BUF_SIZE (768 * 576)
  41
  42 #ifdef CONFIG_DT3155_STREAMING
  43 #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING
  44 #else
  45 #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE
  46 #endif
  47
  48 /*  global initializers (for all boards)  */
  49 #ifdef CONFIG_DT3155_CCIR
  50 static const u8 csr2_init = VT_50HZ;
  51 #define DT3155_CURRENT_NORM V4L2_STD_625_50
  52 static const unsigned int img_width = 768;
  53 static const unsigned int img_height = 576;
  54 static const unsigned int frames_per_sec = 25;
  55 static const struct v4l2_fmtdesc frame_std[] = {
  56         {
  57         .index = 0,
  58         .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  59         .flags = 0,
  60         .description = "CCIR/50Hz 8 bits gray",
  61         .pixelformat = V4L2_PIX_FMT_GREY,
  62         },
  63 };
  64 #else
  65 static const u8 csr2_init = VT_60HZ;
  66 #define DT3155_CURRENT_NORM V4L2_STD_525_60
  67 static const unsigned int img_width = 640;
  68 static const unsigned int img_height = 480;
  69 static const unsigned int frames_per_sec = 30;
  70 static const struct v4l2_fmtdesc frame_std[] = {
  71         {
  72         .index = 0,
  73         .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  74         .flags = 0,
  75         .description = "RS-170/60Hz 8 bits gray",
  76         .pixelformat = V4L2_PIX_FMT_GREY,
  77         },
  78 };
  79 #endif
  80
  81 #define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
  82
  83 static u8 config_init = ACQ_MODE_EVEN;
  84
  85 /**
  86  * read_i2c_reg - reads an internal i2c register
  87  *
  88  * @addr:       dt3155 mmio base address
  89  * @index:      index (internal address) of register to read
  90  * @data:       pointer to byte the read data will be placed in
  91  *
  92  * returns:     zero on success or error code
  93  *
  94  * This function starts reading the specified (by index) register
  95  * and busy waits for the process to finish. The result is placed
  96  * in a byte pointed by data.
  97  */
  98 static int
  99 read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
 100 {
 101         u32 tmp = index;
 102
 103         iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2);
 104         mmiowb();
 105         udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
 106         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
 107                 return -EIO; /* error: NEW_CYCLE not cleared */
 108         tmp = ioread32(addr + IIC_CSR1);
 109         if (tmp & DIRECT_ABORT) {
 110                 /* reset DIRECT_ABORT bit */
 111                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
 112                 return -EIO; /* error: DIRECT_ABORT set */
 113         }
 114         *data = tmp>>24;
 115         return 0;
 116 }
 117
 118 /**
 119  * write_i2c_reg - writes to an internal i2c register
 120  *
 121  * @addr:       dt3155 mmio base address
 122  * @index:      index (internal address) of register to read
 123  * @data:       data to be written
 124  *
 125  * returns:     zero on success or error code
 126  *
 127  * This function starts writting the specified (by index) register
 128  * and busy waits for the process to finish.
 129  */
 130 static int
 131 write_i2c_reg(void __iomem *addr, u8 index, u8 data)
 132 {
 133         u32 tmp = index;
 134
 135         iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
 136         mmiowb();
 137         udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
 138         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
 139                 return -EIO; /* error: NEW_CYCLE not cleared */
 140         if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
 141                 /* reset DIRECT_ABORT bit */
 142                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
 143                 return -EIO; /* error: DIRECT_ABORT set */
 144         }
 145         return 0;
 146 }
 147
 148 /**
 149  * write_i2c_reg_nowait - writes to an internal i2c register
 150  *
 151  * @addr:       dt3155 mmio base address
 152  * @index:      index (internal address) of register to read
 153  * @data:       data to be written
 154  *
 155  * This function starts writting the specified (by index) register
 156  * and then returns.
 157  */
 158 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
 159 {
 160         u32 tmp = index;
 161
 162         iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
 163         mmiowb();
 164 }
 165
 166 /**
 167  * wait_i2c_reg - waits the read/write to finish
 168  *
 169  * @addr:       dt3155 mmio base address
 170  *
 171  * returns:     zero on success or error code
 172  *
 173  * This function waits reading/writting to finish.
 174  */
 175 static int wait_i2c_reg(void __iomem *addr)
 176 {
 177         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
 178                 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
 179         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
 180                 return -EIO; /* error: NEW_CYCLE not cleared */
 181         if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
 182                 /* reset DIRECT_ABORT bit */
 183                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
 184                 return -EIO; /* error: DIRECT_ABORT set */
 185         }
 186         return 0;
 187 }
 188
 189 static int
 190 dt3155_start_acq(struct dt3155_priv *pd)
 191 {
 192         struct vb2_buffer *vb = pd->curr_buf;
 193         dma_addr_t dma_addr;
 194
 195         dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
 196         iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
 197         iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START);
 198         iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE);
 199         iowrite32(img_width, pd->regs + ODD_DMA_STRIDE);
 200         /* enable interrupts, clear all irq flags */
 201         iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
 202                         FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
 203         iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
 204                   FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
 205                                                         pd->regs + CSR1);
 206         wait_i2c_reg(pd->regs);
 207         write_i2c_reg(pd->regs, CONFIG, pd->config);
 208         write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
 209         write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
 210
 211         /*  start the board  */
 212         write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
 213         return 0; /* success  */
 214 }
 215
 216 /*
 217  *      driver-specific callbacks (vb2_ops)
 218  */
 219 static int
 220 dt3155_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt,
 221                 unsigned int *num_buffers, unsigned int *num_planes,
 222                 unsigned int sizes[], void *alloc_ctxs[])
 223
 224 {
 225         struct dt3155_priv *pd = vb2_get_drv_priv(q);
 226         void *ret;
 227
 228         if (*num_buffers == 0)
 229                 *num_buffers = 1;
 230         *num_planes = 1;
 231         sizes[0] = img_width * img_height;
 232         if (pd->q->alloc_ctx[0])
 233                 return 0;
 234         ret = vb2_dma_contig_init_ctx(&pd->pdev->dev);
 235         if (IS_ERR(ret))
 236                 return PTR_ERR(ret);
 237         pd->q->alloc_ctx[0] = ret;
 238         return 0;
 239 }
 240
 241 static void
 242 dt3155_wait_prepare(struct vb2_queue *q)
 243 {
 244         struct dt3155_priv *pd = vb2_get_drv_priv(q);
 245
 246         mutex_unlock(pd->vdev.lock);
 247 }
 248
 249 static void
 250 dt3155_wait_finish(struct vb2_queue *q)
 251 {
 252         struct dt3155_priv *pd = vb2_get_drv_priv(q);
 253
 254         mutex_lock(pd->vdev.lock);
 255 }
 256
 257 static int
 258 dt3155_buf_prepare(struct vb2_buffer *vb)
 259 {
 260         vb2_set_plane_payload(vb, 0, img_width * img_height);
 261         return 0;
 262 }
 263
 264 static void
 265 dt3155_stop_streaming(struct vb2_queue *q)
 266 {
 267         struct dt3155_priv *pd = vb2_get_drv_priv(q);
 268         struct vb2_buffer *vb;
 269
 270         spin_lock_irq(&pd->lock);
 271         while (!list_empty(&pd->dmaq)) {
 272                 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
 273                 list_del(&vb->done_entry);
 274                 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
 275         }
 276         spin_unlock_irq(&pd->lock);
 277         msleep(45); /* irq hendler will stop the hardware */
 278 }
 279
 280 static void
 281 dt3155_buf_queue(struct vb2_buffer *vb)
 282 {
 283         struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
 284
 285         /*  pd->q->streaming = 1 when dt3155_buf_queue() is invoked  */
 286         spin_lock_irq(&pd->lock);
 287         if (pd->curr_buf)
 288                 list_add_tail(&vb->done_entry, &pd->dmaq);
 289         else {
 290                 pd->curr_buf = vb;
 291                 dt3155_start_acq(pd);
 292         }
 293         spin_unlock_irq(&pd->lock);
 294 }
 295 /*
 296  *      end driver-specific callbacks
 297  */
 298
 299 static const struct vb2_ops q_ops = {
 300         .queue_setup = dt3155_queue_setup,
 301         .wait_prepare = dt3155_wait_prepare,
 302         .wait_finish = dt3155_wait_finish,
 303         .buf_prepare = dt3155_buf_prepare,
 304         .stop_streaming = dt3155_stop_streaming,
 305         .buf_queue = dt3155_buf_queue,
 306 };
 307
 308 static irqreturn_t
 309 dt3155_irq_handler_even(int irq, void *dev_id)
 310 {
 311         struct dt3155_priv *ipd = dev_id;
 312         struct vb2_buffer *ivb;
 313         dma_addr_t dma_addr;
 314         u32 tmp;
 315
 316         tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
 317         if (!tmp)
 318                 return IRQ_NONE;  /* not our irq */
 319         if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
 320                 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
 321                                                         ipd->regs + INT_CSR);
 322                 ipd->field_count++;
 323                 return IRQ_HANDLED; /* start of field irq */
 324         }
 325         if ((tmp & FLD_START) && (tmp & FLD_END_ODD))
 326                 ipd->stats.start_before_end++;
 327         /*      check for corrupted fields     */
 328 /*      write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);       */
 329 /*      write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);        */
 330         tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
 331         if (tmp) {
 332                 ipd->stats.corrupted_fields++;
 333                 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
 334                                                 FLD_DN_ODD | FLD_DN_EVEN |
 335                                                 CAP_CONT_EVEN | CAP_CONT_ODD,
 336                                                         ipd->regs + CSR1);
 337                 mmiowb();
 338         }
 339
 340         spin_lock(&ipd->lock);
 341         if (ipd->curr_buf) {
 342                 v4l2_get_timestamp(&ipd->curr_buf->v4l2_buf.timestamp);
 343                 ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1;
 344                 vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE);
 345         }
 346
 347         if (!ipd->q->streaming || list_empty(&ipd->dmaq))
 348                 goto stop_dma;
 349         ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
 350         list_del(&ivb->done_entry);
 351         ipd->curr_buf = ivb;
 352         dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
 353         iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
 354         iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START);
 355         iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE);
 356         iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE);
 357         mmiowb();
 358         /* enable interrupts, clear all irq flags */
 359         iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
 360                         FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
 361         spin_unlock(&ipd->lock);
 362         return IRQ_HANDLED;
 363
 364 stop_dma:
 365         ipd->curr_buf = NULL;
 366         /* stop the board */
 367         write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
 368         iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
 369                   FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1);
 370         /* disable interrupts, clear all irq flags */
 371         iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
 372         spin_unlock(&ipd->lock);
 373         return IRQ_HANDLED;
 374 }
 375
 376 static int
 377 dt3155_open(struct file *filp)
 378 {
 379         int ret = 0;
 380         struct dt3155_priv *pd = video_drvdata(filp);
 381
 382         if (mutex_lock_interruptible(&pd->mux))
 383                 return -ERESTARTSYS;
 384         if (!pd->users) {
 385                 pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL);
 386                 if (!pd->q) {
 387                         ret = -ENOMEM;
 388                         goto err_alloc_queue;
 389                 }
 390                 pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 391                 pd->q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
 392                 pd->q->io_modes = VB2_READ | VB2_MMAP;
 393                 pd->q->ops = &q_ops;
 394                 pd->q->mem_ops = &vb2_dma_contig_memops;
 395                 pd->q->drv_priv = pd;
 396                 pd->curr_buf = NULL;
 397                 pd->field_count = 0;
 398                 ret = vb2_queue_init(pd->q);
 399                 if (ret < 0)
 400                         goto err_request_irq;
 401                 INIT_LIST_HEAD(&pd->dmaq);
 402                 spin_lock_init(&pd->lock);
 403                 /* disable all irqs, clear all irq flags */
 404                 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
 405                                                 pd->regs + INT_CSR);
 406                 ret = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
 407                                                 IRQF_SHARED, DT3155_NAME, pd);
 408                 if (ret)
 409                         goto err_request_irq;
 410         }
 411         pd->users++;
 412         mutex_unlock(&pd->mux);
 413         return 0; /* success */
 414 err_request_irq:
 415         kfree(pd->q);
 416         pd->q = NULL;
 417 err_alloc_queue:
 418         mutex_unlock(&pd->mux);
 419         return ret;
 420 }
 421
 422 static int
 423 dt3155_release(struct file *filp)
 424 {
 425         struct dt3155_priv *pd = video_drvdata(filp);
 426
 427         mutex_lock(&pd->mux);
 428         pd->users--;
 429         BUG_ON(pd->users < 0);
 430         if (!pd->users) {
 431                 vb2_queue_release(pd->q);
 432                 free_irq(pd->pdev->irq, pd);
 433                 if (pd->q->alloc_ctx[0])
 434                         vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]);
 435                 kfree(pd->q);
 436                 pd->q = NULL;
 437         }
 438         mutex_unlock(&pd->mux);
 439         return 0;
 440 }
 441
 442 static ssize_t
 443 dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff)
 444 {
 445         struct dt3155_priv *pd = video_drvdata(filp);
 446         ssize_t res;
 447
 448         if (mutex_lock_interruptible(&pd->mux))
 449                 return -ERESTARTSYS;
 450         res = vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK);
 451         mutex_unlock(&pd->mux);
 452         return res;
 453 }
 454
 455 static unsigned int
 456 dt3155_poll(struct file *filp, struct poll_table_struct *polltbl)
 457 {
 458         struct dt3155_priv *pd = video_drvdata(filp);
 459         unsigned int res;
 460
 461         mutex_lock(&pd->mux);
 462         res = vb2_poll(pd->q, filp, polltbl);
 463         mutex_unlock(&pd->mux);
 464         return res;
 465 }
 466
 467 static int
 468 dt3155_mmap(struct file *filp, struct vm_area_struct *vma)
 469 {
 470         struct dt3155_priv *pd = video_drvdata(filp);
 471         int res;
 472
 473         if (mutex_lock_interruptible(&pd->mux))
 474                 return -ERESTARTSYS;
 475         res = vb2_mmap(pd->q, vma);
 476         mutex_unlock(&pd->mux);
 477         return res;
 478 }
 479
 480 static const struct v4l2_file_operations dt3155_fops = {
 481         .owner = THIS_MODULE,
 482         .open = dt3155_open,
 483         .release = dt3155_release,
 484         .read = dt3155_read,
 485         .poll = dt3155_poll,
 486         .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
 487         .mmap = dt3155_mmap,
 488 };
 489
 490 static int
 491 dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type)
 492 {
 493         struct dt3155_priv *pd = video_drvdata(filp);
 494
 495         return vb2_streamon(pd->q, type);
 496 }
 497
 498 static int
 499 dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type)
 500 {
 501         struct dt3155_priv *pd = video_drvdata(filp);
 502
 503         return vb2_streamoff(pd->q, type);
 504 }
 505
 506 static int
 507 dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap)
 508 {
 509         struct dt3155_priv *pd = video_drvdata(filp);
 510
 511         strcpy(cap->driver, DT3155_NAME);
 512         strcpy(cap->card, DT3155_NAME " frame grabber");
 513         sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
 514         cap->device_caps = V4L2_CAP_VIDEO_CAPTURE |
 515                                 DT3155_CAPTURE_METHOD;
 516         cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
 517         return 0;
 518 }
 519
 520 static int
 521 dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f)
 522 {
 523         if (f->index >= NUM_OF_FORMATS)
 524                 return -EINVAL;
 525         *f = frame_std[f->index];
 526         return 0;
 527 }
 528
 529 static int
 530 dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
 531 {
 532         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 533                 return -EINVAL;
 534         f->fmt.pix.width = img_width;
 535         f->fmt.pix.height = img_height;
 536         f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
 537         f->fmt.pix.field = V4L2_FIELD_NONE;
 538         f->fmt.pix.bytesperline = f->fmt.pix.width;
 539         f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
 540         f->fmt.pix.colorspace = 0;
 541         f->fmt.pix.priv = 0;
 542         return 0;
 543 }
 544
 545 static int
 546 dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
 547 {
 548         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 549                 return -EINVAL;
 550         if (f->fmt.pix.width == img_width &&
 551                 f->fmt.pix.height == img_height &&
 552                 f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY &&
 553                 f->fmt.pix.field == V4L2_FIELD_NONE &&
 554                 f->fmt.pix.bytesperline == f->fmt.pix.width &&
 555                 f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height)
 556                         return 0;
 557         else
 558                 return -EINVAL;
 559 }
 560
 561 static int
 562 dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
 563 {
 564         return dt3155_ioc_g_fmt_vid_cap(filp, p, f);
 565 }
 566
 567 static int
 568 dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b)
 569 {
 570         struct dt3155_priv *pd = video_drvdata(filp);
 571
 572         return vb2_reqbufs(pd->q, b);
 573 }
 574
 575 static int
 576 dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b)
 577 {
 578         struct dt3155_priv *pd = video_drvdata(filp);
 579
 580         return vb2_querybuf(pd->q, b);
 581 }
 582
 583 static int
 584 dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b)
 585 {
 586         struct dt3155_priv *pd = video_drvdata(filp);
 587
 588         return vb2_qbuf(pd->q, b);
 589 }
 590
 591 static int
 592 dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b)
 593 {
 594         struct dt3155_priv *pd = video_drvdata(filp);
 595
 596         return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK);
 597 }
 598
 599 static int
 600 dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm)
 601 {
 602         *norm = DT3155_CURRENT_NORM;
 603         return 0;
 604 }
 605
 606 static int
 607 dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm)
 608 {
 609         *norm = DT3155_CURRENT_NORM;
 610         return 0;
 611 }
 612
 613 static int
 614 dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id norm)
 615 {
 616         if (norm & DT3155_CURRENT_NORM)
 617                 return 0;
 618         return -EINVAL;
 619 }
 620
 621 static int
 622 dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input)
 623 {
 624         if (input->index)
 625                 return -EINVAL;
 626         strcpy(input->name, "Coax in");
 627         input->type = V4L2_INPUT_TYPE_CAMERA;
 628         /*
 629          * FIXME: input->std = 0 according to v4l2 API
 630          * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
 631          * should return -EINVAL
 632          */
 633         input->std = DT3155_CURRENT_NORM;
 634         input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
 635         return 0;
 636 }
 637
 638 static int
 639 dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i)
 640 {
 641         *i = 0;
 642         return 0;
 643 }
 644
 645 static int
 646 dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i)
 647 {
 648         if (i)
 649                 return -EINVAL;
 650         return 0;
 651 }
 652
 653 static int
 654 dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
 655 {
 656         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 657                 return -EINVAL;
 658         parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
 659         parms->parm.capture.capturemode = 0;
 660         parms->parm.capture.timeperframe.numerator = 1001;
 661         parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
 662         parms->parm.capture.extendedmode = 0;
 663         parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
 664         return 0;
 665 }
 666
 667 static int
 668 dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
 669 {
 670         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 671                 return -EINVAL;
 672         parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
 673         parms->parm.capture.capturemode = 0;
 674         parms->parm.capture.timeperframe.numerator = 1001;
 675         parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
 676         parms->parm.capture.extendedmode = 0;
 677         parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
 678         return 0;
 679 }
 680
 681 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
 682         .vidioc_streamon = dt3155_ioc_streamon,
 683         .vidioc_streamoff = dt3155_ioc_streamoff,
 684         .vidioc_querycap = dt3155_ioc_querycap,
 685 /*
 686         .vidioc_g_priority = dt3155_ioc_g_priority,
 687         .vidioc_s_priority = dt3155_ioc_s_priority,
 688 */
 689         .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap,
 690         .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap,
 691         .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap,
 692         .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap,
 693         .vidioc_reqbufs = dt3155_ioc_reqbufs,
 694         .vidioc_querybuf = dt3155_ioc_querybuf,
 695         .vidioc_qbuf = dt3155_ioc_qbuf,
 696         .vidioc_dqbuf = dt3155_ioc_dqbuf,
 697         .vidioc_querystd = dt3155_ioc_querystd,
 698         .vidioc_g_std = dt3155_ioc_g_std,
 699         .vidioc_s_std = dt3155_ioc_s_std,
 700         .vidioc_enum_input = dt3155_ioc_enum_input,
 701         .vidioc_g_input = dt3155_ioc_g_input,
 702         .vidioc_s_input = dt3155_ioc_s_input,
 703 /*
 704         .vidioc_queryctrl = dt3155_ioc_queryctrl,
 705         .vidioc_g_ctrl = dt3155_ioc_g_ctrl,
 706         .vidioc_s_ctrl = dt3155_ioc_s_ctrl,
 707         .vidioc_querymenu = dt3155_ioc_querymenu,
 708         .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
 709         .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
 710 */
 711         .vidioc_g_parm = dt3155_ioc_g_parm,
 712         .vidioc_s_parm = dt3155_ioc_s_parm,
 713 /*
 714         .vidioc_cropcap = dt3155_ioc_cropcap,
 715         .vidioc_g_crop = dt3155_ioc_g_crop,
 716         .vidioc_s_crop = dt3155_ioc_s_crop,
 717         .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
 718         .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
 719 */
 720 };
 721
 722 static int
 723 dt3155_init_board(struct pci_dev *pdev)
 724 {
 725         struct dt3155_priv *pd = pci_get_drvdata(pdev);
 726         void *buf_cpu;
 727         dma_addr_t buf_dma;
 728         int i;
 729         u8 tmp;
 730
 731         pci_set_master(pdev); /* dt3155 needs it */
 732
 733         /*  resetting the adapter  */
 734         iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN,
 735                                                         pd->regs + CSR1);
 736         mmiowb();
 737         msleep(20);
 738
 739         /*  initializing adaper registers  */
 740         iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
 741         mmiowb();
 742         iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
 743         iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
 744         iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
 745         iowrite32(0x00000103, pd->regs + XFER_MODE);
 746         iowrite32(0, pd->regs + RETRY_WAIT_CNT);
 747         iowrite32(0, pd->regs + INT_CSR);
 748         iowrite32(1, pd->regs + EVEN_FLD_MASK);
 749         iowrite32(1, pd->regs + ODD_FLD_MASK);
 750         iowrite32(0, pd->regs + MASK_LENGTH);
 751         iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
 752         iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
 753         mmiowb();
 754
 755         /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
 756         read_i2c_reg(pd->regs, DT_ID, &tmp);
 757         if (tmp != DT3155_ID)
 758                 return -ENODEV;
 759
 760         /* initialize AD LUT */
 761         write_i2c_reg(pd->regs, AD_ADDR, 0);
 762         for (i = 0; i < 256; i++)
 763                 write_i2c_reg(pd->regs, AD_LUT, i);
 764
 765         /* initialize ADC references */
 766         /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
 767         write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
 768         write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
 769         write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
 770         write_i2c_reg(pd->regs, AD_CMD, 34);
 771         write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
 772         write_i2c_reg(pd->regs, AD_CMD, 0);
 773
 774         /* initialize PM LUT */
 775         write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
 776         for (i = 0; i < 256; i++) {
 777                 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
 778                 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
 779         }
 780         write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
 781         for (i = 0; i < 256; i++) {
 782                 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
 783                 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
 784         }
 785         write_i2c_reg(pd->regs, CONFIG, pd->config); /*  ACQ_MODE_EVEN  */
 786
 787         /* select channel 1 for input and set sync level */
 788         write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
 789         write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
 790
 791         /* allocate memory, and initialize the DMA machine */
 792         buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma,
 793                                                                 GFP_KERNEL);
 794         if (!buf_cpu)
 795                 return -ENOMEM;
 796         iowrite32(buf_dma, pd->regs + EVEN_DMA_START);
 797         iowrite32(buf_dma, pd->regs + ODD_DMA_START);
 798         iowrite32(0, pd->regs + EVEN_DMA_STRIDE);
 799         iowrite32(0, pd->regs + ODD_DMA_STRIDE);
 800
 801         /*  Perform a pseudo even field acquire    */
 802         iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
 803         write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
 804         write_i2c_reg(pd->regs, CONFIG, pd->config);
 805         write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL);
 806         write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
 807         msleep(100);
 808         read_i2c_reg(pd->regs, CSR2, &tmp);
 809         write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
 810         write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
 811         write_i2c_reg(pd->regs, CSR2, pd->csr2);
 812         iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
 813
 814         /*  deallocate memory  */
 815         dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma);
 816         if (tmp & BUSY_EVEN)
 817                 return -EIO;
 818         return 0;
 819 }
 820
 821 static struct video_device dt3155_vdev = {
 822         .name = DT3155_NAME,
 823         .fops = &dt3155_fops,
 824         .ioctl_ops = &dt3155_ioctl_ops,
 825         .minor = -1,
 826         .release = video_device_release_empty,
 827         .tvnorms = DT3155_CURRENT_NORM,
 828 };
 829
 830 /* same as in drivers/base/dma-coherent.c */
 831 struct dma_coherent_mem {
 832         void            *virt_base;
 833         dma_addr_t      device_base;
 834         int             size;
 835         int             flags;
 836         unsigned long   *bitmap;
 837 };
 838
 839 static int
 840 dt3155_alloc_coherent(struct device *dev, size_t size, int flags)
 841 {
 842         struct dma_coherent_mem *mem;
 843         dma_addr_t dev_base;
 844         int pages = size >> PAGE_SHIFT;
 845         int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
 846
 847         if ((flags & DMA_MEMORY_MAP) == 0)
 848                 goto out;
 849         if (!size)
 850                 goto out;
 851         if (dev->dma_mem)
 852                 goto out;
 853
 854         mem = kzalloc(sizeof(*mem), GFP_KERNEL);
 855         if (!mem)
 856                 goto out;
 857         mem->virt_base = dma_alloc_coherent(dev, size, &dev_base,
 858                                                         DT3155_COH_FLAGS);
 859         if (!mem->virt_base)
 860                 goto err_alloc_coherent;
 861         mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
 862         if (!mem->bitmap)
 863                 goto err_bitmap;
 864
 865         /* coherent_dma_mask is already set to 32 bits */
 866         mem->device_base = dev_base;
 867         mem->size = pages;
 868         mem->flags = flags;
 869         dev->dma_mem = mem;
 870         return DMA_MEMORY_MAP;
 871
 872 err_bitmap:
 873         dma_free_coherent(dev, size, mem->virt_base, dev_base);
 874 err_alloc_coherent:
 875         kfree(mem);
 876 out:
 877         return 0;
 878 }
 879
 880 static void
 881 dt3155_free_coherent(struct device *dev)
 882 {
 883         struct dma_coherent_mem *mem = dev->dma_mem;
 884
 885         if (!mem)
 886                 return;
 887         dev->dma_mem = NULL;
 888         dma_free_coherent(dev, mem->size << PAGE_SHIFT,
 889                                         mem->virt_base, mem->device_base);
 890         kfree(mem->bitmap);
 891         kfree(mem);
 892 }
 893
 894 static int
 895 dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 896 {
 897         int err;
 898         struct dt3155_priv *pd;
 899
 900         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 901         if (err)
 902                 return -ENODEV;
 903         pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
 904         if (!pd)
 905                 return -ENOMEM;
 906
 907         pd->vdev = dt3155_vdev;
 908         pci_set_drvdata(pdev, pd);    /* for use in dt3155_remove() */
 909         video_set_drvdata(&pd->vdev, pd);  /* for use in video_fops */
 910         pd->users = 0;
 911         pd->pdev = pdev;
 912         INIT_LIST_HEAD(&pd->dmaq);
 913         mutex_init(&pd->mux);
 914         pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */
 915         spin_lock_init(&pd->lock);
 916         pd->csr2 = csr2_init;
 917         pd->config = config_init;
 918         err = pci_enable_device(pdev);
 919         if (err)
 920                 return err;
 921         err = pci_request_region(pdev, 0, pci_name(pdev));
 922         if (err)
 923                 goto err_req_region;
 924         pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
 925         if (!pd->regs) {
 926                 err = -ENOMEM;
 927                 goto err_pci_iomap;
 928         }
 929         err = dt3155_init_board(pdev);
 930         if (err)
 931                 goto err_init_board;
 932         err = video_register_device(&pd->vdev, VFL_TYPE_GRABBER, -1);
 933         if (err)
 934                 goto err_init_board;
 935         if (dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE,
 936                                                         DMA_MEMORY_MAP))
 937                 dev_info(&pdev->dev, "preallocated 8 buffers\n");
 938         dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
 939         return 0;  /*   success   */
 940
 941 err_init_board:
 942         pci_iounmap(pdev, pd->regs);
 943 err_pci_iomap:
 944         pci_release_region(pdev, 0);
 945 err_req_region:
 946         pci_disable_device(pdev);
 947         return err;
 948 }
 949
 950 static void
 951 dt3155_remove(struct pci_dev *pdev)
 952 {
 953         struct dt3155_priv *pd = pci_get_drvdata(pdev);
 954
 955         dt3155_free_coherent(&pdev->dev);
 956         video_unregister_device(&pd->vdev);
 957         pci_iounmap(pdev, pd->regs);
 958         pci_release_region(pdev, 0);
 959         pci_disable_device(pdev);
 960 }
 961
 962 static const struct pci_device_id pci_ids[] = {
 963         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) },
 964         { 0, /* zero marks the end */ },
 965 };
 966 MODULE_DEVICE_TABLE(pci, pci_ids);
 967
 968 static struct pci_driver pci_driver = {
 969         .name = DT3155_NAME,
 970         .id_table = pci_ids,
 971         .probe = dt3155_probe,
 972         .remove = dt3155_remove,
 973 };
 974
 975 module_pci_driver(pci_driver);
 976
 977 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
 978 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
 979 MODULE_VERSION(DT3155_VERSION);
 980 MODULE_LICENSE("GPL");