2 * Copyright (c) 2003-2012 Broadcom Corporation
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <linux/phy.h>
35 #include <linux/delay.h>
36 #include <linux/netdevice.h>
37 #include <linux/smp.h>
38 #include <linux/ethtool.h>
39 #include <linux/module.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/jiffies.h>
43 #include <linux/interrupt.h>
44 #include <linux/platform_device.h>
46 #include <asm/mipsregs.h>
48 * fmn.h - For FMN credit configuration and registering fmn_handler.
49 * FMN is communication mechanism that allows processing agents within
50 * XLR/XLS to communicate each other.
52 #include <asm/netlogic/xlr/fmn.h>
54 #include "platform_net.h"
58 * The readl/writel implementation byteswaps on XLR/XLS, so
59 * we need to use __raw_ IO to read the NAE registers
60 * because they are in the big-endian MMIO area on the SoC.
62 static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
64 __raw_writel(val, base + reg);
67 static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
69 return __raw_readl(base + reg);
72 static inline void xlr_reg_update(u32 *base_addr,
73 u32 off, u32 val, u32 mask)
77 tmp = xlr_nae_rdreg(base_addr, off);
78 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
81 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
83 static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
85 struct nlm_fmn_msg msg;
86 int ret = 0, num_try = 0, stnid;
87 unsigned long paddr, mflags;
89 paddr = virt_to_bus(addr);
90 msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
94 stnid = priv->nd->rfr_station;
96 mflags = nlm_cop2_enable_irqsave();
97 ret = nlm_fmn_send(1, 0, stnid, &msg);
98 nlm_cop2_disable_irqrestore(mflags);
101 } while (++num_try < 10000);
103 pr_err("Send to RFR failed in RX path\n");
107 static inline unsigned char *xlr_alloc_skb(void)
110 int buf_len = sizeof(struct sk_buff *);
111 unsigned char *skb_data;
113 /* skb->data is cache aligned */
114 skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
117 skb_data = skb->data;
118 skb_put(skb, MAC_SKB_BACK_PTR_SIZE);
119 skb_pull(skb, MAC_SKB_BACK_PTR_SIZE);
120 memcpy(skb_data, &skb, buf_len);
125 static void xlr_net_fmn_handler(int bkt, int src_stnid, int size,
126 int code, struct nlm_fmn_msg *msg, void *arg)
129 void *skb_data = NULL;
130 struct net_device *ndev;
131 struct xlr_net_priv *priv;
134 struct xlr_adapter *adapter = (struct xlr_adapter *) arg;
136 length = (msg->msg0 >> 40) & 0x3fff;
138 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
139 addr = addr - MAC_SKB_BACK_PTR_SIZE;
140 skb = (struct sk_buff *) *(unsigned long *)addr;
141 dev_kfree_skb_any((struct sk_buff *)addr);
143 addr = (unsigned char *)
144 bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
145 length = length - BYTE_OFFSET - MAC_CRC_LEN;
146 port = ((int)msg->msg0) & 0x0f;
147 addr = addr - MAC_SKB_BACK_PTR_SIZE;
148 skb = (struct sk_buff *) *(unsigned long *)addr;
149 skb->dev = adapter->netdev[port];
150 if (skb->dev == NULL)
153 priv = netdev_priv(ndev);
155 /* 16 byte IP header align */
156 skb_reserve(skb, BYTE_OFFSET);
157 skb_put(skb, length);
158 skb->protocol = eth_type_trans(skb, skb->dev);
159 skb->dev->last_rx = jiffies;
162 skb_data = xlr_alloc_skb();
164 send_to_rfr_fifo(priv, skb_data);
168 static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
170 return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
176 static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
178 struct xlr_net_priv *priv = netdev_priv(ndev);
179 struct phy_device *phydev = xlr_get_phydev(priv);
183 return phy_ethtool_gset(phydev, ecmd);
186 static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
188 struct xlr_net_priv *priv = netdev_priv(ndev);
189 struct phy_device *phydev = xlr_get_phydev(priv);
193 return phy_ethtool_sset(phydev, ecmd);
196 static struct ethtool_ops xlr_ethtool_ops = {
197 .get_settings = xlr_get_settings,
198 .set_settings = xlr_set_settings,
204 static int xlr_net_fill_rx_ring(struct net_device *ndev)
207 struct xlr_net_priv *priv = netdev_priv(ndev);
210 for (i = 0; i < MAX_FRIN_SPILL/4; i++) {
211 skb_data = xlr_alloc_skb();
213 pr_err("SKB allocation failed\n");
216 send_to_rfr_fifo(priv, skb_data);
218 pr_info("Rx ring setup done\n");
222 static int xlr_net_open(struct net_device *ndev)
225 struct xlr_net_priv *priv = netdev_priv(ndev);
226 struct phy_device *phydev = xlr_get_phydev(priv);
228 /* schedule a link state check */
231 err = phy_start_aneg(phydev);
233 pr_err("Autoneg failed\n");
236 /* Setup the speed from PHY to internal reg*/
237 xlr_set_gmac_speed(priv);
239 netif_tx_start_all_queues(ndev);
244 static int xlr_net_stop(struct net_device *ndev)
246 struct xlr_net_priv *priv = netdev_priv(ndev);
247 struct phy_device *phydev = xlr_get_phydev(priv);
250 netif_tx_stop_all_queues(ndev);
254 static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
257 unsigned long physkb = virt_to_phys(skb);
258 int cpu_core = nlm_core_id();
259 int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */
261 msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */
262 ((u64)127 << 54) | /* No Free back */
263 (u64)skb->len << 40 | /* Length of data */
265 msg->msg1 = (((u64)1 << 63) |
266 ((u64)fr_stn_id << 54) | /* Free back id */
267 (u64)0 << 40 | /* Set len to 0 */
268 ((u64)physkb & 0xffffffff)); /* 32bit address */
269 msg->msg2 = msg->msg3 = 0;
272 static void __maybe_unused xlr_wakeup_queue(unsigned long dev)
274 struct net_device *ndev = (struct net_device *) dev;
275 struct xlr_net_priv *priv = netdev_priv(ndev);
276 struct phy_device *phydev = xlr_get_phydev(priv);
279 netif_tx_wake_queue(netdev_get_tx_queue(ndev, priv->wakeup_q));
282 static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
283 struct net_device *ndev)
285 struct nlm_fmn_msg msg;
286 struct xlr_net_priv *priv = netdev_priv(ndev);
290 xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
291 flags = nlm_cop2_enable_irqsave();
292 ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
293 nlm_cop2_disable_irqrestore(flags);
295 dev_kfree_skb_any(skb);
299 static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb,
301 select_queue_fallback_t fallback)
303 return (u16)smp_processor_id();
306 static void xlr_hw_set_mac_addr(struct net_device *ndev)
308 struct xlr_net_priv *priv = netdev_priv(ndev);
310 /* set mac station address */
311 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
312 ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
313 (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
314 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
315 ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
317 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
318 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
319 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
320 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
322 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
323 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
324 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
325 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
327 if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
328 priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
329 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
332 static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
336 err = eth_mac_addr(ndev, data);
339 xlr_hw_set_mac_addr(ndev);
343 static void xlr_set_rx_mode(struct net_device *ndev)
345 struct xlr_net_priv *priv = netdev_priv(ndev);
348 regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
350 if (ndev->flags & IFF_PROMISC) {
351 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
352 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
353 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
354 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
356 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
357 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
360 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
363 static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
365 struct xlr_net_priv *priv = netdev_priv(ndev);
367 stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
368 stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
369 stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
370 stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
371 stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
372 stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
373 RX_DROP_PACKET_COUNTER);
374 stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
375 TX_DROP_FRAME_COUNTER);
377 stats->multicast = xlr_nae_rdreg(priv->base_addr,
378 RX_MULTICAST_PACKET_COUNTER);
379 stats->collisions = xlr_nae_rdreg(priv->base_addr,
380 TX_TOTAL_COLLISION_COUNTER);
382 stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
383 RX_FRAME_LENGTH_ERROR_COUNTER);
384 stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
385 RX_DROP_PACKET_COUNTER);
386 stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
387 RX_FCS_ERROR_COUNTER);
388 stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
389 RX_ALIGNMENT_ERROR_COUNTER);
391 stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
392 RX_DROP_PACKET_COUNTER);
393 stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
394 RX_CARRIER_SENSE_ERROR_COUNTER);
396 stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
397 stats->rx_frame_errors + stats->rx_fifo_errors +
398 stats->rx_missed_errors);
400 stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
401 TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
402 stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
403 TX_DROP_FRAME_COUNTER);
404 stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
405 TX_DROP_FRAME_COUNTER);
408 static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev,
409 struct rtnl_link_stats64 *stats)
411 xlr_stats(ndev, stats);
415 static struct net_device_ops xlr_netdev_ops = {
416 .ndo_open = xlr_net_open,
417 .ndo_stop = xlr_net_stop,
418 .ndo_start_xmit = xlr_net_start_xmit,
419 .ndo_select_queue = xlr_net_select_queue,
420 .ndo_set_mac_address = xlr_net_set_mac_addr,
421 .ndo_set_rx_mode = xlr_set_rx_mode,
422 .ndo_get_stats64 = xlr_get_stats64,
428 static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
429 int reg_start_1, int reg_size, int size)
433 unsigned long phys_addr;
436 base = priv->base_addr;
438 spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
440 pr_err("Unable to allocate memory for spill area!\n");
442 spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
443 phys_addr = virt_to_phys(spill);
444 dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
446 xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
447 xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
448 xlr_nae_wreg(base, reg_size, spill_size);
454 * Configure the 6 FIFO's that are used by the network accelarator to
455 * communicate with the rest of the XLx device. 4 of the FIFO's are for
456 * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
457 * the NA with free descriptors.
459 static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
461 priv->frin_spill = xlr_config_spill(priv,
462 R_REG_FRIN_SPILL_MEM_START_0,
463 R_REG_FRIN_SPILL_MEM_START_1,
464 R_REG_FRIN_SPILL_MEM_SIZE,
467 priv->frout_spill = xlr_config_spill(priv,
468 R_FROUT_SPILL_MEM_START_0,
469 R_FROUT_SPILL_MEM_START_1,
470 R_FROUT_SPILL_MEM_SIZE,
473 priv->class_0_spill = xlr_config_spill(priv,
474 R_CLASS0_SPILL_MEM_START_0,
475 R_CLASS0_SPILL_MEM_START_1,
476 R_CLASS0_SPILL_MEM_SIZE,
479 priv->class_1_spill = xlr_config_spill(priv,
480 R_CLASS1_SPILL_MEM_START_0,
481 R_CLASS1_SPILL_MEM_START_1,
482 R_CLASS1_SPILL_MEM_SIZE,
485 priv->class_2_spill = xlr_config_spill(priv,
486 R_CLASS2_SPILL_MEM_START_0,
487 R_CLASS2_SPILL_MEM_START_1,
488 R_CLASS2_SPILL_MEM_SIZE,
491 priv->class_3_spill = xlr_config_spill(priv,
492 R_CLASS3_SPILL_MEM_START_0,
493 R_CLASS3_SPILL_MEM_START_1,
494 R_CLASS3_SPILL_MEM_SIZE,
500 * Configure PDE to Round-Robin distribution of packets to the
503 static void xlr_config_pde(struct xlr_net_priv *priv)
508 /* Each core has 8 buckets(station) */
509 for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
510 bkt_map |= (0xff << (i * 8));
512 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
513 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
514 ((bkt_map >> 32) & 0xffffffff));
516 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
517 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
518 ((bkt_map >> 32) & 0xffffffff));
520 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
521 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
522 ((bkt_map >> 32) & 0xffffffff));
524 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
525 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
526 ((bkt_map >> 32) & 0xffffffff));
530 * Setup the Message ring credits, bucket size and other
531 * common configuration
533 static int xlr_config_common(struct xlr_net_priv *priv)
535 struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
536 int start_stn_id = gmac->start_stn_id;
537 int end_stn_id = gmac->end_stn_id;
538 int *bucket_size = priv->nd->bucket_size;
541 /* Setting non-core MsgBktSize(0x321 - 0x325) */
542 for (i = start_stn_id; i <= end_stn_id; i++) {
543 xlr_nae_wreg(priv->base_addr,
544 R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
549 * Setting non-core Credit counter register
550 * Distributing Gmac's credit to CPU's
552 for (i = 0; i < 8; i++) {
553 for (j = 0; j < 8; j++)
554 xlr_nae_wreg(priv->base_addr,
555 (R_CC_CPU0_0 + (i * 8)) + j,
556 gmac->credit_config[(i * 8) + j]);
559 xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
560 xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
561 xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
562 xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
563 xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
564 xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
566 err = xlr_net_fill_rx_ring(priv->ndev);
569 nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
574 static void xlr_config_translate_table(struct xlr_net_priv *priv)
578 int bkts[32]; /* one bucket is assumed for each cpu */
579 int b1, b2, c1, c2, i, j, k;
583 cpu_mask = priv->nd->cpu_mask;
585 pr_info("Using %s-based distribution\n",
586 (use_bkt) ? "bucket" : "class");
588 for (i = 0; i < 32; i++) {
589 if ((1 << i) & cpu_mask) {
590 /* for each cpu, mark the 4+threadid bucket */
591 bkts[j] = ((i / 4) * 8) + (i % 4);
596 /*configure the 128 * 9 Translation table to send to available buckets*/
600 for (i = 0; i < 64; i++) {
602 * On use_bkt set the b0, b1 are used, else
603 * the 4 classes are used, here implemented
604 * a logic to distribute the packets to the
605 * buckets equally or based on the class
614 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
615 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
616 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
618 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
623 static void xlr_config_parser(struct xlr_net_priv *priv)
627 /* Mark it as ETHERNET type */
628 xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
630 /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
631 xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
632 ((0x7f << 8) | (1 << 1)));
634 /* configure the parser : L2 Type is configured in the bootloader */
635 /* extract IP: src, dest protocol */
636 xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
637 (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
639 xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
640 (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
643 /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
644 xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
645 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
646 val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
647 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
648 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
650 xlr_config_translate_table(priv);
653 static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
655 unsigned long timeout, stoptime, checktime;
659 timeout = msecs_to_jiffies(100);
660 stoptime = jiffies + timeout;
663 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
665 /* Write the data which starts the write cycle */
666 xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32) val);
668 /* poll for the read cycle to complete */
671 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
673 timedout = time_after(checktime, stoptime);
676 pr_info("Phy device write err: device busy");
683 static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
685 unsigned long timeout, stoptime, checktime;
689 timeout = msecs_to_jiffies(100);
690 stoptime = jiffies + timeout;
693 /* setup the phy reg to be used */
694 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
695 (phy_addr << 8) | (regnum << 0));
697 /* Issue the read command */
698 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
699 (1 << O_MII_MGMT_COMMAND__rstat));
701 /* poll for the read cycle to complete */
704 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
706 timedout = time_after(checktime, stoptime);
709 pr_info("Phy device read err: device busy");
713 /* clear the read cycle */
714 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
717 return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
720 static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
722 struct xlr_net_priv *priv = bus->priv;
725 ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
726 dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
727 phy_addr, regnum, val, ret);
731 static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
733 struct xlr_net_priv *priv = bus->priv;
736 ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum);
737 dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
738 phy_addr, regnum, ret);
743 * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
744 * which can be configured either SGMII or RGMII, considered SGMII
745 * by default, if board setup to RGMII the port_type need to set
746 * accordingly.Serdes and PCS layer need to configured for SGMII
748 static void xlr_sgmii_init(struct xlr_net_priv *priv)
752 xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
753 xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
754 xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
755 xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
756 xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
757 xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
758 xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
759 xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
760 xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
761 xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
762 xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
764 /* program GPIO values for serdes init parameters */
765 xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
766 xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
768 xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
769 xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
771 /* enable autoneg - more magic */
772 phy = priv->phy_addr % 4 + 27;
773 xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
774 xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
777 void xlr_set_gmac_speed(struct xlr_net_priv *priv)
779 struct phy_device *phydev = xlr_get_phydev(priv);
782 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
783 xlr_sgmii_init(priv);
785 if (phydev->speed != priv->phy_speed) {
786 speed = phydev->speed;
787 if (speed == SPEED_1000) {
788 /* Set interface to Byte mode */
789 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
790 priv->phy_speed = speed;
791 } else if (speed == SPEED_100 || speed == SPEED_10) {
792 /* Set interface to Nibble mode */
793 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
794 priv->phy_speed = speed;
796 /* Set SGMII speed in Interface control reg */
797 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
798 if (speed == SPEED_10)
799 xlr_nae_wreg(priv->base_addr,
800 R_INTERFACE_CONTROL, SGMII_SPEED_10);
801 if (speed == SPEED_100)
802 xlr_nae_wreg(priv->base_addr,
803 R_INTERFACE_CONTROL, SGMII_SPEED_100);
804 if (speed == SPEED_1000)
805 xlr_nae_wreg(priv->base_addr,
806 R_INTERFACE_CONTROL, SGMII_SPEED_1000);
808 if (speed == SPEED_10)
809 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
810 if (speed == SPEED_100)
811 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
812 if (speed == SPEED_1000)
813 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
815 pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
818 static void xlr_gmac_link_adjust(struct net_device *ndev)
820 struct xlr_net_priv *priv = netdev_priv(ndev);
821 struct phy_device *phydev = xlr_get_phydev(priv);
824 intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
826 if (phydev->speed != priv->phy_speed) {
827 xlr_set_gmac_speed(priv);
828 pr_info("gmac%d : Link up\n", priv->port_id);
831 xlr_set_gmac_speed(priv);
832 pr_info("gmac%d : Link down\n", priv->port_id);
836 static int xlr_mii_probe(struct xlr_net_priv *priv)
838 struct phy_device *phydev = xlr_get_phydev(priv);
841 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
845 /* Attach MAC to PHY */
846 phydev = phy_connect(priv->ndev, phydev_name(phydev),
847 &xlr_gmac_link_adjust, priv->nd->phy_interface);
849 if (IS_ERR(phydev)) {
850 pr_err("could not attach PHY\n");
851 return PTR_ERR(phydev);
853 phydev->supported &= (ADVERTISED_10baseT_Full
854 | ADVERTISED_10baseT_Half
855 | ADVERTISED_100baseT_Full
856 | ADVERTISED_100baseT_Half
857 | ADVERTISED_1000baseT_Full
861 phydev->advertising = phydev->supported;
862 phy_attached_info(phydev);
866 static int xlr_setup_mdio(struct xlr_net_priv *priv,
867 struct platform_device *pdev)
871 priv->mii_bus = mdiobus_alloc();
872 if (!priv->mii_bus) {
873 pr_err("mdiobus alloc failed\n");
877 priv->mii_bus->priv = priv;
878 priv->mii_bus->name = "xlr-mdio";
879 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
880 priv->mii_bus->name, priv->port_id);
881 priv->mii_bus->read = xlr_mii_read;
882 priv->mii_bus->write = xlr_mii_write;
883 priv->mii_bus->parent = &pdev->dev;
885 /* Scan only the enabled address */
886 priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
888 /* setting clock divisor to 54 */
889 xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
891 err = mdiobus_register(priv->mii_bus);
893 mdiobus_free(priv->mii_bus);
894 pr_err("mdio bus registration failed\n");
898 pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
899 err = xlr_mii_probe(priv);
901 mdiobus_free(priv->mii_bus);
907 static void xlr_port_enable(struct xlr_net_priv *priv)
909 u32 prid = (read_c0_prid() & 0xf000);
911 /* Setup MAC_CONFIG reg if (xls & rgmii) */
912 if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
913 priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
914 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
915 (1 << O_RX_CONTROL__RGMII), (1 << O_RX_CONTROL__RGMII));
918 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
919 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
920 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
921 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
922 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)));
924 /* Setup tx control reg */
925 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
926 ((1 << O_TX_CONTROL__TxEnable) |
927 (512 << O_TX_CONTROL__TxThreshold)), 0x3fff);
929 /* Setup rx control reg */
930 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
931 1 << O_RX_CONTROL__RxEnable, 1 << O_RX_CONTROL__RxEnable);
934 static void xlr_port_disable(struct xlr_net_priv *priv)
936 /* Setup MAC_CONFIG reg */
938 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
939 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
940 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
943 /* Setup tx control reg */
944 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
945 ((1 << O_TX_CONTROL__TxEnable) |
946 (512 << O_TX_CONTROL__TxThreshold)), 0);
948 /* Setup rx control reg */
949 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
950 1 << O_RX_CONTROL__RxEnable, 0);
954 * Initialization of gmac
956 static int xlr_gmac_init(struct xlr_net_priv *priv,
957 struct platform_device *pdev)
961 pr_info("Initializing the gmac%d\n", priv->port_id);
963 xlr_port_disable(priv);
965 xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
966 (1 << O_DESC_PACK_CTRL__MaxEntry)
967 | (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset)
968 | (1600 << O_DESC_PACK_CTRL__RegularSize));
970 ret = xlr_setup_mdio(priv, pdev);
973 xlr_port_enable(priv);
975 /* Enable Full-duplex/1000Mbps/CRC */
976 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
978 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
979 /* Setup Interrupt mask reg */
980 xlr_nae_wreg(priv->base_addr, R_INTMASK,
981 (1 << O_INTMASK__TxIllegal) |
982 (1 << O_INTMASK__MDInt) |
983 (1 << O_INTMASK__TxFetchError) |
984 (1 << O_INTMASK__P2PSpillEcc) |
985 (1 << O_INTMASK__TagFull) |
986 (1 << O_INTMASK__Underrun) |
987 (1 << O_INTMASK__Abort)
990 /* Clear all stats */
991 xlr_reg_update(priv->base_addr, R_STATCTRL,
992 0, 1 << O_STATCTRL__ClrCnt);
993 xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2,
998 static int xlr_net_probe(struct platform_device *pdev)
1000 struct xlr_net_priv *priv = NULL;
1001 struct net_device *ndev;
1002 struct resource *res;
1003 struct xlr_adapter *adapter;
1006 pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
1008 * Allocate our adapter data structure and attach it to the device.
1010 adapter = (struct xlr_adapter *)
1011 devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
1018 * XLR and XLS have 1 and 2 NAE controller respectively
1019 * Each controller has 4 gmac ports, mapping each controller
1020 * under one parent device, 4 gmac ports under one device.
1022 for (port = 0; port < pdev->num_resources/2; port++) {
1023 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1025 pr_err("Allocation of Ethernet device failed\n");
1029 priv = netdev_priv(ndev);
1032 priv->port_id = (pdev->id * 4) + port;
1033 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1034 res = platform_get_resource(pdev, IORESOURCE_MEM, port);
1037 pr_err("No memory resource for MAC %d\n",
1042 priv->base_addr = devm_ioremap_resource(&pdev->dev, res);
1043 if (IS_ERR(priv->base_addr)) {
1044 err = PTR_ERR(priv->base_addr);
1047 priv->adapter = adapter;
1048 adapter->netdev[port] = ndev;
1050 res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
1052 pr_err("No irq resource for MAC %d\n", priv->port_id);
1057 ndev->irq = res->start;
1059 priv->phy_addr = priv->nd->phy_addr[port];
1060 priv->tx_stnid = priv->nd->tx_stnid[port];
1061 priv->mii_addr = priv->nd->mii_addr;
1062 priv->serdes_addr = priv->nd->serdes_addr;
1063 priv->pcs_addr = priv->nd->pcs_addr;
1064 priv->gpio_addr = priv->nd->gpio_addr;
1066 ndev->netdev_ops = &xlr_netdev_ops;
1067 ndev->watchdog_timeo = HZ;
1069 /* Setup Mac address and Rx mode */
1070 eth_hw_addr_random(ndev);
1071 xlr_hw_set_mac_addr(ndev);
1072 xlr_set_rx_mode(ndev);
1074 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1075 ndev->ethtool_ops = &xlr_ethtool_ops;
1076 SET_NETDEV_DEV(ndev, &pdev->dev);
1078 xlr_config_fifo_spill_area(priv);
1079 /* Configure PDE to Round-Robin pkt distribution */
1080 xlr_config_pde(priv);
1081 xlr_config_parser(priv);
1083 /* Call init with respect to port */
1084 if (strcmp(res->name, "gmac") == 0) {
1085 err = xlr_gmac_init(priv, pdev);
1087 pr_err("gmac%d init failed\n", priv->port_id);
1092 if (priv->port_id == 0 || priv->port_id == 4) {
1093 err = xlr_config_common(priv);
1098 err = register_netdev(ndev);
1100 pr_err("Registering netdev failed for gmac%d\n",
1104 platform_set_drvdata(pdev, priv);
1110 mdiobus_free(priv->mii_bus);
1116 static int xlr_net_remove(struct platform_device *pdev)
1118 struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1120 unregister_netdev(priv->ndev);
1121 mdiobus_unregister(priv->mii_bus);
1122 mdiobus_free(priv->mii_bus);
1123 free_netdev(priv->ndev);
1127 static struct platform_driver xlr_net_driver = {
1128 .probe = xlr_net_probe,
1129 .remove = xlr_net_remove,
1135 module_platform_driver(xlr_net_driver);
1137 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1138 MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1139 MODULE_LICENSE("Dual BSD/GPL");
1140 MODULE_ALIAS("platform:xlr-net");