drivers/staging/rdma/hfi1/chip.c

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 /*
  49  * This file contains all of the code that is specific to the HFI chip
  50  */
  51
  52 #include <linux/pci.h>
  53 #include <linux/delay.h>
  54 #include <linux/interrupt.h>
  55 #include <linux/module.h>
  56
  57 #include "hfi.h"
  58 #include "trace.h"
  59 #include "mad.h"
  60 #include "pio.h"
  61 #include "sdma.h"
  62 #include "eprom.h"
  63 #include "efivar.h"
  64 #include "platform.h"
  65 #include "aspm.h"
  66
  67 #define NUM_IB_PORTS 1
  68
  69 uint kdeth_qp;
  70 module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO);
  71 MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix");
  72
  73 uint num_vls = HFI1_MAX_VLS_SUPPORTED;
  74 module_param(num_vls, uint, S_IRUGO);
  75 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
  76
  77 /*
  78  * Default time to aggregate two 10K packets from the idle state
  79  * (timer not running). The timer starts at the end of the first packet,
  80  * so only the time for one 10K packet and header plus a bit extra is needed.
  81  * 10 * 1024 + 64 header byte = 10304 byte
  82  * 10304 byte / 12.5 GB/s = 824.32ns
  83  */
  84 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
  85 module_param(rcv_intr_timeout, uint, S_IRUGO);
  86 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
  87
  88 uint rcv_intr_count = 16; /* same as qib */
  89 module_param(rcv_intr_count, uint, S_IRUGO);
  90 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
  91
  92 ushort link_crc_mask = SUPPORTED_CRCS;
  93 module_param(link_crc_mask, ushort, S_IRUGO);
  94 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
  95
  96 uint loopback;
  97 module_param_named(loopback, loopback, uint, S_IRUGO);
  98 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
  99
 100 /* Other driver tunables */
 101 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
 102 static ushort crc_14b_sideband = 1;
 103 static uint use_flr = 1;
 104 uint quick_linkup; /* skip LNI */
 105
 106 struct flag_table {
 107         u64 flag;       /* the flag */
 108         char *str;      /* description string */
 109         u16 extra;      /* extra information */
 110         u16 unused0;
 111         u32 unused1;
 112 };
 113
 114 /* str must be a string constant */
 115 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
 116 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
 117
 118 /* Send Error Consequences */
 119 #define SEC_WRITE_DROPPED       0x1
 120 #define SEC_PACKET_DROPPED      0x2
 121 #define SEC_SC_HALTED           0x4     /* per-context only */
 122 #define SEC_SPC_FREEZE          0x8     /* per-HFI only */
 123
 124 #define MIN_KERNEL_KCTXTS         2
 125 #define FIRST_KERNEL_KCTXT        1
 126 /* sizes for both the QP and RSM map tables */
 127 #define NUM_MAP_ENTRIES         256
 128 #define NUM_MAP_REGS             32
 129
 130 /* Bit offset into the GUID which carries HFI id information */
 131 #define GUID_HFI_INDEX_SHIFT     39
 132
 133 /* extract the emulation revision */
 134 #define emulator_rev(dd) ((dd)->irev >> 8)
 135 /* parallel and serial emulation versions are 3 and 4 respectively */
 136 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
 137 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
 138
 139 /* RSM fields */
 140
 141 /* packet type */
 142 #define IB_PACKET_TYPE         2ull
 143 #define QW_SHIFT               6ull
 144 /* QPN[7..1] */
 145 #define QPN_WIDTH              7ull
 146
 147 /* LRH.BTH: QW 0, OFFSET 48 - for match */
 148 #define LRH_BTH_QW             0ull
 149 #define LRH_BTH_BIT_OFFSET     48ull
 150 #define LRH_BTH_OFFSET(off)    ((LRH_BTH_QW << QW_SHIFT) | (off))
 151 #define LRH_BTH_MATCH_OFFSET   LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
 152 #define LRH_BTH_SELECT
 153 #define LRH_BTH_MASK           3ull
 154 #define LRH_BTH_VALUE          2ull
 155
 156 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
 157 #define LRH_SC_QW              0ull
 158 #define LRH_SC_BIT_OFFSET      56ull
 159 #define LRH_SC_OFFSET(off)     ((LRH_SC_QW << QW_SHIFT) | (off))
 160 #define LRH_SC_MATCH_OFFSET    LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
 161 #define LRH_SC_MASK            128ull
 162 #define LRH_SC_VALUE           0ull
 163
 164 /* SC[n..0] QW 0, OFFSET 60 - for select */
 165 #define LRH_SC_SELECT_OFFSET  ((LRH_SC_QW << QW_SHIFT) | (60ull))
 166
 167 /* QPN[m+n:1] QW 1, OFFSET 1 */
 168 #define QPN_SELECT_OFFSET      ((1ull << QW_SHIFT) | (1ull))
 169
 170 /* defines to build power on SC2VL table */
 171 #define SC2VL_VAL( \
 172         num, \
 173         sc0, sc0val, \
 174         sc1, sc1val, \
 175         sc2, sc2val, \
 176         sc3, sc3val, \
 177         sc4, sc4val, \
 178         sc5, sc5val, \
 179         sc6, sc6val, \
 180         sc7, sc7val) \
 181 ( \
 182         ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
 183         ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
 184         ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
 185         ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
 186         ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
 187         ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
 188         ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
 189         ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT)   \
 190 )
 191
 192 #define DC_SC_VL_VAL( \
 193         range, \
 194         e0, e0val, \
 195         e1, e1val, \
 196         e2, e2val, \
 197         e3, e3val, \
 198         e4, e4val, \
 199         e5, e5val, \
 200         e6, e6val, \
 201         e7, e7val, \
 202         e8, e8val, \
 203         e9, e9val, \
 204         e10, e10val, \
 205         e11, e11val, \
 206         e12, e12val, \
 207         e13, e13val, \
 208         e14, e14val, \
 209         e15, e15val) \
 210 ( \
 211         ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
 212         ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
 213         ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
 214         ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
 215         ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
 216         ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
 217         ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
 218         ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
 219         ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
 220         ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
 221         ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
 222         ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
 223         ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
 224         ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
 225         ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
 226         ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
 227 )
 228
 229 /* all CceStatus sub-block freeze bits */
 230 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
 231                         | CCE_STATUS_RXE_FROZE_SMASK \
 232                         | CCE_STATUS_TXE_FROZE_SMASK \
 233                         | CCE_STATUS_TXE_PIO_FROZE_SMASK)
 234 /* all CceStatus sub-block TXE pause bits */
 235 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
 236                         | CCE_STATUS_TXE_PAUSED_SMASK \
 237                         | CCE_STATUS_SDMA_PAUSED_SMASK)
 238 /* all CceStatus sub-block RXE pause bits */
 239 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
 240
 241 /*
 242  * CCE Error flags.
 243  */
 244 static struct flag_table cce_err_status_flags[] = {
 245 /* 0*/  FLAG_ENTRY0("CceCsrParityErr",
 246                 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
 247 /* 1*/  FLAG_ENTRY0("CceCsrReadBadAddrErr",
 248                 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
 249 /* 2*/  FLAG_ENTRY0("CceCsrWriteBadAddrErr",
 250                 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
 251 /* 3*/  FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
 252                 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
 253 /* 4*/  FLAG_ENTRY0("CceTrgtAccessErr",
 254                 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
 255 /* 5*/  FLAG_ENTRY0("CceRspdDataParityErr",
 256                 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
 257 /* 6*/  FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
 258                 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
 259 /* 7*/  FLAG_ENTRY0("CceCsrCfgBusParityErr",
 260                 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
 261 /* 8*/  FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
 262                 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
 263 /* 9*/  FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
 264             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
 265 /*10*/  FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
 266             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
 267 /*11*/  FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
 268             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
 269 /*12*/  FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
 270                 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
 271 /*13*/  FLAG_ENTRY0("PcicRetryMemCorErr",
 272                 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
 273 /*14*/  FLAG_ENTRY0("PcicRetryMemCorErr",
 274                 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
 275 /*15*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 276                 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
 277 /*16*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 278                 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
 279 /*17*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 280                 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
 281 /*18*/  FLAG_ENTRY0("PcicCplDatQCorErr",
 282                 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
 283 /*19*/  FLAG_ENTRY0("PcicNPostHQParityErr",
 284                 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
 285 /*20*/  FLAG_ENTRY0("PcicNPostDatQParityErr",
 286                 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
 287 /*21*/  FLAG_ENTRY0("PcicRetryMemUncErr",
 288                 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
 289 /*22*/  FLAG_ENTRY0("PcicRetrySotMemUncErr",
 290                 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
 291 /*23*/  FLAG_ENTRY0("PcicPostHdQUncErr",
 292                 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
 293 /*24*/  FLAG_ENTRY0("PcicPostDatQUncErr",
 294                 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
 295 /*25*/  FLAG_ENTRY0("PcicCplHdQUncErr",
 296                 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
 297 /*26*/  FLAG_ENTRY0("PcicCplDatQUncErr",
 298                 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
 299 /*27*/  FLAG_ENTRY0("PcicTransmitFrontParityErr",
 300                 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
 301 /*28*/  FLAG_ENTRY0("PcicTransmitBackParityErr",
 302                 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
 303 /*29*/  FLAG_ENTRY0("PcicReceiveParityErr",
 304                 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
 305 /*30*/  FLAG_ENTRY0("CceTrgtCplTimeoutErr",
 306                 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
 307 /*31*/  FLAG_ENTRY0("LATriggered",
 308                 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
 309 /*32*/  FLAG_ENTRY0("CceSegReadBadAddrErr",
 310                 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
 311 /*33*/  FLAG_ENTRY0("CceSegWriteBadAddrErr",
 312                 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
 313 /*34*/  FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
 314                 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
 315 /*35*/  FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
 316                 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
 317 /*36*/  FLAG_ENTRY0("CceMsixTableCorErr",
 318                 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
 319 /*37*/  FLAG_ENTRY0("CceMsixTableUncErr",
 320                 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
 321 /*38*/  FLAG_ENTRY0("CceIntMapCorErr",
 322                 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
 323 /*39*/  FLAG_ENTRY0("CceIntMapUncErr",
 324                 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
 325 /*40*/  FLAG_ENTRY0("CceMsixCsrParityErr",
 326                 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
 327 /*41-63 reserved*/
 328 };
 329
 330 /*
 331  * Misc Error flags
 332  */
 333 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
 334 static struct flag_table misc_err_status_flags[] = {
 335 /* 0*/  FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
 336 /* 1*/  FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
 337 /* 2*/  FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
 338 /* 3*/  FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
 339 /* 4*/  FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
 340 /* 5*/  FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
 341 /* 6*/  FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
 342 /* 7*/  FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
 343 /* 8*/  FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
 344 /* 9*/  FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
 345 /*10*/  FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
 346 /*11*/  FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
 347 /*12*/  FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
 348 };
 349
 350 /*
 351  * TXE PIO Error flags and consequences
 352  */
 353 static struct flag_table pio_err_status_flags[] = {
 354 /* 0*/  FLAG_ENTRY("PioWriteBadCtxt",
 355         SEC_WRITE_DROPPED,
 356         SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
 357 /* 1*/  FLAG_ENTRY("PioWriteAddrParity",
 358         SEC_SPC_FREEZE,
 359         SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
 360 /* 2*/  FLAG_ENTRY("PioCsrParity",
 361         SEC_SPC_FREEZE,
 362         SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
 363 /* 3*/  FLAG_ENTRY("PioSbMemFifo0",
 364         SEC_SPC_FREEZE,
 365         SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
 366 /* 4*/  FLAG_ENTRY("PioSbMemFifo1",
 367         SEC_SPC_FREEZE,
 368         SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
 369 /* 5*/  FLAG_ENTRY("PioPccFifoParity",
 370         SEC_SPC_FREEZE,
 371         SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
 372 /* 6*/  FLAG_ENTRY("PioPecFifoParity",
 373         SEC_SPC_FREEZE,
 374         SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
 375 /* 7*/  FLAG_ENTRY("PioSbrdctlCrrelParity",
 376         SEC_SPC_FREEZE,
 377         SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
 378 /* 8*/  FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
 379         SEC_SPC_FREEZE,
 380         SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
 381 /* 9*/  FLAG_ENTRY("PioPktEvictFifoParityErr",
 382         SEC_SPC_FREEZE,
 383         SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
 384 /*10*/  FLAG_ENTRY("PioSmPktResetParity",
 385         SEC_SPC_FREEZE,
 386         SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
 387 /*11*/  FLAG_ENTRY("PioVlLenMemBank0Unc",
 388         SEC_SPC_FREEZE,
 389         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
 390 /*12*/  FLAG_ENTRY("PioVlLenMemBank1Unc",
 391         SEC_SPC_FREEZE,
 392         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
 393 /*13*/  FLAG_ENTRY("PioVlLenMemBank0Cor",
 394         0,
 395         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
 396 /*14*/  FLAG_ENTRY("PioVlLenMemBank1Cor",
 397         0,
 398         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
 399 /*15*/  FLAG_ENTRY("PioCreditRetFifoParity",
 400         SEC_SPC_FREEZE,
 401         SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
 402 /*16*/  FLAG_ENTRY("PioPpmcPblFifo",
 403         SEC_SPC_FREEZE,
 404         SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
 405 /*17*/  FLAG_ENTRY("PioInitSmIn",
 406         0,
 407         SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
 408 /*18*/  FLAG_ENTRY("PioPktEvictSmOrArbSm",
 409         SEC_SPC_FREEZE,
 410         SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
 411 /*19*/  FLAG_ENTRY("PioHostAddrMemUnc",
 412         SEC_SPC_FREEZE,
 413         SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
 414 /*20*/  FLAG_ENTRY("PioHostAddrMemCor",
 415         0,
 416         SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
 417 /*21*/  FLAG_ENTRY("PioWriteDataParity",
 418         SEC_SPC_FREEZE,
 419         SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
 420 /*22*/  FLAG_ENTRY("PioStateMachine",
 421         SEC_SPC_FREEZE,
 422         SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
 423 /*23*/  FLAG_ENTRY("PioWriteQwValidParity",
 424         SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
 425         SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
 426 /*24*/  FLAG_ENTRY("PioBlockQwCountParity",
 427         SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
 428         SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
 429 /*25*/  FLAG_ENTRY("PioVlfVlLenParity",
 430         SEC_SPC_FREEZE,
 431         SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
 432 /*26*/  FLAG_ENTRY("PioVlfSopParity",
 433         SEC_SPC_FREEZE,
 434         SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
 435 /*27*/  FLAG_ENTRY("PioVlFifoParity",
 436         SEC_SPC_FREEZE,
 437         SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
 438 /*28*/  FLAG_ENTRY("PioPpmcBqcMemParity",
 439         SEC_SPC_FREEZE,
 440         SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
 441 /*29*/  FLAG_ENTRY("PioPpmcSopLen",
 442         SEC_SPC_FREEZE,
 443         SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
 444 /*30-31 reserved*/
 445 /*32*/  FLAG_ENTRY("PioCurrentFreeCntParity",
 446         SEC_SPC_FREEZE,
 447         SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
 448 /*33*/  FLAG_ENTRY("PioLastReturnedCntParity",
 449         SEC_SPC_FREEZE,
 450         SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
 451 /*34*/  FLAG_ENTRY("PioPccSopHeadParity",
 452         SEC_SPC_FREEZE,
 453         SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
 454 /*35*/  FLAG_ENTRY("PioPecSopHeadParityErr",
 455         SEC_SPC_FREEZE,
 456         SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
 457 /*36-63 reserved*/
 458 };
 459
 460 /* TXE PIO errors that cause an SPC freeze */
 461 #define ALL_PIO_FREEZE_ERR \
 462         (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
 463         | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
 464         | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
 465         | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
 466         | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
 467         | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
 468         | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
 469         | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
 470         | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
 471         | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
 472         | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
 473         | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
 474         | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
 475         | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
 476         | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
 477         | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
 478         | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
 479         | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
 480         | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
 481         | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
 482         | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
 483         | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
 484         | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
 485         | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
 486         | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
 487         | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
 488         | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
 489         | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
 490         | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
 491
 492 /*
 493  * TXE SDMA Error flags
 494  */
 495 static struct flag_table sdma_err_status_flags[] = {
 496 /* 0*/  FLAG_ENTRY0("SDmaRpyTagErr",
 497                 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
 498 /* 1*/  FLAG_ENTRY0("SDmaCsrParityErr",
 499                 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
 500 /* 2*/  FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
 501                 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
 502 /* 3*/  FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
 503                 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
 504 /*04-63 reserved*/
 505 };
 506
 507 /* TXE SDMA errors that cause an SPC freeze */
 508 #define ALL_SDMA_FREEZE_ERR  \
 509                 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
 510                 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
 511                 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
 512
 513 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
 514 #define PORT_DISCARD_EGRESS_ERRS \
 515         (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
 516         | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
 517         | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
 518
 519 /*
 520  * TXE Egress Error flags
 521  */
 522 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
 523 static struct flag_table egress_err_status_flags[] = {
 524 /* 0*/  FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
 525 /* 1*/  FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
 526 /* 2 reserved */
 527 /* 3*/  FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
 528                 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
 529 /* 4*/  FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
 530 /* 5*/  FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
 531 /* 6 reserved */
 532 /* 7*/  FLAG_ENTRY0("TxPioLaunchIntfParityErr",
 533                 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
 534 /* 8*/  FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
 535                 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
 536 /* 9-10 reserved */
 537 /*11*/  FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
 538                 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
 539 /*12*/  FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
 540 /*13*/  FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
 541 /*14*/  FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
 542 /*15*/  FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
 543 /*16*/  FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
 544                 SEES(TX_SDMA0_DISALLOWED_PACKET)),
 545 /*17*/  FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
 546                 SEES(TX_SDMA1_DISALLOWED_PACKET)),
 547 /*18*/  FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
 548                 SEES(TX_SDMA2_DISALLOWED_PACKET)),
 549 /*19*/  FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
 550                 SEES(TX_SDMA3_DISALLOWED_PACKET)),
 551 /*20*/  FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
 552                 SEES(TX_SDMA4_DISALLOWED_PACKET)),
 553 /*21*/  FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
 554                 SEES(TX_SDMA5_DISALLOWED_PACKET)),
 555 /*22*/  FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
 556                 SEES(TX_SDMA6_DISALLOWED_PACKET)),
 557 /*23*/  FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
 558                 SEES(TX_SDMA7_DISALLOWED_PACKET)),
 559 /*24*/  FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
 560                 SEES(TX_SDMA8_DISALLOWED_PACKET)),
 561 /*25*/  FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
 562                 SEES(TX_SDMA9_DISALLOWED_PACKET)),
 563 /*26*/  FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
 564                 SEES(TX_SDMA10_DISALLOWED_PACKET)),
 565 /*27*/  FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
 566                 SEES(TX_SDMA11_DISALLOWED_PACKET)),
 567 /*28*/  FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
 568                 SEES(TX_SDMA12_DISALLOWED_PACKET)),
 569 /*29*/  FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
 570                 SEES(TX_SDMA13_DISALLOWED_PACKET)),
 571 /*30*/  FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
 572                 SEES(TX_SDMA14_DISALLOWED_PACKET)),
 573 /*31*/  FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
 574                 SEES(TX_SDMA15_DISALLOWED_PACKET)),
 575 /*32*/  FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
 576                 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
 577 /*33*/  FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
 578                 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
 579 /*34*/  FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
 580                 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
 581 /*35*/  FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
 582                 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
 583 /*36*/  FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
 584                 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
 585 /*37*/  FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
 586                 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
 587 /*38*/  FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
 588                 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
 589 /*39*/  FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
 590                 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
 591 /*40*/  FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
 592                 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
 593 /*41*/  FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
 594 /*42*/  FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
 595 /*43*/  FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
 596 /*44*/  FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
 597 /*45*/  FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
 598 /*46*/  FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
 599 /*47*/  FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
 600 /*48*/  FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
 601 /*49*/  FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
 602 /*50*/  FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
 603 /*51*/  FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
 604 /*52*/  FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
 605 /*53*/  FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
 606 /*54*/  FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
 607 /*55*/  FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
 608 /*56*/  FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
 609 /*57*/  FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
 610 /*58*/  FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
 611 /*59*/  FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
 612 /*60*/  FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
 613 /*61*/  FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
 614 /*62*/  FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
 615                 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
 616 /*63*/  FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
 617                 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
 618 };
 619
 620 /*
 621  * TXE Egress Error Info flags
 622  */
 623 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
 624 static struct flag_table egress_err_info_flags[] = {
 625 /* 0*/  FLAG_ENTRY0("Reserved", 0ull),
 626 /* 1*/  FLAG_ENTRY0("VLErr", SEEI(VL)),
 627 /* 2*/  FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
 628 /* 3*/  FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
 629 /* 4*/  FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
 630 /* 5*/  FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
 631 /* 6*/  FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
 632 /* 7*/  FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
 633 /* 8*/  FLAG_ENTRY0("RawErr", SEEI(RAW)),
 634 /* 9*/  FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
 635 /*10*/  FLAG_ENTRY0("GRHErr", SEEI(GRH)),
 636 /*11*/  FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
 637 /*12*/  FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
 638 /*13*/  FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
 639 /*14*/  FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
 640 /*15*/  FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
 641 /*16*/  FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
 642 /*17*/  FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
 643 /*18*/  FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
 644 /*19*/  FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
 645 /*20*/  FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
 646 /*21*/  FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
 647 };
 648
 649 /* TXE Egress errors that cause an SPC freeze */
 650 #define ALL_TXE_EGRESS_FREEZE_ERR \
 651         (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
 652         | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
 653         | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
 654         | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
 655         | SEES(TX_LAUNCH_CSR_PARITY) \
 656         | SEES(TX_SBRD_CTL_CSR_PARITY) \
 657         | SEES(TX_CONFIG_PARITY) \
 658         | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
 659         | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
 660         | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
 661         | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
 662         | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
 663         | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
 664         | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
 665         | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
 666         | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
 667         | SEES(TX_CREDIT_RETURN_PARITY))
 668
 669 /*
 670  * TXE Send error flags
 671  */
 672 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
 673 static struct flag_table send_err_status_flags[] = {
 674 /* 0*/  FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
 675 /* 1*/  FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
 676 /* 2*/  FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
 677 };
 678
 679 /*
 680  * TXE Send Context Error flags and consequences
 681  */
 682 static struct flag_table sc_err_status_flags[] = {
 683 /* 0*/  FLAG_ENTRY("InconsistentSop",
 684                 SEC_PACKET_DROPPED | SEC_SC_HALTED,
 685                 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
 686 /* 1*/  FLAG_ENTRY("DisallowedPacket",
 687                 SEC_PACKET_DROPPED | SEC_SC_HALTED,
 688                 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
 689 /* 2*/  FLAG_ENTRY("WriteCrossesBoundary",
 690                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 691                 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
 692 /* 3*/  FLAG_ENTRY("WriteOverflow",
 693                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 694                 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
 695 /* 4*/  FLAG_ENTRY("WriteOutOfBounds",
 696                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 697                 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
 698 /* 5-63 reserved*/
 699 };
 700
 701 /*
 702  * RXE Receive Error flags
 703  */
 704 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
 705 static struct flag_table rxe_err_status_flags[] = {
 706 /* 0*/  FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
 707 /* 1*/  FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
 708 /* 2*/  FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
 709 /* 3*/  FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
 710 /* 4*/  FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
 711 /* 5*/  FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
 712 /* 6*/  FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
 713 /* 7*/  FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
 714 /* 8*/  FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
 715 /* 9*/  FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
 716 /*10*/  FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
 717 /*11*/  FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
 718 /*12*/  FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
 719 /*13*/  FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
 720 /*14*/  FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
 721 /*15*/  FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
 722 /*16*/  FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
 723                 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
 724 /*17*/  FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
 725 /*18*/  FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
 726 /*19*/  FLAG_ENTRY0("RxRbufBlockListReadUncErr",
 727                 RXES(RBUF_BLOCK_LIST_READ_UNC)),
 728 /*20*/  FLAG_ENTRY0("RxRbufBlockListReadCorErr",
 729                 RXES(RBUF_BLOCK_LIST_READ_COR)),
 730 /*21*/  FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
 731                 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
 732 /*22*/  FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
 733                 RXES(RBUF_CSR_QENT_CNT_PARITY)),
 734 /*23*/  FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
 735                 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
 736 /*24*/  FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
 737                 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
 738 /*25*/  FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
 739 /*26*/  FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
 740 /*27*/  FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
 741                 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
 742 /*28*/  FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
 743 /*29*/  FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
 744 /*30*/  FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
 745 /*31*/  FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
 746 /*32*/  FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
 747 /*33*/  FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
 748 /*34*/  FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
 749 /*35*/  FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
 750                 RXES(RBUF_FL_INITDONE_PARITY)),
 751 /*36*/  FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
 752                 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
 753 /*37*/  FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
 754 /*38*/  FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
 755 /*39*/  FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
 756 /*40*/  FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
 757                 RXES(LOOKUP_DES_PART1_UNC_COR)),
 758 /*41*/  FLAG_ENTRY0("RxLookupDesPart2ParityErr",
 759                 RXES(LOOKUP_DES_PART2_PARITY)),
 760 /*42*/  FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
 761 /*43*/  FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
 762 /*44*/  FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
 763 /*45*/  FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
 764 /*46*/  FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
 765 /*47*/  FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
 766 /*48*/  FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
 767 /*49*/  FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
 768 /*50*/  FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
 769 /*51*/  FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
 770 /*52*/  FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
 771 /*53*/  FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
 772 /*54*/  FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
 773 /*55*/  FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
 774 /*56*/  FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
 775 /*57*/  FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
 776 /*58*/  FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
 777 /*59*/  FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
 778 /*60*/  FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
 779 /*61*/  FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
 780 /*62*/  FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
 781 /*63*/  FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
 782 };
 783
 784 /* RXE errors that will trigger an SPC freeze */
 785 #define ALL_RXE_FREEZE_ERR  \
 786         (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
 787         | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
 788         | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
 789         | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
 790         | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
 791         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
 792         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
 793         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
 794         | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
 795         | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
 796         | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
 797         | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
 798         | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
 799         | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
 800         | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
 801         | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
 802         | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
 803         | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
 804         | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
 805         | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
 806         | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
 807         | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
 808         | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
 809         | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
 810         | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
 811         | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
 812         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
 813         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
 814         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
 815         | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
 816         | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
 817         | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
 818         | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
 819         | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
 820         | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
 821         | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
 822         | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
 823         | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
 824         | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
 825         | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
 826         | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
 827         | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
 828         | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
 829         | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
 830
 831 #define RXE_FREEZE_ABORT_MASK \
 832         (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
 833         RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
 834         RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
 835
 836 /*
 837  * DCC Error Flags
 838  */
 839 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
 840 static struct flag_table dcc_err_flags[] = {
 841         FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
 842         FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
 843         FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
 844         FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
 845         FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
 846         FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
 847         FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
 848         FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
 849         FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
 850         FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
 851         FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
 852         FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
 853         FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
 854         FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
 855         FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
 856         FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
 857         FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
 858         FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
 859         FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
 860         FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
 861         FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
 862         FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
 863         FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
 864         FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
 865         FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
 866         FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
 867         FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
 868         FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
 869         FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
 870         FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
 871         FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
 872         FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
 873         FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
 874         FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
 875         FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
 876         FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
 877         FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
 878         FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
 879         FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
 880         FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
 881         FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
 882         FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
 883         FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
 884         FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
 885         FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
 886         FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
 887 };
 888
 889 /*
 890  * LCB error flags
 891  */
 892 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
 893 static struct flag_table lcb_err_flags[] = {
 894 /* 0*/  FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
 895 /* 1*/  FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
 896 /* 2*/  FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
 897 /* 3*/  FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
 898                 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
 899 /* 4*/  FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
 900 /* 5*/  FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
 901 /* 6*/  FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
 902 /* 7*/  FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
 903 /* 8*/  FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
 904 /* 9*/  FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
 905 /*10*/  FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
 906 /*11*/  FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
 907 /*12*/  FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
 908 /*13*/  FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
 909                 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
 910 /*14*/  FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
 911 /*15*/  FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
 912 /*16*/  FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
 913 /*17*/  FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
 914 /*18*/  FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
 915 /*19*/  FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
 916                 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
 917 /*20*/  FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
 918 /*21*/  FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
 919 /*22*/  FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
 920 /*23*/  FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
 921 /*24*/  FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
 922 /*25*/  FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
 923 /*26*/  FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
 924                 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
 925 /*27*/  FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
 926 /*28*/  FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
 927                 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
 928 /*29*/  FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
 929                 LCBE(REDUNDANT_FLIT_PARITY_ERR))
 930 };
 931
 932 /*
 933  * DC8051 Error Flags
 934  */
 935 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
 936 static struct flag_table dc8051_err_flags[] = {
 937         FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
 938         FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
 939         FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
 940         FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
 941         FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
 942         FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
 943         FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
 944         FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
 945         FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
 946                     D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
 947         FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
 948 };
 949
 950 /*
 951  * DC8051 Information Error flags
 952  *
 953  * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
 954  */
 955 static struct flag_table dc8051_info_err_flags[] = {
 956         FLAG_ENTRY0("Spico ROM check failed",  SPICO_ROM_FAILED),
 957         FLAG_ENTRY0("Unknown frame received",  UNKNOWN_FRAME),
 958         FLAG_ENTRY0("Target BER not met",      TARGET_BER_NOT_MET),
 959         FLAG_ENTRY0("Serdes internal loopback failure",
 960                     FAILED_SERDES_INTERNAL_LOOPBACK),
 961         FLAG_ENTRY0("Failed SerDes init",      FAILED_SERDES_INIT),
 962         FLAG_ENTRY0("Failed LNI(Polling)",     FAILED_LNI_POLLING),
 963         FLAG_ENTRY0("Failed LNI(Debounce)",    FAILED_LNI_DEBOUNCE),
 964         FLAG_ENTRY0("Failed LNI(EstbComm)",    FAILED_LNI_ESTBCOMM),
 965         FLAG_ENTRY0("Failed LNI(OptEq)",       FAILED_LNI_OPTEQ),
 966         FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
 967         FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
 968         FLAG_ENTRY0("Failed LNI(ConfigLT)",    FAILED_LNI_CONFIGLT),
 969         FLAG_ENTRY0("Host Handshake Timeout",  HOST_HANDSHAKE_TIMEOUT)
 970 };
 971
 972 /*
 973  * DC8051 Information Host Information flags
 974  *
 975  * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
 976  */
 977 static struct flag_table dc8051_info_host_msg_flags[] = {
 978         FLAG_ENTRY0("Host request done", 0x0001),
 979         FLAG_ENTRY0("BC SMA message", 0x0002),
 980         FLAG_ENTRY0("BC PWR_MGM message", 0x0004),
 981         FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
 982         FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
 983         FLAG_ENTRY0("External device config request", 0x0020),
 984         FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
 985         FLAG_ENTRY0("LinkUp achieved", 0x0080),
 986         FLAG_ENTRY0("Link going down", 0x0100),
 987 };
 988
 989 static u32 encoded_size(u32 size);
 990 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
 991 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
 992 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
 993                                u8 *continuous);
 994 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
 995                                   u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
 996 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
 997                                       u8 *remote_tx_rate, u16 *link_widths);
 998 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
 999                                      u8 *flag_bits, u16 *link_widths);
1000 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1001                                   u8 *device_rev);
1002 static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed);
1003 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1004 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1005                             u8 *tx_polarity_inversion,
1006                             u8 *rx_polarity_inversion, u8 *max_rate);
1007 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1008                                 unsigned int context, u64 err_status);
1009 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1010 static void handle_dcc_err(struct hfi1_devdata *dd,
1011                            unsigned int context, u64 err_status);
1012 static void handle_lcb_err(struct hfi1_devdata *dd,
1013                            unsigned int context, u64 err_status);
1014 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1015 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1016 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1017 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1018 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1019 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1020 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1021 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1022 static void set_partition_keys(struct hfi1_pportdata *);
1023 static const char *link_state_name(u32 state);
1024 static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1025                                           u32 state);
1026 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1027                            u64 *out_data);
1028 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1029 static int thermal_init(struct hfi1_devdata *dd);
1030
1031 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1032                                   int msecs);
1033 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
1034 static void handle_temp_err(struct hfi1_devdata *);
1035 static void dc_shutdown(struct hfi1_devdata *);
1036 static void dc_start(struct hfi1_devdata *);
1037
1038 /*
1039  * Error interrupt table entry.  This is used as input to the interrupt
1040  * "clear down" routine used for all second tier error interrupt register.
1041  * Second tier interrupt registers have a single bit representing them
1042  * in the top-level CceIntStatus.
1043  */
1044 struct err_reg_info {
1045         u32 status;             /* status CSR offset */
1046         u32 clear;              /* clear CSR offset */
1047         u32 mask;               /* mask CSR offset */
1048         void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1049         const char *desc;
1050 };
1051
1052 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1053 #define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1054 #define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1055
1056 /*
1057  * Helpers for building HFI and DC error interrupt table entries.  Different
1058  * helpers are needed because of inconsistent register names.
1059  */
1060 #define EE(reg, handler, desc) \
1061         { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1062                 handler, desc }
1063 #define DC_EE1(reg, handler, desc) \
1064         { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1065 #define DC_EE2(reg, handler, desc) \
1066         { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1067
1068 /*
1069  * Table of the "misc" grouping of error interrupts.  Each entry refers to
1070  * another register containing more information.
1071  */
1072 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1073 /* 0*/  EE(CCE_ERR,             handle_cce_err,    "CceErr"),
1074 /* 1*/  EE(RCV_ERR,             handle_rxe_err,    "RxeErr"),
1075 /* 2*/  EE(MISC_ERR,    handle_misc_err,   "MiscErr"),
1076 /* 3*/  { 0, 0, 0, NULL }, /* reserved */
1077 /* 4*/  EE(SEND_PIO_ERR,    handle_pio_err,    "PioErr"),
1078 /* 5*/  EE(SEND_DMA_ERR,    handle_sdma_err,   "SDmaErr"),
1079 /* 6*/  EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1080 /* 7*/  EE(SEND_ERR,    handle_txe_err,    "TxeErr")
1081         /* the rest are reserved */
1082 };
1083
1084 /*
1085  * Index into the Various section of the interrupt sources
1086  * corresponding to the Critical Temperature interrupt.
1087  */
1088 #define TCRIT_INT_SOURCE 4
1089
1090 /*
1091  * SDMA error interrupt entry - refers to another register containing more
1092  * information.
1093  */
1094 static const struct err_reg_info sdma_eng_err =
1095         EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1096
1097 static const struct err_reg_info various_err[NUM_VARIOUS] = {
1098 /* 0*/  { 0, 0, 0, NULL }, /* PbcInt */
1099 /* 1*/  { 0, 0, 0, NULL }, /* GpioAssertInt */
1100 /* 2*/  EE(ASIC_QSFP1,  handle_qsfp_int,        "QSFP1"),
1101 /* 3*/  EE(ASIC_QSFP2,  handle_qsfp_int,        "QSFP2"),
1102 /* 4*/  { 0, 0, 0, NULL }, /* TCritInt */
1103         /* rest are reserved */
1104 };
1105
1106 /*
1107  * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1108  * register can not be derived from the MTU value because 10K is not
1109  * a power of 2. Therefore, we need a constant. Everything else can
1110  * be calculated.
1111  */
1112 #define DCC_CFG_PORT_MTU_CAP_10240 7
1113
1114 /*
1115  * Table of the DC grouping of error interrupts.  Each entry refers to
1116  * another register containing more information.
1117  */
1118 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1119 /* 0*/  DC_EE1(DCC_ERR,         handle_dcc_err,        "DCC Err"),
1120 /* 1*/  DC_EE2(DC_LCB_ERR,      handle_lcb_err,        "LCB Err"),
1121 /* 2*/  DC_EE2(DC_DC8051_ERR,   handle_8051_interrupt, "DC8051 Interrupt"),
1122 /* 3*/  /* dc_lbm_int - special, see is_dc_int() */
1123         /* the rest are reserved */
1124 };
1125
1126 struct cntr_entry {
1127         /*
1128          * counter name
1129          */
1130         char *name;
1131
1132         /*
1133          * csr to read for name (if applicable)
1134          */
1135         u64 csr;
1136
1137         /*
1138          * offset into dd or ppd to store the counter's value
1139          */
1140         int offset;
1141
1142         /*
1143          * flags
1144          */
1145         u8 flags;
1146
1147         /*
1148          * accessor for stat element, context either dd or ppd
1149          */
1150         u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl,
1151                        int mode, u64 data);
1152 };
1153
1154 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1155 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1156
1157 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1158 { \
1159         name, \
1160         csr, \
1161         offset, \
1162         flags, \
1163         accessor \
1164 }
1165
1166 /* 32bit RXE */
1167 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1168 CNTR_ELEM(#name, \
1169           (counter * 8 + RCV_COUNTER_ARRAY32), \
1170           0, flags | CNTR_32BIT, \
1171           port_access_u32_csr)
1172
1173 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1174 CNTR_ELEM(#name, \
1175           (counter * 8 + RCV_COUNTER_ARRAY32), \
1176           0, flags | CNTR_32BIT, \
1177           dev_access_u32_csr)
1178
1179 /* 64bit RXE */
1180 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1181 CNTR_ELEM(#name, \
1182           (counter * 8 + RCV_COUNTER_ARRAY64), \
1183           0, flags, \
1184           port_access_u64_csr)
1185
1186 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1187 CNTR_ELEM(#name, \
1188           (counter * 8 + RCV_COUNTER_ARRAY64), \
1189           0, flags, \
1190           dev_access_u64_csr)
1191
1192 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1193 #define OVR_ELM(ctx) \
1194 CNTR_ELEM("RcvHdrOvr" #ctx, \
1195           (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1196           0, CNTR_NORMAL, port_access_u64_csr)
1197
1198 /* 32bit TXE */
1199 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1200 CNTR_ELEM(#name, \
1201           (counter * 8 + SEND_COUNTER_ARRAY32), \
1202           0, flags | CNTR_32BIT, \
1203           port_access_u32_csr)
1204
1205 /* 64bit TXE */
1206 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1207 CNTR_ELEM(#name, \
1208           (counter * 8 + SEND_COUNTER_ARRAY64), \
1209           0, flags, \
1210           port_access_u64_csr)
1211
1212 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1213 CNTR_ELEM(#name,\
1214           counter * 8 + SEND_COUNTER_ARRAY64, \
1215           0, \
1216           flags, \
1217           dev_access_u64_csr)
1218
1219 /* CCE */
1220 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1221 CNTR_ELEM(#name, \
1222           (counter * 8 + CCE_COUNTER_ARRAY32), \
1223           0, flags | CNTR_32BIT, \
1224           dev_access_u32_csr)
1225
1226 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1227 CNTR_ELEM(#name, \
1228           (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1229           0, flags | CNTR_32BIT, \
1230           dev_access_u32_csr)
1231
1232 /* DC */
1233 #define DC_PERF_CNTR(name, counter, flags) \
1234 CNTR_ELEM(#name, \
1235           counter, \
1236           0, \
1237           flags, \
1238           dev_access_u64_csr)
1239
1240 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1241 CNTR_ELEM(#name, \
1242           counter, \
1243           0, \
1244           flags, \
1245           dc_access_lcb_cntr)
1246
1247 /* ibp counters */
1248 #define SW_IBP_CNTR(name, cntr) \
1249 CNTR_ELEM(#name, \
1250           0, \
1251           0, \
1252           CNTR_SYNTH, \
1253           access_ibp_##cntr)
1254
1255 u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1256 {
1257         if (dd->flags & HFI1_PRESENT) {
1258                 return readq((void __iomem *)dd->kregbase + offset);
1259         }
1260         return -1;
1261 }
1262
1263 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1264 {
1265         if (dd->flags & HFI1_PRESENT)
1266                 writeq(value, (void __iomem *)dd->kregbase + offset);
1267 }
1268
1269 void __iomem *get_csr_addr(
1270         struct hfi1_devdata *dd,
1271         u32 offset)
1272 {
1273         return (void __iomem *)dd->kregbase + offset;
1274 }
1275
1276 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1277                                  int mode, u64 value)
1278 {
1279         u64 ret;
1280
1281         if (mode == CNTR_MODE_R) {
1282                 ret = read_csr(dd, csr);
1283         } else if (mode == CNTR_MODE_W) {
1284                 write_csr(dd, csr, value);
1285                 ret = value;
1286         } else {
1287                 dd_dev_err(dd, "Invalid cntr register access mode");
1288                 return 0;
1289         }
1290
1291         hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1292         return ret;
1293 }
1294
1295 /* Dev Access */
1296 static u64 dev_access_u32_csr(const struct cntr_entry *entry,
1297                               void *context, int vl, int mode, u64 data)
1298 {
1299         struct hfi1_devdata *dd = context;
1300         u64 csr = entry->csr;
1301
1302         if (entry->flags & CNTR_SDMA) {
1303                 if (vl == CNTR_INVALID_VL)
1304                         return 0;
1305                 csr += 0x100 * vl;
1306         } else {
1307                 if (vl != CNTR_INVALID_VL)
1308                         return 0;
1309         }
1310         return read_write_csr(dd, csr, mode, data);
1311 }
1312
1313 static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1314                               void *context, int idx, int mode, u64 data)
1315 {
1316         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1317
1318         if (dd->per_sdma && idx < dd->num_sdma)
1319                 return dd->per_sdma[idx].err_cnt;
1320         return 0;
1321 }
1322
1323 static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1324                               void *context, int idx, int mode, u64 data)
1325 {
1326         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1327
1328         if (dd->per_sdma && idx < dd->num_sdma)
1329                 return dd->per_sdma[idx].sdma_int_cnt;
1330         return 0;
1331 }
1332
1333 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1334                                    void *context, int idx, int mode, u64 data)
1335 {
1336         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1337
1338         if (dd->per_sdma && idx < dd->num_sdma)
1339                 return dd->per_sdma[idx].idle_int_cnt;
1340         return 0;
1341 }
1342
1343 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1344                                        void *context, int idx, int mode,
1345                                        u64 data)
1346 {
1347         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1348
1349         if (dd->per_sdma && idx < dd->num_sdma)
1350                 return dd->per_sdma[idx].progress_int_cnt;
1351         return 0;
1352 }
1353
1354 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
1355                               int vl, int mode, u64 data)
1356 {
1357         struct hfi1_devdata *dd = context;
1358
1359         u64 val = 0;
1360         u64 csr = entry->csr;
1361
1362         if (entry->flags & CNTR_VL) {
1363                 if (vl == CNTR_INVALID_VL)
1364                         return 0;
1365                 csr += 8 * vl;
1366         } else {
1367                 if (vl != CNTR_INVALID_VL)
1368                         return 0;
1369         }
1370
1371         val = read_write_csr(dd, csr, mode, data);
1372         return val;
1373 }
1374
1375 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
1376                               int vl, int mode, u64 data)
1377 {
1378         struct hfi1_devdata *dd = context;
1379         u32 csr = entry->csr;
1380         int ret = 0;
1381
1382         if (vl != CNTR_INVALID_VL)
1383                 return 0;
1384         if (mode == CNTR_MODE_R)
1385                 ret = read_lcb_csr(dd, csr, &data);
1386         else if (mode == CNTR_MODE_W)
1387                 ret = write_lcb_csr(dd, csr, data);
1388
1389         if (ret) {
1390                 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1391                 return 0;
1392         }
1393
1394         hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1395         return data;
1396 }
1397
1398 /* Port Access */
1399 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
1400                                int vl, int mode, u64 data)
1401 {
1402         struct hfi1_pportdata *ppd = context;
1403
1404         if (vl != CNTR_INVALID_VL)
1405                 return 0;
1406         return read_write_csr(ppd->dd, entry->csr, mode, data);
1407 }
1408
1409 static u64 port_access_u64_csr(const struct cntr_entry *entry,
1410                                void *context, int vl, int mode, u64 data)
1411 {
1412         struct hfi1_pportdata *ppd = context;
1413         u64 val;
1414         u64 csr = entry->csr;
1415
1416         if (entry->flags & CNTR_VL) {
1417                 if (vl == CNTR_INVALID_VL)
1418                         return 0;
1419                 csr += 8 * vl;
1420         } else {
1421                 if (vl != CNTR_INVALID_VL)
1422                         return 0;
1423         }
1424         val = read_write_csr(ppd->dd, csr, mode, data);
1425         return val;
1426 }
1427
1428 /* Software defined */
1429 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1430                                 u64 data)
1431 {
1432         u64 ret;
1433
1434         if (mode == CNTR_MODE_R) {
1435                 ret = *cntr;
1436         } else if (mode == CNTR_MODE_W) {
1437                 *cntr = data;
1438                 ret = data;
1439         } else {
1440                 dd_dev_err(dd, "Invalid cntr sw access mode");
1441                 return 0;
1442         }
1443
1444         hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1445
1446         return ret;
1447 }
1448
1449 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
1450                                  int vl, int mode, u64 data)
1451 {
1452         struct hfi1_pportdata *ppd = context;
1453
1454         if (vl != CNTR_INVALID_VL)
1455                 return 0;
1456         return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1457 }
1458
1459 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
1460                                  int vl, int mode, u64 data)
1461 {
1462         struct hfi1_pportdata *ppd = context;
1463
1464         if (vl != CNTR_INVALID_VL)
1465                 return 0;
1466         return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1467 }
1468
1469 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1470                                        void *context, int vl, int mode,
1471                                        u64 data)
1472 {
1473         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1474
1475         if (vl != CNTR_INVALID_VL)
1476                 return 0;
1477         return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1478 }
1479
1480 static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
1481                                    void *context, int vl, int mode, u64 data)
1482 {
1483         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1484         u64 zero = 0;
1485         u64 *counter;
1486
1487         if (vl == CNTR_INVALID_VL)
1488                 counter = &ppd->port_xmit_discards;
1489         else if (vl >= 0 && vl < C_VL_COUNT)
1490                 counter = &ppd->port_xmit_discards_vl[vl];
1491         else
1492                 counter = &zero;
1493
1494         return read_write_sw(ppd->dd, counter, mode, data);
1495 }
1496
1497 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
1498                                        void *context, int vl, int mode,
1499                                        u64 data)
1500 {
1501         struct hfi1_pportdata *ppd = context;
1502
1503         if (vl != CNTR_INVALID_VL)
1504                 return 0;
1505
1506         return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1507                              mode, data);
1508 }
1509
1510 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
1511                                       void *context, int vl, int mode, u64 data)
1512 {
1513         struct hfi1_pportdata *ppd = context;
1514
1515         if (vl != CNTR_INVALID_VL)
1516                 return 0;
1517
1518         return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1519                              mode, data);
1520 }
1521
1522 u64 get_all_cpu_total(u64 __percpu *cntr)
1523 {
1524         int cpu;
1525         u64 counter = 0;
1526
1527         for_each_possible_cpu(cpu)
1528                 counter += *per_cpu_ptr(cntr, cpu);
1529         return counter;
1530 }
1531
1532 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1533                           u64 __percpu *cntr,
1534                           int vl, int mode, u64 data)
1535 {
1536         u64 ret = 0;
1537
1538         if (vl != CNTR_INVALID_VL)
1539                 return 0;
1540
1541         if (mode == CNTR_MODE_R) {
1542                 ret = get_all_cpu_total(cntr) - *z_val;
1543         } else if (mode == CNTR_MODE_W) {
1544                 /* A write can only zero the counter */
1545                 if (data == 0)
1546                         *z_val = get_all_cpu_total(cntr);
1547                 else
1548                         dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1549         } else {
1550                 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1551                 return 0;
1552         }
1553
1554         return ret;
1555 }
1556
1557 static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1558                               void *context, int vl, int mode, u64 data)
1559 {
1560         struct hfi1_devdata *dd = context;
1561
1562         return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1563                               mode, data);
1564 }
1565
1566 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
1567                                    void *context, int vl, int mode, u64 data)
1568 {
1569         struct hfi1_devdata *dd = context;
1570
1571         return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1572                               mode, data);
1573 }
1574
1575 static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1576                               void *context, int vl, int mode, u64 data)
1577 {
1578         struct hfi1_devdata *dd = context;
1579
1580         return dd->verbs_dev.n_piowait;
1581 }
1582
1583 static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1584                                void *context, int vl, int mode, u64 data)
1585 {
1586         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1587
1588         return dd->verbs_dev.n_piodrain;
1589 }
1590
1591 static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1592                               void *context, int vl, int mode, u64 data)
1593 {
1594         struct hfi1_devdata *dd = context;
1595
1596         return dd->verbs_dev.n_txwait;
1597 }
1598
1599 static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1600                                void *context, int vl, int mode, u64 data)
1601 {
1602         struct hfi1_devdata *dd = context;
1603
1604         return dd->verbs_dev.n_kmem_wait;
1605 }
1606
1607 static u64 access_sw_send_schedule(const struct cntr_entry *entry,
1608                                    void *context, int vl, int mode, u64 data)
1609 {
1610         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1611
1612         return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1613                               mode, data);
1614 }
1615
1616 /* Software counters for the error status bits within MISC_ERR_STATUS */
1617 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1618                                              void *context, int vl, int mode,
1619                                              u64 data)
1620 {
1621         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1622
1623         return dd->misc_err_status_cnt[12];
1624 }
1625
1626 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1627                                           void *context, int vl, int mode,
1628                                           u64 data)
1629 {
1630         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1631
1632         return dd->misc_err_status_cnt[11];
1633 }
1634
1635 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1636                                                void *context, int vl, int mode,
1637                                                u64 data)
1638 {
1639         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1640
1641         return dd->misc_err_status_cnt[10];
1642 }
1643
1644 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1645                                                  void *context, int vl,
1646                                                  int mode, u64 data)
1647 {
1648         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1649
1650         return dd->misc_err_status_cnt[9];
1651 }
1652
1653 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1654                                            void *context, int vl, int mode,
1655                                            u64 data)
1656 {
1657         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1658
1659         return dd->misc_err_status_cnt[8];
1660 }
1661
1662 static u64 access_misc_efuse_read_bad_addr_err_cnt(
1663                                 const struct cntr_entry *entry,
1664                                 void *context, int vl, int mode, u64 data)
1665 {
1666         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1667
1668         return dd->misc_err_status_cnt[7];
1669 }
1670
1671 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1672                                                 void *context, int vl,
1673                                                 int mode, u64 data)
1674 {
1675         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1676
1677         return dd->misc_err_status_cnt[6];
1678 }
1679
1680 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1681                                               void *context, int vl, int mode,
1682                                               u64 data)
1683 {
1684         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1685
1686         return dd->misc_err_status_cnt[5];
1687 }
1688
1689 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1690                                             void *context, int vl, int mode,
1691                                             u64 data)
1692 {
1693         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1694
1695         return dd->misc_err_status_cnt[4];
1696 }
1697
1698 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1699                                                  void *context, int vl,
1700                                                  int mode, u64 data)
1701 {
1702         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1703
1704         return dd->misc_err_status_cnt[3];
1705 }
1706
1707 static u64 access_misc_csr_write_bad_addr_err_cnt(
1708                                 const struct cntr_entry *entry,
1709                                 void *context, int vl, int mode, u64 data)
1710 {
1711         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1712
1713         return dd->misc_err_status_cnt[2];
1714 }
1715
1716 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1717                                                  void *context, int vl,
1718                                                  int mode, u64 data)
1719 {
1720         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1721
1722         return dd->misc_err_status_cnt[1];
1723 }
1724
1725 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1726                                           void *context, int vl, int mode,
1727                                           u64 data)
1728 {
1729         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1730
1731         return dd->misc_err_status_cnt[0];
1732 }
1733
1734 /*
1735  * Software counter for the aggregate of
1736  * individual CceErrStatus counters
1737  */
1738 static u64 access_sw_cce_err_status_aggregated_cnt(
1739                                 const struct cntr_entry *entry,
1740                                 void *context, int vl, int mode, u64 data)
1741 {
1742         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1743
1744         return dd->sw_cce_err_status_aggregate;
1745 }
1746
1747 /*
1748  * Software counters corresponding to each of the
1749  * error status bits within CceErrStatus
1750  */
1751 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1752                                               void *context, int vl, int mode,
1753                                               u64 data)
1754 {
1755         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1756
1757         return dd->cce_err_status_cnt[40];
1758 }
1759
1760 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1761                                           void *context, int vl, int mode,
1762                                           u64 data)
1763 {
1764         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1765
1766         return dd->cce_err_status_cnt[39];
1767 }
1768
1769 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1770                                           void *context, int vl, int mode,
1771                                           u64 data)
1772 {
1773         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1774
1775         return dd->cce_err_status_cnt[38];
1776 }
1777
1778 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1779                                              void *context, int vl, int mode,
1780                                              u64 data)
1781 {
1782         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1783
1784         return dd->cce_err_status_cnt[37];
1785 }
1786
1787 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1788                                              void *context, int vl, int mode,
1789                                              u64 data)
1790 {
1791         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1792
1793         return dd->cce_err_status_cnt[36];
1794 }
1795
1796 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1797                                 const struct cntr_entry *entry,
1798                                 void *context, int vl, int mode, u64 data)
1799 {
1800         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1801
1802         return dd->cce_err_status_cnt[35];
1803 }
1804
1805 static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1806                                 const struct cntr_entry *entry,
1807                                 void *context, int vl, int mode, u64 data)
1808 {
1809         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1810
1811         return dd->cce_err_status_cnt[34];
1812 }
1813
1814 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1815                                                  void *context, int vl,
1816                                                  int mode, u64 data)
1817 {
1818         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1819
1820         return dd->cce_err_status_cnt[33];
1821 }
1822
1823 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1824                                                 void *context, int vl, int mode,
1825                                                 u64 data)
1826 {
1827         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1828
1829         return dd->cce_err_status_cnt[32];
1830 }
1831
1832 static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1833                                    void *context, int vl, int mode, u64 data)
1834 {
1835         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1836
1837         return dd->cce_err_status_cnt[31];
1838 }
1839
1840 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1841                                                void *context, int vl, int mode,
1842                                                u64 data)
1843 {
1844         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1845
1846         return dd->cce_err_status_cnt[30];
1847 }
1848
1849 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1850                                               void *context, int vl, int mode,
1851                                               u64 data)
1852 {
1853         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1854
1855         return dd->cce_err_status_cnt[29];
1856 }
1857
1858 static u64 access_pcic_transmit_back_parity_err_cnt(
1859                                 const struct cntr_entry *entry,
1860                                 void *context, int vl, int mode, u64 data)
1861 {
1862         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1863
1864         return dd->cce_err_status_cnt[28];
1865 }
1866
1867 static u64 access_pcic_transmit_front_parity_err_cnt(
1868                                 const struct cntr_entry *entry,
1869                                 void *context, int vl, int mode, u64 data)
1870 {
1871         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1872
1873         return dd->cce_err_status_cnt[27];
1874 }
1875
1876 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1877                                              void *context, int vl, int mode,
1878                                              u64 data)
1879 {
1880         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1881
1882         return dd->cce_err_status_cnt[26];
1883 }
1884
1885 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1886                                             void *context, int vl, int mode,
1887                                             u64 data)
1888 {
1889         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1890
1891         return dd->cce_err_status_cnt[25];
1892 }
1893
1894 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1895                                               void *context, int vl, int mode,
1896                                               u64 data)
1897 {
1898         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1899
1900         return dd->cce_err_status_cnt[24];
1901 }
1902
1903 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1904                                              void *context, int vl, int mode,
1905                                              u64 data)
1906 {
1907         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1908
1909         return dd->cce_err_status_cnt[23];
1910 }
1911
1912 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
1913                                                  void *context, int vl,
1914                                                  int mode, u64 data)
1915 {
1916         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1917
1918         return dd->cce_err_status_cnt[22];
1919 }
1920
1921 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
1922                                          void *context, int vl, int mode,
1923                                          u64 data)
1924 {
1925         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1926
1927         return dd->cce_err_status_cnt[21];
1928 }
1929
1930 static u64 access_pcic_n_post_dat_q_parity_err_cnt(
1931                                 const struct cntr_entry *entry,
1932                                 void *context, int vl, int mode, u64 data)
1933 {
1934         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1935
1936         return dd->cce_err_status_cnt[20];
1937 }
1938
1939 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
1940                                                  void *context, int vl,
1941                                                  int mode, u64 data)
1942 {
1943         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1944
1945         return dd->cce_err_status_cnt[19];
1946 }
1947
1948 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1949                                              void *context, int vl, int mode,
1950                                              u64 data)
1951 {
1952         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1953
1954         return dd->cce_err_status_cnt[18];
1955 }
1956
1957 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1958                                             void *context, int vl, int mode,
1959                                             u64 data)
1960 {
1961         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1962
1963         return dd->cce_err_status_cnt[17];
1964 }
1965
1966 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1967                                               void *context, int vl, int mode,
1968                                               u64 data)
1969 {
1970         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1971
1972         return dd->cce_err_status_cnt[16];
1973 }
1974
1975 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1976                                              void *context, int vl, int mode,
1977                                              u64 data)
1978 {
1979         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1980
1981         return dd->cce_err_status_cnt[15];
1982 }
1983
1984 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
1985                                                  void *context, int vl,
1986                                                  int mode, u64 data)
1987 {
1988         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1989
1990         return dd->cce_err_status_cnt[14];
1991 }
1992
1993 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
1994                                              void *context, int vl, int mode,
1995                                              u64 data)
1996 {
1997         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1998
1999         return dd->cce_err_status_cnt[13];
2000 }
2001
2002 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2003                                 const struct cntr_entry *entry,
2004                                 void *context, int vl, int mode, u64 data)
2005 {
2006         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2007
2008         return dd->cce_err_status_cnt[12];
2009 }
2010
2011 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2012                                 const struct cntr_entry *entry,
2013                                 void *context, int vl, int mode, u64 data)
2014 {
2015         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2016
2017         return dd->cce_err_status_cnt[11];
2018 }
2019
2020 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2021                                 const struct cntr_entry *entry,
2022                                 void *context, int vl, int mode, u64 data)
2023 {
2024         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2025
2026         return dd->cce_err_status_cnt[10];
2027 }
2028
2029 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2030                                 const struct cntr_entry *entry,
2031                                 void *context, int vl, int mode, u64 data)
2032 {
2033         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2034
2035         return dd->cce_err_status_cnt[9];
2036 }
2037
2038 static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2039                                 const struct cntr_entry *entry,
2040                                 void *context, int vl, int mode, u64 data)
2041 {
2042         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2043
2044         return dd->cce_err_status_cnt[8];
2045 }
2046
2047 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2048                                                  void *context, int vl,
2049                                                  int mode, u64 data)
2050 {
2051         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2052
2053         return dd->cce_err_status_cnt[7];
2054 }
2055
2056 static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2057                                 const struct cntr_entry *entry,
2058                                 void *context, int vl, int mode, u64 data)
2059 {
2060         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2061
2062         return dd->cce_err_status_cnt[6];
2063 }
2064
2065 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2066                                                void *context, int vl, int mode,
2067                                                u64 data)
2068 {
2069         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2070
2071         return dd->cce_err_status_cnt[5];
2072 }
2073
2074 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2075                                           void *context, int vl, int mode,
2076                                           u64 data)
2077 {
2078         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2079
2080         return dd->cce_err_status_cnt[4];
2081 }
2082
2083 static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2084                                 const struct cntr_entry *entry,
2085                                 void *context, int vl, int mode, u64 data)
2086 {
2087         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2088
2089         return dd->cce_err_status_cnt[3];
2090 }
2091
2092 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2093                                                  void *context, int vl,
2094                                                  int mode, u64 data)
2095 {
2096         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2097
2098         return dd->cce_err_status_cnt[2];
2099 }
2100
2101 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2102                                                 void *context, int vl,
2103                                                 int mode, u64 data)
2104 {
2105         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2106
2107         return dd->cce_err_status_cnt[1];
2108 }
2109
2110 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2111                                          void *context, int vl, int mode,
2112                                          u64 data)
2113 {
2114         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2115
2116         return dd->cce_err_status_cnt[0];
2117 }
2118
2119 /*
2120  * Software counters corresponding to each of the
2121  * error status bits within RcvErrStatus
2122  */
2123 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2124                                         void *context, int vl, int mode,
2125                                         u64 data)
2126 {
2127         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2128
2129         return dd->rcv_err_status_cnt[63];
2130 }
2131
2132 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2133                                                 void *context, int vl,
2134                                                 int mode, u64 data)
2135 {
2136         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2137
2138         return dd->rcv_err_status_cnt[62];
2139 }
2140
2141 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2142                                                void *context, int vl, int mode,
2143                                                u64 data)
2144 {
2145         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2146
2147         return dd->rcv_err_status_cnt[61];
2148 }
2149
2150 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2151                                          void *context, int vl, int mode,
2152                                          u64 data)
2153 {
2154         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2155
2156         return dd->rcv_err_status_cnt[60];
2157 }
2158
2159 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2160                                                  void *context, int vl,
2161                                                  int mode, u64 data)
2162 {
2163         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2164
2165         return dd->rcv_err_status_cnt[59];
2166 }
2167
2168 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2169                                                  void *context, int vl,
2170                                                  int mode, u64 data)
2171 {
2172         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2173
2174         return dd->rcv_err_status_cnt[58];
2175 }
2176
2177 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2178                                             void *context, int vl, int mode,
2179                                             u64 data)
2180 {
2181         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2182
2183         return dd->rcv_err_status_cnt[57];
2184 }
2185
2186 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2187                                            void *context, int vl, int mode,
2188                                            u64 data)
2189 {
2190         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2191
2192         return dd->rcv_err_status_cnt[56];
2193 }
2194
2195 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2196                                            void *context, int vl, int mode,
2197                                            u64 data)
2198 {
2199         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2200
2201         return dd->rcv_err_status_cnt[55];
2202 }
2203
2204 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2205                                 const struct cntr_entry *entry,
2206                                 void *context, int vl, int mode, u64 data)
2207 {
2208         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2209
2210         return dd->rcv_err_status_cnt[54];
2211 }
2212
2213 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2214                                 const struct cntr_entry *entry,
2215                                 void *context, int vl, int mode, u64 data)
2216 {
2217         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2218
2219         return dd->rcv_err_status_cnt[53];
2220 }
2221
2222 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2223                                                  void *context, int vl,
2224                                                  int mode, u64 data)
2225 {
2226         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2227
2228         return dd->rcv_err_status_cnt[52];
2229 }
2230
2231 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2232                                                  void *context, int vl,
2233                                                  int mode, u64 data)
2234 {
2235         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2236
2237         return dd->rcv_err_status_cnt[51];
2238 }
2239
2240 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2241                                                  void *context, int vl,
2242                                                  int mode, u64 data)
2243 {
2244         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2245
2246         return dd->rcv_err_status_cnt[50];
2247 }
2248
2249 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2250                                                  void *context, int vl,
2251                                                  int mode, u64 data)
2252 {
2253         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2254
2255         return dd->rcv_err_status_cnt[49];
2256 }
2257
2258 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2259                                                  void *context, int vl,
2260                                                  int mode, u64 data)
2261 {
2262         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2263
2264         return dd->rcv_err_status_cnt[48];
2265 }
2266
2267 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2268                                                  void *context, int vl,
2269                                                  int mode, u64 data)
2270 {
2271         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2272
2273         return dd->rcv_err_status_cnt[47];
2274 }
2275
2276 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2277                                          void *context, int vl, int mode,
2278                                          u64 data)
2279 {
2280         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2281
2282         return dd->rcv_err_status_cnt[46];
2283 }
2284
2285 static u64 access_rx_hq_intr_csr_parity_err_cnt(
2286                                 const struct cntr_entry *entry,
2287                                 void *context, int vl, int mode, u64 data)
2288 {
2289         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2290
2291         return dd->rcv_err_status_cnt[45];
2292 }
2293
2294 static u64 access_rx_lookup_csr_parity_err_cnt(
2295                                 const struct cntr_entry *entry,
2296                                 void *context, int vl, int mode, u64 data)
2297 {
2298         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2299
2300         return dd->rcv_err_status_cnt[44];
2301 }
2302
2303 static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2304                                 const struct cntr_entry *entry,
2305                                 void *context, int vl, int mode, u64 data)
2306 {
2307         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2308
2309         return dd->rcv_err_status_cnt[43];
2310 }
2311
2312 static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2313                                 const struct cntr_entry *entry,
2314                                 void *context, int vl, int mode, u64 data)
2315 {
2316         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2317
2318         return dd->rcv_err_status_cnt[42];
2319 }
2320
2321 static u64 access_rx_lookup_des_part2_parity_err_cnt(
2322                                 const struct cntr_entry *entry,
2323                                 void *context, int vl, int mode, u64 data)
2324 {
2325         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2326
2327         return dd->rcv_err_status_cnt[41];
2328 }
2329
2330 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2331                                 const struct cntr_entry *entry,
2332                                 void *context, int vl, int mode, u64 data)
2333 {
2334         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2335
2336         return dd->rcv_err_status_cnt[40];
2337 }
2338
2339 static u64 access_rx_lookup_des_part1_unc_err_cnt(
2340                                 const struct cntr_entry *entry,
2341                                 void *context, int vl, int mode, u64 data)
2342 {
2343         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2344
2345         return dd->rcv_err_status_cnt[39];
2346 }
2347
2348 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2349                                 const struct cntr_entry *entry,
2350                                 void *context, int vl, int mode, u64 data)
2351 {
2352         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2353
2354         return dd->rcv_err_status_cnt[38];
2355 }
2356
2357 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2358                                 const struct cntr_entry *entry,
2359                                 void *context, int vl, int mode, u64 data)
2360 {
2361         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2362
2363         return dd->rcv_err_status_cnt[37];
2364 }
2365
2366 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2367                                 const struct cntr_entry *entry,
2368                                 void *context, int vl, int mode, u64 data)
2369 {
2370         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2371
2372         return dd->rcv_err_status_cnt[36];
2373 }
2374
2375 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2376                                 const struct cntr_entry *entry,
2377                                 void *context, int vl, int mode, u64 data)
2378 {
2379         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2380
2381         return dd->rcv_err_status_cnt[35];
2382 }
2383
2384 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2385                                 const struct cntr_entry *entry,
2386                                 void *context, int vl, int mode, u64 data)
2387 {
2388         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2389
2390         return dd->rcv_err_status_cnt[34];
2391 }
2392
2393 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2394                                 const struct cntr_entry *entry,
2395                                 void *context, int vl, int mode, u64 data)
2396 {
2397         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2398
2399         return dd->rcv_err_status_cnt[33];
2400 }
2401
2402 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2403                                         void *context, int vl, int mode,
2404                                         u64 data)
2405 {
2406         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2407
2408         return dd->rcv_err_status_cnt[32];
2409 }
2410
2411 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2412                                        void *context, int vl, int mode,
2413                                        u64 data)
2414 {
2415         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2416
2417         return dd->rcv_err_status_cnt[31];
2418 }
2419
2420 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2421                                           void *context, int vl, int mode,
2422                                           u64 data)
2423 {
2424         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2425
2426         return dd->rcv_err_status_cnt[30];
2427 }
2428
2429 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2430                                              void *context, int vl, int mode,
2431                                              u64 data)
2432 {
2433         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2434
2435         return dd->rcv_err_status_cnt[29];
2436 }
2437
2438 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2439                                                  void *context, int vl,
2440                                                  int mode, u64 data)
2441 {
2442         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2443
2444         return dd->rcv_err_status_cnt[28];
2445 }
2446
2447 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2448                                 const struct cntr_entry *entry,
2449                                 void *context, int vl, int mode, u64 data)
2450 {
2451         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2452
2453         return dd->rcv_err_status_cnt[27];
2454 }
2455
2456 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2457                                 const struct cntr_entry *entry,
2458                                 void *context, int vl, int mode, u64 data)
2459 {
2460         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2461
2462         return dd->rcv_err_status_cnt[26];
2463 }
2464
2465 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2466                                 const struct cntr_entry *entry,
2467                                 void *context, int vl, int mode, u64 data)
2468 {
2469         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2470
2471         return dd->rcv_err_status_cnt[25];
2472 }
2473
2474 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2475                                 const struct cntr_entry *entry,
2476                                 void *context, int vl, int mode, u64 data)
2477 {
2478         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2479
2480         return dd->rcv_err_status_cnt[24];
2481 }
2482
2483 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2484                                 const struct cntr_entry *entry,
2485                                 void *context, int vl, int mode, u64 data)
2486 {
2487         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2488
2489         return dd->rcv_err_status_cnt[23];
2490 }
2491
2492 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2493                                 const struct cntr_entry *entry,
2494                                 void *context, int vl, int mode, u64 data)
2495 {
2496         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2497
2498         return dd->rcv_err_status_cnt[22];
2499 }
2500
2501 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2502                                 const struct cntr_entry *entry,
2503                                 void *context, int vl, int mode, u64 data)
2504 {
2505         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2506
2507         return dd->rcv_err_status_cnt[21];
2508 }
2509
2510 static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2511                                 const struct cntr_entry *entry,
2512                                 void *context, int vl, int mode, u64 data)
2513 {
2514         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2515
2516         return dd->rcv_err_status_cnt[20];
2517 }
2518
2519 static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2520                                 const struct cntr_entry *entry,
2521                                 void *context, int vl, int mode, u64 data)
2522 {
2523         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2524
2525         return dd->rcv_err_status_cnt[19];
2526 }
2527
2528 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2529                                                  void *context, int vl,
2530                                                  int mode, u64 data)
2531 {
2532         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2533
2534         return dd->rcv_err_status_cnt[18];
2535 }
2536
2537 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2538                                                  void *context, int vl,
2539                                                  int mode, u64 data)
2540 {
2541         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2542
2543         return dd->rcv_err_status_cnt[17];
2544 }
2545
2546 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2547                                 const struct cntr_entry *entry,
2548                                 void *context, int vl, int mode, u64 data)
2549 {
2550         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2551
2552         return dd->rcv_err_status_cnt[16];
2553 }
2554
2555 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2556                                 const struct cntr_entry *entry,
2557                                 void *context, int vl, int mode, u64 data)
2558 {
2559         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2560
2561         return dd->rcv_err_status_cnt[15];
2562 }
2563
2564 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2565                                                 void *context, int vl,
2566                                                 int mode, u64 data)
2567 {
2568         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2569
2570         return dd->rcv_err_status_cnt[14];
2571 }
2572
2573 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2574                                                 void *context, int vl,
2575                                                 int mode, u64 data)
2576 {
2577         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2578
2579         return dd->rcv_err_status_cnt[13];
2580 }
2581
2582 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2583                                               void *context, int vl, int mode,
2584                                               u64 data)
2585 {
2586         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2587
2588         return dd->rcv_err_status_cnt[12];
2589 }
2590
2591 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2592                                           void *context, int vl, int mode,
2593                                           u64 data)
2594 {
2595         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2596
2597         return dd->rcv_err_status_cnt[11];
2598 }
2599
2600 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2601                                           void *context, int vl, int mode,
2602                                           u64 data)
2603 {
2604         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2605
2606         return dd->rcv_err_status_cnt[10];
2607 }
2608
2609 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2610                                                void *context, int vl, int mode,
2611                                                u64 data)
2612 {
2613         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2614
2615         return dd->rcv_err_status_cnt[9];
2616 }
2617
2618 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2619                                             void *context, int vl, int mode,
2620                                             u64 data)
2621 {
2622         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2623
2624         return dd->rcv_err_status_cnt[8];
2625 }
2626
2627 static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2628                                 const struct cntr_entry *entry,
2629                                 void *context, int vl, int mode, u64 data)
2630 {
2631         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2632
2633         return dd->rcv_err_status_cnt[7];
2634 }
2635
2636 static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2637                                 const struct cntr_entry *entry,
2638                                 void *context, int vl, int mode, u64 data)
2639 {
2640         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2641
2642         return dd->rcv_err_status_cnt[6];
2643 }
2644
2645 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2646                                           void *context, int vl, int mode,
2647                                           u64 data)
2648 {
2649         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2650
2651         return dd->rcv_err_status_cnt[5];
2652 }
2653
2654 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2655                                           void *context, int vl, int mode,
2656                                           u64 data)
2657 {
2658         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2659
2660         return dd->rcv_err_status_cnt[4];
2661 }
2662
2663 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2664                                          void *context, int vl, int mode,
2665                                          u64 data)
2666 {
2667         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2668
2669         return dd->rcv_err_status_cnt[3];
2670 }
2671
2672 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2673                                          void *context, int vl, int mode,
2674                                          u64 data)
2675 {
2676         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2677
2678         return dd->rcv_err_status_cnt[2];
2679 }
2680
2681 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2682                                             void *context, int vl, int mode,
2683                                             u64 data)
2684 {
2685         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2686
2687         return dd->rcv_err_status_cnt[1];
2688 }
2689
2690 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2691                                          void *context, int vl, int mode,
2692                                          u64 data)
2693 {
2694         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2695
2696         return dd->rcv_err_status_cnt[0];
2697 }
2698
2699 /*
2700  * Software counters corresponding to each of the
2701  * error status bits within SendPioErrStatus
2702  */
2703 static u64 access_pio_pec_sop_head_parity_err_cnt(
2704                                 const struct cntr_entry *entry,
2705                                 void *context, int vl, int mode, u64 data)
2706 {
2707         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2708
2709         return dd->send_pio_err_status_cnt[35];
2710 }
2711
2712 static u64 access_pio_pcc_sop_head_parity_err_cnt(
2713                                 const struct cntr_entry *entry,
2714                                 void *context, int vl, int mode, u64 data)
2715 {
2716         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2717
2718         return dd->send_pio_err_status_cnt[34];
2719 }
2720
2721 static u64 access_pio_last_returned_cnt_parity_err_cnt(
2722                                 const struct cntr_entry *entry,
2723                                 void *context, int vl, int mode, u64 data)
2724 {
2725         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2726
2727         return dd->send_pio_err_status_cnt[33];
2728 }
2729
2730 static u64 access_pio_current_free_cnt_parity_err_cnt(
2731                                 const struct cntr_entry *entry,
2732                                 void *context, int vl, int mode, u64 data)
2733 {
2734         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2735
2736         return dd->send_pio_err_status_cnt[32];
2737 }
2738
2739 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2740                                           void *context, int vl, int mode,
2741                                           u64 data)
2742 {
2743         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2744
2745         return dd->send_pio_err_status_cnt[31];
2746 }
2747
2748 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2749                                           void *context, int vl, int mode,
2750                                           u64 data)
2751 {
2752         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2753
2754         return dd->send_pio_err_status_cnt[30];
2755 }
2756
2757 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2758                                            void *context, int vl, int mode,
2759                                            u64 data)
2760 {
2761         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2762
2763         return dd->send_pio_err_status_cnt[29];
2764 }
2765
2766 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2767                                 const struct cntr_entry *entry,
2768                                 void *context, int vl, int mode, u64 data)
2769 {
2770         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2771
2772         return dd->send_pio_err_status_cnt[28];
2773 }
2774
2775 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2776                                              void *context, int vl, int mode,
2777                                              u64 data)
2778 {
2779         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2780
2781         return dd->send_pio_err_status_cnt[27];
2782 }
2783
2784 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2785                                              void *context, int vl, int mode,
2786                                              u64 data)
2787 {
2788         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2789
2790         return dd->send_pio_err_status_cnt[26];
2791 }
2792
2793 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2794                                                 void *context, int vl,
2795                                                 int mode, u64 data)
2796 {
2797         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2798
2799         return dd->send_pio_err_status_cnt[25];
2800 }
2801
2802 static u64 access_pio_block_qw_count_parity_err_cnt(
2803                                 const struct cntr_entry *entry,
2804                                 void *context, int vl, int mode, u64 data)
2805 {
2806         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2807
2808         return dd->send_pio_err_status_cnt[24];
2809 }
2810
2811 static u64 access_pio_write_qw_valid_parity_err_cnt(
2812                                 const struct cntr_entry *entry,
2813                                 void *context, int vl, int mode, u64 data)
2814 {
2815         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2816
2817         return dd->send_pio_err_status_cnt[23];
2818 }
2819
2820 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2821                                             void *context, int vl, int mode,
2822                                             u64 data)
2823 {
2824         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2825
2826         return dd->send_pio_err_status_cnt[22];
2827 }
2828
2829 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2830                                                 void *context, int vl,
2831                                                 int mode, u64 data)
2832 {
2833         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2834
2835         return dd->send_pio_err_status_cnt[21];
2836 }
2837
2838 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2839                                                 void *context, int vl,
2840                                                 int mode, u64 data)
2841 {
2842         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2843
2844         return dd->send_pio_err_status_cnt[20];
2845 }
2846
2847 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2848                                                 void *context, int vl,
2849                                                 int mode, u64 data)
2850 {
2851         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2852
2853         return dd->send_pio_err_status_cnt[19];
2854 }
2855
2856 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2857                                 const struct cntr_entry *entry,
2858                                 void *context, int vl, int mode, u64 data)
2859 {
2860         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2861
2862         return dd->send_pio_err_status_cnt[18];
2863 }
2864
2865 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2866                                          void *context, int vl, int mode,
2867                                          u64 data)
2868 {
2869         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2870
2871         return dd->send_pio_err_status_cnt[17];
2872 }
2873
2874 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2875                                             void *context, int vl, int mode,
2876                                             u64 data)
2877 {
2878         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2879
2880         return dd->send_pio_err_status_cnt[16];
2881 }
2882
2883 static u64 access_pio_credit_ret_fifo_parity_err_cnt(
2884                                 const struct cntr_entry *entry,
2885                                 void *context, int vl, int mode, u64 data)
2886 {
2887         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2888
2889         return dd->send_pio_err_status_cnt[15];
2890 }
2891
2892 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
2893                                 const struct cntr_entry *entry,
2894                                 void *context, int vl, int mode, u64 data)
2895 {
2896         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2897
2898         return dd->send_pio_err_status_cnt[14];
2899 }
2900
2901 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
2902                                 const struct cntr_entry *entry,
2903                                 void *context, int vl, int mode, u64 data)
2904 {
2905         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2906
2907         return dd->send_pio_err_status_cnt[13];
2908 }
2909
2910 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
2911                                 const struct cntr_entry *entry,
2912                                 void *context, int vl, int mode, u64 data)
2913 {
2914         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2915
2916         return dd->send_pio_err_status_cnt[12];
2917 }
2918
2919 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
2920                                 const struct cntr_entry *entry,
2921                                 void *context, int vl, int mode, u64 data)
2922 {
2923         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2924
2925         return dd->send_pio_err_status_cnt[11];
2926 }
2927
2928 static u64 access_pio_sm_pkt_reset_parity_err_cnt(
2929                                 const struct cntr_entry *entry,
2930                                 void *context, int vl, int mode, u64 data)
2931 {
2932         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2933
2934         return dd->send_pio_err_status_cnt[10];
2935 }
2936
2937 static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
2938                                 const struct cntr_entry *entry,
2939                                 void *context, int vl, int mode, u64 data)
2940 {
2941         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2942
2943         return dd->send_pio_err_status_cnt[9];
2944 }
2945
2946 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
2947                                 const struct cntr_entry *entry,
2948                                 void *context, int vl, int mode, u64 data)
2949 {
2950         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2951
2952         return dd->send_pio_err_status_cnt[8];
2953 }
2954
2955 static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
2956                                 const struct cntr_entry *entry,
2957                                 void *context, int vl, int mode, u64 data)
2958 {
2959         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2960
2961         return dd->send_pio_err_status_cnt[7];
2962 }
2963
2964 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
2965                                               void *context, int vl, int mode,
2966                                               u64 data)
2967 {
2968         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2969
2970         return dd->send_pio_err_status_cnt[6];
2971 }
2972
2973 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
2974                                               void *context, int vl, int mode,
2975                                               u64 data)
2976 {
2977         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2978
2979         return dd->send_pio_err_status_cnt[5];
2980 }
2981
2982 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
2983                                            void *context, int vl, int mode,
2984                                            u64 data)
2985 {
2986         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2987
2988         return dd->send_pio_err_status_cnt[4];
2989 }
2990
2991 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
2992                                            void *context, int vl, int mode,
2993                                            u64 data)
2994 {
2995         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2996
2997         return dd->send_pio_err_status_cnt[3];
2998 }
2999
3000 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3001                                          void *context, int vl, int mode,
3002                                          u64 data)
3003 {
3004         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3005
3006         return dd->send_pio_err_status_cnt[2];
3007 }
3008
3009 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3010                                                 void *context, int vl,
3011                                                 int mode, u64 data)
3012 {
3013         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3014
3015         return dd->send_pio_err_status_cnt[1];
3016 }
3017
3018 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3019                                              void *context, int vl, int mode,
3020                                              u64 data)
3021 {
3022         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3023
3024         return dd->send_pio_err_status_cnt[0];
3025 }
3026
3027 /*
3028  * Software counters corresponding to each of the
3029  * error status bits within SendDmaErrStatus
3030  */
3031 static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3032                                 const struct cntr_entry *entry,
3033                                 void *context, int vl, int mode, u64 data)
3034 {
3035         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3036
3037         return dd->send_dma_err_status_cnt[3];
3038 }
3039
3040 static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3041                                 const struct cntr_entry *entry,
3042                                 void *context, int vl, int mode, u64 data)
3043 {
3044         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3045
3046         return dd->send_dma_err_status_cnt[2];
3047 }
3048
3049 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3050                                           void *context, int vl, int mode,
3051                                           u64 data)
3052 {
3053         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3054
3055         return dd->send_dma_err_status_cnt[1];
3056 }
3057
3058 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3059                                        void *context, int vl, int mode,
3060                                        u64 data)
3061 {
3062         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3063
3064         return dd->send_dma_err_status_cnt[0];
3065 }
3066
3067 /*
3068  * Software counters corresponding to each of the
3069  * error status bits within SendEgressErrStatus
3070  */
3071 static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3072                                 const struct cntr_entry *entry,
3073                                 void *context, int vl, int mode, u64 data)
3074 {
3075         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3076
3077         return dd->send_egress_err_status_cnt[63];
3078 }
3079
3080 static u64 access_tx_read_sdma_memory_csr_err_cnt(
3081                                 const struct cntr_entry *entry,
3082                                 void *context, int vl, int mode, u64 data)
3083 {
3084         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3085
3086         return dd->send_egress_err_status_cnt[62];
3087 }
3088
3089 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3090                                              void *context, int vl, int mode,
3091                                              u64 data)
3092 {
3093         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3094
3095         return dd->send_egress_err_status_cnt[61];
3096 }
3097
3098 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3099                                                  void *context, int vl,
3100                                                  int mode, u64 data)
3101 {
3102         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3103
3104         return dd->send_egress_err_status_cnt[60];
3105 }
3106
3107 static u64 access_tx_read_sdma_memory_cor_err_cnt(
3108                                 const struct cntr_entry *entry,
3109                                 void *context, int vl, int mode, u64 data)
3110 {
3111         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3112
3113         return dd->send_egress_err_status_cnt[59];
3114 }
3115
3116 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3117                                         void *context, int vl, int mode,
3118                                         u64 data)
3119 {
3120         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3121
3122         return dd->send_egress_err_status_cnt[58];
3123 }
3124
3125 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3126                                             void *context, int vl, int mode,
3127                                             u64 data)
3128 {
3129         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3130
3131         return dd->send_egress_err_status_cnt[57];
3132 }
3133
3134 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3135                                               void *context, int vl, int mode,
3136                                               u64 data)
3137 {
3138         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3139
3140         return dd->send_egress_err_status_cnt[56];
3141 }
3142
3143 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3144                                               void *context, int vl, int mode,
3145                                               u64 data)
3146 {
3147         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3148
3149         return dd->send_egress_err_status_cnt[55];
3150 }
3151
3152 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3153                                               void *context, int vl, int mode,
3154                                               u64 data)
3155 {
3156         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3157
3158         return dd->send_egress_err_status_cnt[54];
3159 }
3160
3161 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3162                                               void *context, int vl, int mode,
3163                                               u64 data)
3164 {
3165         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3166
3167         return dd->send_egress_err_status_cnt[53];
3168 }
3169
3170 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3171                                               void *context, int vl, int mode,
3172                                               u64 data)
3173 {
3174         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3175
3176         return dd->send_egress_err_status_cnt[52];
3177 }
3178
3179 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3180                                               void *context, int vl, int mode,
3181                                               u64 data)
3182 {
3183         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3184
3185         return dd->send_egress_err_status_cnt[51];
3186 }
3187
3188 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3189                                               void *context, int vl, int mode,
3190                                               u64 data)
3191 {
3192         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3193
3194         return dd->send_egress_err_status_cnt[50];
3195 }
3196
3197 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3198                                               void *context, int vl, int mode,
3199                                               u64 data)
3200 {
3201         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3202
3203         return dd->send_egress_err_status_cnt[49];
3204 }
3205
3206 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3207                                               void *context, int vl, int mode,
3208                                               u64 data)
3209 {
3210         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3211
3212         return dd->send_egress_err_status_cnt[48];
3213 }
3214
3215 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3216                                               void *context, int vl, int mode,
3217                                               u64 data)
3218 {
3219         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3220
3221         return dd->send_egress_err_status_cnt[47];
3222 }
3223
3224 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3225                                             void *context, int vl, int mode,
3226                                             u64 data)
3227 {
3228         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3229
3230         return dd->send_egress_err_status_cnt[46];
3231 }
3232
3233 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3234                                              void *context, int vl, int mode,
3235                                              u64 data)
3236 {
3237         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3238
3239         return dd->send_egress_err_status_cnt[45];
3240 }
3241
3242 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3243                                                  void *context, int vl,
3244                                                  int mode, u64 data)
3245 {
3246         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3247
3248         return dd->send_egress_err_status_cnt[44];
3249 }
3250
3251 static u64 access_tx_read_sdma_memory_unc_err_cnt(
3252                                 const struct cntr_entry *entry,
3253                                 void *context, int vl, int mode, u64 data)
3254 {
3255         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3256
3257         return dd->send_egress_err_status_cnt[43];
3258 }
3259
3260 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3261                                         void *context, int vl, int mode,
3262                                         u64 data)
3263 {
3264         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3265
3266         return dd->send_egress_err_status_cnt[42];
3267 }
3268
3269 static u64 access_tx_credit_return_partiy_err_cnt(
3270                                 const struct cntr_entry *entry,
3271                                 void *context, int vl, int mode, u64 data)
3272 {
3273         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3274
3275         return dd->send_egress_err_status_cnt[41];
3276 }
3277
3278 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3279                                 const struct cntr_entry *entry,
3280                                 void *context, int vl, int mode, u64 data)
3281 {
3282         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3283
3284         return dd->send_egress_err_status_cnt[40];
3285 }
3286
3287 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3288                                 const struct cntr_entry *entry,
3289                                 void *context, int vl, int mode, u64 data)
3290 {
3291         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3292
3293         return dd->send_egress_err_status_cnt[39];
3294 }
3295
3296 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3297                                 const struct cntr_entry *entry,
3298                                 void *context, int vl, int mode, u64 data)
3299 {
3300         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3301
3302         return dd->send_egress_err_status_cnt[38];
3303 }
3304
3305 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3306                                 const struct cntr_entry *entry,
3307                                 void *context, int vl, int mode, u64 data)
3308 {
3309         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3310
3311         return dd->send_egress_err_status_cnt[37];
3312 }
3313
3314 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3315                                 const struct cntr_entry *entry,
3316                                 void *context, int vl, int mode, u64 data)
3317 {
3318         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3319
3320         return dd->send_egress_err_status_cnt[36];
3321 }
3322
3323 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3324                                 const struct cntr_entry *entry,
3325                                 void *context, int vl, int mode, u64 data)
3326 {
3327         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3328
3329         return dd->send_egress_err_status_cnt[35];
3330 }
3331
3332 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3333                                 const struct cntr_entry *entry,
3334                                 void *context, int vl, int mode, u64 data)
3335 {
3336         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3337
3338         return dd->send_egress_err_status_cnt[34];
3339 }
3340
3341 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3342                                 const struct cntr_entry *entry,
3343                                 void *context, int vl, int mode, u64 data)
3344 {
3345         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3346
3347         return dd->send_egress_err_status_cnt[33];
3348 }
3349
3350 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3351                                 const struct cntr_entry *entry,
3352                                 void *context, int vl, int mode, u64 data)
3353 {
3354         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3355
3356         return dd->send_egress_err_status_cnt[32];
3357 }
3358
3359 static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3360                                 const struct cntr_entry *entry,
3361                                 void *context, int vl, int mode, u64 data)
3362 {
3363         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3364
3365         return dd->send_egress_err_status_cnt[31];
3366 }
3367
3368 static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3369                                 const struct cntr_entry *entry,
3370                                 void *context, int vl, int mode, u64 data)
3371 {
3372         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3373
3374         return dd->send_egress_err_status_cnt[30];
3375 }
3376
3377 static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3378                                 const struct cntr_entry *entry,
3379                                 void *context, int vl, int mode, u64 data)
3380 {
3381         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3382
3383         return dd->send_egress_err_status_cnt[29];
3384 }
3385
3386 static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3387                                 const struct cntr_entry *entry,
3388                                 void *context, int vl, int mode, u64 data)
3389 {
3390         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3391
3392         return dd->send_egress_err_status_cnt[28];
3393 }
3394
3395 static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3396                                 const struct cntr_entry *entry,
3397                                 void *context, int vl, int mode, u64 data)
3398 {
3399         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3400
3401         return dd->send_egress_err_status_cnt[27];
3402 }
3403
3404 static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3405                                 const struct cntr_entry *entry,
3406                                 void *context, int vl, int mode, u64 data)
3407 {
3408         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3409
3410         return dd->send_egress_err_status_cnt[26];
3411 }
3412
3413 static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3414                                 const struct cntr_entry *entry,
3415                                 void *context, int vl, int mode, u64 data)
3416 {
3417         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3418
3419         return dd->send_egress_err_status_cnt[25];
3420 }
3421
3422 static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3423                                 const struct cntr_entry *entry,
3424                                 void *context, int vl, int mode, u64 data)
3425 {
3426         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3427
3428         return dd->send_egress_err_status_cnt[24];
3429 }
3430
3431 static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3432                                 const struct cntr_entry *entry,
3433                                 void *context, int vl, int mode, u64 data)
3434 {
3435         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3436
3437         return dd->send_egress_err_status_cnt[23];
3438 }
3439
3440 static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3441                                 const struct cntr_entry *entry,
3442                                 void *context, int vl, int mode, u64 data)
3443 {
3444         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3445
3446         return dd->send_egress_err_status_cnt[22];
3447 }
3448
3449 static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3450                                 const struct cntr_entry *entry,
3451                                 void *context, int vl, int mode, u64 data)
3452 {
3453         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3454
3455         return dd->send_egress_err_status_cnt[21];
3456 }
3457
3458 static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3459                                 const struct cntr_entry *entry,
3460                                 void *context, int vl, int mode, u64 data)
3461 {
3462         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3463
3464         return dd->send_egress_err_status_cnt[20];
3465 }
3466
3467 static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3468                                 const struct cntr_entry *entry,
3469                                 void *context, int vl, int mode, u64 data)
3470 {
3471         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3472
3473         return dd->send_egress_err_status_cnt[19];
3474 }
3475
3476 static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3477                                 const struct cntr_entry *entry,
3478                                 void *context, int vl, int mode, u64 data)
3479 {
3480         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3481
3482         return dd->send_egress_err_status_cnt[18];
3483 }
3484
3485 static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3486                                 const struct cntr_entry *entry,
3487                                 void *context, int vl, int mode, u64 data)
3488 {
3489         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3490
3491         return dd->send_egress_err_status_cnt[17];
3492 }
3493
3494 static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3495                                 const struct cntr_entry *entry,
3496                                 void *context, int vl, int mode, u64 data)
3497 {
3498         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3499
3500         return dd->send_egress_err_status_cnt[16];
3501 }
3502
3503 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3504                                            void *context, int vl, int mode,
3505                                            u64 data)
3506 {
3507         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3508
3509         return dd->send_egress_err_status_cnt[15];
3510 }
3511
3512 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3513                                                  void *context, int vl,
3514                                                  int mode, u64 data)
3515 {
3516         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3517
3518         return dd->send_egress_err_status_cnt[14];
3519 }
3520
3521 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3522                                                void *context, int vl, int mode,
3523                                                u64 data)
3524 {
3525         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3526
3527         return dd->send_egress_err_status_cnt[13];
3528 }
3529
3530 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3531                                         void *context, int vl, int mode,
3532                                         u64 data)
3533 {
3534         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3535
3536         return dd->send_egress_err_status_cnt[12];
3537 }
3538
3539 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3540                                 const struct cntr_entry *entry,
3541                                 void *context, int vl, int mode, u64 data)
3542 {
3543         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3544
3545         return dd->send_egress_err_status_cnt[11];
3546 }
3547
3548 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3549                                              void *context, int vl, int mode,
3550                                              u64 data)
3551 {
3552         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3553
3554         return dd->send_egress_err_status_cnt[10];
3555 }
3556
3557 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3558                                             void *context, int vl, int mode,
3559                                             u64 data)
3560 {
3561         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3562
3563         return dd->send_egress_err_status_cnt[9];
3564 }
3565
3566 static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3567                                 const struct cntr_entry *entry,
3568                                 void *context, int vl, int mode, u64 data)
3569 {
3570         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3571
3572         return dd->send_egress_err_status_cnt[8];
3573 }
3574
3575 static u64 access_tx_pio_launch_intf_parity_err_cnt(
3576                                 const struct cntr_entry *entry,
3577                                 void *context, int vl, int mode, u64 data)
3578 {
3579         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3580
3581         return dd->send_egress_err_status_cnt[7];
3582 }
3583
3584 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3585                                             void *context, int vl, int mode,
3586                                             u64 data)
3587 {
3588         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3589
3590         return dd->send_egress_err_status_cnt[6];
3591 }
3592
3593 static u64 access_tx_incorrect_link_state_err_cnt(
3594                                 const struct cntr_entry *entry,
3595                                 void *context, int vl, int mode, u64 data)
3596 {
3597         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3598
3599         return dd->send_egress_err_status_cnt[5];
3600 }
3601
3602 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3603                                       void *context, int vl, int mode,
3604                                       u64 data)
3605 {
3606         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3607
3608         return dd->send_egress_err_status_cnt[4];
3609 }
3610
3611 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3612                                 const struct cntr_entry *entry,
3613                                 void *context, int vl, int mode, u64 data)
3614 {
3615         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3616
3617         return dd->send_egress_err_status_cnt[3];
3618 }
3619
3620 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3621                                             void *context, int vl, int mode,
3622                                             u64 data)
3623 {
3624         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3625
3626         return dd->send_egress_err_status_cnt[2];
3627 }
3628
3629 static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3630                                 const struct cntr_entry *entry,
3631                                 void *context, int vl, int mode, u64 data)
3632 {
3633         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3634
3635         return dd->send_egress_err_status_cnt[1];
3636 }
3637
3638 static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3639                                 const struct cntr_entry *entry,
3640                                 void *context, int vl, int mode, u64 data)
3641 {
3642         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3643
3644         return dd->send_egress_err_status_cnt[0];
3645 }
3646
3647 /*
3648  * Software counters corresponding to each of the
3649  * error status bits within SendErrStatus
3650  */
3651 static u64 access_send_csr_write_bad_addr_err_cnt(
3652                                 const struct cntr_entry *entry,
3653                                 void *context, int vl, int mode, u64 data)
3654 {
3655         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3656
3657         return dd->send_err_status_cnt[2];
3658 }
3659
3660 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3661                                                  void *context, int vl,
3662                                                  int mode, u64 data)
3663 {
3664         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3665
3666         return dd->send_err_status_cnt[1];
3667 }
3668
3669 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3670                                       void *context, int vl, int mode,
3671                                       u64 data)
3672 {
3673         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3674
3675         return dd->send_err_status_cnt[0];
3676 }
3677
3678 /*
3679  * Software counters corresponding to each of the
3680  * error status bits within SendCtxtErrStatus
3681  */
3682 static u64 access_pio_write_out_of_bounds_err_cnt(
3683                                 const struct cntr_entry *entry,
3684                                 void *context, int vl, int mode, u64 data)
3685 {
3686         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3687
3688         return dd->sw_ctxt_err_status_cnt[4];
3689 }
3690
3691 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3692                                              void *context, int vl, int mode,
3693                                              u64 data)
3694 {
3695         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3696
3697         return dd->sw_ctxt_err_status_cnt[3];
3698 }
3699
3700 static u64 access_pio_write_crosses_boundary_err_cnt(
3701                                 const struct cntr_entry *entry,
3702                                 void *context, int vl, int mode, u64 data)
3703 {
3704         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3705
3706         return dd->sw_ctxt_err_status_cnt[2];
3707 }
3708
3709 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3710                                                 void *context, int vl,
3711                                                 int mode, u64 data)
3712 {
3713         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3714
3715         return dd->sw_ctxt_err_status_cnt[1];
3716 }
3717
3718 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3719                                                void *context, int vl, int mode,
3720                                                u64 data)
3721 {
3722         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3723
3724         return dd->sw_ctxt_err_status_cnt[0];
3725 }
3726
3727 /*
3728  * Software counters corresponding to each of the
3729  * error status bits within SendDmaEngErrStatus
3730  */
3731 static u64 access_sdma_header_request_fifo_cor_err_cnt(
3732                                 const struct cntr_entry *entry,
3733                                 void *context, int vl, int mode, u64 data)
3734 {
3735         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3736
3737         return dd->sw_send_dma_eng_err_status_cnt[23];
3738 }
3739
3740 static u64 access_sdma_header_storage_cor_err_cnt(
3741                                 const struct cntr_entry *entry,
3742                                 void *context, int vl, int mode, u64 data)
3743 {
3744         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3745
3746         return dd->sw_send_dma_eng_err_status_cnt[22];
3747 }
3748
3749 static u64 access_sdma_packet_tracking_cor_err_cnt(
3750                                 const struct cntr_entry *entry,
3751                                 void *context, int vl, int mode, u64 data)
3752 {
3753         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3754
3755         return dd->sw_send_dma_eng_err_status_cnt[21];
3756 }
3757
3758 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3759                                             void *context, int vl, int mode,
3760                                             u64 data)
3761 {
3762         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3763
3764         return dd->sw_send_dma_eng_err_status_cnt[20];
3765 }
3766
3767 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3768                                               void *context, int vl, int mode,
3769                                               u64 data)
3770 {
3771         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3772
3773         return dd->sw_send_dma_eng_err_status_cnt[19];
3774 }
3775
3776 static u64 access_sdma_header_request_fifo_unc_err_cnt(
3777                                 const struct cntr_entry *entry,
3778                                 void *context, int vl, int mode, u64 data)
3779 {
3780         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3781
3782         return dd->sw_send_dma_eng_err_status_cnt[18];
3783 }
3784
3785 static u64 access_sdma_header_storage_unc_err_cnt(
3786                                 const struct cntr_entry *entry,
3787                                 void *context, int vl, int mode, u64 data)
3788 {
3789         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3790
3791         return dd->sw_send_dma_eng_err_status_cnt[17];
3792 }
3793
3794 static u64 access_sdma_packet_tracking_unc_err_cnt(
3795                                 const struct cntr_entry *entry,
3796                                 void *context, int vl, int mode, u64 data)
3797 {
3798         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3799
3800         return dd->sw_send_dma_eng_err_status_cnt[16];
3801 }
3802
3803 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3804                                             void *context, int vl, int mode,
3805                                             u64 data)
3806 {
3807         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3808
3809         return dd->sw_send_dma_eng_err_status_cnt[15];
3810 }
3811
3812 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3813                                               void *context, int vl, int mode,
3814                                               u64 data)
3815 {
3816         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3817
3818         return dd->sw_send_dma_eng_err_status_cnt[14];
3819 }
3820
3821 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3822                                        void *context, int vl, int mode,
3823                                        u64 data)
3824 {
3825         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3826
3827         return dd->sw_send_dma_eng_err_status_cnt[13];
3828 }
3829
3830 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3831                                              void *context, int vl, int mode,
3832                                              u64 data)
3833 {
3834         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3835
3836         return dd->sw_send_dma_eng_err_status_cnt[12];
3837 }
3838
3839 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3840                                               void *context, int vl, int mode,
3841                                               u64 data)
3842 {
3843         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3844
3845         return dd->sw_send_dma_eng_err_status_cnt[11];
3846 }
3847
3848 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3849                                              void *context, int vl, int mode,
3850                                              u64 data)
3851 {
3852         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3853
3854         return dd->sw_send_dma_eng_err_status_cnt[10];
3855 }
3856
3857 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3858                                           void *context, int vl, int mode,
3859                                           u64 data)
3860 {
3861         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3862
3863         return dd->sw_send_dma_eng_err_status_cnt[9];
3864 }
3865
3866 static u64 access_sdma_packet_desc_overflow_err_cnt(
3867                                 const struct cntr_entry *entry,
3868                                 void *context, int vl, int mode, u64 data)
3869 {
3870         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3871
3872         return dd->sw_send_dma_eng_err_status_cnt[8];
3873 }
3874
3875 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3876                                                void *context, int vl,
3877                                                int mode, u64 data)
3878 {
3879         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3880
3881         return dd->sw_send_dma_eng_err_status_cnt[7];
3882 }
3883
3884 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
3885                                     void *context, int vl, int mode, u64 data)
3886 {
3887         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3888
3889         return dd->sw_send_dma_eng_err_status_cnt[6];
3890 }
3891
3892 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
3893                                         void *context, int vl, int mode,
3894                                         u64 data)
3895 {
3896         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3897
3898         return dd->sw_send_dma_eng_err_status_cnt[5];
3899 }
3900
3901 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
3902                                           void *context, int vl, int mode,
3903                                           u64 data)
3904 {
3905         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3906
3907         return dd->sw_send_dma_eng_err_status_cnt[4];
3908 }
3909
3910 static u64 access_sdma_tail_out_of_bounds_err_cnt(
3911                                 const struct cntr_entry *entry,
3912                                 void *context, int vl, int mode, u64 data)
3913 {
3914         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3915
3916         return dd->sw_send_dma_eng_err_status_cnt[3];
3917 }
3918
3919 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
3920                                         void *context, int vl, int mode,
3921                                         u64 data)
3922 {
3923         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3924
3925         return dd->sw_send_dma_eng_err_status_cnt[2];
3926 }
3927
3928 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
3929                                             void *context, int vl, int mode,
3930                                             u64 data)
3931 {
3932         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3933
3934         return dd->sw_send_dma_eng_err_status_cnt[1];
3935 }
3936
3937 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
3938                                         void *context, int vl, int mode,
3939                                         u64 data)
3940 {
3941         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3942
3943         return dd->sw_send_dma_eng_err_status_cnt[0];
3944 }
3945
3946 #define def_access_sw_cpu(cntr) \
3947 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry,               \
3948                               void *context, int vl, int mode, u64 data)      \
3949 {                                                                             \
3950         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;        \
3951         return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr,       \
3952                               ppd->ibport_data.rvp.cntr, vl,                  \
3953                               mode, data);                                    \
3954 }
3955
3956 def_access_sw_cpu(rc_acks);
3957 def_access_sw_cpu(rc_qacks);
3958 def_access_sw_cpu(rc_delayed_comp);
3959
3960 #define def_access_ibp_counter(cntr) \
3961 static u64 access_ibp_##cntr(const struct cntr_entry *entry,                  \
3962                                 void *context, int vl, int mode, u64 data)    \
3963 {                                                                             \
3964         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;        \
3965                                                                               \
3966         if (vl != CNTR_INVALID_VL)                                            \
3967                 return 0;                                                     \
3968                                                                               \
3969         return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr,        \
3970                              mode, data);                                     \
3971 }
3972
3973 def_access_ibp_counter(loop_pkts);
3974 def_access_ibp_counter(rc_resends);
3975 def_access_ibp_counter(rnr_naks);
3976 def_access_ibp_counter(other_naks);
3977 def_access_ibp_counter(rc_timeouts);
3978 def_access_ibp_counter(pkt_drops);
3979 def_access_ibp_counter(dmawait);
3980 def_access_ibp_counter(rc_seqnak);
3981 def_access_ibp_counter(rc_dupreq);
3982 def_access_ibp_counter(rdma_seq);
3983 def_access_ibp_counter(unaligned);
3984 def_access_ibp_counter(seq_naks);
3985
3986 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
3987 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
3988 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
3989                         CNTR_NORMAL),
3990 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
3991                         CNTR_NORMAL),
3992 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
3993                         RCV_TID_FLOW_GEN_MISMATCH_CNT,
3994                         CNTR_NORMAL),
3995 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
3996                         CNTR_NORMAL),
3997 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
3998                         RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
3999 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4000                         CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4001 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4002                         CNTR_NORMAL),
4003 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4004                         CNTR_NORMAL),
4005 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4006                         CNTR_NORMAL),
4007 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4008                         CNTR_NORMAL),
4009 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4010                         CNTR_NORMAL),
4011 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4012                         CNTR_NORMAL),
4013 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4014                         CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4015 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4016                         CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4017 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4018                               CNTR_SYNTH),
4019 [C_DC_RCV_ERR] = DC_PERF_CNTR(DcRecvErr, DCC_ERR_PORTRCV_ERR_CNT, CNTR_SYNTH),
4020 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4021                                  CNTR_SYNTH),
4022 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4023                                   CNTR_SYNTH),
4024 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4025                                   CNTR_SYNTH),
4026 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4027                                    DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4028 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4029                                   DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4030                                   CNTR_SYNTH),
4031 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4032                                 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4033 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4034                                CNTR_SYNTH),
4035 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4036                               CNTR_SYNTH),
4037 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4038                                CNTR_SYNTH),
4039 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4040                                  CNTR_SYNTH),
4041 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4042                                 CNTR_SYNTH),
4043 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4044                                 CNTR_SYNTH),
4045 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4046                                CNTR_SYNTH),
4047 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4048                                  CNTR_SYNTH | CNTR_VL),
4049 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4050                                 CNTR_SYNTH | CNTR_VL),
4051 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4052 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4053                                  CNTR_SYNTH | CNTR_VL),
4054 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4055 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4056                                  CNTR_SYNTH | CNTR_VL),
4057 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4058                               CNTR_SYNTH),
4059 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4060                                  CNTR_SYNTH | CNTR_VL),
4061 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4062                                 CNTR_SYNTH),
4063 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4064                                    CNTR_SYNTH | CNTR_VL),
4065 [C_DC_TOTAL_CRC] =
4066         DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4067                          CNTR_SYNTH),
4068 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4069                                   CNTR_SYNTH),
4070 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4071                                   CNTR_SYNTH),
4072 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4073                                   CNTR_SYNTH),
4074 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4075                                   CNTR_SYNTH),
4076 [C_DC_CRC_MULT_LN] =
4077         DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4078                          CNTR_SYNTH),
4079 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4080                                     CNTR_SYNTH),
4081 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4082                                     CNTR_SYNTH),
4083 [C_DC_SEQ_CRC_CNT] =
4084         DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4085                          CNTR_SYNTH),
4086 [C_DC_ESC0_ONLY_CNT] =
4087         DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4088                          CNTR_SYNTH),
4089 [C_DC_ESC0_PLUS1_CNT] =
4090         DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4091                          CNTR_SYNTH),
4092 [C_DC_ESC0_PLUS2_CNT] =
4093         DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4094                          CNTR_SYNTH),
4095 [C_DC_REINIT_FROM_PEER_CNT] =
4096         DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4097                          CNTR_SYNTH),
4098 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4099                                   CNTR_SYNTH),
4100 [C_DC_MISC_FLG_CNT] =
4101         DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4102                          CNTR_SYNTH),
4103 [C_DC_PRF_GOOD_LTP_CNT] =
4104         DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4105 [C_DC_PRF_ACCEPTED_LTP_CNT] =
4106         DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4107                          CNTR_SYNTH),
4108 [C_DC_PRF_RX_FLIT_CNT] =
4109         DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4110 [C_DC_PRF_TX_FLIT_CNT] =
4111         DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4112 [C_DC_PRF_CLK_CNTR] =
4113         DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4114 [C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4115         DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4116 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4117         DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4118                          CNTR_SYNTH),
4119 [C_DC_PG_STS_TX_SBE_CNT] =
4120         DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4121 [C_DC_PG_STS_TX_MBE_CNT] =
4122         DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4123                          CNTR_SYNTH),
4124 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4125                             access_sw_cpu_intr),
4126 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4127                             access_sw_cpu_rcv_limit),
4128 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4129                             access_sw_vtx_wait),
4130 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4131                             access_sw_pio_wait),
4132 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4133                             access_sw_pio_drain),
4134 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4135                             access_sw_kmem_wait),
4136 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4137                             access_sw_send_schedule),
4138 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4139                                       SEND_DMA_DESC_FETCHED_CNT, 0,
4140                                       CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4141                                       dev_access_u32_csr),
4142 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4143                              CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4144                              access_sde_int_cnt),
4145 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4146                              CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4147                              access_sde_err_cnt),
4148 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4149                                   CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4150                                   access_sde_idle_int_cnt),
4151 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4152                                       CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4153                                       access_sde_progress_int_cnt),
4154 /* MISC_ERR_STATUS */
4155 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4156                                 CNTR_NORMAL,
4157                                 access_misc_pll_lock_fail_err_cnt),
4158 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4159                                 CNTR_NORMAL,
4160                                 access_misc_mbist_fail_err_cnt),
4161 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4162                                 CNTR_NORMAL,
4163                                 access_misc_invalid_eep_cmd_err_cnt),
4164 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4165                                 CNTR_NORMAL,
4166                                 access_misc_efuse_done_parity_err_cnt),
4167 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4168                                 CNTR_NORMAL,
4169                                 access_misc_efuse_write_err_cnt),
4170 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4171                                 0, CNTR_NORMAL,
4172                                 access_misc_efuse_read_bad_addr_err_cnt),
4173 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4174                                 CNTR_NORMAL,
4175                                 access_misc_efuse_csr_parity_err_cnt),
4176 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4177                                 CNTR_NORMAL,
4178                                 access_misc_fw_auth_failed_err_cnt),
4179 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4180                                 CNTR_NORMAL,
4181                                 access_misc_key_mismatch_err_cnt),
4182 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4183                                 CNTR_NORMAL,
4184                                 access_misc_sbus_write_failed_err_cnt),
4185 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4186                                 CNTR_NORMAL,
4187                                 access_misc_csr_write_bad_addr_err_cnt),
4188 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4189                                 CNTR_NORMAL,
4190                                 access_misc_csr_read_bad_addr_err_cnt),
4191 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4192                                 CNTR_NORMAL,
4193                                 access_misc_csr_parity_err_cnt),
4194 /* CceErrStatus */
4195 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4196                                 CNTR_NORMAL,
4197                                 access_sw_cce_err_status_aggregated_cnt),
4198 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4199                                 CNTR_NORMAL,
4200                                 access_cce_msix_csr_parity_err_cnt),
4201 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4202                                 CNTR_NORMAL,
4203                                 access_cce_int_map_unc_err_cnt),
4204 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4205                                 CNTR_NORMAL,
4206                                 access_cce_int_map_cor_err_cnt),
4207 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4208                                 CNTR_NORMAL,
4209                                 access_cce_msix_table_unc_err_cnt),
4210 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4211                                 CNTR_NORMAL,
4212                                 access_cce_msix_table_cor_err_cnt),
4213 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4214                                 0, CNTR_NORMAL,
4215                                 access_cce_rxdma_conv_fifo_parity_err_cnt),
4216 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4217                                 0, CNTR_NORMAL,
4218                                 access_cce_rcpl_async_fifo_parity_err_cnt),
4219 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4220                                 CNTR_NORMAL,
4221                                 access_cce_seg_write_bad_addr_err_cnt),
4222 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4223                                 CNTR_NORMAL,
4224                                 access_cce_seg_read_bad_addr_err_cnt),
4225 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4226                                 CNTR_NORMAL,
4227                                 access_la_triggered_cnt),
4228 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4229                                 CNTR_NORMAL,
4230                                 access_cce_trgt_cpl_timeout_err_cnt),
4231 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4232                                 CNTR_NORMAL,
4233                                 access_pcic_receive_parity_err_cnt),
4234 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4235                                 CNTR_NORMAL,
4236                                 access_pcic_transmit_back_parity_err_cnt),
4237 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4238                                 0, CNTR_NORMAL,
4239                                 access_pcic_transmit_front_parity_err_cnt),
4240 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4241                                 CNTR_NORMAL,
4242                                 access_pcic_cpl_dat_q_unc_err_cnt),
4243 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4244                                 CNTR_NORMAL,
4245                                 access_pcic_cpl_hd_q_unc_err_cnt),
4246 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4247                                 CNTR_NORMAL,
4248                                 access_pcic_post_dat_q_unc_err_cnt),
4249 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4250                                 CNTR_NORMAL,
4251                                 access_pcic_post_hd_q_unc_err_cnt),
4252 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4253                                 CNTR_NORMAL,
4254                                 access_pcic_retry_sot_mem_unc_err_cnt),
4255 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4256                                 CNTR_NORMAL,
4257                                 access_pcic_retry_mem_unc_err),
4258 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4259                                 CNTR_NORMAL,
4260                                 access_pcic_n_post_dat_q_parity_err_cnt),
4261 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4262                                 CNTR_NORMAL,
4263                                 access_pcic_n_post_h_q_parity_err_cnt),
4264 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4265                                 CNTR_NORMAL,
4266                                 access_pcic_cpl_dat_q_cor_err_cnt),
4267 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4268                                 CNTR_NORMAL,
4269                                 access_pcic_cpl_hd_q_cor_err_cnt),
4270 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4271                                 CNTR_NORMAL,
4272                                 access_pcic_post_dat_q_cor_err_cnt),
4273 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4274                                 CNTR_NORMAL,
4275                                 access_pcic_post_hd_q_cor_err_cnt),
4276 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4277                                 CNTR_NORMAL,
4278                                 access_pcic_retry_sot_mem_cor_err_cnt),
4279 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4280                                 CNTR_NORMAL,
4281                                 access_pcic_retry_mem_cor_err_cnt),
4282 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4283                                 "CceCli1AsyncFifoDbgParityError", 0, 0,
4284                                 CNTR_NORMAL,
4285                                 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4286 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4287                                 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4288                                 CNTR_NORMAL,
4289                                 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4290                                 ),
4291 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4292                         "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4293                         CNTR_NORMAL,
4294                         access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4295 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4296                         "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4297                         CNTR_NORMAL,
4298                         access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4299 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4300                         0, CNTR_NORMAL,
4301                         access_cce_cli2_async_fifo_parity_err_cnt),
4302 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4303                         CNTR_NORMAL,
4304                         access_cce_csr_cfg_bus_parity_err_cnt),
4305 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4306                         0, CNTR_NORMAL,
4307                         access_cce_cli0_async_fifo_parity_err_cnt),
4308 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4309                         CNTR_NORMAL,
4310                         access_cce_rspd_data_parity_err_cnt),
4311 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4312                         CNTR_NORMAL,
4313                         access_cce_trgt_access_err_cnt),
4314 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4315                         0, CNTR_NORMAL,
4316                         access_cce_trgt_async_fifo_parity_err_cnt),
4317 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4318                         CNTR_NORMAL,
4319                         access_cce_csr_write_bad_addr_err_cnt),
4320 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4321                         CNTR_NORMAL,
4322                         access_cce_csr_read_bad_addr_err_cnt),
4323 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4324                         CNTR_NORMAL,
4325                         access_ccs_csr_parity_err_cnt),
4326
4327 /* RcvErrStatus */
4328 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4329                         CNTR_NORMAL,
4330                         access_rx_csr_parity_err_cnt),
4331 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4332                         CNTR_NORMAL,
4333                         access_rx_csr_write_bad_addr_err_cnt),
4334 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4335                         CNTR_NORMAL,
4336                         access_rx_csr_read_bad_addr_err_cnt),
4337 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4338                         CNTR_NORMAL,
4339                         access_rx_dma_csr_unc_err_cnt),
4340 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4341                         CNTR_NORMAL,
4342                         access_rx_dma_dq_fsm_encoding_err_cnt),
4343 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4344                         CNTR_NORMAL,
4345                         access_rx_dma_eq_fsm_encoding_err_cnt),
4346 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4347                         CNTR_NORMAL,
4348                         access_rx_dma_csr_parity_err_cnt),
4349 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4350                         CNTR_NORMAL,
4351                         access_rx_rbuf_data_cor_err_cnt),
4352 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4353                         CNTR_NORMAL,
4354                         access_rx_rbuf_data_unc_err_cnt),
4355 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4356                         CNTR_NORMAL,
4357                         access_rx_dma_data_fifo_rd_cor_err_cnt),
4358 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4359                         CNTR_NORMAL,
4360                         access_rx_dma_data_fifo_rd_unc_err_cnt),
4361 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4362                         CNTR_NORMAL,
4363                         access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4364 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4365                         CNTR_NORMAL,
4366                         access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4367 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4368                         CNTR_NORMAL,
4369                         access_rx_rbuf_desc_part2_cor_err_cnt),
4370 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4371                         CNTR_NORMAL,
4372                         access_rx_rbuf_desc_part2_unc_err_cnt),
4373 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4374                         CNTR_NORMAL,
4375                         access_rx_rbuf_desc_part1_cor_err_cnt),
4376 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4377                         CNTR_NORMAL,
4378                         access_rx_rbuf_desc_part1_unc_err_cnt),
4379 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4380                         CNTR_NORMAL,
4381                         access_rx_hq_intr_fsm_err_cnt),
4382 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4383                         CNTR_NORMAL,
4384                         access_rx_hq_intr_csr_parity_err_cnt),
4385 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4386                         CNTR_NORMAL,
4387                         access_rx_lookup_csr_parity_err_cnt),
4388 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4389                         CNTR_NORMAL,
4390                         access_rx_lookup_rcv_array_cor_err_cnt),
4391 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4392                         CNTR_NORMAL,
4393                         access_rx_lookup_rcv_array_unc_err_cnt),
4394 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4395                         0, CNTR_NORMAL,
4396                         access_rx_lookup_des_part2_parity_err_cnt),
4397 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4398                         0, CNTR_NORMAL,
4399                         access_rx_lookup_des_part1_unc_cor_err_cnt),
4400 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4401                         CNTR_NORMAL,
4402                         access_rx_lookup_des_part1_unc_err_cnt),
4403 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4404                         CNTR_NORMAL,
4405                         access_rx_rbuf_next_free_buf_cor_err_cnt),
4406 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4407                         CNTR_NORMAL,
4408                         access_rx_rbuf_next_free_buf_unc_err_cnt),
4409 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4410                         "RxRbufFlInitWrAddrParityErr", 0, 0,
4411                         CNTR_NORMAL,
4412                         access_rbuf_fl_init_wr_addr_parity_err_cnt),
4413 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4414                         0, CNTR_NORMAL,
4415                         access_rx_rbuf_fl_initdone_parity_err_cnt),
4416 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4417                         0, CNTR_NORMAL,
4418                         access_rx_rbuf_fl_write_addr_parity_err_cnt),
4419 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4420                         CNTR_NORMAL,
4421                         access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4422 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4423                         CNTR_NORMAL,
4424                         access_rx_rbuf_empty_err_cnt),
4425 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4426                         CNTR_NORMAL,
4427                         access_rx_rbuf_full_err_cnt),
4428 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4429                         CNTR_NORMAL,
4430                         access_rbuf_bad_lookup_err_cnt),
4431 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4432                         CNTR_NORMAL,
4433                         access_rbuf_ctx_id_parity_err_cnt),
4434 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4435                         CNTR_NORMAL,
4436                         access_rbuf_csr_qeopdw_parity_err_cnt),
4437 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4438                         "RxRbufCsrQNumOfPktParityErr", 0, 0,
4439                         CNTR_NORMAL,
4440                         access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4441 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4442                         "RxRbufCsrQTlPtrParityErr", 0, 0,
4443                         CNTR_NORMAL,
4444                         access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4445 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4446                         0, CNTR_NORMAL,
4447                         access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4448 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4449                         0, CNTR_NORMAL,
4450                         access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4451 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4452                         0, 0, CNTR_NORMAL,
4453                         access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4454 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4455                         0, CNTR_NORMAL,
4456                         access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4457 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4458                         "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4459                         CNTR_NORMAL,
4460                         access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4461 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4462                         0, CNTR_NORMAL,
4463                         access_rx_rbuf_block_list_read_cor_err_cnt),
4464 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4465                         0, CNTR_NORMAL,
4466                         access_rx_rbuf_block_list_read_unc_err_cnt),
4467 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4468                         CNTR_NORMAL,
4469                         access_rx_rbuf_lookup_des_cor_err_cnt),
4470 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4471                         CNTR_NORMAL,
4472                         access_rx_rbuf_lookup_des_unc_err_cnt),
4473 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4474                         "RxRbufLookupDesRegUncCorErr", 0, 0,
4475                         CNTR_NORMAL,
4476                         access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4477 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4478                         CNTR_NORMAL,
4479                         access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4480 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4481                         CNTR_NORMAL,
4482                         access_rx_rbuf_free_list_cor_err_cnt),
4483 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4484                         CNTR_NORMAL,
4485                         access_rx_rbuf_free_list_unc_err_cnt),
4486 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4487                         CNTR_NORMAL,
4488                         access_rx_rcv_fsm_encoding_err_cnt),
4489 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4490                         CNTR_NORMAL,
4491                         access_rx_dma_flag_cor_err_cnt),
4492 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4493                         CNTR_NORMAL,
4494                         access_rx_dma_flag_unc_err_cnt),
4495 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4496                         CNTR_NORMAL,
4497                         access_rx_dc_sop_eop_parity_err_cnt),
4498 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4499                         CNTR_NORMAL,
4500                         access_rx_rcv_csr_parity_err_cnt),
4501 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4502                         CNTR_NORMAL,
4503                         access_rx_rcv_qp_map_table_cor_err_cnt),
4504 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4505                         CNTR_NORMAL,
4506                         access_rx_rcv_qp_map_table_unc_err_cnt),
4507 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4508                         CNTR_NORMAL,
4509                         access_rx_rcv_data_cor_err_cnt),
4510 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4511                         CNTR_NORMAL,
4512                         access_rx_rcv_data_unc_err_cnt),
4513 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4514                         CNTR_NORMAL,
4515                         access_rx_rcv_hdr_cor_err_cnt),
4516 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4517                         CNTR_NORMAL,
4518                         access_rx_rcv_hdr_unc_err_cnt),
4519 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4520                         CNTR_NORMAL,
4521                         access_rx_dc_intf_parity_err_cnt),
4522 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4523                         CNTR_NORMAL,
4524                         access_rx_dma_csr_cor_err_cnt),
4525 /* SendPioErrStatus */
4526 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4527                         CNTR_NORMAL,
4528                         access_pio_pec_sop_head_parity_err_cnt),
4529 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4530                         CNTR_NORMAL,
4531                         access_pio_pcc_sop_head_parity_err_cnt),
4532 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4533                         0, 0, CNTR_NORMAL,
4534                         access_pio_last_returned_cnt_parity_err_cnt),
4535 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4536                         0, CNTR_NORMAL,
4537                         access_pio_current_free_cnt_parity_err_cnt),
4538 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4539                         CNTR_NORMAL,
4540                         access_pio_reserved_31_err_cnt),
4541 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4542                         CNTR_NORMAL,
4543                         access_pio_reserved_30_err_cnt),
4544 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4545                         CNTR_NORMAL,
4546                         access_pio_ppmc_sop_len_err_cnt),
4547 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4548                         CNTR_NORMAL,
4549                         access_pio_ppmc_bqc_mem_parity_err_cnt),
4550 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4551                         CNTR_NORMAL,
4552                         access_pio_vl_fifo_parity_err_cnt),
4553 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4554                         CNTR_NORMAL,
4555                         access_pio_vlf_sop_parity_err_cnt),
4556 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4557                         CNTR_NORMAL,
4558                         access_pio_vlf_v1_len_parity_err_cnt),
4559 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4560                         CNTR_NORMAL,
4561                         access_pio_block_qw_count_parity_err_cnt),
4562 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4563                         CNTR_NORMAL,
4564                         access_pio_write_qw_valid_parity_err_cnt),
4565 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4566                         CNTR_NORMAL,
4567                         access_pio_state_machine_err_cnt),
4568 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4569                         CNTR_NORMAL,
4570                         access_pio_write_data_parity_err_cnt),
4571 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4572                         CNTR_NORMAL,
4573                         access_pio_host_addr_mem_cor_err_cnt),
4574 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4575                         CNTR_NORMAL,
4576                         access_pio_host_addr_mem_unc_err_cnt),
4577 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4578                         CNTR_NORMAL,
4579                         access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4580 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4581                         CNTR_NORMAL,
4582                         access_pio_init_sm_in_err_cnt),
4583 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4584                         CNTR_NORMAL,
4585                         access_pio_ppmc_pbl_fifo_err_cnt),
4586 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4587                         0, CNTR_NORMAL,
4588                         access_pio_credit_ret_fifo_parity_err_cnt),
4589 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4590                         CNTR_NORMAL,
4591                         access_pio_v1_len_mem_bank1_cor_err_cnt),
4592 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4593                         CNTR_NORMAL,
4594                         access_pio_v1_len_mem_bank0_cor_err_cnt),
4595 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4596                         CNTR_NORMAL,
4597                         access_pio_v1_len_mem_bank1_unc_err_cnt),
4598 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4599                         CNTR_NORMAL,
4600                         access_pio_v1_len_mem_bank0_unc_err_cnt),
4601 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4602                         CNTR_NORMAL,
4603                         access_pio_sm_pkt_reset_parity_err_cnt),
4604 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4605                         CNTR_NORMAL,
4606                         access_pio_pkt_evict_fifo_parity_err_cnt),
4607 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4608                         "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4609                         CNTR_NORMAL,
4610                         access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4611 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4612                         CNTR_NORMAL,
4613                         access_pio_sbrdctl_crrel_parity_err_cnt),
4614 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4615                         CNTR_NORMAL,
4616                         access_pio_pec_fifo_parity_err_cnt),
4617 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4618                         CNTR_NORMAL,
4619                         access_pio_pcc_fifo_parity_err_cnt),
4620 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4621                         CNTR_NORMAL,
4622                         access_pio_sb_mem_fifo1_err_cnt),
4623 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4624                         CNTR_NORMAL,
4625                         access_pio_sb_mem_fifo0_err_cnt),
4626 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4627                         CNTR_NORMAL,
4628                         access_pio_csr_parity_err_cnt),
4629 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4630                         CNTR_NORMAL,
4631                         access_pio_write_addr_parity_err_cnt),
4632 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4633                         CNTR_NORMAL,
4634                         access_pio_write_bad_ctxt_err_cnt),
4635 /* SendDmaErrStatus */
4636 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4637                         0, CNTR_NORMAL,
4638                         access_sdma_pcie_req_tracking_cor_err_cnt),
4639 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4640                         0, CNTR_NORMAL,
4641                         access_sdma_pcie_req_tracking_unc_err_cnt),
4642 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4643                         CNTR_NORMAL,
4644                         access_sdma_csr_parity_err_cnt),
4645 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4646                         CNTR_NORMAL,
4647                         access_sdma_rpy_tag_err_cnt),
4648 /* SendEgressErrStatus */
4649 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4650                         CNTR_NORMAL,
4651                         access_tx_read_pio_memory_csr_unc_err_cnt),
4652 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4653                         0, CNTR_NORMAL,
4654                         access_tx_read_sdma_memory_csr_err_cnt),
4655 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4656                         CNTR_NORMAL,
4657                         access_tx_egress_fifo_cor_err_cnt),
4658 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4659                         CNTR_NORMAL,
4660                         access_tx_read_pio_memory_cor_err_cnt),
4661 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4662                         CNTR_NORMAL,
4663                         access_tx_read_sdma_memory_cor_err_cnt),
4664 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4665                         CNTR_NORMAL,
4666                         access_tx_sb_hdr_cor_err_cnt),
4667 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4668                         CNTR_NORMAL,
4669                         access_tx_credit_overrun_err_cnt),
4670 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4671                         CNTR_NORMAL,
4672                         access_tx_launch_fifo8_cor_err_cnt),
4673 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4674                         CNTR_NORMAL,
4675                         access_tx_launch_fifo7_cor_err_cnt),
4676 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4677                         CNTR_NORMAL,
4678                         access_tx_launch_fifo6_cor_err_cnt),
4679 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4680                         CNTR_NORMAL,
4681                         access_tx_launch_fifo5_cor_err_cnt),
4682 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4683                         CNTR_NORMAL,
4684                         access_tx_launch_fifo4_cor_err_cnt),
4685 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4686                         CNTR_NORMAL,
4687                         access_tx_launch_fifo3_cor_err_cnt),
4688 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4689                         CNTR_NORMAL,
4690                         access_tx_launch_fifo2_cor_err_cnt),
4691 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4692                         CNTR_NORMAL,
4693                         access_tx_launch_fifo1_cor_err_cnt),
4694 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4695                         CNTR_NORMAL,
4696                         access_tx_launch_fifo0_cor_err_cnt),
4697 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4698                         CNTR_NORMAL,
4699                         access_tx_credit_return_vl_err_cnt),
4700 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4701                         CNTR_NORMAL,
4702                         access_tx_hcrc_insertion_err_cnt),
4703 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4704                         CNTR_NORMAL,
4705                         access_tx_egress_fifo_unc_err_cnt),
4706 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4707                         CNTR_NORMAL,
4708                         access_tx_read_pio_memory_unc_err_cnt),
4709 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4710                         CNTR_NORMAL,
4711                         access_tx_read_sdma_memory_unc_err_cnt),
4712 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4713                         CNTR_NORMAL,
4714                         access_tx_sb_hdr_unc_err_cnt),
4715 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4716                         CNTR_NORMAL,
4717                         access_tx_credit_return_partiy_err_cnt),
4718 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4719                         0, 0, CNTR_NORMAL,
4720                         access_tx_launch_fifo8_unc_or_parity_err_cnt),
4721 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4722                         0, 0, CNTR_NORMAL,
4723                         access_tx_launch_fifo7_unc_or_parity_err_cnt),
4724 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4725                         0, 0, CNTR_NORMAL,
4726                         access_tx_launch_fifo6_unc_or_parity_err_cnt),
4727 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4728                         0, 0, CNTR_NORMAL,
4729                         access_tx_launch_fifo5_unc_or_parity_err_cnt),
4730 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4731                         0, 0, CNTR_NORMAL,
4732                         access_tx_launch_fifo4_unc_or_parity_err_cnt),
4733 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4734                         0, 0, CNTR_NORMAL,
4735                         access_tx_launch_fifo3_unc_or_parity_err_cnt),
4736 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4737                         0, 0, CNTR_NORMAL,
4738                         access_tx_launch_fifo2_unc_or_parity_err_cnt),
4739 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4740                         0, 0, CNTR_NORMAL,
4741                         access_tx_launch_fifo1_unc_or_parity_err_cnt),
4742 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4743                         0, 0, CNTR_NORMAL,
4744                         access_tx_launch_fifo0_unc_or_parity_err_cnt),
4745 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4746                         0, 0, CNTR_NORMAL,
4747                         access_tx_sdma15_disallowed_packet_err_cnt),
4748 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4749                         0, 0, CNTR_NORMAL,
4750                         access_tx_sdma14_disallowed_packet_err_cnt),
4751 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4752                         0, 0, CNTR_NORMAL,
4753                         access_tx_sdma13_disallowed_packet_err_cnt),
4754 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4755                         0, 0, CNTR_NORMAL,
4756                         access_tx_sdma12_disallowed_packet_err_cnt),
4757 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4758                         0, 0, CNTR_NORMAL,
4759                         access_tx_sdma11_disallowed_packet_err_cnt),
4760 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4761                         0, 0, CNTR_NORMAL,
4762                         access_tx_sdma10_disallowed_packet_err_cnt),
4763 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4764                         0, 0, CNTR_NORMAL,
4765                         access_tx_sdma9_disallowed_packet_err_cnt),
4766 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4767                         0, 0, CNTR_NORMAL,
4768                         access_tx_sdma8_disallowed_packet_err_cnt),
4769 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4770                         0, 0, CNTR_NORMAL,
4771                         access_tx_sdma7_disallowed_packet_err_cnt),
4772 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4773                         0, 0, CNTR_NORMAL,
4774                         access_tx_sdma6_disallowed_packet_err_cnt),
4775 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4776                         0, 0, CNTR_NORMAL,
4777                         access_tx_sdma5_disallowed_packet_err_cnt),
4778 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4779                         0, 0, CNTR_NORMAL,
4780                         access_tx_sdma4_disallowed_packet_err_cnt),
4781 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4782                         0, 0, CNTR_NORMAL,
4783                         access_tx_sdma3_disallowed_packet_err_cnt),
4784 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4785                         0, 0, CNTR_NORMAL,
4786                         access_tx_sdma2_disallowed_packet_err_cnt),
4787 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4788                         0, 0, CNTR_NORMAL,
4789                         access_tx_sdma1_disallowed_packet_err_cnt),
4790 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4791                         0, 0, CNTR_NORMAL,
4792                         access_tx_sdma0_disallowed_packet_err_cnt),
4793 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4794                         CNTR_NORMAL,
4795                         access_tx_config_parity_err_cnt),
4796 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4797                         CNTR_NORMAL,
4798                         access_tx_sbrd_ctl_csr_parity_err_cnt),
4799 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4800                         CNTR_NORMAL,
4801                         access_tx_launch_csr_parity_err_cnt),
4802 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4803                         CNTR_NORMAL,
4804                         access_tx_illegal_vl_err_cnt),
4805 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4806                         "TxSbrdCtlStateMachineParityErr", 0, 0,
4807                         CNTR_NORMAL,
4808                         access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4809 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4810                         CNTR_NORMAL,
4811                         access_egress_reserved_10_err_cnt),
4812 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4813                         CNTR_NORMAL,
4814                         access_egress_reserved_9_err_cnt),
4815 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4816                         0, 0, CNTR_NORMAL,
4817                         access_tx_sdma_launch_intf_parity_err_cnt),
4818 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4819                         CNTR_NORMAL,
4820                         access_tx_pio_launch_intf_parity_err_cnt),
4821 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4822                         CNTR_NORMAL,
4823                         access_egress_reserved_6_err_cnt),
4824 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4825                         CNTR_NORMAL,
4826                         access_tx_incorrect_link_state_err_cnt),
4827 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4828                         CNTR_NORMAL,
4829                         access_tx_linkdown_err_cnt),
4830 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4831                         "EgressFifoUnderrunOrParityErr", 0, 0,
4832                         CNTR_NORMAL,
4833                         access_tx_egress_fifi_underrun_or_parity_err_cnt),
4834 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4835                         CNTR_NORMAL,
4836                         access_egress_reserved_2_err_cnt),
4837 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4838                         CNTR_NORMAL,
4839                         access_tx_pkt_integrity_mem_unc_err_cnt),
4840 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4841                         CNTR_NORMAL,
4842                         access_tx_pkt_integrity_mem_cor_err_cnt),
4843 /* SendErrStatus */
4844 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4845                         CNTR_NORMAL,
4846                         access_send_csr_write_bad_addr_err_cnt),
4847 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4848                         CNTR_NORMAL,
4849                         access_send_csr_read_bad_addr_err_cnt),
4850 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4851                         CNTR_NORMAL,
4852                         access_send_csr_parity_cnt),
4853 /* SendCtxtErrStatus */
4854 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4855                         CNTR_NORMAL,
4856                         access_pio_write_out_of_bounds_err_cnt),
4857 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4858                         CNTR_NORMAL,
4859                         access_pio_write_overflow_err_cnt),
4860 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4861                         0, 0, CNTR_NORMAL,
4862                         access_pio_write_crosses_boundary_err_cnt),
4863 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4864                         CNTR_NORMAL,
4865                         access_pio_disallowed_packet_err_cnt),
4866 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4867                         CNTR_NORMAL,
4868                         access_pio_inconsistent_sop_err_cnt),
4869 /* SendDmaEngErrStatus */
4870 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4871                         0, 0, CNTR_NORMAL,
4872                         access_sdma_header_request_fifo_cor_err_cnt),
4873 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4874                         CNTR_NORMAL,
4875                         access_sdma_header_storage_cor_err_cnt),
4876 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4877                         CNTR_NORMAL,
4878                         access_sdma_packet_tracking_cor_err_cnt),
4879 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4880                         CNTR_NORMAL,
4881                         access_sdma_assembly_cor_err_cnt),
4882 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
4883                         CNTR_NORMAL,
4884                         access_sdma_desc_table_cor_err_cnt),
4885 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
4886                         0, 0, CNTR_NORMAL,
4887                         access_sdma_header_request_fifo_unc_err_cnt),
4888 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
4889                         CNTR_NORMAL,
4890                         access_sdma_header_storage_unc_err_cnt),
4891 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
4892                         CNTR_NORMAL,
4893                         access_sdma_packet_tracking_unc_err_cnt),
4894 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
4895                         CNTR_NORMAL,
4896                         access_sdma_assembly_unc_err_cnt),
4897 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
4898                         CNTR_NORMAL,
4899                         access_sdma_desc_table_unc_err_cnt),
4900 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
4901                         CNTR_NORMAL,
4902                         access_sdma_timeout_err_cnt),
4903 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
4904                         CNTR_NORMAL,
4905                         access_sdma_header_length_err_cnt),
4906 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
4907                         CNTR_NORMAL,
4908                         access_sdma_header_address_err_cnt),
4909 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
4910                         CNTR_NORMAL,
4911                         access_sdma_header_select_err_cnt),
4912 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
4913                         CNTR_NORMAL,
4914                         access_sdma_reserved_9_err_cnt),
4915 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
4916                         CNTR_NORMAL,
4917                         access_sdma_packet_desc_overflow_err_cnt),
4918 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
4919                         CNTR_NORMAL,
4920                         access_sdma_length_mismatch_err_cnt),
4921 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
4922                         CNTR_NORMAL,
4923                         access_sdma_halt_err_cnt),
4924 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
4925                         CNTR_NORMAL,
4926                         access_sdma_mem_read_err_cnt),
4927 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
4928                         CNTR_NORMAL,
4929                         access_sdma_first_desc_err_cnt),
4930 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
4931                         CNTR_NORMAL,
4932                         access_sdma_tail_out_of_bounds_err_cnt),
4933 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
4934                         CNTR_NORMAL,
4935                         access_sdma_too_long_err_cnt),
4936 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
4937                         CNTR_NORMAL,
4938                         access_sdma_gen_mismatch_err_cnt),
4939 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
4940                         CNTR_NORMAL,
4941                         access_sdma_wrong_dw_err_cnt),
4942 };
4943
4944 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
4945 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
4946                         CNTR_NORMAL),
4947 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
4948                         CNTR_NORMAL),
4949 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
4950                         CNTR_NORMAL),
4951 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
4952                         CNTR_NORMAL),
4953 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
4954                         CNTR_NORMAL),
4955 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
4956                         CNTR_NORMAL),
4957 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
4958                         CNTR_NORMAL),
4959 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
4960 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
4961 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
4962 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
4963                                       CNTR_SYNTH | CNTR_VL),
4964 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
4965                                      CNTR_SYNTH | CNTR_VL),
4966 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
4967                                       CNTR_SYNTH | CNTR_VL),
4968 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
4969 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
4970 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
4971                              access_sw_link_dn_cnt),
4972 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
4973                            access_sw_link_up_cnt),
4974 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
4975                                  access_sw_unknown_frame_cnt),
4976 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
4977                              access_sw_xmit_discards),
4978 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
4979                                 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
4980                                 access_sw_xmit_discards),
4981 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
4982                                  access_xmit_constraint_errs),
4983 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
4984                                 access_rcv_constraint_errs),
4985 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
4986 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
4987 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
4988 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
4989 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
4990 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
4991 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
4992 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
4993 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
4994 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
4995 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
4996 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
4997 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
4998                                access_sw_cpu_rc_acks),
4999 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
5000                                 access_sw_cpu_rc_qacks),
5001 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
5002                                        access_sw_cpu_rc_delayed_comp),
5003 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5004 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5005 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5006 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5007 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5008 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5009 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5010 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5011 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5012 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5013 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5014 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5015 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5016 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5017 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5018 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5019 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5020 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5021 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5022 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5023 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5024 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5025 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5026 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5027 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5028 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5029 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5030 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5031 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5032 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5033 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5034 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5035 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5036 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5037 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5038 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5039 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5040 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5041 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5042 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5043 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5044 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5045 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5046 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5047 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5048 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5049 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5050 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5051 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5052 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5053 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5054 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5055 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5056 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5057 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5058 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5059 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5060 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5061 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5062 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5063 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5064 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5065 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5066 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5067 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5068 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5069 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5070 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5071 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5072 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5073 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5074 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5075 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5076 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5077 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5078 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5079 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5080 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5081 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5082 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5083 };
5084
5085 /* ======================================================================== */
5086
5087 /* return true if this is chip revision revision a */
5088 int is_ax(struct hfi1_devdata *dd)
5089 {
5090         u8 chip_rev_minor =
5091                 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5092                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
5093         return (chip_rev_minor & 0xf0) == 0;
5094 }
5095
5096 /* return true if this is chip revision revision b */
5097 int is_bx(struct hfi1_devdata *dd)
5098 {
5099         u8 chip_rev_minor =
5100                 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5101                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
5102         return (chip_rev_minor & 0xF0) == 0x10;
5103 }
5104
5105 /*
5106  * Append string s to buffer buf.  Arguments curp and len are the current
5107  * position and remaining length, respectively.
5108  *
5109  * return 0 on success, 1 on out of room
5110  */
5111 static int append_str(char *buf, char **curp, int *lenp, const char *s)
5112 {
5113         char *p = *curp;
5114         int len = *lenp;
5115         int result = 0; /* success */
5116         char c;
5117
5118         /* add a comma, if first in the buffer */
5119         if (p != buf) {
5120                 if (len == 0) {
5121                         result = 1; /* out of room */
5122                         goto done;
5123                 }
5124                 *p++ = ',';
5125                 len--;
5126         }
5127
5128         /* copy the string */
5129         while ((c = *s++) != 0) {
5130                 if (len == 0) {
5131                         result = 1; /* out of room */
5132                         goto done;
5133                 }
5134                 *p++ = c;
5135                 len--;
5136         }
5137
5138 done:
5139         /* write return values */
5140         *curp = p;
5141         *lenp = len;
5142
5143         return result;
5144 }
5145
5146 /*
5147  * Using the given flag table, print a comma separated string into
5148  * the buffer.  End in '*' if the buffer is too short.
5149  */
5150 static char *flag_string(char *buf, int buf_len, u64 flags,
5151                          struct flag_table *table, int table_size)
5152 {
5153         char extra[32];
5154         char *p = buf;
5155         int len = buf_len;
5156         int no_room = 0;
5157         int i;
5158
5159         /* make sure there is at least 2 so we can form "*" */
5160         if (len < 2)
5161                 return "";
5162
5163         len--;  /* leave room for a nul */
5164         for (i = 0; i < table_size; i++) {
5165                 if (flags & table[i].flag) {
5166                         no_room = append_str(buf, &p, &len, table[i].str);
5167                         if (no_room)
5168                                 break;
5169                         flags &= ~table[i].flag;
5170                 }
5171         }
5172
5173         /* any undocumented bits left? */
5174         if (!no_room && flags) {
5175                 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5176                 no_room = append_str(buf, &p, &len, extra);
5177         }
5178
5179         /* add * if ran out of room */
5180         if (no_room) {
5181                 /* may need to back up to add space for a '*' */
5182                 if (len == 0)
5183                         --p;
5184                 *p++ = '*';
5185         }
5186
5187         /* add final nul - space already allocated above */
5188         *p = 0;
5189         return buf;
5190 }
5191
5192 /* first 8 CCE error interrupt source names */
5193 static const char * const cce_misc_names[] = {
5194         "CceErrInt",            /* 0 */
5195         "RxeErrInt",            /* 1 */
5196         "MiscErrInt",           /* 2 */
5197         "Reserved3",            /* 3 */
5198         "PioErrInt",            /* 4 */
5199         "SDmaErrInt",           /* 5 */
5200         "EgressErrInt",         /* 6 */
5201         "TxeErrInt"             /* 7 */
5202 };
5203
5204 /*
5205  * Return the miscellaneous error interrupt name.
5206  */
5207 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5208 {
5209         if (source < ARRAY_SIZE(cce_misc_names))
5210                 strncpy(buf, cce_misc_names[source], bsize);
5211         else
5212                 snprintf(buf, bsize, "Reserved%u",
5213                          source + IS_GENERAL_ERR_START);
5214
5215         return buf;
5216 }
5217
5218 /*
5219  * Return the SDMA engine error interrupt name.
5220  */
5221 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5222 {
5223         snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5224         return buf;
5225 }
5226
5227 /*
5228  * Return the send context error interrupt name.
5229  */
5230 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5231 {
5232         snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5233         return buf;
5234 }
5235
5236 static const char * const various_names[] = {
5237         "PbcInt",
5238         "GpioAssertInt",
5239         "Qsfp1Int",
5240         "Qsfp2Int",
5241         "TCritInt"
5242 };
5243
5244 /*
5245  * Return the various interrupt name.
5246  */
5247 static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5248 {
5249         if (source < ARRAY_SIZE(various_names))
5250                 strncpy(buf, various_names[source], bsize);
5251         else
5252                 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
5253         return buf;
5254 }
5255
5256 /*
5257  * Return the DC interrupt name.
5258  */
5259 static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5260 {
5261         static const char * const dc_int_names[] = {
5262                 "common",
5263                 "lcb",
5264                 "8051",
5265                 "lbm"   /* local block merge */
5266         };
5267
5268         if (source < ARRAY_SIZE(dc_int_names))
5269                 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5270         else
5271                 snprintf(buf, bsize, "DCInt%u", source);
5272         return buf;
5273 }
5274
5275 static const char * const sdma_int_names[] = {
5276         "SDmaInt",
5277         "SdmaIdleInt",
5278         "SdmaProgressInt",
5279 };
5280
5281 /*
5282  * Return the SDMA engine interrupt name.
5283  */
5284 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5285 {
5286         /* what interrupt */
5287         unsigned int what  = source / TXE_NUM_SDMA_ENGINES;
5288         /* which engine */
5289         unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5290
5291         if (likely(what < 3))
5292                 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5293         else
5294                 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5295         return buf;
5296 }
5297
5298 /*
5299  * Return the receive available interrupt name.
5300  */
5301 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5302 {
5303         snprintf(buf, bsize, "RcvAvailInt%u", source);
5304         return buf;
5305 }
5306
5307 /*
5308  * Return the receive urgent interrupt name.
5309  */
5310 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5311 {
5312         snprintf(buf, bsize, "RcvUrgentInt%u", source);
5313         return buf;
5314 }
5315
5316 /*
5317  * Return the send credit interrupt name.
5318  */
5319 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5320 {
5321         snprintf(buf, bsize, "SendCreditInt%u", source);
5322         return buf;
5323 }
5324
5325 /*
5326  * Return the reserved interrupt name.
5327  */
5328 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5329 {
5330         snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5331         return buf;
5332 }
5333
5334 static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5335 {
5336         return flag_string(buf, buf_len, flags,
5337                            cce_err_status_flags,
5338                            ARRAY_SIZE(cce_err_status_flags));
5339 }
5340
5341 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5342 {
5343         return flag_string(buf, buf_len, flags,
5344                            rxe_err_status_flags,
5345                            ARRAY_SIZE(rxe_err_status_flags));
5346 }
5347
5348 static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5349 {
5350         return flag_string(buf, buf_len, flags, misc_err_status_flags,
5351                            ARRAY_SIZE(misc_err_status_flags));
5352 }
5353
5354 static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5355 {
5356         return flag_string(buf, buf_len, flags,
5357                            pio_err_status_flags,
5358                            ARRAY_SIZE(pio_err_status_flags));
5359 }
5360
5361 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5362 {
5363         return flag_string(buf, buf_len, flags,
5364                            sdma_err_status_flags,
5365                            ARRAY_SIZE(sdma_err_status_flags));
5366 }
5367
5368 static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5369 {
5370         return flag_string(buf, buf_len, flags,
5371                            egress_err_status_flags,
5372                            ARRAY_SIZE(egress_err_status_flags));
5373 }
5374
5375 static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5376 {
5377         return flag_string(buf, buf_len, flags,
5378                            egress_err_info_flags,
5379                            ARRAY_SIZE(egress_err_info_flags));
5380 }
5381
5382 static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5383 {
5384         return flag_string(buf, buf_len, flags,
5385                            send_err_status_flags,
5386                            ARRAY_SIZE(send_err_status_flags));
5387 }
5388
5389 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5390 {
5391         char buf[96];
5392         int i = 0;
5393
5394         /*
5395          * For most these errors, there is nothing that can be done except
5396          * report or record it.
5397          */
5398         dd_dev_info(dd, "CCE Error: %s\n",
5399                     cce_err_status_string(buf, sizeof(buf), reg));
5400
5401         if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5402             is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
5403                 /* this error requires a manual drop into SPC freeze mode */
5404                 /* then a fix up */
5405                 start_freeze_handling(dd->pport, FREEZE_SELF);
5406         }
5407
5408         for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5409                 if (reg & (1ull << i)) {
5410                         incr_cntr64(&dd->cce_err_status_cnt[i]);
5411                         /* maintain a counter over all cce_err_status errors */
5412                         incr_cntr64(&dd->sw_cce_err_status_aggregate);
5413                 }
5414         }
5415 }
5416
5417 /*
5418  * Check counters for receive errors that do not have an interrupt
5419  * associated with them.
5420  */
5421 #define RCVERR_CHECK_TIME 10
5422 static void update_rcverr_timer(unsigned long opaque)
5423 {
5424         struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
5425         struct hfi1_pportdata *ppd = dd->pport;
5426         u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5427
5428         if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
5429             ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
5430                 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
5431                 set_link_down_reason(
5432                 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5433                 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5434                 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
5435         }
5436         dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
5437
5438         mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5439 }
5440
5441 static int init_rcverr(struct hfi1_devdata *dd)
5442 {
5443         setup_timer(&dd->rcverr_timer, update_rcverr_timer, (unsigned long)dd);
5444         /* Assume the hardware counter has been reset */
5445         dd->rcv_ovfl_cnt = 0;
5446         return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5447 }
5448
5449 static void free_rcverr(struct hfi1_devdata *dd)
5450 {
5451         if (dd->rcverr_timer.data)
5452                 del_timer_sync(&dd->rcverr_timer);
5453         dd->rcverr_timer.data = 0;
5454 }
5455
5456 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5457 {
5458         char buf[96];
5459         int i = 0;
5460
5461         dd_dev_info(dd, "Receive Error: %s\n",
5462                     rxe_err_status_string(buf, sizeof(buf), reg));
5463
5464         if (reg & ALL_RXE_FREEZE_ERR) {
5465                 int flags = 0;
5466
5467                 /*
5468                  * Freeze mode recovery is disabled for the errors
5469                  * in RXE_FREEZE_ABORT_MASK
5470                  */
5471                 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
5472                         flags = FREEZE_ABORT;
5473
5474                 start_freeze_handling(dd->pport, flags);
5475         }
5476
5477         for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5478                 if (reg & (1ull << i))
5479                         incr_cntr64(&dd->rcv_err_status_cnt[i]);
5480         }
5481 }
5482
5483 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5484 {
5485         char buf[96];
5486         int i = 0;
5487
5488         dd_dev_info(dd, "Misc Error: %s",
5489                     misc_err_status_string(buf, sizeof(buf), reg));
5490         for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5491                 if (reg & (1ull << i))
5492                         incr_cntr64(&dd->misc_err_status_cnt[i]);
5493         }
5494 }
5495
5496 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5497 {
5498         char buf[96];
5499         int i = 0;
5500
5501         dd_dev_info(dd, "PIO Error: %s\n",
5502                     pio_err_status_string(buf, sizeof(buf), reg));
5503
5504         if (reg & ALL_PIO_FREEZE_ERR)
5505                 start_freeze_handling(dd->pport, 0);
5506
5507         for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5508                 if (reg & (1ull << i))
5509                         incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5510         }
5511 }
5512
5513 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5514 {
5515         char buf[96];
5516         int i = 0;
5517
5518         dd_dev_info(dd, "SDMA Error: %s\n",
5519                     sdma_err_status_string(buf, sizeof(buf), reg));
5520
5521         if (reg & ALL_SDMA_FREEZE_ERR)
5522                 start_freeze_handling(dd->pport, 0);
5523
5524         for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5525                 if (reg & (1ull << i))
5526                         incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5527         }
5528 }
5529
5530 static inline void __count_port_discards(struct hfi1_pportdata *ppd)
5531 {
5532         incr_cntr64(&ppd->port_xmit_discards);
5533 }
5534
5535 static void count_port_inactive(struct hfi1_devdata *dd)
5536 {
5537         __count_port_discards(dd->pport);
5538 }
5539
5540 /*
5541  * We have had a "disallowed packet" error during egress. Determine the
5542  * integrity check which failed, and update relevant error counter, etc.
5543  *
5544  * Note that the SEND_EGRESS_ERR_INFO register has only a single
5545  * bit of state per integrity check, and so we can miss the reason for an
5546  * egress error if more than one packet fails the same integrity check
5547  * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5548  */
5549 static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5550                                         int vl)
5551 {
5552         struct hfi1_pportdata *ppd = dd->pport;
5553         u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5554         u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5555         char buf[96];
5556
5557         /* clear down all observed info as quickly as possible after read */
5558         write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5559
5560         dd_dev_info(dd,
5561                     "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5562                     info, egress_err_info_string(buf, sizeof(buf), info), src);
5563
5564         /* Eventually add other counters for each bit */
5565         if (info & PORT_DISCARD_EGRESS_ERRS) {
5566                 int weight, i;
5567
5568                 /*
5569                  * Count all applicable bits as individual errors and
5570                  * attribute them to the packet that triggered this handler.
5571                  * This may not be completely accurate due to limitations
5572                  * on the available hardware error information.  There is
5573                  * a single information register and any number of error
5574                  * packets may have occurred and contributed to it before
5575                  * this routine is called.  This means that:
5576                  * a) If multiple packets with the same error occur before
5577                  *    this routine is called, earlier packets are missed.
5578                  *    There is only a single bit for each error type.
5579                  * b) Errors may not be attributed to the correct VL.
5580                  *    The driver is attributing all bits in the info register
5581                  *    to the packet that triggered this call, but bits
5582                  *    could be an accumulation of different packets with
5583                  *    different VLs.
5584                  * c) A single error packet may have multiple counts attached
5585                  *    to it.  There is no way for the driver to know if
5586                  *    multiple bits set in the info register are due to a
5587                  *    single packet or multiple packets.  The driver assumes
5588                  *    multiple packets.
5589                  */
5590                 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS);
5591                 for (i = 0; i < weight; i++) {
5592                         __count_port_discards(ppd);
5593                         if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5594                                 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5595                         else if (vl == 15)
5596                                 incr_cntr64(&ppd->port_xmit_discards_vl
5597                                             [C_VL_15]);
5598                 }
5599         }
5600 }
5601
5602 /*
5603  * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5604  * register. Does it represent a 'port inactive' error?
5605  */
5606 static inline int port_inactive_err(u64 posn)
5607 {
5608         return (posn >= SEES(TX_LINKDOWN) &&
5609                 posn <= SEES(TX_INCORRECT_LINK_STATE));
5610 }
5611
5612 /*
5613  * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5614  * register. Does it represent a 'disallowed packet' error?
5615  */
5616 static inline int disallowed_pkt_err(int posn)
5617 {
5618         return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5619                 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5620 }
5621
5622 /*
5623  * Input value is a bit position of one of the SDMA engine disallowed
5624  * packet errors.  Return which engine.  Use of this must be guarded by
5625  * disallowed_pkt_err().
5626  */
5627 static inline int disallowed_pkt_engine(int posn)
5628 {
5629         return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5630 }
5631
5632 /*
5633  * Translate an SDMA engine to a VL.  Return -1 if the tranlation cannot
5634  * be done.
5635  */
5636 static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5637 {
5638         struct sdma_vl_map *m;
5639         int vl;
5640
5641         /* range check */
5642         if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5643                 return -1;
5644
5645         rcu_read_lock();
5646         m = rcu_dereference(dd->sdma_map);
5647         vl = m->engine_to_vl[engine];
5648         rcu_read_unlock();
5649
5650         return vl;
5651 }
5652
5653 /*
5654  * Translate the send context (sofware index) into a VL.  Return -1 if the
5655  * translation cannot be done.
5656  */
5657 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5658 {
5659         struct send_context_info *sci;
5660         struct send_context *sc;
5661         int i;
5662
5663         sci = &dd->send_contexts[sw_index];
5664
5665         /* there is no information for user (PSM) and ack contexts */
5666         if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15))
5667                 return -1;
5668
5669         sc = sci->sc;
5670         if (!sc)
5671                 return -1;
5672         if (dd->vld[15].sc == sc)
5673                 return 15;
5674         for (i = 0; i < num_vls; i++)
5675                 if (dd->vld[i].sc == sc)
5676                         return i;
5677
5678         return -1;
5679 }
5680
5681 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5682 {
5683         u64 reg_copy = reg, handled = 0;
5684         char buf[96];
5685         int i = 0;
5686
5687         if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5688                 start_freeze_handling(dd->pport, 0);
5689         else if (is_ax(dd) &&
5690                  (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5691                  (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
5692                 start_freeze_handling(dd->pport, 0);
5693
5694         while (reg_copy) {
5695                 int posn = fls64(reg_copy);
5696                 /* fls64() returns a 1-based offset, we want it zero based */
5697                 int shift = posn - 1;
5698                 u64 mask = 1ULL << shift;
5699
5700                 if (port_inactive_err(shift)) {
5701                         count_port_inactive(dd);
5702                         handled |= mask;
5703                 } else if (disallowed_pkt_err(shift)) {
5704                         int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5705
5706                         handle_send_egress_err_info(dd, vl);
5707                         handled |= mask;
5708                 }
5709                 reg_copy &= ~mask;
5710         }
5711
5712         reg &= ~handled;
5713
5714         if (reg)
5715                 dd_dev_info(dd, "Egress Error: %s\n",
5716                             egress_err_status_string(buf, sizeof(buf), reg));
5717
5718         for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5719                 if (reg & (1ull << i))
5720                         incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5721         }
5722 }
5723
5724 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5725 {
5726         char buf[96];
5727         int i = 0;
5728
5729         dd_dev_info(dd, "Send Error: %s\n",
5730                     send_err_status_string(buf, sizeof(buf), reg));
5731
5732         for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5733                 if (reg & (1ull << i))
5734                         incr_cntr64(&dd->send_err_status_cnt[i]);
5735         }
5736 }
5737
5738 /*
5739  * The maximum number of times the error clear down will loop before
5740  * blocking a repeating error.  This value is arbitrary.
5741  */
5742 #define MAX_CLEAR_COUNT 20
5743
5744 /*
5745  * Clear and handle an error register.  All error interrupts are funneled
5746  * through here to have a central location to correctly handle single-
5747  * or multi-shot errors.
5748  *
5749  * For non per-context registers, call this routine with a context value
5750  * of 0 so the per-context offset is zero.
5751  *
5752  * If the handler loops too many times, assume that something is wrong
5753  * and can't be fixed, so mask the error bits.
5754  */
5755 static void interrupt_clear_down(struct hfi1_devdata *dd,
5756                                  u32 context,
5757                                  const struct err_reg_info *eri)
5758 {
5759         u64 reg;
5760         u32 count;
5761
5762         /* read in a loop until no more errors are seen */
5763         count = 0;
5764         while (1) {
5765                 reg = read_kctxt_csr(dd, context, eri->status);
5766                 if (reg == 0)
5767                         break;
5768                 write_kctxt_csr(dd, context, eri->clear, reg);
5769                 if (likely(eri->handler))
5770                         eri->handler(dd, context, reg);
5771                 count++;
5772                 if (count > MAX_CLEAR_COUNT) {
5773                         u64 mask;
5774
5775                         dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
5776                                    eri->desc, reg);
5777                         /*
5778                          * Read-modify-write so any other masked bits
5779                          * remain masked.
5780                          */
5781                         mask = read_kctxt_csr(dd, context, eri->mask);
5782                         mask &= ~reg;
5783                         write_kctxt_csr(dd, context, eri->mask, mask);
5784                         break;
5785                 }
5786         }
5787 }
5788
5789 /*
5790  * CCE block "misc" interrupt.  Source is < 16.
5791  */
5792 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5793 {
5794         const struct err_reg_info *eri = &misc_errs[source];
5795
5796         if (eri->handler) {
5797                 interrupt_clear_down(dd, 0, eri);
5798         } else {
5799                 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
5800                            source);
5801         }
5802 }
5803
5804 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5805 {
5806         return flag_string(buf, buf_len, flags,
5807                            sc_err_status_flags,
5808                            ARRAY_SIZE(sc_err_status_flags));
5809 }
5810
5811 /*
5812  * Send context error interrupt.  Source (hw_context) is < 160.
5813  *
5814  * All send context errors cause the send context to halt.  The normal
5815  * clear-down mechanism cannot be used because we cannot clear the
5816  * error bits until several other long-running items are done first.
5817  * This is OK because with the context halted, nothing else is going
5818  * to happen on it anyway.
5819  */
5820 static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5821                                 unsigned int hw_context)
5822 {
5823         struct send_context_info *sci;
5824         struct send_context *sc;
5825         char flags[96];
5826         u64 status;
5827         u32 sw_index;
5828         int i = 0;
5829
5830         sw_index = dd->hw_to_sw[hw_context];
5831         if (sw_index >= dd->num_send_contexts) {
5832                 dd_dev_err(dd,
5833                            "out of range sw index %u for send context %u\n",
5834                            sw_index, hw_context);
5835                 return;
5836         }
5837         sci = &dd->send_contexts[sw_index];
5838         sc = sci->sc;
5839         if (!sc) {
5840                 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
5841                            sw_index, hw_context);
5842                 return;
5843         }
5844
5845         /* tell the software that a halt has begun */
5846         sc_stop(sc, SCF_HALTED);
5847
5848         status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
5849
5850         dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
5851                     send_context_err_status_string(flags, sizeof(flags),
5852                                                    status));
5853
5854         if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
5855                 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
5856
5857         /*
5858          * Automatically restart halted kernel contexts out of interrupt
5859          * context.  User contexts must ask the driver to restart the context.
5860          */
5861         if (sc->type != SC_USER)
5862                 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
5863
5864         /*
5865          * Update the counters for the corresponding status bits.
5866          * Note that these particular counters are aggregated over all
5867          * 160 contexts.
5868          */
5869         for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
5870                 if (status & (1ull << i))
5871                         incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
5872         }
5873 }
5874
5875 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
5876                                 unsigned int source, u64 status)
5877 {
5878         struct sdma_engine *sde;
5879         int i = 0;
5880
5881         sde = &dd->per_sdma[source];
5882 #ifdef CONFIG_SDMA_VERBOSITY
5883         dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5884                    slashstrip(__FILE__), __LINE__, __func__);
5885         dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
5886                    sde->this_idx, source, (unsigned long long)status);
5887 #endif
5888         sde->err_cnt++;
5889         sdma_engine_error(sde, status);
5890
5891         /*
5892         * Update the counters for the corresponding status bits.
5893         * Note that these particular counters are aggregated over
5894         * all 16 DMA engines.
5895         */
5896         for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
5897                 if (status & (1ull << i))
5898                         incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
5899         }
5900 }
5901
5902 /*
5903  * CCE block SDMA error interrupt.  Source is < 16.
5904  */
5905 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
5906 {
5907 #ifdef CONFIG_SDMA_VERBOSITY
5908         struct sdma_engine *sde = &dd->per_sdma[source];
5909
5910         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5911                    slashstrip(__FILE__), __LINE__, __func__);
5912         dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
5913                    source);
5914         sdma_dumpstate(sde);
5915 #endif
5916         interrupt_clear_down(dd, source, &sdma_eng_err);
5917 }
5918
5919 /*
5920  * CCE block "various" interrupt.  Source is < 8.
5921  */
5922 static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
5923 {
5924         const struct err_reg_info *eri = &various_err[source];
5925
5926         /*
5927          * TCritInt cannot go through interrupt_clear_down()
5928          * because it is not a second tier interrupt. The handler
5929          * should be called directly.
5930          */
5931         if (source == TCRIT_INT_SOURCE)
5932                 handle_temp_err(dd);
5933         else if (eri->handler)
5934                 interrupt_clear_down(dd, 0, eri);
5935         else
5936                 dd_dev_info(dd,
5937                             "%s: Unimplemented/reserved interrupt %d\n",
5938                             __func__, source);
5939 }
5940
5941 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
5942 {
5943         /* src_ctx is always zero */
5944         struct hfi1_pportdata *ppd = dd->pport;
5945         unsigned long flags;
5946         u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
5947
5948         if (reg & QSFP_HFI0_MODPRST_N) {
5949                 if (!qsfp_mod_present(ppd)) {
5950                         dd_dev_info(dd, "%s: QSFP module removed\n",
5951                                     __func__);
5952
5953                         ppd->driver_link_ready = 0;
5954                         /*
5955                          * Cable removed, reset all our information about the
5956                          * cache and cable capabilities
5957                          */
5958
5959                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
5960                         /*
5961                          * We don't set cache_refresh_required here as we expect
5962                          * an interrupt when a cable is inserted
5963                          */
5964                         ppd->qsfp_info.cache_valid = 0;
5965                         ppd->qsfp_info.reset_needed = 0;
5966                         ppd->qsfp_info.limiting_active = 0;
5967                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
5968                                                flags);
5969                         /* Invert the ModPresent pin now to detect plug-in */
5970                         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
5971                                   ASIC_QSFP1_INVERT, qsfp_int_mgmt);
5972
5973                         if ((ppd->offline_disabled_reason >
5974                           HFI1_ODR_MASK(
5975                           OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
5976                           (ppd->offline_disabled_reason ==
5977                           HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
5978                                 ppd->offline_disabled_reason =
5979                                 HFI1_ODR_MASK(
5980                                 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
5981
5982                         if (ppd->host_link_state == HLS_DN_POLL) {
5983                                 /*
5984                                  * The link is still in POLL. This means
5985                                  * that the normal link down processing
5986                                  * will not happen. We have to do it here
5987                                  * before turning the DC off.
5988                                  */
5989                                 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
5990                         }
5991                 } else {
5992                         dd_dev_info(dd, "%s: QSFP module inserted\n",
5993                                     __func__);
5994
5995                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
5996                         ppd->qsfp_info.cache_valid = 0;
5997                         ppd->qsfp_info.cache_refresh_required = 1;
5998                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
5999                                                flags);
6000
6001                         /*
6002                          * Stop inversion of ModPresent pin to detect
6003                          * removal of the cable
6004                          */
6005                         qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
6006                         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6007                                   ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6008
6009                         ppd->offline_disabled_reason =
6010                                 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
6011                 }
6012         }
6013
6014         if (reg & QSFP_HFI0_INT_N) {
6015                 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n",
6016                             __func__);
6017                 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6018                 ppd->qsfp_info.check_interrupt_flags = 1;
6019                 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6020         }
6021
6022         /* Schedule the QSFP work only if there is a cable attached. */
6023         if (qsfp_mod_present(ppd))
6024                 queue_work(ppd->hfi1_wq, &ppd->qsfp_info.qsfp_work);
6025 }
6026
6027 static int request_host_lcb_access(struct hfi1_devdata *dd)
6028 {
6029         int ret;
6030
6031         ret = do_8051_command(dd, HCMD_MISC,
6032                               (u64)HCMD_MISC_REQUEST_LCB_ACCESS <<
6033                               LOAD_DATA_FIELD_ID_SHIFT, NULL);
6034         if (ret != HCMD_SUCCESS) {
6035                 dd_dev_err(dd, "%s: command failed with error %d\n",
6036                            __func__, ret);
6037         }
6038         return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6039 }
6040
6041 static int request_8051_lcb_access(struct hfi1_devdata *dd)
6042 {
6043         int ret;
6044
6045         ret = do_8051_command(dd, HCMD_MISC,
6046                               (u64)HCMD_MISC_GRANT_LCB_ACCESS <<
6047                               LOAD_DATA_FIELD_ID_SHIFT, NULL);
6048         if (ret != HCMD_SUCCESS) {
6049                 dd_dev_err(dd, "%s: command failed with error %d\n",
6050                            __func__, ret);
6051         }
6052         return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6053 }
6054
6055 /*
6056  * Set the LCB selector - allow host access.  The DCC selector always
6057  * points to the host.
6058  */
6059 static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6060 {
6061         write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6062                   DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6063                   DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6064 }
6065
6066 /*
6067  * Clear the LCB selector - allow 8051 access.  The DCC selector always
6068  * points to the host.
6069  */
6070 static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6071 {
6072         write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6073                   DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6074 }
6075
6076 /*
6077  * Acquire LCB access from the 8051.  If the host already has access,
6078  * just increment a counter.  Otherwise, inform the 8051 that the
6079  * host is taking access.
6080  *
6081  * Returns:
6082  *      0 on success
6083  *      -EBUSY if the 8051 has control and cannot be disturbed
6084  *      -errno if unable to acquire access from the 8051
6085  */
6086 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6087 {
6088         struct hfi1_pportdata *ppd = dd->pport;
6089         int ret = 0;
6090
6091         /*
6092          * Use the host link state lock so the operation of this routine
6093          * { link state check, selector change, count increment } can occur
6094          * as a unit against a link state change.  Otherwise there is a
6095          * race between the state change and the count increment.
6096          */
6097         if (sleep_ok) {
6098                 mutex_lock(&ppd->hls_lock);
6099         } else {
6100                 while (!mutex_trylock(&ppd->hls_lock))
6101                         udelay(1);
6102         }
6103
6104         /* this access is valid only when the link is up */
6105         if ((ppd->host_link_state & HLS_UP) == 0) {
6106                 dd_dev_info(dd, "%s: link state %s not up\n",
6107                             __func__, link_state_name(ppd->host_link_state));
6108                 ret = -EBUSY;
6109                 goto done;
6110         }
6111
6112         if (dd->lcb_access_count == 0) {
6113                 ret = request_host_lcb_access(dd);
6114                 if (ret) {
6115                         dd_dev_err(dd,
6116                                    "%s: unable to acquire LCB access, err %d\n",
6117                                    __func__, ret);
6118                         goto done;
6119                 }
6120                 set_host_lcb_access(dd);
6121         }
6122         dd->lcb_access_count++;
6123 done:
6124         mutex_unlock(&ppd->hls_lock);
6125         return ret;
6126 }
6127
6128 /*
6129  * Release LCB access by decrementing the use count.  If the count is moving
6130  * from 1 to 0, inform 8051 that it has control back.
6131  *
6132  * Returns:
6133  *      0 on success
6134  *      -errno if unable to release access to the 8051
6135  */
6136 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6137 {
6138         int ret = 0;
6139
6140         /*
6141          * Use the host link state lock because the acquire needed it.
6142          * Here, we only need to keep { selector change, count decrement }
6143          * as a unit.
6144          */
6145         if (sleep_ok) {
6146                 mutex_lock(&dd->pport->hls_lock);
6147         } else {
6148                 while (!mutex_trylock(&dd->pport->hls_lock))
6149                         udelay(1);
6150         }
6151
6152         if (dd->lcb_access_count == 0) {
6153                 dd_dev_err(dd, "%s: LCB access count is zero.  Skipping.\n",
6154                            __func__);
6155                 goto done;
6156         }
6157
6158         if (dd->lcb_access_count == 1) {
6159                 set_8051_lcb_access(dd);
6160                 ret = request_8051_lcb_access(dd);
6161                 if (ret) {
6162                         dd_dev_err(dd,
6163                                    "%s: unable to release LCB access, err %d\n",
6164                                    __func__, ret);
6165                         /* restore host access if the grant didn't work */
6166                         set_host_lcb_access(dd);
6167                         goto done;
6168                 }
6169         }
6170         dd->lcb_access_count--;
6171 done:
6172         mutex_unlock(&dd->pport->hls_lock);
6173         return ret;
6174 }
6175
6176 /*
6177  * Initialize LCB access variables and state.  Called during driver load,
6178  * after most of the initialization is finished.
6179  *
6180  * The DC default is LCB access on for the host.  The driver defaults to
6181  * leaving access to the 8051.  Assign access now - this constrains the call
6182  * to this routine to be after all LCB set-up is done.  In particular, after
6183  * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6184  */
6185 static void init_lcb_access(struct hfi1_devdata *dd)
6186 {
6187         dd->lcb_access_count = 0;
6188 }
6189
6190 /*
6191  * Write a response back to a 8051 request.
6192  */
6193 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6194 {
6195         write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
6196                   DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6197                   (u64)return_code <<
6198                   DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6199                   (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
6200 }
6201
6202 /*
6203  * Handle host requests from the 8051.
6204  */
6205 static void handle_8051_request(struct hfi1_pportdata *ppd)
6206 {
6207         struct hfi1_devdata *dd = ppd->dd;
6208         u64 reg;
6209         u16 data = 0;
6210         u8 type;
6211
6212         reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6213         if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6214                 return; /* no request */
6215
6216         /* zero out COMPLETED so the response is seen */
6217         write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6218
6219         /* extract request details */
6220         type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6221                         & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6222         data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6223                         & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6224
6225         switch (type) {
6226         case HREQ_LOAD_CONFIG:
6227         case HREQ_SAVE_CONFIG:
6228         case HREQ_READ_CONFIG:
6229         case HREQ_SET_TX_EQ_ABS:
6230         case HREQ_SET_TX_EQ_REL:
6231         case HREQ_ENABLE:
6232                 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
6233                             type);
6234                 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6235                 break;
6236         case HREQ_CONFIG_DONE:
6237                 hreq_response(dd, HREQ_SUCCESS, 0);
6238                 break;
6239
6240         case HREQ_INTERFACE_TEST:
6241                 hreq_response(dd, HREQ_SUCCESS, data);
6242                 break;
6243         default:
6244                 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6245                 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6246                 break;
6247         }
6248 }
6249
6250 static void write_global_credit(struct hfi1_devdata *dd,
6251                                 u8 vau, u16 total, u16 shared)
6252 {
6253         write_csr(dd, SEND_CM_GLOBAL_CREDIT,
6254                   ((u64)total <<
6255                    SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) |
6256                   ((u64)shared <<
6257                    SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) |
6258                   ((u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT));
6259 }
6260
6261 /*
6262  * Set up initial VL15 credits of the remote.  Assumes the rest of
6263  * the CM credit registers are zero from a previous global or credit reset .
6264  */
6265 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf)
6266 {
6267         /* leave shared count at zero for both global and VL15 */
6268         write_global_credit(dd, vau, vl15buf, 0);
6269
6270         /* We may need some credits for another VL when sending packets
6271          * with the snoop interface. Dividing it down the middle for VL15
6272          * and VL0 should suffice.
6273          */
6274         if (unlikely(dd->hfi1_snoop.mode_flag == HFI1_PORT_SNOOP_MODE)) {
6275                 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)(vl15buf >> 1)
6276                     << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6277                 write_csr(dd, SEND_CM_CREDIT_VL, (u64)(vl15buf >> 1)
6278                     << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT);
6279         } else {
6280                 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6281                         << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6282         }
6283 }
6284
6285 /*
6286  * Zero all credit details from the previous connection and
6287  * reset the CM manager's internal counters.
6288  */
6289 void reset_link_credits(struct hfi1_devdata *dd)
6290 {
6291         int i;
6292
6293         /* remove all previous VL credit limits */
6294         for (i = 0; i < TXE_NUM_DATA_VL; i++)
6295                 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
6296         write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6297         write_global_credit(dd, 0, 0, 0);
6298         /* reset the CM block */
6299         pio_send_control(dd, PSC_CM_RESET);
6300 }
6301
6302 /* convert a vCU to a CU */
6303 static u32 vcu_to_cu(u8 vcu)
6304 {
6305         return 1 << vcu;
6306 }
6307
6308 /* convert a CU to a vCU */
6309 static u8 cu_to_vcu(u32 cu)
6310 {
6311         return ilog2(cu);
6312 }
6313
6314 /* convert a vAU to an AU */
6315 static u32 vau_to_au(u8 vau)
6316 {
6317         return 8 * (1 << vau);
6318 }
6319
6320 static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6321 {
6322         ppd->sm_trap_qp = 0x0;
6323         ppd->sa_qp = 0x1;
6324 }
6325
6326 /*
6327  * Graceful LCB shutdown.  This leaves the LCB FIFOs in reset.
6328  */
6329 static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6330 {
6331         u64 reg;
6332
6333         /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6334         write_csr(dd, DC_LCB_CFG_RUN, 0);
6335         /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6336         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
6337                   1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
6338         /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6339         dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6340         reg = read_csr(dd, DCC_CFG_RESET);
6341         write_csr(dd, DCC_CFG_RESET, reg |
6342                   (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT) |
6343                   (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT));
6344         (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
6345         if (!abort) {
6346                 udelay(1);    /* must hold for the longer of 16cclks or 20ns */
6347                 write_csr(dd, DCC_CFG_RESET, reg);
6348                 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6349         }
6350 }
6351
6352 /*
6353  * This routine should be called after the link has been transitioned to
6354  * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6355  * reset).
6356  *
6357  * The expectation is that the caller of this routine would have taken
6358  * care of properly transitioning the link into the correct state.
6359  */
6360 static void dc_shutdown(struct hfi1_devdata *dd)
6361 {
6362         unsigned long flags;
6363
6364         spin_lock_irqsave(&dd->dc8051_lock, flags);
6365         if (dd->dc_shutdown) {
6366                 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6367                 return;
6368         }
6369         dd->dc_shutdown = 1;
6370         spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6371         /* Shutdown the LCB */
6372         lcb_shutdown(dd, 1);
6373         /*
6374          * Going to OFFLINE would have causes the 8051 to put the
6375          * SerDes into reset already. Just need to shut down the 8051,
6376          * itself.
6377          */
6378         write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6379 }
6380
6381 /*
6382  * Calling this after the DC has been brought out of reset should not
6383  * do any damage.
6384  */
6385 static void dc_start(struct hfi1_devdata *dd)
6386 {
6387         unsigned long flags;
6388         int ret;
6389
6390         spin_lock_irqsave(&dd->dc8051_lock, flags);
6391         if (!dd->dc_shutdown)
6392                 goto done;
6393         spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6394         /* Take the 8051 out of reset */
6395         write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6396         /* Wait until 8051 is ready */
6397         ret = wait_fm_ready(dd, TIMEOUT_8051_START);
6398         if (ret) {
6399                 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
6400                            __func__);
6401         }
6402         /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6403         write_csr(dd, DCC_CFG_RESET, 0x10);
6404         /* lcb_shutdown() with abort=1 does not restore these */
6405         write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6406         spin_lock_irqsave(&dd->dc8051_lock, flags);
6407         dd->dc_shutdown = 0;
6408 done:
6409         spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6410 }
6411
6412 /*
6413  * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6414  */
6415 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6416 {
6417         u64 rx_radr, tx_radr;
6418         u32 version;
6419
6420         if (dd->icode != ICODE_FPGA_EMULATION)
6421                 return;
6422
6423         /*
6424          * These LCB defaults on emulator _s are good, nothing to do here:
6425          *      LCB_CFG_TX_FIFOS_RADR
6426          *      LCB_CFG_RX_FIFOS_RADR
6427          *      LCB_CFG_LN_DCLK
6428          *      LCB_CFG_IGNORE_LOST_RCLK
6429          */
6430         if (is_emulator_s(dd))
6431                 return;
6432         /* else this is _p */
6433
6434         version = emulator_rev(dd);
6435         if (!is_ax(dd))
6436                 version = 0x2d; /* all B0 use 0x2d or higher settings */
6437
6438         if (version <= 0x12) {
6439                 /* release 0x12 and below */
6440
6441                 /*
6442                  * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6443                  * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6444                  * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6445                  */
6446                 rx_radr =
6447                       0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6448                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6449                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6450                 /*
6451                  * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6452                  * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6453                  */
6454                 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6455         } else if (version <= 0x18) {
6456                 /* release 0x13 up to 0x18 */
6457                 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6458                 rx_radr =
6459                       0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6460                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6461                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6462                 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6463         } else if (version == 0x19) {
6464                 /* release 0x19 */
6465                 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6466                 rx_radr =
6467                       0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6468                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6469                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6470                 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6471         } else if (version == 0x1a) {
6472                 /* release 0x1a */
6473                 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6474                 rx_radr =
6475                       0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6476                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6477                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6478                 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6479                 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6480         } else {
6481                 /* release 0x1b and higher */
6482                 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6483                 rx_radr =
6484                       0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6485                     | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6486                     | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6487                 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6488         }
6489
6490         write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6491         /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6492         write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
6493                   DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6494         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6495 }
6496
6497 /*
6498  * Handle a SMA idle message
6499  *
6500  * This is a work-queue function outside of the interrupt.
6501  */
6502 void handle_sma_message(struct work_struct *work)
6503 {
6504         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6505                                                         sma_message_work);
6506         struct hfi1_devdata *dd = ppd->dd;
6507         u64 msg;
6508         int ret;
6509
6510         /*
6511          * msg is bytes 1-4 of the 40-bit idle message - the command code
6512          * is stripped off
6513          */
6514         ret = read_idle_sma(dd, &msg);
6515         if (ret)
6516                 return;
6517         dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6518         /*
6519          * React to the SMA message.  Byte[1] (0 for us) is the command.
6520          */
6521         switch (msg & 0xff) {
6522         case SMA_IDLE_ARM:
6523                 /*
6524                  * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6525                  * State Transitions
6526                  *
6527                  * Only expected in INIT or ARMED, discard otherwise.
6528                  */
6529                 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6530                         ppd->neighbor_normal = 1;
6531                 break;
6532         case SMA_IDLE_ACTIVE:
6533                 /*
6534                  * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6535                  * State Transitions
6536                  *
6537                  * Can activate the node.  Discard otherwise.
6538                  */
6539                 if (ppd->host_link_state == HLS_UP_ARMED &&
6540                     ppd->is_active_optimize_enabled) {
6541                         ppd->neighbor_normal = 1;
6542                         ret = set_link_state(ppd, HLS_UP_ACTIVE);
6543                         if (ret)
6544                                 dd_dev_err(
6545                                         dd,
6546                                         "%s: received Active SMA idle message, couldn't set link to Active\n",
6547                                         __func__);
6548                 }
6549                 break;
6550         default:
6551                 dd_dev_err(dd,
6552                            "%s: received unexpected SMA idle message 0x%llx\n",
6553                            __func__, msg);
6554                 break;
6555         }
6556 }
6557
6558 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6559 {
6560         u64 rcvctrl;
6561         unsigned long flags;
6562
6563         spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6564         rcvctrl = read_csr(dd, RCV_CTRL);
6565         rcvctrl |= add;
6566         rcvctrl &= ~clear;
6567         write_csr(dd, RCV_CTRL, rcvctrl);
6568         spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6569 }
6570
6571 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6572 {
6573         adjust_rcvctrl(dd, add, 0);
6574 }
6575
6576 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6577 {
6578         adjust_rcvctrl(dd, 0, clear);
6579 }
6580
6581 /*
6582  * Called from all interrupt handlers to start handling an SPC freeze.
6583  */
6584 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6585 {
6586         struct hfi1_devdata *dd = ppd->dd;
6587         struct send_context *sc;
6588         int i;
6589
6590         if (flags & FREEZE_SELF)
6591                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6592
6593         /* enter frozen mode */
6594         dd->flags |= HFI1_FROZEN;
6595
6596         /* notify all SDMA engines that they are going into a freeze */
6597         sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6598
6599         /* do halt pre-handling on all enabled send contexts */
6600         for (i = 0; i < dd->num_send_contexts; i++) {
6601                 sc = dd->send_contexts[i].sc;
6602                 if (sc && (sc->flags & SCF_ENABLED))
6603                         sc_stop(sc, SCF_FROZEN | SCF_HALTED);
6604         }
6605
6606         /* Send context are frozen. Notify user space */
6607         hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6608
6609         if (flags & FREEZE_ABORT) {
6610                 dd_dev_err(dd,
6611                            "Aborted freeze recovery. Please REBOOT system\n");
6612                 return;
6613         }
6614         /* queue non-interrupt handler */
6615         queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6616 }
6617
6618 /*
6619  * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6620  * depending on the "freeze" parameter.
6621  *
6622  * No need to return an error if it times out, our only option
6623  * is to proceed anyway.
6624  */
6625 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6626 {
6627         unsigned long timeout;
6628         u64 reg;
6629
6630         timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6631         while (1) {
6632                 reg = read_csr(dd, CCE_STATUS);
6633                 if (freeze) {
6634                         /* waiting until all indicators are set */
6635                         if ((reg & ALL_FROZE) == ALL_FROZE)
6636                                 return; /* all done */
6637                 } else {
6638                         /* waiting until all indicators are clear */
6639                         if ((reg & ALL_FROZE) == 0)
6640                                 return; /* all done */
6641                 }
6642
6643                 if (time_after(jiffies, timeout)) {
6644                         dd_dev_err(dd,
6645                                    "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6646                                    freeze ? "" : "un", reg & ALL_FROZE,
6647                                    freeze ? ALL_FROZE : 0ull);
6648                         return;
6649                 }
6650                 usleep_range(80, 120);
6651         }
6652 }
6653
6654 /*
6655  * Do all freeze handling for the RXE block.
6656  */
6657 static void rxe_freeze(struct hfi1_devdata *dd)
6658 {
6659         int i;
6660
6661         /* disable port */
6662         clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6663
6664         /* disable all receive contexts */
6665         for (i = 0; i < dd->num_rcv_contexts; i++)
6666                 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, i);
6667 }
6668
6669 /*
6670  * Unfreeze handling for the RXE block - kernel contexts only.
6671  * This will also enable the port.  User contexts will do unfreeze
6672  * handling on a per-context basis as they call into the driver.
6673  *
6674  */
6675 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6676 {
6677         u32 rcvmask;
6678         int i;
6679
6680         /* enable all kernel contexts */
6681         for (i = 0; i < dd->n_krcv_queues; i++) {
6682                 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6683                 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6684                 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
6685                         HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6686                 hfi1_rcvctrl(dd, rcvmask, i);
6687         }
6688
6689         /* enable port */
6690         add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6691 }
6692
6693 /*
6694  * Non-interrupt SPC freeze handling.
6695  *
6696  * This is a work-queue function outside of the triggering interrupt.
6697  */
6698 void handle_freeze(struct work_struct *work)
6699 {
6700         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6701                                                                 freeze_work);
6702         struct hfi1_devdata *dd = ppd->dd;
6703
6704         /* wait for freeze indicators on all affected blocks */
6705         wait_for_freeze_status(dd, 1);
6706
6707         /* SPC is now frozen */
6708
6709         /* do send PIO freeze steps */
6710         pio_freeze(dd);
6711
6712         /* do send DMA freeze steps */
6713         sdma_freeze(dd);
6714
6715         /* do send egress freeze steps - nothing to do */
6716
6717         /* do receive freeze steps */
6718         rxe_freeze(dd);
6719
6720         /*
6721          * Unfreeze the hardware - clear the freeze, wait for each
6722          * block's frozen bit to clear, then clear the frozen flag.
6723          */
6724         write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6725         wait_for_freeze_status(dd, 0);
6726
6727         if (is_ax(dd)) {
6728                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6729                 wait_for_freeze_status(dd, 1);
6730                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6731                 wait_for_freeze_status(dd, 0);
6732         }
6733
6734         /* do send PIO unfreeze steps for kernel contexts */
6735         pio_kernel_unfreeze(dd);
6736
6737         /* do send DMA unfreeze steps */
6738         sdma_unfreeze(dd);
6739
6740         /* do send egress unfreeze steps - nothing to do */
6741
6742         /* do receive unfreeze steps for kernel contexts */
6743         rxe_kernel_unfreeze(dd);
6744
6745         /*
6746          * The unfreeze procedure touches global device registers when
6747          * it disables and re-enables RXE. Mark the device unfrozen
6748          * after all that is done so other parts of the driver waiting
6749          * for the device to unfreeze don't do things out of order.
6750          *
6751          * The above implies that the meaning of HFI1_FROZEN flag is
6752          * "Device has gone into freeze mode and freeze mode handling
6753          * is still in progress."
6754          *
6755          * The flag will be removed when freeze mode processing has
6756          * completed.
6757          */
6758         dd->flags &= ~HFI1_FROZEN;
6759         wake_up(&dd->event_queue);
6760
6761         /* no longer frozen */
6762 }
6763
6764 /*
6765  * Handle a link up interrupt from the 8051.
6766  *
6767  * This is a work-queue function outside of the interrupt.
6768  */
6769 void handle_link_up(struct work_struct *work)
6770 {
6771         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6772                                                   link_up_work);
6773         set_link_state(ppd, HLS_UP_INIT);
6774
6775         /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6776         read_ltp_rtt(ppd->dd);
6777         /*
6778          * OPA specifies that certain counters are cleared on a transition
6779          * to link up, so do that.
6780          */
6781         clear_linkup_counters(ppd->dd);
6782         /*
6783          * And (re)set link up default values.
6784          */
6785         set_linkup_defaults(ppd);
6786
6787         /* enforce link speed enabled */
6788         if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6789                 /* oops - current speed is not enabled, bounce */
6790                 dd_dev_err(ppd->dd,
6791                            "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6792                            ppd->link_speed_active, ppd->link_speed_enabled);
6793                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
6794                                      OPA_LINKDOWN_REASON_SPEED_POLICY);
6795                 set_link_state(ppd, HLS_DN_OFFLINE);
6796                 tune_serdes(ppd);
6797                 start_link(ppd);
6798         }
6799 }
6800
6801 /*
6802  * Several pieces of LNI information were cached for SMA in ppd.
6803  * Reset these on link down
6804  */
6805 static void reset_neighbor_info(struct hfi1_pportdata *ppd)
6806 {
6807         ppd->neighbor_guid = 0;
6808         ppd->neighbor_port_number = 0;
6809         ppd->neighbor_type = 0;
6810         ppd->neighbor_fm_security = 0;
6811 }
6812
6813 /*
6814  * Handle a link down interrupt from the 8051.
6815  *
6816  * This is a work-queue function outside of the interrupt.
6817  */
6818 void handle_link_down(struct work_struct *work)
6819 {
6820         u8 lcl_reason, neigh_reason = 0;
6821         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6822                                                                 link_down_work);
6823
6824         if ((ppd->host_link_state &
6825              (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
6826              ppd->port_type == PORT_TYPE_FIXED)
6827                 ppd->offline_disabled_reason =
6828                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
6829
6830         /* Go offline first, then deal with reading/writing through 8051 */
6831         set_link_state(ppd, HLS_DN_OFFLINE);
6832
6833         lcl_reason = 0;
6834         read_planned_down_reason_code(ppd->dd, &neigh_reason);
6835
6836         /*
6837          * If no reason, assume peer-initiated but missed
6838          * LinkGoingDown idle flits.
6839          */
6840         if (neigh_reason == 0)
6841                 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
6842
6843         set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
6844
6845         reset_neighbor_info(ppd);
6846
6847         /* disable the port */
6848         clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6849
6850         /*
6851          * If there is no cable attached, turn the DC off. Otherwise,
6852          * start the link bring up.
6853          */
6854         if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd)) {
6855                 dc_shutdown(ppd->dd);
6856         } else {
6857                 tune_serdes(ppd);
6858                 start_link(ppd);
6859         }
6860 }
6861
6862 void handle_link_bounce(struct work_struct *work)
6863 {
6864         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6865                                                         link_bounce_work);
6866
6867         /*
6868          * Only do something if the link is currently up.
6869          */
6870         if (ppd->host_link_state & HLS_UP) {
6871                 set_link_state(ppd, HLS_DN_OFFLINE);
6872                 tune_serdes(ppd);
6873                 start_link(ppd);
6874         } else {
6875                 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
6876                             __func__, link_state_name(ppd->host_link_state));
6877         }
6878 }
6879
6880 /*
6881  * Mask conversion: Capability exchange to Port LTP.  The capability
6882  * exchange has an implicit 16b CRC that is mandatory.
6883  */
6884 static int cap_to_port_ltp(int cap)
6885 {
6886         int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
6887
6888         if (cap & CAP_CRC_14B)
6889                 port_ltp |= PORT_LTP_CRC_MODE_14;
6890         if (cap & CAP_CRC_48B)
6891                 port_ltp |= PORT_LTP_CRC_MODE_48;
6892         if (cap & CAP_CRC_12B_16B_PER_LANE)
6893                 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
6894
6895         return port_ltp;
6896 }
6897
6898 /*
6899  * Convert an OPA Port LTP mask to capability mask
6900  */
6901 int port_ltp_to_cap(int port_ltp)
6902 {
6903         int cap_mask = 0;
6904
6905         if (port_ltp & PORT_LTP_CRC_MODE_14)
6906                 cap_mask |= CAP_CRC_14B;
6907         if (port_ltp & PORT_LTP_CRC_MODE_48)
6908                 cap_mask |= CAP_CRC_48B;
6909         if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
6910                 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
6911
6912         return cap_mask;
6913 }
6914
6915 /*
6916  * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
6917  */
6918 static int lcb_to_port_ltp(int lcb_crc)
6919 {
6920         int port_ltp = 0;
6921
6922         if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
6923                 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
6924         else if (lcb_crc == LCB_CRC_48B)
6925                 port_ltp = PORT_LTP_CRC_MODE_48;
6926         else if (lcb_crc == LCB_CRC_14B)
6927                 port_ltp = PORT_LTP_CRC_MODE_14;
6928         else
6929                 port_ltp = PORT_LTP_CRC_MODE_16;
6930
6931         return port_ltp;
6932 }
6933
6934 /*
6935  * Our neighbor has indicated that we are allowed to act as a fabric
6936  * manager, so place the full management partition key in the second
6937  * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
6938  * that we should already have the limited management partition key in
6939  * array element 1, and also that the port is not yet up when
6940  * add_full_mgmt_pkey() is invoked.
6941  */
6942 static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
6943 {
6944         struct hfi1_devdata *dd = ppd->dd;
6945
6946         /* Sanity check - ppd->pkeys[2] should be 0, or already initalized */
6947         if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
6948                 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
6949                             __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
6950         ppd->pkeys[2] = FULL_MGMT_P_KEY;
6951         (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
6952 }
6953
6954 /*
6955  * Convert the given link width to the OPA link width bitmask.
6956  */
6957 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
6958 {
6959         switch (width) {
6960         case 0:
6961                 /*
6962                  * Simulator and quick linkup do not set the width.
6963                  * Just set it to 4x without complaint.
6964                  */
6965                 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
6966                         return OPA_LINK_WIDTH_4X;
6967                 return 0; /* no lanes up */
6968         case 1: return OPA_LINK_WIDTH_1X;
6969         case 2: return OPA_LINK_WIDTH_2X;
6970         case 3: return OPA_LINK_WIDTH_3X;
6971         default:
6972                 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
6973                             __func__, width);
6974                 /* fall through */
6975         case 4: return OPA_LINK_WIDTH_4X;
6976         }
6977 }
6978
6979 /*
6980  * Do a population count on the bottom nibble.
6981  */
6982 static const u8 bit_counts[16] = {
6983         0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
6984 };
6985
6986 static inline u8 nibble_to_count(u8 nibble)
6987 {
6988         return bit_counts[nibble & 0xf];
6989 }
6990
6991 /*
6992  * Read the active lane information from the 8051 registers and return
6993  * their widths.
6994  *
6995  * Active lane information is found in these 8051 registers:
6996  *      enable_lane_tx
6997  *      enable_lane_rx
6998  */
6999 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7000                             u16 *rx_width)
7001 {
7002         u16 tx, rx;
7003         u8 enable_lane_rx;
7004         u8 enable_lane_tx;
7005         u8 tx_polarity_inversion;
7006         u8 rx_polarity_inversion;
7007         u8 max_rate;
7008
7009         /* read the active lanes */
7010         read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
7011                          &rx_polarity_inversion, &max_rate);
7012         read_local_lni(dd, &enable_lane_rx);
7013
7014         /* convert to counts */
7015         tx = nibble_to_count(enable_lane_tx);
7016         rx = nibble_to_count(enable_lane_rx);
7017
7018         /*
7019          * Set link_speed_active here, overriding what was set in
7020          * handle_verify_cap().  The ASIC 8051 firmware does not correctly
7021          * set the max_rate field in handle_verify_cap until v0.19.
7022          */
7023         if ((dd->icode == ICODE_RTL_SILICON) &&
7024             (dd->dc8051_ver < dc8051_ver(0, 19))) {
7025                 /* max_rate: 0 = 12.5G, 1 = 25G */
7026                 switch (max_rate) {
7027                 case 0:
7028                         dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7029                         break;
7030                 default:
7031                         dd_dev_err(dd,
7032                                    "%s: unexpected max rate %d, using 25Gb\n",
7033                                    __func__, (int)max_rate);
7034                         /* fall through */
7035                 case 1:
7036                         dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7037                         break;
7038                 }
7039         }
7040
7041         dd_dev_info(dd,
7042                     "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7043                     enable_lane_tx, tx, enable_lane_rx, rx);
7044         *tx_width = link_width_to_bits(dd, tx);
7045         *rx_width = link_width_to_bits(dd, rx);
7046 }
7047
7048 /*
7049  * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7050  * Valid after the end of VerifyCap and during LinkUp.  Does not change
7051  * after link up.  I.e. look elsewhere for downgrade information.
7052  *
7053  * Bits are:
7054  *      + bits [7:4] contain the number of active transmitters
7055  *      + bits [3:0] contain the number of active receivers
7056  * These are numbers 1 through 4 and can be different values if the
7057  * link is asymmetric.
7058  *
7059  * verify_cap_local_fm_link_width[0] retains its original value.
7060  */
7061 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7062                               u16 *rx_width)
7063 {
7064         u16 widths, tx, rx;
7065         u8 misc_bits, local_flags;
7066         u16 active_tx, active_rx;
7067
7068         read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths);
7069         tx = widths >> 12;
7070         rx = (widths >> 8) & 0xf;
7071
7072         *tx_width = link_width_to_bits(dd, tx);
7073         *rx_width = link_width_to_bits(dd, rx);
7074
7075         /* print the active widths */
7076         get_link_widths(dd, &active_tx, &active_rx);
7077 }
7078
7079 /*
7080  * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7081  * hardware information when the link first comes up.
7082  *
7083  * The link width is not available until after VerifyCap.AllFramesReceived
7084  * (the trigger for handle_verify_cap), so this is outside that routine
7085  * and should be called when the 8051 signals linkup.
7086  */
7087 void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7088 {
7089         u16 tx_width, rx_width;
7090
7091         /* get end-of-LNI link widths */
7092         get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7093
7094         /* use tx_width as the link is supposed to be symmetric on link up */
7095         ppd->link_width_active = tx_width;
7096         /* link width downgrade active (LWD.A) starts out matching LW.A */
7097         ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7098         ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7099         /* per OPA spec, on link up LWD.E resets to LWD.S */
7100         ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7101         /* cache the active egress rate (units {10^6 bits/sec]) */
7102         ppd->current_egress_rate = active_egress_rate(ppd);
7103 }
7104
7105 /*
7106  * Handle a verify capabilities interrupt from the 8051.
7107  *
7108  * This is a work-queue function outside of the interrupt.
7109  */
7110 void handle_verify_cap(struct work_struct *work)
7111 {
7112         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7113                                                                 link_vc_work);
7114         struct hfi1_devdata *dd = ppd->dd;
7115         u64 reg;
7116         u8 power_management;
7117         u8 continious;
7118         u8 vcu;
7119         u8 vau;
7120         u8 z;
7121         u16 vl15buf;
7122         u16 link_widths;
7123         u16 crc_mask;
7124         u16 crc_val;
7125         u16 device_id;
7126         u16 active_tx, active_rx;
7127         u8 partner_supported_crc;
7128         u8 remote_tx_rate;
7129         u8 device_rev;
7130
7131         set_link_state(ppd, HLS_VERIFY_CAP);
7132
7133         lcb_shutdown(dd, 0);
7134         adjust_lcb_for_fpga_serdes(dd);
7135
7136         /*
7137          * These are now valid:
7138          *      remote VerifyCap fields in the general LNI config
7139          *      CSR DC8051_STS_REMOTE_GUID
7140          *      CSR DC8051_STS_REMOTE_NODE_TYPE
7141          *      CSR DC8051_STS_REMOTE_FM_SECURITY
7142          *      CSR DC8051_STS_REMOTE_PORT_NO
7143          */
7144
7145         read_vc_remote_phy(dd, &power_management, &continious);
7146         read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf,
7147                               &partner_supported_crc);
7148         read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7149         read_remote_device_id(dd, &device_id, &device_rev);
7150         /*
7151          * And the 'MgmtAllowed' information, which is exchanged during
7152          * LNI, is also be available at this point.
7153          */
7154         read_mgmt_allowed(dd, &ppd->mgmt_allowed);
7155         /* print the active widths */
7156         get_link_widths(dd, &active_tx, &active_rx);
7157         dd_dev_info(dd,
7158                     "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7159                     (int)power_management, (int)continious);
7160         dd_dev_info(dd,
7161                     "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7162                     (int)vau, (int)z, (int)vcu, (int)vl15buf,
7163                     (int)partner_supported_crc);
7164         dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
7165                     (u32)remote_tx_rate, (u32)link_widths);
7166         dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
7167                     (u32)device_id, (u32)device_rev);
7168         /*
7169          * The peer vAU value just read is the peer receiver value.  HFI does
7170          * not support a transmit vAU of 0 (AU == 8).  We advertised that
7171          * with Z=1 in the fabric capabilities sent to the peer.  The peer
7172          * will see our Z=1, and, if it advertised a vAU of 0, will move its
7173          * receive to vAU of 1 (AU == 16).  Do the same here.  We do not care
7174          * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7175          * subject to the Z value exception.
7176          */
7177         if (vau == 0)
7178                 vau = 1;
7179         set_up_vl15(dd, vau, vl15buf);
7180
7181         /* set up the LCB CRC mode */
7182         crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7183
7184         /* order is important: use the lowest bit in common */
7185         if (crc_mask & CAP_CRC_14B)
7186                 crc_val = LCB_CRC_14B;
7187         else if (crc_mask & CAP_CRC_48B)
7188                 crc_val = LCB_CRC_48B;
7189         else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7190                 crc_val = LCB_CRC_12B_16B_PER_LANE;
7191         else
7192                 crc_val = LCB_CRC_16B;
7193
7194         dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7195         write_csr(dd, DC_LCB_CFG_CRC_MODE,
7196                   (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7197
7198         /* set (14b only) or clear sideband credit */
7199         reg = read_csr(dd, SEND_CM_CTRL);
7200         if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7201                 write_csr(dd, SEND_CM_CTRL,
7202                           reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7203         } else {
7204                 write_csr(dd, SEND_CM_CTRL,
7205                           reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7206         }
7207
7208         ppd->link_speed_active = 0;     /* invalid value */
7209         if (dd->dc8051_ver < dc8051_ver(0, 20)) {
7210                 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7211                 switch (remote_tx_rate) {
7212                 case 0:
7213                         ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7214                         break;
7215                 case 1:
7216                         ppd->link_speed_active = OPA_LINK_SPEED_25G;
7217                         break;
7218                 }
7219         } else {
7220                 /* actual rate is highest bit of the ANDed rates */
7221                 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7222
7223                 if (rate & 2)
7224                         ppd->link_speed_active = OPA_LINK_SPEED_25G;
7225                 else if (rate & 1)
7226                         ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7227         }
7228         if (ppd->link_speed_active == 0) {
7229                 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
7230                            __func__, (int)remote_tx_rate);
7231                 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7232         }
7233
7234         /*
7235          * Cache the values of the supported, enabled, and active
7236          * LTP CRC modes to return in 'portinfo' queries. But the bit
7237          * flags that are returned in the portinfo query differ from
7238          * what's in the link_crc_mask, crc_sizes, and crc_val
7239          * variables. Convert these here.
7240          */
7241         ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7242                 /* supported crc modes */
7243         ppd->port_ltp_crc_mode |=
7244                 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7245                 /* enabled crc modes */
7246         ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7247                 /* active crc mode */
7248
7249         /* set up the remote credit return table */
7250         assign_remote_cm_au_table(dd, vcu);
7251
7252         /*
7253          * The LCB is reset on entry to handle_verify_cap(), so this must
7254          * be applied on every link up.
7255          *
7256          * Adjust LCB error kill enable to kill the link if
7257          * these RBUF errors are seen:
7258          *      REPLAY_BUF_MBE_SMASK
7259          *      FLIT_INPUT_BUF_MBE_SMASK
7260          */
7261         if (is_ax(dd)) {                        /* fixed in B0 */
7262                 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7263                 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7264                         | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7265                 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7266         }
7267
7268         /* pull LCB fifos out of reset - all fifo clocks must be stable */
7269         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7270
7271         /* give 8051 access to the LCB CSRs */
7272         write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7273         set_8051_lcb_access(dd);
7274
7275         ppd->neighbor_guid =
7276                 read_csr(dd, DC_DC8051_STS_REMOTE_GUID);
7277         ppd->neighbor_port_number = read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) &
7278                                         DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK;
7279         ppd->neighbor_type =
7280                 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) &
7281                 DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK;
7282         ppd->neighbor_fm_security =
7283                 read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) &
7284                 DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK;
7285         dd_dev_info(dd,
7286                     "Neighbor Guid: %llx Neighbor type %d MgmtAllowed %d FM security bypass %d\n",
7287                     ppd->neighbor_guid, ppd->neighbor_type,
7288                     ppd->mgmt_allowed, ppd->neighbor_fm_security);
7289         if (ppd->mgmt_allowed)
7290                 add_full_mgmt_pkey(ppd);
7291
7292         /* tell the 8051 to go to LinkUp */
7293         set_link_state(ppd, HLS_GOING_UP);
7294 }
7295
7296 /*
7297  * Apply the link width downgrade enabled policy against the current active
7298  * link widths.
7299  *
7300  * Called when the enabled policy changes or the active link widths change.
7301  */
7302 void apply_link_downgrade_policy(struct hfi1_pportdata *ppd, int refresh_widths)
7303 {
7304         int do_bounce = 0;
7305         int tries;
7306         u16 lwde;
7307         u16 tx, rx;
7308
7309         /* use the hls lock to avoid a race with actual link up */
7310         tries = 0;
7311 retry:
7312         mutex_lock(&ppd->hls_lock);
7313         /* only apply if the link is up */
7314         if (!(ppd->host_link_state & HLS_UP)) {
7315                 /* still going up..wait and retry */
7316                 if (ppd->host_link_state & HLS_GOING_UP) {
7317                         if (++tries < 1000) {
7318                                 mutex_unlock(&ppd->hls_lock);
7319                                 usleep_range(100, 120); /* arbitrary */
7320                                 goto retry;
7321                         }
7322                         dd_dev_err(ppd->dd,
7323                                    "%s: giving up waiting for link state change\n",
7324                                    __func__);
7325                 }
7326                 goto done;
7327         }
7328
7329         lwde = ppd->link_width_downgrade_enabled;
7330
7331         if (refresh_widths) {
7332                 get_link_widths(ppd->dd, &tx, &rx);
7333                 ppd->link_width_downgrade_tx_active = tx;
7334                 ppd->link_width_downgrade_rx_active = rx;
7335         }
7336
7337         if (lwde == 0) {
7338                 /* downgrade is disabled */
7339
7340                 /* bounce if not at starting active width */
7341                 if ((ppd->link_width_active !=
7342                      ppd->link_width_downgrade_tx_active) ||
7343                     (ppd->link_width_active !=
7344                      ppd->link_width_downgrade_rx_active)) {
7345                         dd_dev_err(ppd->dd,
7346                                    "Link downgrade is disabled and link has downgraded, downing link\n");
7347                         dd_dev_err(ppd->dd,
7348                                    "  original 0x%x, tx active 0x%x, rx active 0x%x\n",
7349                                    ppd->link_width_active,
7350                                    ppd->link_width_downgrade_tx_active,
7351                                    ppd->link_width_downgrade_rx_active);
7352                         do_bounce = 1;
7353                 }
7354         } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 ||
7355                    (lwde & ppd->link_width_downgrade_rx_active) == 0) {
7356                 /* Tx or Rx is outside the enabled policy */
7357                 dd_dev_err(ppd->dd,
7358                            "Link is outside of downgrade allowed, downing link\n");
7359                 dd_dev_err(ppd->dd,
7360                            "  enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7361                            lwde, ppd->link_width_downgrade_tx_active,
7362                            ppd->link_width_downgrade_rx_active);
7363                 do_bounce = 1;
7364         }
7365
7366 done:
7367         mutex_unlock(&ppd->hls_lock);
7368
7369         if (do_bounce) {
7370                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
7371                                      OPA_LINKDOWN_REASON_WIDTH_POLICY);
7372                 set_link_state(ppd, HLS_DN_OFFLINE);
7373                 tune_serdes(ppd);
7374                 start_link(ppd);
7375         }
7376 }
7377
7378 /*
7379  * Handle a link downgrade interrupt from the 8051.
7380  *
7381  * This is a work-queue function outside of the interrupt.
7382  */
7383 void handle_link_downgrade(struct work_struct *work)
7384 {
7385         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7386                                                         link_downgrade_work);
7387
7388         dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7389         apply_link_downgrade_policy(ppd, 1);
7390 }
7391
7392 static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7393 {
7394         return flag_string(buf, buf_len, flags, dcc_err_flags,
7395                 ARRAY_SIZE(dcc_err_flags));
7396 }
7397
7398 static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7399 {
7400         return flag_string(buf, buf_len, flags, lcb_err_flags,
7401                 ARRAY_SIZE(lcb_err_flags));
7402 }
7403
7404 static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7405 {
7406         return flag_string(buf, buf_len, flags, dc8051_err_flags,
7407                 ARRAY_SIZE(dc8051_err_flags));
7408 }
7409
7410 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7411 {
7412         return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7413                 ARRAY_SIZE(dc8051_info_err_flags));
7414 }
7415
7416 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7417 {
7418         return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7419                 ARRAY_SIZE(dc8051_info_host_msg_flags));
7420 }
7421
7422 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7423 {
7424         struct hfi1_pportdata *ppd = dd->pport;
7425         u64 info, err, host_msg;
7426         int queue_link_down = 0;
7427         char buf[96];
7428
7429         /* look at the flags */
7430         if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7431                 /* 8051 information set by firmware */
7432                 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7433                 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7434                 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7435                         & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7436                 host_msg = (info >>
7437                         DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7438                         & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7439
7440                 /*
7441                  * Handle error flags.
7442                  */
7443                 if (err & FAILED_LNI) {
7444                         /*
7445                          * LNI error indications are cleared by the 8051
7446                          * only when starting polling.  Only pay attention
7447                          * to them when in the states that occur during
7448                          * LNI.
7449                          */
7450                         if (ppd->host_link_state
7451                             & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7452                                 queue_link_down = 1;
7453                                 dd_dev_info(dd, "Link error: %s\n",
7454                                             dc8051_info_err_string(buf,
7455                                                                    sizeof(buf),
7456                                                                    err &
7457                                                                    FAILED_LNI));
7458                         }
7459                         err &= ~(u64)FAILED_LNI;
7460                 }
7461                 /* unknown frames can happen durning LNI, just count */
7462                 if (err & UNKNOWN_FRAME) {
7463                         ppd->unknown_frame_count++;
7464                         err &= ~(u64)UNKNOWN_FRAME;
7465                 }
7466                 if (err) {
7467                         /* report remaining errors, but do not do anything */
7468                         dd_dev_err(dd, "8051 info error: %s\n",
7469                                    dc8051_info_err_string(buf, sizeof(buf),
7470                                                           err));
7471                 }
7472
7473                 /*
7474                  * Handle host message flags.
7475                  */
7476                 if (host_msg & HOST_REQ_DONE) {
7477                         /*
7478                          * Presently, the driver does a busy wait for
7479                          * host requests to complete.  This is only an
7480                          * informational message.
7481                          * NOTE: The 8051 clears the host message
7482                          * information *on the next 8051 command*.
7483                          * Therefore, when linkup is achieved,
7484                          * this flag will still be set.
7485                          */
7486                         host_msg &= ~(u64)HOST_REQ_DONE;
7487                 }
7488                 if (host_msg & BC_SMA_MSG) {
7489                         queue_work(ppd->hfi1_wq, &ppd->sma_message_work);
7490                         host_msg &= ~(u64)BC_SMA_MSG;
7491                 }
7492                 if (host_msg & LINKUP_ACHIEVED) {
7493                         dd_dev_info(dd, "8051: Link up\n");
7494                         queue_work(ppd->hfi1_wq, &ppd->link_up_work);
7495                         host_msg &= ~(u64)LINKUP_ACHIEVED;
7496                 }
7497                 if (host_msg & EXT_DEVICE_CFG_REQ) {
7498                         handle_8051_request(ppd);
7499                         host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7500                 }
7501                 if (host_msg & VERIFY_CAP_FRAME) {
7502                         queue_work(ppd->hfi1_wq, &ppd->link_vc_work);
7503                         host_msg &= ~(u64)VERIFY_CAP_FRAME;
7504                 }
7505                 if (host_msg & LINK_GOING_DOWN) {
7506                         const char *extra = "";
7507                         /* no downgrade action needed if going down */
7508                         if (host_msg & LINK_WIDTH_DOWNGRADED) {
7509                                 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7510                                 extra = " (ignoring downgrade)";
7511                         }
7512                         dd_dev_info(dd, "8051: Link down%s\n", extra);
7513                         queue_link_down = 1;
7514                         host_msg &= ~(u64)LINK_GOING_DOWN;
7515                 }
7516                 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7517                         queue_work(ppd->hfi1_wq, &ppd->link_downgrade_work);
7518                         host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7519                 }
7520                 if (host_msg) {
7521                         /* report remaining messages, but do not do anything */
7522                         dd_dev_info(dd, "8051 info host message: %s\n",
7523                                     dc8051_info_host_msg_string(buf,
7524                                                                 sizeof(buf),
7525                                                                 host_msg));
7526                 }
7527
7528                 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7529         }
7530         if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7531                 /*
7532                  * Lost the 8051 heartbeat.  If this happens, we
7533                  * receive constant interrupts about it.  Disable
7534                  * the interrupt after the first.
7535                  */
7536                 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7537                 write_csr(dd, DC_DC8051_ERR_EN,
7538                           read_csr(dd, DC_DC8051_ERR_EN) &
7539                           ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
7540
7541                 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7542         }
7543         if (reg) {
7544                 /* report the error, but do not do anything */
7545                 dd_dev_err(dd, "8051 error: %s\n",
7546                            dc8051_err_string(buf, sizeof(buf), reg));
7547         }
7548
7549         if (queue_link_down) {
7550                 /*
7551                  * if the link is already going down or disabled, do not
7552                  * queue another
7553                  */
7554                 if ((ppd->host_link_state &
7555                     (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
7556                     ppd->link_enabled == 0) {
7557                         dd_dev_info(dd, "%s: not queuing link down\n",
7558                                     __func__);
7559                 } else {
7560                         queue_work(ppd->hfi1_wq, &ppd->link_down_work);
7561                 }
7562         }
7563 }
7564
7565 static const char * const fm_config_txt[] = {
7566 [0] =
7567         "BadHeadDist: Distance violation between two head flits",
7568 [1] =
7569         "BadTailDist: Distance violation between two tail flits",
7570 [2] =
7571         "BadCtrlDist: Distance violation between two credit control flits",
7572 [3] =
7573         "BadCrdAck: Credits return for unsupported VL",
7574 [4] =
7575         "UnsupportedVLMarker: Received VL Marker",
7576 [5] =
7577         "BadPreempt: Exceeded the preemption nesting level",
7578 [6] =
7579         "BadControlFlit: Received unsupported control flit",
7580 /* no 7 */
7581 [8] =
7582         "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7583 };
7584
7585 static const char * const port_rcv_txt[] = {
7586 [1] =
7587         "BadPktLen: Illegal PktLen",
7588 [2] =
7589         "PktLenTooLong: Packet longer than PktLen",
7590 [3] =
7591         "PktLenTooShort: Packet shorter than PktLen",
7592 [4] =
7593         "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7594 [5] =
7595         "BadDLID: Illegal DLID (0, doesn't match HFI)",
7596 [6] =
7597         "BadL2: Illegal L2 opcode",
7598 [7] =
7599         "BadSC: Unsupported SC",
7600 [9] =
7601         "BadRC: Illegal RC",
7602 [11] =
7603         "PreemptError: Preempting with same VL",
7604 [12] =
7605         "PreemptVL15: Preempting a VL15 packet",
7606 };
7607
7608 #define OPA_LDR_FMCONFIG_OFFSET 16
7609 #define OPA_LDR_PORTRCV_OFFSET 0
7610 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7611 {
7612         u64 info, hdr0, hdr1;
7613         const char *extra;
7614         char buf[96];
7615         struct hfi1_pportdata *ppd = dd->pport;
7616         u8 lcl_reason = 0;
7617         int do_bounce = 0;
7618
7619         if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7620                 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7621                         info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7622                         dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7623                         /* set status bit */
7624                         dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7625                 }
7626                 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7627         }
7628
7629         if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7630                 struct hfi1_pportdata *ppd = dd->pport;
7631                 /* this counter saturates at (2^32) - 1 */
7632                 if (ppd->link_downed < (u32)UINT_MAX)
7633                         ppd->link_downed++;
7634                 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7635         }
7636
7637         if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7638                 u8 reason_valid = 1;
7639
7640                 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7641                 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7642                         dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7643                         /* set status bit */
7644                         dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
7645                 }
7646                 switch (info) {
7647                 case 0:
7648                 case 1:
7649                 case 2:
7650                 case 3:
7651                 case 4:
7652                 case 5:
7653                 case 6:
7654                         extra = fm_config_txt[info];
7655                         break;
7656                 case 8:
7657                         extra = fm_config_txt[info];
7658                         if (ppd->port_error_action &
7659                             OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7660                                 do_bounce = 1;
7661                                 /*
7662                                  * lcl_reason cannot be derived from info
7663                                  * for this error
7664                                  */
7665                                 lcl_reason =
7666                                   OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7667                         }
7668                         break;
7669                 default:
7670                         reason_valid = 0;
7671                         snprintf(buf, sizeof(buf), "reserved%lld", info);
7672                         extra = buf;
7673                         break;
7674                 }
7675
7676                 if (reason_valid && !do_bounce) {
7677                         do_bounce = ppd->port_error_action &
7678                                         (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
7679                         lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
7680                 }
7681
7682                 /* just report this */
7683                 dd_dev_info(dd, "DCC Error: fmconfig error: %s\n", extra);
7684                 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
7685         }
7686
7687         if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
7688                 u8 reason_valid = 1;
7689
7690                 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
7691                 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
7692                 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
7693                 if (!(dd->err_info_rcvport.status_and_code &
7694                       OPA_EI_STATUS_SMASK)) {
7695                         dd->err_info_rcvport.status_and_code =
7696                                 info & OPA_EI_CODE_SMASK;
7697                         /* set status bit */
7698                         dd->err_info_rcvport.status_and_code |=
7699                                 OPA_EI_STATUS_SMASK;
7700                         /*
7701                          * save first 2 flits in the packet that caused
7702                          * the error
7703                          */
7704                          dd->err_info_rcvport.packet_flit1 = hdr0;
7705                          dd->err_info_rcvport.packet_flit2 = hdr1;
7706                 }
7707                 switch (info) {
7708                 case 1:
7709                 case 2:
7710                 case 3:
7711                 case 4:
7712                 case 5:
7713                 case 6:
7714                 case 7:
7715                 case 9:
7716                 case 11:
7717                 case 12:
7718                         extra = port_rcv_txt[info];
7719                         break;
7720                 default:
7721                         reason_valid = 0;
7722                         snprintf(buf, sizeof(buf), "reserved%lld", info);
7723                         extra = buf;
7724                         break;
7725                 }
7726
7727                 if (reason_valid && !do_bounce) {
7728                         do_bounce = ppd->port_error_action &
7729                                         (1 << (OPA_LDR_PORTRCV_OFFSET + info));
7730                         lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
7731                 }
7732
7733                 /* just report this */
7734                 dd_dev_info(dd, "DCC Error: PortRcv error: %s\n", extra);
7735                 dd_dev_info(dd, "           hdr0 0x%llx, hdr1 0x%llx\n",
7736                             hdr0, hdr1);
7737
7738                 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
7739         }
7740
7741         if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
7742                 /* informative only */
7743                 dd_dev_info(dd, "8051 access to LCB blocked\n");
7744                 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
7745         }
7746         if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
7747                 /* informative only */
7748                 dd_dev_info(dd, "host access to LCB blocked\n");
7749                 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
7750         }
7751
7752         /* report any remaining errors */
7753         if (reg)
7754                 dd_dev_info(dd, "DCC Error: %s\n",
7755                             dcc_err_string(buf, sizeof(buf), reg));
7756
7757         if (lcl_reason == 0)
7758                 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
7759
7760         if (do_bounce) {
7761                 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
7762                 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
7763                 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
7764         }
7765 }
7766
7767 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7768 {
7769         char buf[96];
7770
7771         dd_dev_info(dd, "LCB Error: %s\n",
7772                     lcb_err_string(buf, sizeof(buf), reg));
7773 }
7774
7775 /*
7776  * CCE block DC interrupt.  Source is < 8.
7777  */
7778 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
7779 {
7780         const struct err_reg_info *eri = &dc_errs[source];
7781
7782         if (eri->handler) {
7783                 interrupt_clear_down(dd, 0, eri);
7784         } else if (source == 3 /* dc_lbm_int */) {
7785                 /*
7786                  * This indicates that a parity error has occurred on the
7787                  * address/control lines presented to the LBM.  The error
7788                  * is a single pulse, there is no associated error flag,
7789                  * and it is non-maskable.  This is because if a parity
7790                  * error occurs on the request the request is dropped.
7791                  * This should never occur, but it is nice to know if it
7792                  * ever does.
7793                  */
7794                 dd_dev_err(dd, "Parity error in DC LBM block\n");
7795         } else {
7796                 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
7797         }
7798 }
7799
7800 /*
7801  * TX block send credit interrupt.  Source is < 160.
7802  */
7803 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
7804 {
7805         sc_group_release_update(dd, source);
7806 }
7807
7808 /*
7809  * TX block SDMA interrupt.  Source is < 48.
7810  *
7811  * SDMA interrupts are grouped by type:
7812  *
7813  *       0 -  N-1 = SDma
7814  *       N - 2N-1 = SDmaProgress
7815  *      2N - 3N-1 = SDmaIdle
7816  */
7817 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
7818 {
7819         /* what interrupt */
7820         unsigned int what  = source / TXE_NUM_SDMA_ENGINES;
7821         /* which engine */
7822         unsigned int which = source % TXE_NUM_SDMA_ENGINES;
7823
7824 #ifdef CONFIG_SDMA_VERBOSITY
7825         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
7826                    slashstrip(__FILE__), __LINE__, __func__);
7827         sdma_dumpstate(&dd->per_sdma[which]);
7828 #endif
7829
7830         if (likely(what < 3 && which < dd->num_sdma)) {
7831                 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
7832         } else {
7833                 /* should not happen */
7834                 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
7835         }
7836 }
7837
7838 /*
7839  * RX block receive available interrupt.  Source is < 160.
7840  */
7841 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
7842 {
7843         struct hfi1_ctxtdata *rcd;
7844         char *err_detail;
7845
7846         if (likely(source < dd->num_rcv_contexts)) {
7847                 rcd = dd->rcd[source];
7848                 if (rcd) {
7849                         if (source < dd->first_user_ctxt)
7850                                 rcd->do_interrupt(rcd, 0);
7851                         else
7852                                 handle_user_interrupt(rcd);
7853                         return; /* OK */
7854                 }
7855                 /* received an interrupt, but no rcd */
7856                 err_detail = "dataless";
7857         } else {
7858                 /* received an interrupt, but are not using that context */
7859                 err_detail = "out of range";
7860         }
7861         dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
7862                    err_detail, source);
7863 }
7864
7865 /*
7866  * RX block receive urgent interrupt.  Source is < 160.
7867  */
7868 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
7869 {
7870         struct hfi1_ctxtdata *rcd;
7871         char *err_detail;
7872
7873         if (likely(source < dd->num_rcv_contexts)) {
7874                 rcd = dd->rcd[source];
7875                 if (rcd) {
7876                         /* only pay attention to user urgent interrupts */
7877                         if (source >= dd->first_user_ctxt)
7878                                 handle_user_interrupt(rcd);
7879                         return; /* OK */
7880                 }
7881                 /* received an interrupt, but no rcd */
7882                 err_detail = "dataless";
7883         } else {
7884                 /* received an interrupt, but are not using that context */
7885                 err_detail = "out of range";
7886         }
7887         dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
7888                    err_detail, source);
7889 }
7890
7891 /*
7892  * Reserved range interrupt.  Should not be called in normal operation.
7893  */
7894 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
7895 {
7896         char name[64];
7897
7898         dd_dev_err(dd, "unexpected %s interrupt\n",
7899                    is_reserved_name(name, sizeof(name), source));
7900 }
7901
7902 static const struct is_table is_table[] = {
7903 /*
7904  * start                 end
7905  *                              name func               interrupt func
7906  */
7907 { IS_GENERAL_ERR_START,  IS_GENERAL_ERR_END,
7908                                 is_misc_err_name,       is_misc_err_int },
7909 { IS_SDMAENG_ERR_START,  IS_SDMAENG_ERR_END,
7910                                 is_sdma_eng_err_name,   is_sdma_eng_err_int },
7911 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
7912                                 is_sendctxt_err_name,   is_sendctxt_err_int },
7913 { IS_SDMA_START,             IS_SDMA_END,
7914                                 is_sdma_eng_name,       is_sdma_eng_int },
7915 { IS_VARIOUS_START,          IS_VARIOUS_END,
7916                                 is_various_name,        is_various_int },
7917 { IS_DC_START,       IS_DC_END,
7918                                 is_dc_name,             is_dc_int },
7919 { IS_RCVAVAIL_START,     IS_RCVAVAIL_END,
7920                                 is_rcv_avail_name,      is_rcv_avail_int },
7921 { IS_RCVURGENT_START,    IS_RCVURGENT_END,
7922                                 is_rcv_urgent_name,     is_rcv_urgent_int },
7923 { IS_SENDCREDIT_START,   IS_SENDCREDIT_END,
7924                                 is_send_credit_name,    is_send_credit_int},
7925 { IS_RESERVED_START,     IS_RESERVED_END,
7926                                 is_reserved_name,       is_reserved_int},
7927 };
7928
7929 /*
7930  * Interrupt source interrupt - called when the given source has an interrupt.
7931  * Source is a bit index into an array of 64-bit integers.
7932  */
7933 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
7934 {
7935         const struct is_table *entry;
7936
7937         /* avoids a double compare by walking the table in-order */
7938         for (entry = &is_table[0]; entry->is_name; entry++) {
7939                 if (source < entry->end) {
7940                         trace_hfi1_interrupt(dd, entry, source);
7941                         entry->is_int(dd, source - entry->start);
7942                         return;
7943                 }
7944         }
7945         /* fell off the end */
7946         dd_dev_err(dd, "invalid interrupt source %u\n", source);
7947 }
7948
7949 /*
7950  * General interrupt handler.  This is able to correctly handle
7951  * all interrupts in case INTx is used.
7952  */
7953 static irqreturn_t general_interrupt(int irq, void *data)
7954 {
7955         struct hfi1_devdata *dd = data;
7956         u64 regs[CCE_NUM_INT_CSRS];
7957         u32 bit;
7958         int i;
7959
7960         this_cpu_inc(*dd->int_counter);
7961
7962         /* phase 1: scan and clear all handled interrupts */
7963         for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
7964                 if (dd->gi_mask[i] == 0) {
7965                         regs[i] = 0;    /* used later */
7966                         continue;
7967                 }
7968                 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
7969                                 dd->gi_mask[i];
7970                 /* only clear if anything is set */
7971                 if (regs[i])
7972                         write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
7973         }
7974
7975         /* phase 2: call the appropriate handler */
7976         for_each_set_bit(bit, (unsigned long *)&regs[0],
7977                          CCE_NUM_INT_CSRS * 64) {
7978                 is_interrupt(dd, bit);
7979         }
7980
7981         return IRQ_HANDLED;
7982 }
7983
7984 static irqreturn_t sdma_interrupt(int irq, void *data)
7985 {
7986         struct sdma_engine *sde = data;
7987         struct hfi1_devdata *dd = sde->dd;
7988         u64 status;
7989
7990 #ifdef CONFIG_SDMA_VERBOSITY
7991         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
7992                    slashstrip(__FILE__), __LINE__, __func__);
7993         sdma_dumpstate(sde);
7994 #endif
7995
7996         this_cpu_inc(*dd->int_counter);
7997
7998         /* This read_csr is really bad in the hot path */
7999         status = read_csr(dd,
8000                           CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
8001                           & sde->imask;
8002         if (likely(status)) {
8003                 /* clear the interrupt(s) */
8004                 write_csr(dd,
8005                           CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
8006                           status);
8007
8008                 /* handle the interrupt(s) */
8009                 sdma_engine_interrupt(sde, status);
8010         } else
8011                 dd_dev_err(dd, "SDMA engine %u interrupt, but no status bits set\n",
8012                            sde->this_idx);
8013
8014         return IRQ_HANDLED;
8015 }
8016
8017 /*
8018  * Clear the receive interrupt.  Use a read of the interrupt clear CSR
8019  * to insure that the write completed.  This does NOT guarantee that
8020  * queued DMA writes to memory from the chip are pushed.
8021  */
8022 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8023 {
8024         struct hfi1_devdata *dd = rcd->dd;
8025         u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8026
8027         mmiowb();       /* make sure everything before is written */
8028         write_csr(dd, addr, rcd->imask);
8029         /* force the above write on the chip and get a value back */
8030         (void)read_csr(dd, addr);
8031 }
8032
8033 /* force the receive interrupt */
8034 void force_recv_intr(struct hfi1_ctxtdata *rcd)
8035 {
8036         write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8037 }
8038
8039 /*
8040  * Return non-zero if a packet is present.
8041  *
8042  * This routine is called when rechecking for packets after the RcvAvail
8043  * interrupt has been cleared down.  First, do a quick check of memory for
8044  * a packet present.  If not found, use an expensive CSR read of the context
8045  * tail to determine the actual tail.  The CSR read is necessary because there
8046  * is no method to push pending DMAs to memory other than an interrupt and we
8047  * are trying to determine if we need to force an interrupt.
8048  */
8049 static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8050 {
8051         u32 tail;
8052         int present;
8053
8054         if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
8055                 present = (rcd->seq_cnt ==
8056                                 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
8057         else /* is RDMA rtail */
8058                 present = (rcd->head != get_rcvhdrtail(rcd));
8059
8060         if (present)
8061                 return 1;
8062
8063         /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8064         tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8065         return rcd->head != tail;
8066 }
8067
8068 /*
8069  * Receive packet IRQ handler.  This routine expects to be on its own IRQ.
8070  * This routine will try to handle packets immediately (latency), but if
8071  * it finds too many, it will invoke the thread handler (bandwitdh).  The
8072  * chip receive interrupt is *not* cleared down until this or the thread (if
8073  * invoked) is finished.  The intent is to avoid extra interrupts while we
8074  * are processing packets anyway.
8075  */
8076 static irqreturn_t receive_context_interrupt(int irq, void *data)
8077 {
8078         struct hfi1_ctxtdata *rcd = data;
8079         struct hfi1_devdata *dd = rcd->dd;
8080         int disposition;
8081         int present;
8082
8083         trace_hfi1_receive_interrupt(dd, rcd->ctxt);
8084         this_cpu_inc(*dd->int_counter);
8085         aspm_ctx_disable(rcd);
8086
8087         /* receive interrupt remains blocked while processing packets */
8088         disposition = rcd->do_interrupt(rcd, 0);
8089
8090         /*
8091          * Too many packets were seen while processing packets in this
8092          * IRQ handler.  Invoke the handler thread.  The receive interrupt
8093          * remains blocked.
8094          */
8095         if (disposition == RCV_PKT_LIMIT)
8096                 return IRQ_WAKE_THREAD;
8097
8098         /*
8099          * The packet processor detected no more packets.  Clear the receive
8100          * interrupt and recheck for a packet packet that may have arrived
8101          * after the previous check and interrupt clear.  If a packet arrived,
8102          * force another interrupt.
8103          */
8104         clear_recv_intr(rcd);
8105         present = check_packet_present(rcd);
8106         if (present)
8107                 force_recv_intr(rcd);
8108
8109         return IRQ_HANDLED;
8110 }
8111
8112 /*
8113  * Receive packet thread handler.  This expects to be invoked with the
8114  * receive interrupt still blocked.
8115  */
8116 static irqreturn_t receive_context_thread(int irq, void *data)
8117 {
8118         struct hfi1_ctxtdata *rcd = data;
8119         int present;
8120
8121         /* receive interrupt is still blocked from the IRQ handler */
8122         (void)rcd->do_interrupt(rcd, 1);
8123
8124         /*
8125          * The packet processor will only return if it detected no more
8126          * packets.  Hold IRQs here so we can safely clear the interrupt and
8127          * recheck for a packet that may have arrived after the previous
8128          * check and the interrupt clear.  If a packet arrived, force another
8129          * interrupt.
8130          */
8131         local_irq_disable();
8132         clear_recv_intr(rcd);
8133         present = check_packet_present(rcd);
8134         if (present)
8135                 force_recv_intr(rcd);
8136         local_irq_enable();
8137
8138         return IRQ_HANDLED;
8139 }
8140
8141 /* ========================================================================= */
8142
8143 u32 read_physical_state(struct hfi1_devdata *dd)
8144 {
8145         u64 reg;
8146
8147         reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8148         return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8149                                 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8150 }
8151
8152 u32 read_logical_state(struct hfi1_devdata *dd)
8153 {
8154         u64 reg;
8155
8156         reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8157         return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8158                                 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8159 }
8160
8161 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8162 {
8163         u64 reg;
8164
8165         reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8166         /* clear current state, set new state */
8167         reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8168         reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8169         write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8170 }
8171
8172 /*
8173  * Use the 8051 to read a LCB CSR.
8174  */
8175 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8176 {
8177         u32 regno;
8178         int ret;
8179
8180         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8181                 if (acquire_lcb_access(dd, 0) == 0) {
8182                         *data = read_csr(dd, addr);
8183                         release_lcb_access(dd, 0);
8184                         return 0;
8185                 }
8186                 return -EBUSY;
8187         }
8188
8189         /* register is an index of LCB registers: (offset - base) / 8 */
8190         regno = (addr - DC_LCB_CFG_RUN) >> 3;
8191         ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8192         if (ret != HCMD_SUCCESS)
8193                 return -EBUSY;
8194         return 0;
8195 }
8196
8197 /*
8198  * Read an LCB CSR.  Access may not be in host control, so check.
8199  * Return 0 on success, -EBUSY on failure.
8200  */
8201 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8202 {
8203         struct hfi1_pportdata *ppd = dd->pport;
8204
8205         /* if up, go through the 8051 for the value */
8206         if (ppd->host_link_state & HLS_UP)
8207                 return read_lcb_via_8051(dd, addr, data);
8208         /* if going up or down, no access */
8209         if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8210                 return -EBUSY;
8211         /* otherwise, host has access */
8212         *data = read_csr(dd, addr);
8213         return 0;
8214 }
8215
8216 /*
8217  * Use the 8051 to write a LCB CSR.
8218  */
8219 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8220 {
8221         u32 regno;
8222         int ret;
8223
8224         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
8225             (dd->dc8051_ver < dc8051_ver(0, 20))) {
8226                 if (acquire_lcb_access(dd, 0) == 0) {
8227                         write_csr(dd, addr, data);
8228                         release_lcb_access(dd, 0);
8229                         return 0;
8230                 }
8231                 return -EBUSY;
8232         }
8233
8234         /* register is an index of LCB registers: (offset - base) / 8 */
8235         regno = (addr - DC_LCB_CFG_RUN) >> 3;
8236         ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8237         if (ret != HCMD_SUCCESS)
8238                 return -EBUSY;
8239         return 0;
8240 }
8241
8242 /*
8243  * Write an LCB CSR.  Access may not be in host control, so check.
8244  * Return 0 on success, -EBUSY on failure.
8245  */
8246 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8247 {
8248         struct hfi1_pportdata *ppd = dd->pport;
8249
8250         /* if up, go through the 8051 for the value */
8251         if (ppd->host_link_state & HLS_UP)
8252                 return write_lcb_via_8051(dd, addr, data);
8253         /* if going up or down, no access */
8254         if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8255                 return -EBUSY;
8256         /* otherwise, host has access */
8257         write_csr(dd, addr, data);
8258         return 0;
8259 }
8260
8261 /*
8262  * Returns:
8263  *      < 0 = Linux error, not able to get access
8264  *      > 0 = 8051 command RETURN_CODE
8265  */
8266 static int do_8051_command(
8267         struct hfi1_devdata *dd,
8268         u32 type,
8269         u64 in_data,
8270         u64 *out_data)
8271 {
8272         u64 reg, completed;
8273         int return_code;
8274         unsigned long flags;
8275         unsigned long timeout;
8276
8277         hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8278
8279         /*
8280          * Alternative to holding the lock for a long time:
8281          * - keep busy wait - have other users bounce off
8282          */
8283         spin_lock_irqsave(&dd->dc8051_lock, flags);
8284
8285         /* We can't send any commands to the 8051 if it's in reset */
8286         if (dd->dc_shutdown) {
8287                 return_code = -ENODEV;
8288                 goto fail;
8289         }
8290
8291         /*
8292          * If an 8051 host command timed out previously, then the 8051 is
8293          * stuck.
8294          *
8295          * On first timeout, attempt to reset and restart the entire DC
8296          * block (including 8051). (Is this too big of a hammer?)
8297          *
8298          * If the 8051 times out a second time, the reset did not bring it
8299          * back to healthy life. In that case, fail any subsequent commands.
8300          */
8301         if (dd->dc8051_timed_out) {
8302                 if (dd->dc8051_timed_out > 1) {
8303                         dd_dev_err(dd,
8304                                    "Previous 8051 host command timed out, skipping command %u\n",
8305                                    type);
8306                         return_code = -ENXIO;
8307                         goto fail;
8308                 }
8309                 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8310                 dc_shutdown(dd);
8311                 dc_start(dd);
8312                 spin_lock_irqsave(&dd->dc8051_lock, flags);
8313         }
8314
8315         /*
8316          * If there is no timeout, then the 8051 command interface is
8317          * waiting for a command.
8318          */
8319
8320         /*
8321          * When writing a LCB CSR, out_data contains the full value to
8322          * to be written, while in_data contains the relative LCB
8323          * address in 7:0.  Do the work here, rather than the caller,
8324          * of distrubting the write data to where it needs to go:
8325          *
8326          * Write data
8327          *   39:00 -> in_data[47:8]
8328          *   47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8329          *   63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8330          */
8331         if (type == HCMD_WRITE_LCB_CSR) {
8332                 in_data |= ((*out_data) & 0xffffffffffull) << 8;
8333                 reg = ((((*out_data) >> 40) & 0xff) <<
8334                                 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8335                       | ((((*out_data) >> 48) & 0xffff) <<
8336                                 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8337                 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8338         }
8339
8340         /*
8341          * Do two writes: the first to stabilize the type and req_data, the
8342          * second to activate.
8343          */
8344         reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8345                         << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8346                 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8347                         << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8348         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8349         reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8350         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8351
8352         /* wait for completion, alternate: interrupt */
8353         timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8354         while (1) {
8355                 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8356                 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8357                 if (completed)
8358                         break;
8359                 if (time_after(jiffies, timeout)) {
8360                         dd->dc8051_timed_out++;
8361                         dd_dev_err(dd, "8051 host command %u timeout\n", type);
8362                         if (out_data)
8363                                 *out_data = 0;
8364                         return_code = -ETIMEDOUT;
8365                         goto fail;
8366                 }
8367                 udelay(2);
8368         }
8369
8370         if (out_data) {
8371                 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8372                                 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8373                 if (type == HCMD_READ_LCB_CSR) {
8374                         /* top 16 bits are in a different register */
8375                         *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8376                                 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8377                                 << (48
8378                                     - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8379                 }
8380         }
8381         return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8382                                 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8383         dd->dc8051_timed_out = 0;
8384         /*
8385          * Clear command for next user.
8386          */
8387         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8388
8389 fail:
8390         spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8391
8392         return return_code;
8393 }
8394
8395 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8396 {
8397         return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8398 }
8399
8400 int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8401                      u8 lane_id, u32 config_data)
8402 {
8403         u64 data;
8404         int ret;
8405
8406         data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8407                 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8408                 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8409         ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8410         if (ret != HCMD_SUCCESS) {
8411                 dd_dev_err(dd,
8412                            "load 8051 config: field id %d, lane %d, err %d\n",
8413                            (int)field_id, (int)lane_id, ret);
8414         }
8415         return ret;
8416 }
8417
8418 /*
8419  * Read the 8051 firmware "registers".  Use the RAM directly.  Always
8420  * set the result, even on error.
8421  * Return 0 on success, -errno on failure
8422  */
8423 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8424                      u32 *result)
8425 {
8426         u64 big_data;
8427         u32 addr;
8428         int ret;
8429
8430         /* address start depends on the lane_id */
8431         if (lane_id < 4)
8432                 addr = (4 * NUM_GENERAL_FIELDS)
8433                         + (lane_id * 4 * NUM_LANE_FIELDS);
8434         else
8435                 addr = 0;
8436         addr += field_id * 4;
8437
8438         /* read is in 8-byte chunks, hardware will truncate the address down */
8439         ret = read_8051_data(dd, addr, 8, &big_data);
8440
8441         if (ret == 0) {
8442                 /* extract the 4 bytes we want */
8443                 if (addr & 0x4)
8444                         *result = (u32)(big_data >> 32);
8445                 else
8446                         *result = (u32)big_data;
8447         } else {
8448                 *result = 0;
8449                 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
8450                            __func__, lane_id, field_id);
8451         }
8452
8453         return ret;
8454 }
8455
8456 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8457                               u8 continuous)
8458 {
8459         u32 frame;
8460
8461         frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8462                 | power_management << POWER_MANAGEMENT_SHIFT;
8463         return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8464                                 GENERAL_CONFIG, frame);
8465 }
8466
8467 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8468                                  u16 vl15buf, u8 crc_sizes)
8469 {
8470         u32 frame;
8471
8472         frame = (u32)vau << VAU_SHIFT
8473                 | (u32)z << Z_SHIFT
8474                 | (u32)vcu << VCU_SHIFT
8475                 | (u32)vl15buf << VL15BUF_SHIFT
8476                 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8477         return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8478                                 GENERAL_CONFIG, frame);
8479 }
8480
8481 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
8482                                      u8 *flag_bits, u16 *link_widths)
8483 {
8484         u32 frame;
8485
8486         read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8487                          &frame);
8488         *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8489         *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8490         *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8491 }
8492
8493 static int write_vc_local_link_width(struct hfi1_devdata *dd,
8494                                      u8 misc_bits,
8495                                      u8 flag_bits,
8496                                      u16 link_widths)
8497 {
8498         u32 frame;
8499
8500         frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8501                 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8502                 | (u32)link_widths << LINK_WIDTH_SHIFT;
8503         return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8504                      frame);
8505 }
8506
8507 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8508                                  u8 device_rev)
8509 {
8510         u32 frame;
8511
8512         frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8513                 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8514         return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8515 }
8516
8517 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8518                                   u8 *device_rev)
8519 {
8520         u32 frame;
8521
8522         read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
8523         *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
8524         *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
8525                         & REMOTE_DEVICE_REV_MASK;
8526 }
8527
8528 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_a, u8 *ver_b)
8529 {
8530         u32 frame;
8531
8532         read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
8533         *ver_a = (frame >> STS_FM_VERSION_A_SHIFT) & STS_FM_VERSION_A_MASK;
8534         *ver_b = (frame >> STS_FM_VERSION_B_SHIFT) & STS_FM_VERSION_B_MASK;
8535 }
8536
8537 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
8538                                u8 *continuous)
8539 {
8540         u32 frame;
8541
8542         read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
8543         *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
8544                                         & POWER_MANAGEMENT_MASK;
8545         *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
8546                                         & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
8547 }
8548
8549 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
8550                                   u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
8551 {
8552         u32 frame;
8553
8554         read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
8555         *vau = (frame >> VAU_SHIFT) & VAU_MASK;
8556         *z = (frame >> Z_SHIFT) & Z_MASK;
8557         *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
8558         *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
8559         *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
8560 }
8561
8562 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
8563                                       u8 *remote_tx_rate,
8564                                       u16 *link_widths)
8565 {
8566         u32 frame;
8567
8568         read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
8569                          &frame);
8570         *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
8571                                 & REMOTE_TX_RATE_MASK;
8572         *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8573 }
8574
8575 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8576 {
8577         u32 frame;
8578
8579         read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
8580         *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8581 }
8582
8583 static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed)
8584 {
8585         u32 frame;
8586
8587         read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
8588         *mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT) & MGMT_ALLOWED_MASK;
8589 }
8590
8591 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8592 {
8593         read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
8594 }
8595
8596 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
8597 {
8598         read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
8599 }
8600
8601 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
8602 {
8603         u32 frame;
8604         int ret;
8605
8606         *link_quality = 0;
8607         if (dd->pport->host_link_state & HLS_UP) {
8608                 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
8609                                        &frame);
8610                 if (ret == 0)
8611                         *link_quality = (frame >> LINK_QUALITY_SHIFT)
8612                                                 & LINK_QUALITY_MASK;
8613         }
8614 }
8615
8616 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
8617 {
8618         u32 frame;
8619
8620         read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
8621         *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
8622 }
8623
8624 static int read_tx_settings(struct hfi1_devdata *dd,
8625                             u8 *enable_lane_tx,
8626                             u8 *tx_polarity_inversion,
8627                             u8 *rx_polarity_inversion,
8628                             u8 *max_rate)
8629 {
8630         u32 frame;
8631         int ret;
8632
8633         ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
8634         *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
8635                                 & ENABLE_LANE_TX_MASK;
8636         *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
8637                                 & TX_POLARITY_INVERSION_MASK;
8638         *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
8639                                 & RX_POLARITY_INVERSION_MASK;
8640         *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
8641         return ret;
8642 }
8643
8644 static int write_tx_settings(struct hfi1_devdata *dd,
8645                              u8 enable_lane_tx,
8646                              u8 tx_polarity_inversion,
8647                              u8 rx_polarity_inversion,
8648                              u8 max_rate)
8649 {
8650         u32 frame;
8651
8652         /* no need to mask, all variable sizes match field widths */
8653         frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
8654                 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
8655                 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
8656                 | max_rate << MAX_RATE_SHIFT;
8657         return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
8658 }
8659
8660 static void check_fabric_firmware_versions(struct hfi1_devdata *dd)
8661 {
8662         u32 frame, version, prod_id;
8663         int ret, lane;
8664
8665         /* 4 lanes */
8666         for (lane = 0; lane < 4; lane++) {
8667                 ret = read_8051_config(dd, SPICO_FW_VERSION, lane, &frame);
8668                 if (ret) {
8669                         dd_dev_err(dd,
8670                                    "Unable to read lane %d firmware details\n",
8671                                    lane);
8672                         continue;
8673                 }
8674                 version = (frame >> SPICO_ROM_VERSION_SHIFT)
8675                                         & SPICO_ROM_VERSION_MASK;
8676                 prod_id = (frame >> SPICO_ROM_PROD_ID_SHIFT)
8677                                         & SPICO_ROM_PROD_ID_MASK;
8678                 dd_dev_info(dd,
8679                             "Lane %d firmware: version 0x%04x, prod_id 0x%04x\n",
8680                             lane, version, prod_id);
8681         }
8682 }
8683
8684 /*
8685  * Read an idle LCB message.
8686  *
8687  * Returns 0 on success, -EINVAL on error
8688  */
8689 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
8690 {
8691         int ret;
8692
8693         ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out);
8694         if (ret != HCMD_SUCCESS) {
8695                 dd_dev_err(dd, "read idle message: type %d, err %d\n",
8696                            (u32)type, ret);
8697                 return -EINVAL;
8698         }
8699         dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
8700         /* return only the payload as we already know the type */
8701         *data_out >>= IDLE_PAYLOAD_SHIFT;
8702         return 0;
8703 }
8704
8705 /*
8706  * Read an idle SMA message.  To be done in response to a notification from
8707  * the 8051.
8708  *
8709  * Returns 0 on success, -EINVAL on error
8710  */
8711 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
8712 {
8713         return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT,
8714                                  data);
8715 }
8716
8717 /*
8718  * Send an idle LCB message.
8719  *
8720  * Returns 0 on success, -EINVAL on error
8721  */
8722 static int send_idle_message(struct hfi1_devdata *dd, u64 data)
8723 {
8724         int ret;
8725
8726         dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
8727         ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
8728         if (ret != HCMD_SUCCESS) {
8729                 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
8730                            data, ret);
8731                 return -EINVAL;
8732         }
8733         return 0;
8734 }
8735
8736 /*
8737  * Send an idle SMA message.
8738  *
8739  * Returns 0 on success, -EINVAL on error
8740  */
8741 int send_idle_sma(struct hfi1_devdata *dd, u64 message)
8742 {
8743         u64 data;
8744
8745         data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) |
8746                 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
8747         return send_idle_message(dd, data);
8748 }
8749
8750 /*
8751  * Initialize the LCB then do a quick link up.  This may or may not be
8752  * in loopback.
8753  *
8754  * return 0 on success, -errno on error
8755  */
8756 static int do_quick_linkup(struct hfi1_devdata *dd)
8757 {
8758         u64 reg;
8759         unsigned long timeout;
8760         int ret;
8761
8762         lcb_shutdown(dd, 0);
8763
8764         if (loopback) {
8765                 /* LCB_CFG_LOOPBACK.VAL = 2 */
8766                 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
8767                 write_csr(dd, DC_LCB_CFG_LOOPBACK,
8768                           IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
8769                 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
8770         }
8771
8772         /* start the LCBs */
8773         /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
8774         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
8775
8776         /* simulator only loopback steps */
8777         if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8778                 /* LCB_CFG_RUN.EN = 1 */
8779                 write_csr(dd, DC_LCB_CFG_RUN,
8780                           1ull << DC_LCB_CFG_RUN_EN_SHIFT);
8781
8782                 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
8783                 timeout = jiffies + msecs_to_jiffies(10);
8784                 while (1) {
8785                         reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
8786                         if (reg)
8787                                 break;
8788                         if (time_after(jiffies, timeout)) {
8789                                 dd_dev_err(dd,
8790                                            "timeout waiting for LINK_TRANSFER_ACTIVE\n");
8791                                 return -ETIMEDOUT;
8792                         }
8793                         udelay(2);
8794                 }
8795
8796                 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
8797                           1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
8798         }
8799
8800         if (!loopback) {
8801                 /*
8802                  * When doing quick linkup and not in loopback, both
8803                  * sides must be done with LCB set-up before either
8804                  * starts the quick linkup.  Put a delay here so that
8805                  * both sides can be started and have a chance to be
8806                  * done with LCB set up before resuming.
8807                  */
8808                 dd_dev_err(dd,
8809                            "Pausing for peer to be finished with LCB set up\n");
8810                 msleep(5000);
8811                 dd_dev_err(dd, "Continuing with quick linkup\n");
8812         }
8813
8814         write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
8815         set_8051_lcb_access(dd);
8816
8817         /*
8818          * State "quick" LinkUp request sets the physical link state to
8819          * LinkUp without a verify capability sequence.
8820          * This state is in simulator v37 and later.
8821          */
8822         ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
8823         if (ret != HCMD_SUCCESS) {
8824                 dd_dev_err(dd,
8825                            "%s: set physical link state to quick LinkUp failed with return %d\n",
8826                            __func__, ret);
8827
8828                 set_host_lcb_access(dd);
8829                 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
8830
8831                 if (ret >= 0)
8832                         ret = -EINVAL;
8833                 return ret;
8834         }
8835
8836         return 0; /* success */
8837 }
8838
8839 /*
8840  * Set the SerDes to internal loopback mode.
8841  * Returns 0 on success, -errno on error.
8842  */
8843 static int set_serdes_loopback_mode(struct hfi1_devdata *dd)
8844 {
8845         int ret;
8846
8847         ret = set_physical_link_state(dd, PLS_INTERNAL_SERDES_LOOPBACK);
8848         if (ret == HCMD_SUCCESS)
8849                 return 0;
8850         dd_dev_err(dd,
8851                    "Set physical link state to SerDes Loopback failed with return %d\n",
8852                    ret);
8853         if (ret >= 0)
8854                 ret = -EINVAL;
8855         return ret;
8856 }
8857
8858 /*
8859  * Do all special steps to set up loopback.
8860  */
8861 static int init_loopback(struct hfi1_devdata *dd)
8862 {
8863         dd_dev_info(dd, "Entering loopback mode\n");
8864
8865         /* all loopbacks should disable self GUID check */
8866         write_csr(dd, DC_DC8051_CFG_MODE,
8867                   (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
8868
8869         /*
8870          * The simulator has only one loopback option - LCB.  Switch
8871          * to that option, which includes quick link up.
8872          *
8873          * Accept all valid loopback values.
8874          */
8875         if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) &&
8876             (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB ||
8877              loopback == LOOPBACK_CABLE)) {
8878                 loopback = LOOPBACK_LCB;
8879                 quick_linkup = 1;
8880                 return 0;
8881         }
8882
8883         /* handle serdes loopback */
8884         if (loopback == LOOPBACK_SERDES) {
8885                 /* internal serdes loopack needs quick linkup on RTL */
8886                 if (dd->icode == ICODE_RTL_SILICON)
8887                         quick_linkup = 1;
8888                 return set_serdes_loopback_mode(dd);
8889         }
8890
8891         /* LCB loopback - handled at poll time */
8892         if (loopback == LOOPBACK_LCB) {
8893                 quick_linkup = 1; /* LCB is always quick linkup */
8894
8895                 /* not supported in emulation due to emulation RTL changes */
8896                 if (dd->icode == ICODE_FPGA_EMULATION) {
8897                         dd_dev_err(dd,
8898                                    "LCB loopback not supported in emulation\n");
8899                         return -EINVAL;
8900                 }
8901                 return 0;
8902         }
8903
8904         /* external cable loopback requires no extra steps */
8905         if (loopback == LOOPBACK_CABLE)
8906                 return 0;
8907
8908         dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
8909         return -EINVAL;
8910 }
8911
8912 /*
8913  * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
8914  * used in the Verify Capability link width attribute.
8915  */
8916 static u16 opa_to_vc_link_widths(u16 opa_widths)
8917 {
8918         int i;
8919         u16 result = 0;
8920
8921         static const struct link_bits {
8922                 u16 from;
8923                 u16 to;
8924         } opa_link_xlate[] = {
8925                 { OPA_LINK_WIDTH_1X, 1 << (1 - 1)  },
8926                 { OPA_LINK_WIDTH_2X, 1 << (2 - 1)  },
8927                 { OPA_LINK_WIDTH_3X, 1 << (3 - 1)  },
8928                 { OPA_LINK_WIDTH_4X, 1 << (4 - 1)  },
8929         };
8930
8931         for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
8932                 if (opa_widths & opa_link_xlate[i].from)
8933                         result |= opa_link_xlate[i].to;
8934         }
8935         return result;
8936 }
8937
8938 /*
8939  * Set link attributes before moving to polling.
8940  */
8941 static int set_local_link_attributes(struct hfi1_pportdata *ppd)
8942 {
8943         struct hfi1_devdata *dd = ppd->dd;
8944         u8 enable_lane_tx;
8945         u8 tx_polarity_inversion;
8946         u8 rx_polarity_inversion;
8947         int ret;
8948
8949         /* reset our fabric serdes to clear any lingering problems */
8950         fabric_serdes_reset(dd);
8951
8952         /* set the local tx rate - need to read-modify-write */
8953         ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
8954                                &rx_polarity_inversion, &ppd->local_tx_rate);
8955         if (ret)
8956                 goto set_local_link_attributes_fail;
8957
8958         if (dd->dc8051_ver < dc8051_ver(0, 20)) {
8959                 /* set the tx rate to the fastest enabled */
8960                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
8961                         ppd->local_tx_rate = 1;
8962                 else
8963                         ppd->local_tx_rate = 0;
8964         } else {
8965                 /* set the tx rate to all enabled */
8966                 ppd->local_tx_rate = 0;
8967                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
8968                         ppd->local_tx_rate |= 2;
8969                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
8970                         ppd->local_tx_rate |= 1;
8971         }
8972
8973         enable_lane_tx = 0xF; /* enable all four lanes */
8974         ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
8975                                 rx_polarity_inversion, ppd->local_tx_rate);
8976         if (ret != HCMD_SUCCESS)
8977                 goto set_local_link_attributes_fail;
8978
8979         /*
8980          * DC supports continuous updates.
8981          */
8982         ret = write_vc_local_phy(dd,
8983                                  0 /* no power management */,
8984                                  1 /* continuous updates */);
8985         if (ret != HCMD_SUCCESS)
8986                 goto set_local_link_attributes_fail;
8987
8988         /* z=1 in the next call: AU of 0 is not supported by the hardware */
8989         ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
8990                                     ppd->port_crc_mode_enabled);
8991         if (ret != HCMD_SUCCESS)
8992                 goto set_local_link_attributes_fail;
8993
8994         ret = write_vc_local_link_width(dd, 0, 0,
8995                                         opa_to_vc_link_widths(
8996                                                 ppd->link_width_enabled));
8997         if (ret != HCMD_SUCCESS)
8998                 goto set_local_link_attributes_fail;
8999
9000         /* let peer know who we are */
9001         ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9002         if (ret == HCMD_SUCCESS)
9003                 return 0;
9004
9005 set_local_link_attributes_fail:
9006         dd_dev_err(dd,
9007                    "Failed to set local link attributes, return 0x%x\n",
9008                    ret);
9009         return ret;
9010 }
9011
9012 /*
9013  * Call this to start the link.
9014  * Do not do anything if the link is disabled.
9015  * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9016  */
9017 int start_link(struct hfi1_pportdata *ppd)
9018 {
9019         if (!ppd->link_enabled) {
9020                 dd_dev_info(ppd->dd,
9021                             "%s: stopping link start because link is disabled\n",
9022                             __func__);
9023                 return 0;
9024         }
9025         if (!ppd->driver_link_ready) {
9026                 dd_dev_info(ppd->dd,
9027                             "%s: stopping link start because driver is not ready\n",
9028                             __func__);
9029                 return 0;
9030         }
9031
9032         return set_link_state(ppd, HLS_DN_POLL);
9033 }
9034
9035 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9036 {
9037         struct hfi1_devdata *dd = ppd->dd;
9038         u64 mask;
9039         unsigned long timeout;
9040
9041         /*
9042          * Check for QSFP interrupt for t_init (SFF 8679)
9043          */
9044         timeout = jiffies + msecs_to_jiffies(2000);
9045         while (1) {
9046                 mask = read_csr(dd, dd->hfi1_id ?
9047                                 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
9048                 if (!(mask & QSFP_HFI0_INT_N)) {
9049                         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR :
9050                                   ASIC_QSFP1_CLEAR, QSFP_HFI0_INT_N);
9051                         break;
9052                 }
9053                 if (time_after(jiffies, timeout)) {
9054                         dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9055                                     __func__);
9056                         break;
9057                 }
9058                 udelay(2);
9059         }
9060 }
9061
9062 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9063 {
9064         struct hfi1_devdata *dd = ppd->dd;
9065         u64 mask;
9066
9067         mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9068         if (enable)
9069                 mask |= (u64)QSFP_HFI0_INT_N;
9070         else
9071                 mask &= ~(u64)QSFP_HFI0_INT_N;
9072         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9073 }
9074
9075 void reset_qsfp(struct hfi1_pportdata *ppd)
9076 {
9077         struct hfi1_devdata *dd = ppd->dd;
9078         u64 mask, qsfp_mask;
9079
9080         /* Disable INT_N from triggering QSFP interrupts */
9081         set_qsfp_int_n(ppd, 0);
9082
9083         /* Reset the QSFP */
9084         mask = (u64)QSFP_HFI0_RESET_N;
9085         qsfp_mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_OE : ASIC_QSFP1_OE);
9086         qsfp_mask |= mask;
9087         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_OE : ASIC_QSFP1_OE, qsfp_mask);
9088
9089         qsfp_mask = read_csr(dd,
9090                              dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
9091         qsfp_mask &= ~mask;
9092         write_csr(dd,
9093                   dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9094
9095         udelay(10);
9096
9097         qsfp_mask |= mask;
9098         write_csr(dd,
9099                   dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9100
9101         wait_for_qsfp_init(ppd);
9102
9103         /*
9104          * Allow INT_N to trigger the QSFP interrupt to watch
9105          * for alarms and warnings
9106          */
9107         set_qsfp_int_n(ppd, 1);
9108 }
9109
9110 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9111                                         u8 *qsfp_interrupt_status)
9112 {
9113         struct hfi1_devdata *dd = ppd->dd;
9114
9115         if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
9116             (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
9117                 dd_dev_info(dd, "%s: QSFP cable on fire\n",
9118                             __func__);
9119
9120         if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
9121             (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9122                 dd_dev_info(dd, "%s: QSFP cable temperature too low\n",
9123                             __func__);
9124
9125         if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
9126             (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9127                 dd_dev_info(dd, "%s: QSFP supply voltage too high\n",
9128                             __func__);
9129
9130         if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
9131             (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9132                 dd_dev_info(dd, "%s: QSFP supply voltage too low\n",
9133                             __func__);
9134
9135         /* Byte 2 is vendor specific */
9136
9137         if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
9138             (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9139                 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too high\n",
9140                             __func__);
9141
9142         if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
9143             (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9144                 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too low\n",
9145                             __func__);
9146
9147         if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
9148             (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9149                 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too high\n",
9150                             __func__);
9151
9152         if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
9153             (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9154                 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too low\n",
9155                             __func__);
9156
9157         if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
9158             (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9159                 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too high\n",
9160                             __func__);
9161
9162         if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
9163             (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9164                 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too low\n",
9165                             __func__);
9166
9167         if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
9168             (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9169                 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too high\n",
9170                             __func__);
9171
9172         if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
9173             (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9174                 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too low\n",
9175                             __func__);
9176
9177         if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
9178             (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9179                 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too high\n",
9180                             __func__);
9181
9182         if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
9183             (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9184                 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too low\n",
9185                             __func__);
9186
9187         if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
9188             (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9189                 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too high\n",
9190                             __func__);
9191
9192         if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
9193             (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9194                 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too low\n",
9195                             __func__);
9196
9197         /* Bytes 9-10 and 11-12 are reserved */
9198         /* Bytes 13-15 are vendor specific */
9199
9200         return 0;
9201 }
9202
9203 /* This routine will only be scheduled if the QSFP module present is asserted */
9204 void qsfp_event(struct work_struct *work)
9205 {
9206         struct qsfp_data *qd;
9207         struct hfi1_pportdata *ppd;
9208         struct hfi1_devdata *dd;
9209
9210         qd = container_of(work, struct qsfp_data, qsfp_work);
9211         ppd = qd->ppd;
9212         dd = ppd->dd;
9213
9214         /* Sanity check */
9215         if (!qsfp_mod_present(ppd))
9216                 return;
9217
9218         /*
9219          * Turn DC back on after cables has been
9220          * re-inserted. Up until now, the DC has been in
9221          * reset to save power.
9222          */
9223         dc_start(dd);
9224
9225         if (qd->cache_refresh_required) {
9226                 set_qsfp_int_n(ppd, 0);
9227
9228                 wait_for_qsfp_init(ppd);
9229
9230                 /*
9231                  * Allow INT_N to trigger the QSFP interrupt to watch
9232                  * for alarms and warnings
9233                  */
9234                 set_qsfp_int_n(ppd, 1);
9235
9236                 tune_serdes(ppd);
9237
9238                 start_link(ppd);
9239         }
9240
9241         if (qd->check_interrupt_flags) {
9242                 u8 qsfp_interrupt_status[16] = {0,};
9243
9244                 if (one_qsfp_read(ppd, dd->hfi1_id, 6,
9245                                   &qsfp_interrupt_status[0], 16) != 16) {
9246                         dd_dev_info(dd,
9247                                     "%s: Failed to read status of QSFP module\n",
9248                                     __func__);
9249                 } else {
9250                         unsigned long flags;
9251
9252                         handle_qsfp_error_conditions(
9253                                         ppd, qsfp_interrupt_status);
9254                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9255                         ppd->qsfp_info.check_interrupt_flags = 0;
9256                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
9257                                                flags);
9258                 }
9259         }
9260 }
9261
9262 static void init_qsfp_int(struct hfi1_devdata *dd)
9263 {
9264         struct hfi1_pportdata *ppd = dd->pport;
9265         u64 qsfp_mask, cce_int_mask;
9266         const int qsfp1_int_smask = QSFP1_INT % 64;
9267         const int qsfp2_int_smask = QSFP2_INT % 64;
9268
9269         /*
9270          * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9271          * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9272          * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9273          * the index of the appropriate CSR in the CCEIntMask CSR array
9274          */
9275         cce_int_mask = read_csr(dd, CCE_INT_MASK +
9276                                 (8 * (QSFP1_INT / 64)));
9277         if (dd->hfi1_id) {
9278                 cce_int_mask &= ~((u64)1 << qsfp1_int_smask);
9279                 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)),
9280                           cce_int_mask);
9281         } else {
9282                 cce_int_mask &= ~((u64)1 << qsfp2_int_smask);
9283                 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)),
9284                           cce_int_mask);
9285         }
9286
9287         qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9288         /* Clear current status to avoid spurious interrupts */
9289         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9290                   qsfp_mask);
9291         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9292                   qsfp_mask);
9293
9294         set_qsfp_int_n(ppd, 0);
9295
9296         /* Handle active low nature of INT_N and MODPRST_N pins */
9297         if (qsfp_mod_present(ppd))
9298                 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9299         write_csr(dd,
9300                   dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9301                   qsfp_mask);
9302 }
9303
9304 /*
9305  * Do a one-time initialize of the LCB block.
9306  */
9307 static void init_lcb(struct hfi1_devdata *dd)
9308 {
9309         /* simulator does not correctly handle LCB cclk loopback, skip */
9310         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9311                 return;
9312
9313         /* the DC has been reset earlier in the driver load */
9314
9315         /* set LCB for cclk loopback on the port */
9316         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9317         write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9318         write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9319         write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9320         write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9321         write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9322         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9323 }
9324
9325 int bringup_serdes(struct hfi1_pportdata *ppd)
9326 {
9327         struct hfi1_devdata *dd = ppd->dd;
9328         u64 guid;
9329         int ret;
9330
9331         if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9332                 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9333
9334         guid = ppd->guid;
9335         if (!guid) {
9336                 if (dd->base_guid)
9337                         guid = dd->base_guid + ppd->port - 1;
9338                 ppd->guid = guid;
9339         }
9340
9341         /* Set linkinit_reason on power up per OPA spec */
9342         ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9343
9344         /* one-time init of the LCB */
9345         init_lcb(dd);
9346
9347         if (loopback) {
9348                 ret = init_loopback(dd);
9349                 if (ret < 0)
9350                         return ret;
9351         }
9352
9353         /* tune the SERDES to a ballpark setting for
9354          * optimal signal and bit error rate
9355          * Needs to be done before starting the link
9356          */
9357         tune_serdes(ppd);
9358
9359         return start_link(ppd);
9360 }
9361
9362 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9363 {
9364         struct hfi1_devdata *dd = ppd->dd;
9365
9366         /*
9367          * Shut down the link and keep it down.   First turn off that the
9368          * driver wants to allow the link to be up (driver_link_ready).
9369          * Then make sure the link is not automatically restarted
9370          * (link_enabled).  Cancel any pending restart.  And finally
9371          * go offline.
9372          */
9373         ppd->driver_link_ready = 0;
9374         ppd->link_enabled = 0;
9375
9376         ppd->offline_disabled_reason =
9377                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED);
9378         set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SMA_DISABLED, 0,
9379                              OPA_LINKDOWN_REASON_SMA_DISABLED);
9380         set_link_state(ppd, HLS_DN_OFFLINE);
9381
9382         /* disable the port */
9383         clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9384 }
9385
9386 static inline int init_cpu_counters(struct hfi1_devdata *dd)
9387 {
9388         struct hfi1_pportdata *ppd;
9389         int i;
9390
9391         ppd = (struct hfi1_pportdata *)(dd + 1);
9392         for (i = 0; i < dd->num_pports; i++, ppd++) {
9393                 ppd->ibport_data.rvp.rc_acks = NULL;
9394                 ppd->ibport_data.rvp.rc_qacks = NULL;
9395                 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9396                 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9397                 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9398                 if (!ppd->ibport_data.rvp.rc_acks ||
9399                     !ppd->ibport_data.rvp.rc_delayed_comp ||
9400                     !ppd->ibport_data.rvp.rc_qacks)
9401                         return -ENOMEM;
9402         }
9403
9404         return 0;
9405 }
9406
9407 static const char * const pt_names[] = {
9408         "expected",
9409         "eager",
9410         "invalid"
9411 };
9412
9413 static const char *pt_name(u32 type)
9414 {
9415         return type >= ARRAY_SIZE(pt_names) ? "unknown" : pt_names[type];
9416 }
9417
9418 /*
9419  * index is the index into the receive array
9420  */
9421 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9422                   u32 type, unsigned long pa, u16 order)
9423 {
9424         u64 reg;
9425         void __iomem *base = (dd->rcvarray_wc ? dd->rcvarray_wc :
9426                               (dd->kregbase + RCV_ARRAY));
9427
9428         if (!(dd->flags & HFI1_PRESENT))
9429                 goto done;
9430
9431         if (type == PT_INVALID) {
9432                 pa = 0;
9433         } else if (type > PT_INVALID) {
9434                 dd_dev_err(dd,
9435                            "unexpected receive array type %u for index %u, not handled\n",
9436                            type, index);
9437                 goto done;
9438         }
9439
9440         hfi1_cdbg(TID, "type %s, index 0x%x, pa 0x%lx, bsize 0x%lx",
9441                   pt_name(type), index, pa, (unsigned long)order);
9442
9443 #define RT_ADDR_SHIFT 12        /* 4KB kernel address boundary */
9444         reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9445                 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9446                 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9447                                         << RCV_ARRAY_RT_ADDR_SHIFT;
9448         writeq(reg, base + (index * 8));
9449
9450         if (type == PT_EAGER)
9451                 /*
9452                  * Eager entries are written one-by-one so we have to push them
9453                  * after we write the entry.
9454                  */
9455                 flush_wc();
9456 done:
9457         return;
9458 }
9459
9460 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9461 {
9462         struct hfi1_devdata *dd = rcd->dd;
9463         u32 i;
9464
9465         /* this could be optimized */
9466         for (i = rcd->eager_base; i < rcd->eager_base +
9467                      rcd->egrbufs.alloced; i++)
9468                 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9469
9470         for (i = rcd->expected_base;
9471                         i < rcd->expected_base + rcd->expected_count; i++)
9472                 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9473 }
9474
9475 int hfi1_get_base_kinfo(struct hfi1_ctxtdata *rcd,
9476                         struct hfi1_ctxt_info *kinfo)
9477 {
9478         kinfo->runtime_flags = (HFI1_MISC_GET() << HFI1_CAP_USER_SHIFT) |
9479                 HFI1_CAP_UGET(MASK) | HFI1_CAP_KGET(K2U);
9480         return 0;
9481 }
9482
9483 struct hfi1_message_header *hfi1_get_msgheader(
9484                                 struct hfi1_devdata *dd, __le32 *rhf_addr)
9485 {
9486         u32 offset = rhf_hdrq_offset(rhf_to_cpu(rhf_addr));
9487
9488         return (struct hfi1_message_header *)
9489                 (rhf_addr - dd->rhf_offset + offset);
9490 }
9491
9492 static const char * const ib_cfg_name_strings[] = {
9493         "HFI1_IB_CFG_LIDLMC",
9494         "HFI1_IB_CFG_LWID_DG_ENB",
9495         "HFI1_IB_CFG_LWID_ENB",
9496         "HFI1_IB_CFG_LWID",
9497         "HFI1_IB_CFG_SPD_ENB",
9498         "HFI1_IB_CFG_SPD",
9499         "HFI1_IB_CFG_RXPOL_ENB",
9500         "HFI1_IB_CFG_LREV_ENB",
9501         "HFI1_IB_CFG_LINKLATENCY",
9502         "HFI1_IB_CFG_HRTBT",
9503         "HFI1_IB_CFG_OP_VLS",
9504         "HFI1_IB_CFG_VL_HIGH_CAP",
9505         "HFI1_IB_CFG_VL_LOW_CAP",
9506         "HFI1_IB_CFG_OVERRUN_THRESH",
9507         "HFI1_IB_CFG_PHYERR_THRESH",
9508         "HFI1_IB_CFG_LINKDEFAULT",
9509         "HFI1_IB_CFG_PKEYS",
9510         "HFI1_IB_CFG_MTU",
9511         "HFI1_IB_CFG_LSTATE",
9512         "HFI1_IB_CFG_VL_HIGH_LIMIT",
9513         "HFI1_IB_CFG_PMA_TICKS",
9514         "HFI1_IB_CFG_PORT"
9515 };
9516
9517 static const char *ib_cfg_name(int which)
9518 {
9519         if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
9520                 return "invalid";
9521         return ib_cfg_name_strings[which];
9522 }
9523
9524 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9525 {
9526         struct hfi1_devdata *dd = ppd->dd;
9527         int val = 0;
9528
9529         switch (which) {
9530         case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
9531                 val = ppd->link_width_enabled;
9532                 break;
9533         case HFI1_IB_CFG_LWID: /* currently active Link-width */
9534                 val = ppd->link_width_active;
9535                 break;
9536         case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
9537                 val = ppd->link_speed_enabled;
9538                 break;
9539         case HFI1_IB_CFG_SPD: /* current Link speed */
9540                 val = ppd->link_speed_active;
9541                 break;
9542
9543         case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
9544         case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
9545         case HFI1_IB_CFG_LINKLATENCY:
9546                 goto unimplemented;
9547
9548         case HFI1_IB_CFG_OP_VLS:
9549                 val = ppd->vls_operational;
9550                 break;
9551         case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9552                 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
9553                 break;
9554         case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
9555                 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
9556                 break;
9557         case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
9558                 val = ppd->overrun_threshold;
9559                 break;
9560         case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
9561                 val = ppd->phy_error_threshold;
9562                 break;
9563         case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9564                 val = dd->link_default;
9565                 break;
9566
9567         case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
9568         case HFI1_IB_CFG_PMA_TICKS:
9569         default:
9570 unimplemented:
9571                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
9572                         dd_dev_info(
9573                                 dd,
9574                                 "%s: which %s: not implemented\n",
9575                                 __func__,
9576                                 ib_cfg_name(which));
9577                 break;
9578         }
9579
9580         return val;
9581 }
9582
9583 /*
9584  * The largest MAD packet size.
9585  */
9586 #define MAX_MAD_PACKET 2048
9587
9588 /*
9589  * Return the maximum header bytes that can go on the _wire_
9590  * for this device. This count includes the ICRC which is
9591  * not part of the packet held in memory but it is appended
9592  * by the HW.
9593  * This is dependent on the device's receive header entry size.
9594  * HFI allows this to be set per-receive context, but the
9595  * driver presently enforces a global value.
9596  */
9597 u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
9598 {
9599         /*
9600          * The maximum non-payload (MTU) bytes in LRH.PktLen are
9601          * the Receive Header Entry Size minus the PBC (or RHF) size
9602          * plus one DW for the ICRC appended by HW.
9603          *
9604          * dd->rcd[0].rcvhdrqentsize is in DW.
9605          * We use rcd[0] as all context will have the same value. Also,
9606          * the first kernel context would have been allocated by now so
9607          * we are guaranteed a valid value.
9608          */
9609         return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
9610 }
9611
9612 /*
9613  * Set Send Length
9614  * @ppd - per port data
9615  *
9616  * Set the MTU by limiting how many DWs may be sent.  The SendLenCheck*
9617  * registers compare against LRH.PktLen, so use the max bytes included
9618  * in the LRH.
9619  *
9620  * This routine changes all VL values except VL15, which it maintains at
9621  * the same value.
9622  */
9623 static void set_send_length(struct hfi1_pportdata *ppd)
9624 {
9625         struct hfi1_devdata *dd = ppd->dd;
9626         u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
9627         u32 maxvlmtu = dd->vld[15].mtu;
9628         u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
9629                               & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
9630                 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
9631         int i;
9632         u32 thres;
9633
9634         for (i = 0; i < ppd->vls_supported; i++) {
9635                 if (dd->vld[i].mtu > maxvlmtu)
9636                         maxvlmtu = dd->vld[i].mtu;
9637                 if (i <= 3)
9638                         len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
9639                                  & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
9640                                 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
9641                 else
9642                         len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
9643                                  & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
9644                                 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
9645         }
9646         write_csr(dd, SEND_LEN_CHECK0, len1);
9647         write_csr(dd, SEND_LEN_CHECK1, len2);
9648         /* adjust kernel credit return thresholds based on new MTUs */
9649         /* all kernel receive contexts have the same hdrqentsize */
9650         for (i = 0; i < ppd->vls_supported; i++) {
9651                 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50),
9652                             sc_mtu_to_threshold(dd->vld[i].sc,
9653                                                 dd->vld[i].mtu,
9654                                                 dd->rcd[0]->rcvhdrqentsize));
9655                 sc_set_cr_threshold(dd->vld[i].sc, thres);
9656         }
9657         thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50),
9658                     sc_mtu_to_threshold(dd->vld[15].sc,
9659                                         dd->vld[15].mtu,
9660                                         dd->rcd[0]->rcvhdrqentsize));
9661         sc_set_cr_threshold(dd->vld[15].sc, thres);
9662
9663         /* Adjust maximum MTU for the port in DC */
9664         dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
9665                 (ilog2(maxvlmtu >> 8) + 1);
9666         len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
9667         len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
9668         len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
9669                 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
9670         write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
9671 }
9672
9673 static void set_lidlmc(struct hfi1_pportdata *ppd)
9674 {
9675         int i;
9676         u64 sreg = 0;
9677         struct hfi1_devdata *dd = ppd->dd;
9678         u32 mask = ~((1U << ppd->lmc) - 1);
9679         u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
9680
9681         if (dd->hfi1_snoop.mode_flag)
9682                 dd_dev_info(dd, "Set lid/lmc while snooping");
9683
9684         c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
9685                 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
9686         c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
9687                         << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
9688               ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
9689                         << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
9690         write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
9691
9692         /*
9693          * Iterate over all the send contexts and set their SLID check
9694          */
9695         sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
9696                         SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
9697                (((ppd->lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
9698                         SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
9699
9700         for (i = 0; i < dd->chip_send_contexts; i++) {
9701                 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
9702                           i, (u32)sreg);
9703                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
9704         }
9705
9706         /* Now we have to do the same thing for the sdma engines */
9707         sdma_update_lmc(dd, mask, ppd->lid);
9708 }
9709
9710 static int wait_phy_linkstate(struct hfi1_devdata *dd, u32 state, u32 msecs)
9711 {
9712         unsigned long timeout;
9713         u32 curr_state;
9714
9715         timeout = jiffies + msecs_to_jiffies(msecs);
9716         while (1) {
9717                 curr_state = read_physical_state(dd);
9718                 if (curr_state == state)
9719                         break;
9720                 if (time_after(jiffies, timeout)) {
9721                         dd_dev_err(dd,
9722                                    "timeout waiting for phy link state 0x%x, current state is 0x%x\n",
9723                                    state, curr_state);
9724                         return -ETIMEDOUT;
9725                 }
9726                 usleep_range(1950, 2050); /* sleep 2ms-ish */
9727         }
9728
9729         return 0;
9730 }
9731
9732 /*
9733  * Helper for set_link_state().  Do not call except from that routine.
9734  * Expects ppd->hls_mutex to be held.
9735  *
9736  * @rem_reason value to be sent to the neighbor
9737  *
9738  * LinkDownReasons only set if transition succeeds.
9739  */
9740 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
9741 {
9742         struct hfi1_devdata *dd = ppd->dd;
9743         u32 pstate, previous_state;
9744         u32 last_local_state;
9745         u32 last_remote_state;
9746         int ret;
9747         int do_transition;
9748         int do_wait;
9749
9750         previous_state = ppd->host_link_state;
9751         ppd->host_link_state = HLS_GOING_OFFLINE;
9752         pstate = read_physical_state(dd);
9753         if (pstate == PLS_OFFLINE) {
9754                 do_transition = 0;      /* in right state */
9755                 do_wait = 0;            /* ...no need to wait */
9756         } else if ((pstate & 0xff) == PLS_OFFLINE) {
9757                 do_transition = 0;      /* in an offline transient state */
9758                 do_wait = 1;            /* ...wait for it to settle */
9759         } else {
9760                 do_transition = 1;      /* need to move to offline */
9761                 do_wait = 1;            /* ...will need to wait */
9762         }
9763
9764         if (do_transition) {
9765                 ret = set_physical_link_state(dd,
9766                                               (rem_reason << 8) | PLS_OFFLINE);
9767
9768                 if (ret != HCMD_SUCCESS) {
9769                         dd_dev_err(dd,
9770                                    "Failed to transition to Offline link state, return %d\n",
9771                                    ret);
9772                         return -EINVAL;
9773                 }
9774                 if (ppd->offline_disabled_reason ==
9775                                 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
9776                         ppd->offline_disabled_reason =
9777                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
9778         }
9779
9780         if (do_wait) {
9781                 /* it can take a while for the link to go down */
9782                 ret = wait_phy_linkstate(dd, PLS_OFFLINE, 10000);
9783                 if (ret < 0)
9784                         return ret;
9785         }
9786
9787         /* make sure the logical state is also down */
9788         wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
9789
9790         /*
9791          * Now in charge of LCB - must be after the physical state is
9792          * offline.quiet and before host_link_state is changed.
9793          */
9794         set_host_lcb_access(dd);
9795         write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9796         ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
9797
9798         if (ppd->port_type == PORT_TYPE_QSFP &&
9799             ppd->qsfp_info.limiting_active &&
9800             qsfp_mod_present(ppd)) {
9801                 int ret;
9802
9803                 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT);
9804                 if (ret == 0) {
9805                         set_qsfp_tx(ppd, 0);
9806                         release_chip_resource(dd, qsfp_resource(dd));
9807                 } else {
9808                         /* not fatal, but should warn */
9809                         dd_dev_err(dd,
9810                                    "Unable to acquire lock to turn off QSFP TX\n");
9811                 }
9812         }
9813
9814         /*
9815          * The LNI has a mandatory wait time after the physical state
9816          * moves to Offline.Quiet.  The wait time may be different
9817          * depending on how the link went down.  The 8051 firmware
9818          * will observe the needed wait time and only move to ready
9819          * when that is completed.  The largest of the quiet timeouts
9820          * is 6s, so wait that long and then at least 0.5s more for
9821          * other transitions, and another 0.5s for a buffer.
9822          */
9823         ret = wait_fm_ready(dd, 7000);
9824         if (ret) {
9825                 dd_dev_err(dd,
9826                            "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
9827                 /* state is really offline, so make it so */
9828                 ppd->host_link_state = HLS_DN_OFFLINE;
9829                 return ret;
9830         }
9831
9832         /*
9833          * The state is now offline and the 8051 is ready to accept host
9834          * requests.
9835          *      - change our state
9836          *      - notify others if we were previously in a linkup state
9837          */
9838         ppd->host_link_state = HLS_DN_OFFLINE;
9839         if (previous_state & HLS_UP) {
9840                 /* went down while link was up */
9841                 handle_linkup_change(dd, 0);
9842         } else if (previous_state
9843                         & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
9844                 /* went down while attempting link up */
9845                 /* byte 1 of last_*_state is the failure reason */
9846                 read_last_local_state(dd, &last_local_state);
9847                 read_last_remote_state(dd, &last_remote_state);
9848                 dd_dev_err(dd,
9849                            "LNI failure last states: local 0x%08x, remote 0x%08x\n",
9850                            last_local_state, last_remote_state);
9851         }
9852
9853         /* the active link width (downgrade) is 0 on link down */
9854         ppd->link_width_active = 0;
9855         ppd->link_width_downgrade_tx_active = 0;
9856         ppd->link_width_downgrade_rx_active = 0;
9857         ppd->current_egress_rate = 0;
9858         return 0;
9859 }
9860
9861 /* return the link state name */
9862 static const char *link_state_name(u32 state)
9863 {
9864         const char *name;
9865         int n = ilog2(state);
9866         static const char * const names[] = {
9867                 [__HLS_UP_INIT_BP]       = "INIT",
9868                 [__HLS_UP_ARMED_BP]      = "ARMED",
9869                 [__HLS_UP_ACTIVE_BP]     = "ACTIVE",
9870                 [__HLS_DN_DOWNDEF_BP]    = "DOWNDEF",
9871                 [__HLS_DN_POLL_BP]       = "POLL",
9872                 [__HLS_DN_DISABLE_BP]    = "DISABLE",
9873                 [__HLS_DN_OFFLINE_BP]    = "OFFLINE",
9874                 [__HLS_VERIFY_CAP_BP]    = "VERIFY_CAP",
9875                 [__HLS_GOING_UP_BP]      = "GOING_UP",
9876                 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
9877                 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
9878         };
9879
9880         name = n < ARRAY_SIZE(names) ? names[n] : NULL;
9881         return name ? name : "unknown";
9882 }
9883
9884 /* return the link state reason name */
9885 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
9886 {
9887         if (state == HLS_UP_INIT) {
9888                 switch (ppd->linkinit_reason) {
9889                 case OPA_LINKINIT_REASON_LINKUP:
9890                         return "(LINKUP)";
9891                 case OPA_LINKINIT_REASON_FLAPPING:
9892                         return "(FLAPPING)";
9893                 case OPA_LINKINIT_OUTSIDE_POLICY:
9894                         return "(OUTSIDE_POLICY)";
9895                 case OPA_LINKINIT_QUARANTINED:
9896                         return "(QUARANTINED)";
9897                 case OPA_LINKINIT_INSUFIC_CAPABILITY:
9898                         return "(INSUFIC_CAPABILITY)";
9899                 default:
9900                         break;
9901                 }
9902         }
9903         return "";
9904 }
9905
9906 /*
9907  * driver_physical_state - convert the driver's notion of a port's
9908  * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
9909  * Return -1 (converted to a u32) to indicate error.
9910  */
9911 u32 driver_physical_state(struct hfi1_pportdata *ppd)
9912 {
9913         switch (ppd->host_link_state) {
9914         case HLS_UP_INIT:
9915         case HLS_UP_ARMED:
9916         case HLS_UP_ACTIVE:
9917                 return IB_PORTPHYSSTATE_LINKUP;
9918         case HLS_DN_POLL:
9919                 return IB_PORTPHYSSTATE_POLLING;
9920         case HLS_DN_DISABLE:
9921                 return IB_PORTPHYSSTATE_DISABLED;
9922         case HLS_DN_OFFLINE:
9923                 return OPA_PORTPHYSSTATE_OFFLINE;
9924         case HLS_VERIFY_CAP:
9925                 return IB_PORTPHYSSTATE_POLLING;
9926         case HLS_GOING_UP:
9927                 return IB_PORTPHYSSTATE_POLLING;
9928         case HLS_GOING_OFFLINE:
9929                 return OPA_PORTPHYSSTATE_OFFLINE;
9930         case HLS_LINK_COOLDOWN:
9931                 return OPA_PORTPHYSSTATE_OFFLINE;
9932         case HLS_DN_DOWNDEF:
9933         default:
9934                 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
9935                            ppd->host_link_state);
9936                 return  -1;
9937         }
9938 }
9939
9940 /*
9941  * driver_logical_state - convert the driver's notion of a port's
9942  * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
9943  * (converted to a u32) to indicate error.
9944  */
9945 u32 driver_logical_state(struct hfi1_pportdata *ppd)
9946 {
9947         if (ppd->host_link_state && !(ppd->host_link_state & HLS_UP))
9948                 return IB_PORT_DOWN;
9949
9950         switch (ppd->host_link_state & HLS_UP) {
9951         case HLS_UP_INIT:
9952                 return IB_PORT_INIT;
9953         case HLS_UP_ARMED:
9954                 return IB_PORT_ARMED;
9955         case HLS_UP_ACTIVE:
9956                 return IB_PORT_ACTIVE;
9957         default:
9958                 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
9959                            ppd->host_link_state);
9960         return -1;
9961         }
9962 }
9963
9964 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
9965                           u8 neigh_reason, u8 rem_reason)
9966 {
9967         if (ppd->local_link_down_reason.latest == 0 &&
9968             ppd->neigh_link_down_reason.latest == 0) {
9969                 ppd->local_link_down_reason.latest = lcl_reason;
9970                 ppd->neigh_link_down_reason.latest = neigh_reason;
9971                 ppd->remote_link_down_reason = rem_reason;
9972         }
9973 }
9974
9975 /*
9976  * Change the physical and/or logical link state.
9977  *
9978  * Do not call this routine while inside an interrupt.  It contains
9979  * calls to routines that can take multiple seconds to finish.
9980  *
9981  * Returns 0 on success, -errno on failure.
9982  */
9983 int set_link_state(struct hfi1_pportdata *ppd, u32 state)
9984 {
9985         struct hfi1_devdata *dd = ppd->dd;
9986         struct ib_event event = {.device = NULL};
9987         int ret1, ret = 0;
9988         int was_up, is_down;
9989         int orig_new_state, poll_bounce;
9990
9991         mutex_lock(&ppd->hls_lock);
9992
9993         orig_new_state = state;
9994         if (state == HLS_DN_DOWNDEF)
9995                 state = dd->link_default;
9996
9997         /* interpret poll -> poll as a link bounce */
9998         poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
9999                       state == HLS_DN_POLL;
10000
10001         dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
10002                     link_state_name(ppd->host_link_state),
10003                     link_state_name(orig_new_state),
10004                     poll_bounce ? "(bounce) " : "",
10005                     link_state_reason_name(ppd, state));
10006
10007         was_up = !!(ppd->host_link_state & HLS_UP);
10008
10009         /*
10010          * If we're going to a (HLS_*) link state that implies the logical
10011          * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10012          * reset is_sm_config_started to 0.
10013          */
10014         if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10015                 ppd->is_sm_config_started = 0;
10016
10017         /*
10018          * Do nothing if the states match.  Let a poll to poll link bounce
10019          * go through.
10020          */
10021         if (ppd->host_link_state == state && !poll_bounce)
10022                 goto done;
10023
10024         switch (state) {
10025         case HLS_UP_INIT:
10026                 if (ppd->host_link_state == HLS_DN_POLL &&
10027                     (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
10028                         /*
10029                          * Quick link up jumps from polling to here.
10030                          *
10031                          * Whether in normal or loopback mode, the
10032                          * simulator jumps from polling to link up.
10033                          * Accept that here.
10034                          */
10035                         /* OK */
10036                 } else if (ppd->host_link_state != HLS_GOING_UP) {
10037                         goto unexpected;
10038                 }
10039
10040                 ppd->host_link_state = HLS_UP_INIT;
10041                 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10042                 if (ret) {
10043                         /* logical state didn't change, stay at going_up */
10044                         ppd->host_link_state = HLS_GOING_UP;
10045                         dd_dev_err(dd,
10046                                    "%s: logical state did not change to INIT\n",
10047                                    __func__);
10048                 } else {
10049                         /* clear old transient LINKINIT_REASON code */
10050                         if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10051                                 ppd->linkinit_reason =
10052                                         OPA_LINKINIT_REASON_LINKUP;
10053
10054                         /* enable the port */
10055                         add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10056
10057                         handle_linkup_change(dd, 1);
10058                 }
10059                 break;
10060         case HLS_UP_ARMED:
10061                 if (ppd->host_link_state != HLS_UP_INIT)
10062                         goto unexpected;
10063
10064                 ppd->host_link_state = HLS_UP_ARMED;
10065                 set_logical_state(dd, LSTATE_ARMED);
10066                 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10067                 if (ret) {
10068                         /* logical state didn't change, stay at init */
10069                         ppd->host_link_state = HLS_UP_INIT;
10070                         dd_dev_err(dd,
10071                                    "%s: logical state did not change to ARMED\n",
10072                                    __func__);
10073                 }
10074                 /*
10075                  * The simulator does not currently implement SMA messages,
10076                  * so neighbor_normal is not set.  Set it here when we first
10077                  * move to Armed.
10078                  */
10079                 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10080                         ppd->neighbor_normal = 1;
10081                 break;
10082         case HLS_UP_ACTIVE:
10083                 if (ppd->host_link_state != HLS_UP_ARMED)
10084                         goto unexpected;
10085
10086                 ppd->host_link_state = HLS_UP_ACTIVE;
10087                 set_logical_state(dd, LSTATE_ACTIVE);
10088                 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10089                 if (ret) {
10090                         /* logical state didn't change, stay at armed */
10091                         ppd->host_link_state = HLS_UP_ARMED;
10092                         dd_dev_err(dd,
10093                                    "%s: logical state did not change to ACTIVE\n",
10094                                    __func__);
10095                 } else {
10096                         /* tell all engines to go running */
10097                         sdma_all_running(dd);
10098
10099                         /* Signal the IB layer that the port has went active */
10100                         event.device = &dd->verbs_dev.rdi.ibdev;
10101                         event.element.port_num = ppd->port;
10102                         event.event = IB_EVENT_PORT_ACTIVE;
10103                 }
10104                 break;
10105         case HLS_DN_POLL:
10106                 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10107                      ppd->host_link_state == HLS_DN_OFFLINE) &&
10108                     dd->dc_shutdown)
10109                         dc_start(dd);
10110                 /* Hand LED control to the DC */
10111                 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10112
10113                 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10114                         u8 tmp = ppd->link_enabled;
10115
10116                         ret = goto_offline(ppd, ppd->remote_link_down_reason);
10117                         if (ret) {
10118                                 ppd->link_enabled = tmp;
10119                                 break;
10120                         }
10121                         ppd->remote_link_down_reason = 0;
10122
10123                         if (ppd->driver_link_ready)
10124                                 ppd->link_enabled = 1;
10125                 }
10126
10127                 set_all_slowpath(ppd->dd);
10128                 ret = set_local_link_attributes(ppd);
10129                 if (ret)
10130                         break;
10131
10132                 ppd->port_error_action = 0;
10133                 ppd->host_link_state = HLS_DN_POLL;
10134
10135                 if (quick_linkup) {
10136                         /* quick linkup does not go into polling */
10137                         ret = do_quick_linkup(dd);
10138                 } else {
10139                         ret1 = set_physical_link_state(dd, PLS_POLLING);
10140                         if (ret1 != HCMD_SUCCESS) {
10141                                 dd_dev_err(dd,
10142                                            "Failed to transition to Polling link state, return 0x%x\n",
10143                                            ret1);
10144                                 ret = -EINVAL;
10145                         }
10146                 }
10147                 ppd->offline_disabled_reason =
10148                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
10149                 /*
10150                  * If an error occurred above, go back to offline.  The
10151                  * caller may reschedule another attempt.
10152                  */
10153                 if (ret)
10154                         goto_offline(ppd, 0);
10155                 break;
10156         case HLS_DN_DISABLE:
10157                 /* link is disabled */
10158                 ppd->link_enabled = 0;
10159
10160                 /* allow any state to transition to disabled */
10161
10162                 /* must transition to offline first */
10163                 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10164                         ret = goto_offline(ppd, ppd->remote_link_down_reason);
10165                         if (ret)
10166                                 break;
10167                         ppd->remote_link_down_reason = 0;
10168                 }
10169
10170                 ret1 = set_physical_link_state(dd, PLS_DISABLED);
10171                 if (ret1 != HCMD_SUCCESS) {
10172                         dd_dev_err(dd,
10173                                    "Failed to transition to Disabled link state, return 0x%x\n",
10174                                    ret1);
10175                         ret = -EINVAL;
10176                         break;
10177                 }
10178                 ppd->host_link_state = HLS_DN_DISABLE;
10179                 dc_shutdown(dd);
10180                 break;
10181         case HLS_DN_OFFLINE:
10182                 if (ppd->host_link_state == HLS_DN_DISABLE)
10183                         dc_start(dd);
10184
10185                 /* allow any state to transition to offline */
10186                 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10187                 if (!ret)
10188                         ppd->remote_link_down_reason = 0;
10189                 break;
10190         case HLS_VERIFY_CAP:
10191                 if (ppd->host_link_state != HLS_DN_POLL)
10192                         goto unexpected;
10193                 ppd->host_link_state = HLS_VERIFY_CAP;
10194                 break;
10195         case HLS_GOING_UP:
10196                 if (ppd->host_link_state != HLS_VERIFY_CAP)
10197                         goto unexpected;
10198
10199                 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10200                 if (ret1 != HCMD_SUCCESS) {
10201                         dd_dev_err(dd,
10202                                    "Failed to transition to link up state, return 0x%x\n",
10203                                    ret1);
10204                         ret = -EINVAL;
10205                         break;
10206                 }
10207                 ppd->host_link_state = HLS_GOING_UP;
10208                 break;
10209
10210         case HLS_GOING_OFFLINE:         /* transient within goto_offline() */
10211         case HLS_LINK_COOLDOWN:         /* transient within goto_offline() */
10212         default:
10213                 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
10214                             __func__, state);
10215                 ret = -EINVAL;
10216                 break;
10217         }
10218
10219         is_down = !!(ppd->host_link_state & (HLS_DN_POLL |
10220                         HLS_DN_DISABLE | HLS_DN_OFFLINE));
10221
10222         if (was_up && is_down && ppd->local_link_down_reason.sma == 0 &&
10223             ppd->neigh_link_down_reason.sma == 0) {
10224                 ppd->local_link_down_reason.sma =
10225                   ppd->local_link_down_reason.latest;
10226                 ppd->neigh_link_down_reason.sma =
10227                   ppd->neigh_link_down_reason.latest;
10228         }
10229
10230         goto done;
10231
10232 unexpected:
10233         dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
10234                    __func__, link_state_name(ppd->host_link_state),
10235                    link_state_name(state));
10236         ret = -EINVAL;
10237
10238 done:
10239         mutex_unlock(&ppd->hls_lock);
10240
10241         if (event.device)
10242                 ib_dispatch_event(&event);
10243
10244         return ret;
10245 }
10246
10247 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
10248 {
10249         u64 reg;
10250         int ret = 0;
10251
10252         switch (which) {
10253         case HFI1_IB_CFG_LIDLMC:
10254                 set_lidlmc(ppd);
10255                 break;
10256         case HFI1_IB_CFG_VL_HIGH_LIMIT:
10257                 /*
10258                  * The VL Arbitrator high limit is sent in units of 4k
10259                  * bytes, while HFI stores it in units of 64 bytes.
10260                  */
10261                 val *= 4096 / 64;
10262                 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
10263                         << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
10264                 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
10265                 break;
10266         case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10267                 /* HFI only supports POLL as the default link down state */
10268                 if (val != HLS_DN_POLL)
10269                         ret = -EINVAL;
10270                 break;
10271         case HFI1_IB_CFG_OP_VLS:
10272                 if (ppd->vls_operational != val) {
10273                         ppd->vls_operational = val;
10274                         if (!ppd->port)
10275                                 ret = -EINVAL;
10276                 }
10277                 break;
10278         /*
10279          * For link width, link width downgrade, and speed enable, always AND
10280          * the setting with what is actually supported.  This has two benefits.
10281          * First, enabled can't have unsupported values, no matter what the
10282          * SM or FM might want.  Second, the ALL_SUPPORTED wildcards that mean
10283          * "fill in with your supported value" have all the bits in the
10284          * field set, so simply ANDing with supported has the desired result.
10285          */
10286         case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
10287                 ppd->link_width_enabled = val & ppd->link_width_supported;
10288                 break;
10289         case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
10290                 ppd->link_width_downgrade_enabled =
10291                                 val & ppd->link_width_downgrade_supported;
10292                 break;
10293         case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10294                 ppd->link_speed_enabled = val & ppd->link_speed_supported;
10295                 break;
10296         case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10297                 /*
10298                  * HFI does not follow IB specs, save this value
10299                  * so we can report it, if asked.
10300                  */
10301                 ppd->overrun_threshold = val;
10302                 break;
10303         case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10304                 /*
10305                  * HFI does not follow IB specs, save this value
10306                  * so we can report it, if asked.
10307                  */
10308                 ppd->phy_error_threshold = val;
10309                 break;
10310
10311         case HFI1_IB_CFG_MTU:
10312                 set_send_length(ppd);
10313                 break;
10314
10315         case HFI1_IB_CFG_PKEYS:
10316                 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
10317                         set_partition_keys(ppd);
10318                 break;
10319
10320         default:
10321                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10322                         dd_dev_info(ppd->dd,
10323                                     "%s: which %s, val 0x%x: not implemented\n",
10324                                     __func__, ib_cfg_name(which), val);
10325                 break;
10326         }
10327         return ret;
10328 }
10329
10330 /* begin functions related to vl arbitration table caching */
10331 static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
10332 {
10333         int i;
10334
10335         BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10336                         VL_ARB_LOW_PRIO_TABLE_SIZE);
10337         BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10338                         VL_ARB_HIGH_PRIO_TABLE_SIZE);
10339
10340         /*
10341          * Note that we always return values directly from the
10342          * 'vl_arb_cache' (and do no CSR reads) in response to a
10343          * 'Get(VLArbTable)'. This is obviously correct after a
10344          * 'Set(VLArbTable)', since the cache will then be up to
10345          * date. But it's also correct prior to any 'Set(VLArbTable)'
10346          * since then both the cache, and the relevant h/w registers
10347          * will be zeroed.
10348          */
10349
10350         for (i = 0; i < MAX_PRIO_TABLE; i++)
10351                 spin_lock_init(&ppd->vl_arb_cache[i].lock);
10352 }
10353
10354 /*
10355  * vl_arb_lock_cache
10356  *
10357  * All other vl_arb_* functions should be called only after locking
10358  * the cache.
10359  */
10360 static inline struct vl_arb_cache *
10361 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
10362 {
10363         if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
10364                 return NULL;
10365         spin_lock(&ppd->vl_arb_cache[idx].lock);
10366         return &ppd->vl_arb_cache[idx];
10367 }
10368
10369 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
10370 {
10371         spin_unlock(&ppd->vl_arb_cache[idx].lock);
10372 }
10373
10374 static void vl_arb_get_cache(struct vl_arb_cache *cache,
10375                              struct ib_vl_weight_elem *vl)
10376 {
10377         memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
10378 }
10379
10380 static void vl_arb_set_cache(struct vl_arb_cache *cache,
10381                              struct ib_vl_weight_elem *vl)
10382 {
10383         memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10384 }
10385
10386 static int vl_arb_match_cache(struct vl_arb_cache *cache,
10387                               struct ib_vl_weight_elem *vl)
10388 {
10389         return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10390 }
10391
10392 /* end functions related to vl arbitration table caching */
10393
10394 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
10395                           u32 size, struct ib_vl_weight_elem *vl)
10396 {
10397         struct hfi1_devdata *dd = ppd->dd;
10398         u64 reg;
10399         unsigned int i, is_up = 0;
10400         int drain, ret = 0;
10401
10402         mutex_lock(&ppd->hls_lock);
10403
10404         if (ppd->host_link_state & HLS_UP)
10405                 is_up = 1;
10406
10407         drain = !is_ax(dd) && is_up;
10408
10409         if (drain)
10410                 /*
10411                  * Before adjusting VL arbitration weights, empty per-VL
10412                  * FIFOs, otherwise a packet whose VL weight is being
10413                  * set to 0 could get stuck in a FIFO with no chance to
10414                  * egress.
10415                  */
10416                 ret = stop_drain_data_vls(dd);
10417
10418         if (ret) {
10419                 dd_dev_err(
10420                         dd,
10421                         "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
10422                         __func__);
10423                 goto err;
10424         }
10425
10426         for (i = 0; i < size; i++, vl++) {
10427                 /*
10428                  * NOTE: The low priority shift and mask are used here, but
10429                  * they are the same for both the low and high registers.
10430                  */
10431                 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
10432                                 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
10433                       | (((u64)vl->weight
10434                                 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
10435                                 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
10436                 write_csr(dd, target + (i * 8), reg);
10437         }
10438         pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
10439
10440         if (drain)
10441                 open_fill_data_vls(dd); /* reopen all VLs */
10442
10443 err:
10444         mutex_unlock(&ppd->hls_lock);
10445
10446         return ret;
10447 }
10448
10449 /*
10450  * Read one credit merge VL register.
10451  */
10452 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
10453                            struct vl_limit *vll)
10454 {
10455         u64 reg = read_csr(dd, csr);
10456
10457         vll->dedicated = cpu_to_be16(
10458                 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
10459                 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
10460         vll->shared = cpu_to_be16(
10461                 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
10462                 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
10463 }
10464
10465 /*
10466  * Read the current credit merge limits.
10467  */
10468 static int get_buffer_control(struct hfi1_devdata *dd,
10469                               struct buffer_control *bc, u16 *overall_limit)
10470 {
10471         u64 reg;
10472         int i;
10473
10474         /* not all entries are filled in */
10475         memset(bc, 0, sizeof(*bc));
10476
10477         /* OPA and HFI have a 1-1 mapping */
10478         for (i = 0; i < TXE_NUM_DATA_VL; i++)
10479                 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
10480
10481         /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
10482         read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
10483
10484         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10485         bc->overall_shared_limit = cpu_to_be16(
10486                 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
10487                 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
10488         if (overall_limit)
10489                 *overall_limit = (reg
10490                         >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
10491                         & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
10492         return sizeof(struct buffer_control);
10493 }
10494
10495 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10496 {
10497         u64 reg;
10498         int i;
10499
10500         /* each register contains 16 SC->VLnt mappings, 4 bits each */
10501         reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
10502         for (i = 0; i < sizeof(u64); i++) {
10503                 u8 byte = *(((u8 *)&reg) + i);
10504
10505                 dp->vlnt[2 * i] = byte & 0xf;
10506                 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
10507         }
10508
10509         reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
10510         for (i = 0; i < sizeof(u64); i++) {
10511                 u8 byte = *(((u8 *)&reg) + i);
10512
10513                 dp->vlnt[16 + (2 * i)] = byte & 0xf;
10514                 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
10515         }
10516         return sizeof(struct sc2vlnt);
10517 }
10518
10519 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
10520                               struct ib_vl_weight_elem *vl)
10521 {
10522         unsigned int i;
10523
10524         for (i = 0; i < nelems; i++, vl++) {
10525                 vl->vl = 0xf;
10526                 vl->weight = 0;
10527         }
10528 }
10529
10530 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10531 {
10532         write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
10533                   DC_SC_VL_VAL(15_0,
10534                                0, dp->vlnt[0] & 0xf,
10535                                1, dp->vlnt[1] & 0xf,
10536                                2, dp->vlnt[2] & 0xf,
10537                                3, dp->vlnt[3] & 0xf,
10538                                4, dp->vlnt[4] & 0xf,
10539                                5, dp->vlnt[5] & 0xf,
10540                                6, dp->vlnt[6] & 0xf,
10541                                7, dp->vlnt[7] & 0xf,
10542                                8, dp->vlnt[8] & 0xf,
10543                                9, dp->vlnt[9] & 0xf,
10544                                10, dp->vlnt[10] & 0xf,
10545                                11, dp->vlnt[11] & 0xf,
10546                                12, dp->vlnt[12] & 0xf,
10547                                13, dp->vlnt[13] & 0xf,
10548                                14, dp->vlnt[14] & 0xf,
10549                                15, dp->vlnt[15] & 0xf));
10550         write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
10551                   DC_SC_VL_VAL(31_16,
10552                                16, dp->vlnt[16] & 0xf,
10553                                17, dp->vlnt[17] & 0xf,
10554                                18, dp->vlnt[18] & 0xf,
10555                                19, dp->vlnt[19] & 0xf,
10556                                20, dp->vlnt[20] & 0xf,
10557                                21, dp->vlnt[21] & 0xf,
10558                                22, dp->vlnt[22] & 0xf,
10559                                23, dp->vlnt[23] & 0xf,
10560                                24, dp->vlnt[24] & 0xf,
10561                                25, dp->vlnt[25] & 0xf,
10562                                26, dp->vlnt[26] & 0xf,
10563                                27, dp->vlnt[27] & 0xf,
10564                                28, dp->vlnt[28] & 0xf,
10565                                29, dp->vlnt[29] & 0xf,
10566                                30, dp->vlnt[30] & 0xf,
10567                                31, dp->vlnt[31] & 0xf));
10568 }
10569
10570 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
10571                         u16 limit)
10572 {
10573         if (limit != 0)
10574                 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
10575                             what, (int)limit, idx);
10576 }
10577
10578 /* change only the shared limit portion of SendCmGLobalCredit */
10579 static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
10580 {
10581         u64 reg;
10582
10583         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10584         reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
10585         reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
10586         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10587 }
10588
10589 /* change only the total credit limit portion of SendCmGLobalCredit */
10590 static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
10591 {
10592         u64 reg;
10593
10594         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10595         reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
10596         reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
10597         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10598 }
10599
10600 /* set the given per-VL shared limit */
10601 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
10602 {
10603         u64 reg;
10604         u32 addr;
10605
10606         if (vl < TXE_NUM_DATA_VL)
10607                 addr = SEND_CM_CREDIT_VL + (8 * vl);
10608         else
10609                 addr = SEND_CM_CREDIT_VL15;
10610
10611         reg = read_csr(dd, addr);
10612         reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
10613         reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
10614         write_csr(dd, addr, reg);
10615 }
10616
10617 /* set the given per-VL dedicated limit */
10618 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
10619 {
10620         u64 reg;
10621         u32 addr;
10622
10623         if (vl < TXE_NUM_DATA_VL)
10624                 addr = SEND_CM_CREDIT_VL + (8 * vl);
10625         else
10626                 addr = SEND_CM_CREDIT_VL15;
10627
10628         reg = read_csr(dd, addr);
10629         reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
10630         reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
10631         write_csr(dd, addr, reg);
10632 }
10633
10634 /* spin until the given per-VL status mask bits clear */
10635 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
10636                                      const char *which)
10637 {
10638         unsigned long timeout;
10639         u64 reg;
10640
10641         timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
10642         while (1) {
10643                 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
10644
10645                 if (reg == 0)
10646                         return; /* success */
10647                 if (time_after(jiffies, timeout))
10648                         break;          /* timed out */
10649                 udelay(1);
10650         }
10651
10652         dd_dev_err(dd,
10653                    "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
10654                    which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
10655         /*
10656          * If this occurs, it is likely there was a credit loss on the link.
10657          * The only recovery from that is a link bounce.
10658          */
10659         dd_dev_err(dd,
10660                    "Continuing anyway.  A credit loss may occur.  Suggest a link bounce\n");
10661 }
10662
10663 /*
10664  * The number of credits on the VLs may be changed while everything
10665  * is "live", but the following algorithm must be followed due to
10666  * how the hardware is actually implemented.  In particular,
10667  * Return_Credit_Status[] is the only correct status check.
10668  *
10669  * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
10670  *     set Global_Shared_Credit_Limit = 0
10671  *     use_all_vl = 1
10672  * mask0 = all VLs that are changing either dedicated or shared limits
10673  * set Shared_Limit[mask0] = 0
10674  * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
10675  * if (changing any dedicated limit)
10676  *     mask1 = all VLs that are lowering dedicated limits
10677  *     lower Dedicated_Limit[mask1]
10678  *     spin until Return_Credit_Status[mask1] == 0
10679  *     raise Dedicated_Limits
10680  * raise Shared_Limits
10681  * raise Global_Shared_Credit_Limit
10682  *
10683  * lower = if the new limit is lower, set the limit to the new value
10684  * raise = if the new limit is higher than the current value (may be changed
10685  *      earlier in the algorithm), set the new limit to the new value
10686  */
10687 int set_buffer_control(struct hfi1_pportdata *ppd,
10688                        struct buffer_control *new_bc)
10689 {
10690         struct hfi1_devdata *dd = ppd->dd;
10691         u64 changing_mask, ld_mask, stat_mask;
10692         int change_count;
10693         int i, use_all_mask;
10694         int this_shared_changing;
10695         int vl_count = 0, ret;
10696         /*
10697          * A0: add the variable any_shared_limit_changing below and in the
10698          * algorithm above.  If removing A0 support, it can be removed.
10699          */
10700         int any_shared_limit_changing;
10701         struct buffer_control cur_bc;
10702         u8 changing[OPA_MAX_VLS];
10703         u8 lowering_dedicated[OPA_MAX_VLS];
10704         u16 cur_total;
10705         u32 new_total = 0;
10706         const u64 all_mask =
10707         SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
10708          | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
10709          | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
10710          | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
10711          | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
10712          | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
10713          | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
10714          | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
10715          | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
10716
10717 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
10718 #define NUM_USABLE_VLS 16       /* look at VL15 and less */
10719
10720         /* find the new total credits, do sanity check on unused VLs */
10721         for (i = 0; i < OPA_MAX_VLS; i++) {
10722                 if (valid_vl(i)) {
10723                         new_total += be16_to_cpu(new_bc->vl[i].dedicated);
10724                         continue;
10725                 }
10726                 nonzero_msg(dd, i, "dedicated",
10727                             be16_to_cpu(new_bc->vl[i].dedicated));
10728                 nonzero_msg(dd, i, "shared",
10729                             be16_to_cpu(new_bc->vl[i].shared));
10730                 new_bc->vl[i].dedicated = 0;
10731                 new_bc->vl[i].shared = 0;
10732         }
10733         new_total += be16_to_cpu(new_bc->overall_shared_limit);
10734
10735         /* fetch the current values */
10736         get_buffer_control(dd, &cur_bc, &cur_total);
10737
10738         /*
10739          * Create the masks we will use.
10740          */
10741         memset(changing, 0, sizeof(changing));
10742         memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
10743         /*
10744          * NOTE: Assumes that the individual VL bits are adjacent and in
10745          * increasing order
10746          */
10747         stat_mask =
10748                 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
10749         changing_mask = 0;
10750         ld_mask = 0;
10751         change_count = 0;
10752         any_shared_limit_changing = 0;
10753         for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
10754                 if (!valid_vl(i))
10755                         continue;
10756                 this_shared_changing = new_bc->vl[i].shared
10757                                                 != cur_bc.vl[i].shared;
10758                 if (this_shared_changing)
10759                         any_shared_limit_changing = 1;
10760                 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated ||
10761                     this_shared_changing) {
10762                         changing[i] = 1;
10763                         changing_mask |= stat_mask;
10764                         change_count++;
10765                 }
10766                 if (be16_to_cpu(new_bc->vl[i].dedicated) <
10767                                         be16_to_cpu(cur_bc.vl[i].dedicated)) {
10768                         lowering_dedicated[i] = 1;
10769                         ld_mask |= stat_mask;
10770                 }
10771         }
10772
10773         /* bracket the credit change with a total adjustment */
10774         if (new_total > cur_total)
10775                 set_global_limit(dd, new_total);
10776
10777         /*
10778          * Start the credit change algorithm.
10779          */
10780         use_all_mask = 0;
10781         if ((be16_to_cpu(new_bc->overall_shared_limit) <
10782              be16_to_cpu(cur_bc.overall_shared_limit)) ||
10783             (is_ax(dd) && any_shared_limit_changing)) {
10784                 set_global_shared(dd, 0);
10785                 cur_bc.overall_shared_limit = 0;
10786                 use_all_mask = 1;
10787         }
10788
10789         for (i = 0; i < NUM_USABLE_VLS; i++) {
10790                 if (!valid_vl(i))
10791                         continue;
10792
10793                 if (changing[i]) {
10794                         set_vl_shared(dd, i, 0);
10795                         cur_bc.vl[i].shared = 0;
10796                 }
10797         }
10798
10799         wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
10800                                  "shared");
10801
10802         if (change_count > 0) {
10803                 for (i = 0; i < NUM_USABLE_VLS; i++) {
10804                         if (!valid_vl(i))
10805                                 continue;
10806
10807                         if (lowering_dedicated[i]) {
10808                                 set_vl_dedicated(dd, i,
10809                                                  be16_to_cpu(new_bc->
10810                                                              vl[i].dedicated));
10811                                 cur_bc.vl[i].dedicated =
10812                                                 new_bc->vl[i].dedicated;
10813                         }
10814                 }
10815
10816                 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
10817
10818                 /* now raise all dedicated that are going up */
10819                 for (i = 0; i < NUM_USABLE_VLS; i++) {
10820                         if (!valid_vl(i))
10821                                 continue;
10822
10823                         if (be16_to_cpu(new_bc->vl[i].dedicated) >
10824                                         be16_to_cpu(cur_bc.vl[i].dedicated))
10825                                 set_vl_dedicated(dd, i,
10826                                                  be16_to_cpu(new_bc->
10827                                                              vl[i].dedicated));
10828                 }
10829         }
10830
10831         /* next raise all shared that are going up */
10832         for (i = 0; i < NUM_USABLE_VLS; i++) {
10833                 if (!valid_vl(i))
10834                         continue;
10835
10836                 if (be16_to_cpu(new_bc->vl[i].shared) >
10837                                 be16_to_cpu(cur_bc.vl[i].shared))
10838                         set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
10839         }
10840
10841         /* finally raise the global shared */
10842         if (be16_to_cpu(new_bc->overall_shared_limit) >
10843             be16_to_cpu(cur_bc.overall_shared_limit))
10844                 set_global_shared(dd,
10845                                   be16_to_cpu(new_bc->overall_shared_limit));
10846
10847         /* bracket the credit change with a total adjustment */
10848         if (new_total < cur_total)
10849                 set_global_limit(dd, new_total);
10850
10851         /*
10852          * Determine the actual number of operational VLS using the number of
10853          * dedicated and shared credits for each VL.
10854          */
10855         if (change_count > 0) {
10856                 for (i = 0; i < TXE_NUM_DATA_VL; i++)
10857                         if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
10858                             be16_to_cpu(new_bc->vl[i].shared) > 0)
10859                                 vl_count++;
10860                 ppd->actual_vls_operational = vl_count;
10861                 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
10862                                     ppd->actual_vls_operational :
10863                                     ppd->vls_operational,
10864                                     NULL);
10865                 if (ret == 0)
10866                         ret = pio_map_init(dd, ppd->port - 1, vl_count ?
10867                                            ppd->actual_vls_operational :
10868                                            ppd->vls_operational, NULL);
10869                 if (ret)
10870                         return ret;
10871         }
10872         return 0;
10873 }
10874
10875 /*
10876  * Read the given fabric manager table. Return the size of the
10877  * table (in bytes) on success, and a negative error code on
10878  * failure.
10879  */
10880 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
10881
10882 {
10883         int size;
10884         struct vl_arb_cache *vlc;
10885
10886         switch (which) {
10887         case FM_TBL_VL_HIGH_ARB:
10888                 size = 256;
10889                 /*
10890                  * OPA specifies 128 elements (of 2 bytes each), though
10891                  * HFI supports only 16 elements in h/w.
10892                  */
10893                 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
10894                 vl_arb_get_cache(vlc, t);
10895                 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
10896                 break;
10897         case FM_TBL_VL_LOW_ARB:
10898                 size = 256;
10899                 /*
10900                  * OPA specifies 128 elements (of 2 bytes each), though
10901                  * HFI supports only 16 elements in h/w.
10902                  */
10903                 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
10904                 vl_arb_get_cache(vlc, t);
10905                 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
10906                 break;
10907         case FM_TBL_BUFFER_CONTROL:
10908                 size = get_buffer_control(ppd->dd, t, NULL);
10909                 break;
10910         case FM_TBL_SC2VLNT:
10911                 size = get_sc2vlnt(ppd->dd, t);
10912                 break;
10913         case FM_TBL_VL_PREEMPT_ELEMS:
10914                 size = 256;
10915                 /* OPA specifies 128 elements, of 2 bytes each */
10916                 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
10917                 break;
10918         case FM_TBL_VL_PREEMPT_MATRIX:
10919                 size = 256;
10920                 /*
10921                  * OPA specifies that this is the same size as the VL
10922                  * arbitration tables (i.e., 256 bytes).
10923                  */
10924                 break;
10925         default:
10926                 return -EINVAL;
10927         }
10928         return size;
10929 }
10930
10931 /*
10932  * Write the given fabric manager table.
10933  */
10934 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
10935 {
10936         int ret = 0;
10937         struct vl_arb_cache *vlc;
10938
10939         switch (which) {
10940         case FM_TBL_VL_HIGH_ARB:
10941                 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
10942                 if (vl_arb_match_cache(vlc, t)) {
10943                         vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
10944                         break;
10945                 }
10946                 vl_arb_set_cache(vlc, t);
10947                 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
10948                 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
10949                                      VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
10950                 break;
10951         case FM_TBL_VL_LOW_ARB:
10952                 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
10953                 if (vl_arb_match_cache(vlc, t)) {
10954                         vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
10955                         break;
10956                 }
10957                 vl_arb_set_cache(vlc, t);
10958                 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
10959                 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
10960                                      VL_ARB_LOW_PRIO_TABLE_SIZE, t);
10961                 break;
10962         case FM_TBL_BUFFER_CONTROL:
10963                 ret = set_buffer_control(ppd, t);
10964                 break;
10965         case FM_TBL_SC2VLNT:
10966                 set_sc2vlnt(ppd->dd, t);
10967                 break;
10968         default:
10969                 ret = -EINVAL;
10970         }
10971         return ret;
10972 }
10973
10974 /*
10975  * Disable all data VLs.
10976  *
10977  * Return 0 if disabled, non-zero if the VLs cannot be disabled.
10978  */
10979 static int disable_data_vls(struct hfi1_devdata *dd)
10980 {
10981         if (is_ax(dd))
10982                 return 1;
10983
10984         pio_send_control(dd, PSC_DATA_VL_DISABLE);
10985
10986         return 0;
10987 }
10988
10989 /*
10990  * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
10991  * Just re-enables all data VLs (the "fill" part happens
10992  * automatically - the name was chosen for symmetry with
10993  * stop_drain_data_vls()).
10994  *
10995  * Return 0 if successful, non-zero if the VLs cannot be enabled.
10996  */
10997 int open_fill_data_vls(struct hfi1_devdata *dd)
10998 {
10999         if (is_ax(dd))
11000                 return 1;
11001
11002         pio_send_control(dd, PSC_DATA_VL_ENABLE);
11003
11004         return 0;
11005 }
11006
11007 /*
11008  * drain_data_vls() - assumes that disable_data_vls() has been called,
11009  * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11010  * engines to drop to 0.
11011  */
11012 static void drain_data_vls(struct hfi1_devdata *dd)
11013 {
11014         sc_wait(dd);
11015         sdma_wait(dd);
11016         pause_for_credit_return(dd);
11017 }
11018
11019 /*
11020  * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11021  *
11022  * Use open_fill_data_vls() to resume using data VLs.  This pair is
11023  * meant to be used like this:
11024  *
11025  * stop_drain_data_vls(dd);
11026  * // do things with per-VL resources
11027  * open_fill_data_vls(dd);
11028  */
11029 int stop_drain_data_vls(struct hfi1_devdata *dd)
11030 {
11031         int ret;
11032
11033         ret = disable_data_vls(dd);
11034         if (ret == 0)
11035                 drain_data_vls(dd);
11036
11037         return ret;
11038 }
11039
11040 /*
11041  * Convert a nanosecond time to a cclock count.  No matter how slow
11042  * the cclock, a non-zero ns will always have a non-zero result.
11043  */
11044 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11045 {
11046         u32 cclocks;
11047
11048         if (dd->icode == ICODE_FPGA_EMULATION)
11049                 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11050         else  /* simulation pretends to be ASIC */
11051                 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11052         if (ns && !cclocks)     /* if ns nonzero, must be at least 1 */
11053                 cclocks = 1;
11054         return cclocks;
11055 }
11056
11057 /*
11058  * Convert a cclock count to nanoseconds. Not matter how slow
11059  * the cclock, a non-zero cclocks will always have a non-zero result.
11060  */
11061 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11062 {
11063         u32 ns;
11064
11065         if (dd->icode == ICODE_FPGA_EMULATION)
11066                 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11067         else  /* simulation pretends to be ASIC */
11068                 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11069         if (cclocks && !ns)
11070                 ns = 1;
11071         return ns;
11072 }
11073
11074 /*
11075  * Dynamically adjust the receive interrupt timeout for a context based on
11076  * incoming packet rate.
11077  *
11078  * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11079  */
11080 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11081 {
11082         struct hfi1_devdata *dd = rcd->dd;
11083         u32 timeout = rcd->rcvavail_timeout;
11084
11085         /*
11086          * This algorithm doubles or halves the timeout depending on whether
11087          * the number of packets received in this interrupt were less than or
11088          * greater equal the interrupt count.
11089          *
11090          * The calculations below do not allow a steady state to be achieved.
11091          * Only at the endpoints it is possible to have an unchanging
11092          * timeout.
11093          */
11094         if (npkts < rcv_intr_count) {
11095                 /*
11096                  * Not enough packets arrived before the timeout, adjust
11097                  * timeout downward.
11098                  */
11099                 if (timeout < 2) /* already at minimum? */
11100                         return;
11101                 timeout >>= 1;
11102         } else {
11103                 /*
11104                  * More than enough packets arrived before the timeout, adjust
11105                  * timeout upward.
11106                  */
11107                 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11108                         return;
11109                 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11110         }
11111
11112         rcd->rcvavail_timeout = timeout;
11113         /*
11114          * timeout cannot be larger than rcv_intr_timeout_csr which has already
11115          * been verified to be in range
11116          */
11117         write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11118                         (u64)timeout <<
11119                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11120 }
11121
11122 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11123                     u32 intr_adjust, u32 npkts)
11124 {
11125         struct hfi1_devdata *dd = rcd->dd;
11126         u64 reg;
11127         u32 ctxt = rcd->ctxt;
11128
11129         /*
11130          * Need to write timeout register before updating RcvHdrHead to ensure
11131          * that a new value is used when the HW decides to restart counting.
11132          */
11133         if (intr_adjust)
11134                 adjust_rcv_timeout(rcd, npkts);
11135         if (updegr) {
11136                 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11137                         << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11138                 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11139         }
11140         mmiowb();
11141         reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11142                 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11143                         << RCV_HDR_HEAD_HEAD_SHIFT);
11144         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11145         mmiowb();
11146 }
11147
11148 u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11149 {
11150         u32 head, tail;
11151
11152         head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11153                 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11154
11155         if (rcd->rcvhdrtail_kvaddr)
11156                 tail = get_rcvhdrtail(rcd);
11157         else
11158                 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11159
11160         return head == tail;
11161 }
11162
11163 /*
11164  * Context Control and Receive Array encoding for buffer size:
11165  *      0x0 invalid
11166  *      0x1   4 KB
11167  *      0x2   8 KB
11168  *      0x3  16 KB
11169  *      0x4  32 KB
11170  *      0x5  64 KB
11171  *      0x6 128 KB
11172  *      0x7 256 KB
11173  *      0x8 512 KB (Receive Array only)
11174  *      0x9   1 MB (Receive Array only)
11175  *      0xa   2 MB (Receive Array only)
11176  *
11177  *      0xB-0xF - reserved (Receive Array only)
11178  *
11179  *
11180  * This routine assumes that the value has already been sanity checked.
11181  */
11182 static u32 encoded_size(u32 size)
11183 {
11184         switch (size) {
11185         case   4 * 1024: return 0x1;
11186         case   8 * 1024: return 0x2;
11187         case  16 * 1024: return 0x3;
11188         case  32 * 1024: return 0x4;
11189         case  64 * 1024: return 0x5;
11190         case 128 * 1024: return 0x6;
11191         case 256 * 1024: return 0x7;
11192         case 512 * 1024: return 0x8;
11193         case   1 * 1024 * 1024: return 0x9;
11194         case   2 * 1024 * 1024: return 0xa;
11195         }
11196         return 0x1;     /* if invalid, go with the minimum size */
11197 }
11198
11199 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt)
11200 {
11201         struct hfi1_ctxtdata *rcd;
11202         u64 rcvctrl, reg;
11203         int did_enable = 0;
11204
11205         rcd = dd->rcd[ctxt];
11206         if (!rcd)
11207                 return;
11208
11209         hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11210
11211         rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11212         /* if the context already enabled, don't do the extra steps */
11213         if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11214             !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
11215                 /* reset the tail and hdr addresses, and sequence count */
11216                 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
11217                                 rcd->rcvhdrq_phys);
11218                 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11219                         write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11220                                         rcd->rcvhdrqtailaddr_phys);
11221                 rcd->seq_cnt = 1;
11222
11223                 /* reset the cached receive header queue head value */
11224                 rcd->head = 0;
11225
11226                 /*
11227                  * Zero the receive header queue so we don't get false
11228                  * positives when checking the sequence number.  The
11229                  * sequence numbers could land exactly on the same spot.
11230                  * E.g. a rcd restart before the receive header wrapped.
11231                  */
11232                 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
11233
11234                 /* starting timeout */
11235                 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
11236
11237                 /* enable the context */
11238                 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
11239
11240                 /* clean the egr buffer size first */
11241                 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11242                 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
11243                                 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
11244                                         << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
11245
11246                 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11247                 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
11248                 did_enable = 1;
11249
11250                 /* zero RcvEgrIndexHead */
11251                 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
11252
11253                 /* set eager count and base index */
11254                 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
11255                         & RCV_EGR_CTRL_EGR_CNT_MASK)
11256                        << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
11257                         (((rcd->eager_base >> RCV_SHIFT)
11258                           & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
11259                          << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
11260                 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
11261
11262                 /*
11263                  * Set TID (expected) count and base index.
11264                  * rcd->expected_count is set to individual RcvArray entries,
11265                  * not pairs, and the CSR takes a pair-count in groups of
11266                  * four, so divide by 8.
11267                  */
11268                 reg = (((rcd->expected_count >> RCV_SHIFT)
11269                                         & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
11270                                 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
11271                       (((rcd->expected_base >> RCV_SHIFT)
11272                                         & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
11273                                 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
11274                 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
11275                 if (ctxt == HFI1_CTRL_CTXT)
11276                         write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
11277         }
11278         if (op & HFI1_RCVCTRL_CTXT_DIS) {
11279                 write_csr(dd, RCV_VL15, 0);
11280                 /*
11281                  * When receive context is being disabled turn on tail
11282                  * update with a dummy tail address and then disable
11283                  * receive context.
11284                  */
11285                 if (dd->rcvhdrtail_dummy_physaddr) {
11286                         write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11287                                         dd->rcvhdrtail_dummy_physaddr);
11288                         /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
11289                         rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11290                 }
11291
11292                 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11293         }
11294         if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11295                 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11296         if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11297                 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11298         if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_phys)
11299                 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11300         if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11301                 /* See comment on RcvCtxtCtrl.TailUpd above */
11302                 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11303                         rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11304         }
11305         if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11306                 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11307         if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
11308                 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11309         if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
11310                 /*
11311                  * In one-packet-per-eager mode, the size comes from
11312                  * the RcvArray entry.
11313                  */
11314                 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11315                 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11316         }
11317         if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
11318                 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11319         if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
11320                 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11321         if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
11322                 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11323         if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
11324                 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11325         if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
11326                 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11327         rcd->rcvctrl = rcvctrl;
11328         hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
11329         write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl);
11330
11331         /* work around sticky RcvCtxtStatus.BlockedRHQFull */
11332         if (did_enable &&
11333             (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
11334                 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11335                 if (reg != 0) {
11336                         dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
11337                                     ctxt, reg);
11338                         read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11339                         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
11340                         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
11341                         read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11342                         reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11343                         dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
11344                                     ctxt, reg, reg == 0 ? "not" : "still");
11345                 }
11346         }
11347
11348         if (did_enable) {
11349                 /*
11350                  * The interrupt timeout and count must be set after
11351                  * the context is enabled to take effect.
11352                  */
11353                 /* set interrupt timeout */
11354                 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
11355                                 (u64)rcd->rcvavail_timeout <<
11356                                 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11357
11358                 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11359                 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
11360                 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11361         }
11362
11363         if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11364                 /*
11365                  * If the context has been disabled and the Tail Update has
11366                  * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11367                  * so it doesn't contain an address that is invalid.
11368                  */
11369                 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11370                                 dd->rcvhdrtail_dummy_physaddr);
11371 }
11372
11373 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
11374 {
11375         int ret;
11376         u64 val = 0;
11377
11378         if (namep) {
11379                 ret = dd->cntrnameslen;
11380                 *namep = dd->cntrnames;
11381         } else {
11382                 const struct cntr_entry *entry;
11383                 int i, j;
11384
11385                 ret = (dd->ndevcntrs) * sizeof(u64);
11386
11387                 /* Get the start of the block of counters */
11388                 *cntrp = dd->cntrs;
11389
11390                 /*
11391                  * Now go and fill in each counter in the block.
11392                  */
11393                 for (i = 0; i < DEV_CNTR_LAST; i++) {
11394                         entry = &dev_cntrs[i];
11395                         hfi1_cdbg(CNTR, "reading %s", entry->name);
11396                         if (entry->flags & CNTR_DISABLED) {
11397                                 /* Nothing */
11398                                 hfi1_cdbg(CNTR, "\tDisabled\n");
11399                         } else {
11400                                 if (entry->flags & CNTR_VL) {
11401                                         hfi1_cdbg(CNTR, "\tPer VL\n");
11402                                         for (j = 0; j < C_VL_COUNT; j++) {
11403                                                 val = entry->rw_cntr(entry,
11404                                                                   dd, j,
11405                                                                   CNTR_MODE_R,
11406                                                                   0);
11407                                                 hfi1_cdbg(
11408                                                    CNTR,
11409                                                    "\t\tRead 0x%llx for %d\n",
11410                                                    val, j);
11411                                                 dd->cntrs[entry->offset + j] =
11412                                                                             val;
11413                                         }
11414                                 } else if (entry->flags & CNTR_SDMA) {
11415                                         hfi1_cdbg(CNTR,
11416                                                   "\t Per SDMA Engine\n");
11417                                         for (j = 0; j < dd->chip_sdma_engines;
11418                                              j++) {
11419                                                 val =
11420                                                 entry->rw_cntr(entry, dd, j,
11421                                                                CNTR_MODE_R, 0);
11422                                                 hfi1_cdbg(CNTR,
11423                                                           "\t\tRead 0x%llx for %d\n",
11424                                                           val, j);
11425                                                 dd->cntrs[entry->offset + j] =
11426                                                                         val;
11427                                         }
11428                                 } else {
11429                                         val = entry->rw_cntr(entry, dd,
11430                                                         CNTR_INVALID_VL,
11431                                                         CNTR_MODE_R, 0);
11432                                         dd->cntrs[entry->offset] = val;
11433                                         hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11434                                 }
11435                         }
11436                 }
11437         }
11438         return ret;
11439 }
11440
11441 /*
11442  * Used by sysfs to create files for hfi stats to read
11443  */
11444 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp)
11445 {
11446         int ret;
11447         u64 val = 0;
11448
11449         if (namep) {
11450                 ret = ppd->dd->portcntrnameslen;
11451                 *namep = ppd->dd->portcntrnames;
11452         } else {
11453                 const struct cntr_entry *entry;
11454                 int i, j;
11455
11456                 ret = ppd->dd->nportcntrs * sizeof(u64);
11457                 *cntrp = ppd->cntrs;
11458
11459                 for (i = 0; i < PORT_CNTR_LAST; i++) {
11460                         entry = &port_cntrs[i];
11461                         hfi1_cdbg(CNTR, "reading %s", entry->name);
11462                         if (entry->flags & CNTR_DISABLED) {
11463                                 /* Nothing */
11464                                 hfi1_cdbg(CNTR, "\tDisabled\n");
11465                                 continue;
11466                         }
11467
11468                         if (entry->flags & CNTR_VL) {
11469                                 hfi1_cdbg(CNTR, "\tPer VL");
11470                                 for (j = 0; j < C_VL_COUNT; j++) {
11471                                         val = entry->rw_cntr(entry, ppd, j,
11472                                                                CNTR_MODE_R,
11473                                                                0);
11474                                         hfi1_cdbg(
11475                                            CNTR,
11476                                            "\t\tRead 0x%llx for %d",
11477                                            val, j);
11478                                         ppd->cntrs[entry->offset + j] = val;
11479                                 }
11480                         } else {
11481                                 val = entry->rw_cntr(entry, ppd,
11482                                                        CNTR_INVALID_VL,
11483                                                        CNTR_MODE_R,
11484                                                        0);
11485                                 ppd->cntrs[entry->offset] = val;
11486                                 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11487                         }
11488                 }
11489         }
11490         return ret;
11491 }
11492
11493 static void free_cntrs(struct hfi1_devdata *dd)
11494 {
11495         struct hfi1_pportdata *ppd;
11496         int i;
11497
11498         if (dd->synth_stats_timer.data)
11499                 del_timer_sync(&dd->synth_stats_timer);
11500         dd->synth_stats_timer.data = 0;
11501         ppd = (struct hfi1_pportdata *)(dd + 1);
11502         for (i = 0; i < dd->num_pports; i++, ppd++) {
11503                 kfree(ppd->cntrs);
11504                 kfree(ppd->scntrs);
11505                 free_percpu(ppd->ibport_data.rvp.rc_acks);
11506                 free_percpu(ppd->ibport_data.rvp.rc_qacks);
11507                 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
11508                 ppd->cntrs = NULL;
11509                 ppd->scntrs = NULL;
11510                 ppd->ibport_data.rvp.rc_acks = NULL;
11511                 ppd->ibport_data.rvp.rc_qacks = NULL;
11512                 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
11513         }
11514         kfree(dd->portcntrnames);
11515         dd->portcntrnames = NULL;
11516         kfree(dd->cntrs);
11517         dd->cntrs = NULL;
11518         kfree(dd->scntrs);
11519         dd->scntrs = NULL;
11520         kfree(dd->cntrnames);
11521         dd->cntrnames = NULL;
11522 }
11523
11524 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
11525 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
11526
11527 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
11528                               u64 *psval, void *context, int vl)
11529 {
11530         u64 val;
11531         u64 sval = *psval;
11532
11533         if (entry->flags & CNTR_DISABLED) {
11534                 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11535                 return 0;
11536         }
11537
11538         hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11539
11540         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
11541
11542         /* If its a synthetic counter there is more work we need to do */
11543         if (entry->flags & CNTR_SYNTH) {
11544                 if (sval == CNTR_MAX) {
11545                         /* No need to read already saturated */
11546                         return CNTR_MAX;
11547                 }
11548
11549                 if (entry->flags & CNTR_32BIT) {
11550                         /* 32bit counters can wrap multiple times */
11551                         u64 upper = sval >> 32;
11552                         u64 lower = (sval << 32) >> 32;
11553
11554                         if (lower > val) { /* hw wrapped */
11555                                 if (upper == CNTR_32BIT_MAX)
11556                                         val = CNTR_MAX;
11557                                 else
11558                                         upper++;
11559                         }
11560
11561                         if (val != CNTR_MAX)
11562                                 val = (upper << 32) | val;
11563
11564                 } else {
11565                         /* If we rolled we are saturated */
11566                         if ((val < sval) || (val > CNTR_MAX))
11567                                 val = CNTR_MAX;
11568                 }
11569         }
11570
11571         *psval = val;
11572
11573         hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11574
11575         return val;
11576 }
11577
11578 static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
11579                                struct cntr_entry *entry,
11580                                u64 *psval, void *context, int vl, u64 data)
11581 {
11582         u64 val;
11583
11584         if (entry->flags & CNTR_DISABLED) {
11585                 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11586                 return 0;
11587         }
11588
11589         hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11590
11591         if (entry->flags & CNTR_SYNTH) {
11592                 *psval = data;
11593                 if (entry->flags & CNTR_32BIT) {
11594                         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11595                                              (data << 32) >> 32);
11596                         val = data; /* return the full 64bit value */
11597                 } else {
11598                         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11599                                              data);
11600                 }
11601         } else {
11602                 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
11603         }
11604
11605         *psval = val;
11606
11607         hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11608
11609         return val;
11610 }
11611
11612 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
11613 {
11614         struct cntr_entry *entry;
11615         u64 *sval;
11616
11617         entry = &dev_cntrs[index];
11618         sval = dd->scntrs + entry->offset;
11619
11620         if (vl != CNTR_INVALID_VL)
11621                 sval += vl;
11622
11623         return read_dev_port_cntr(dd, entry, sval, dd, vl);
11624 }
11625
11626 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
11627 {
11628         struct cntr_entry *entry;
11629         u64 *sval;
11630
11631         entry = &dev_cntrs[index];
11632         sval = dd->scntrs + entry->offset;
11633
11634         if (vl != CNTR_INVALID_VL)
11635                 sval += vl;
11636
11637         return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
11638 }
11639
11640 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
11641 {
11642         struct cntr_entry *entry;
11643         u64 *sval;
11644
11645         entry = &port_cntrs[index];
11646         sval = ppd->scntrs + entry->offset;
11647
11648         if (vl != CNTR_INVALID_VL)
11649                 sval += vl;
11650
11651         if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11652             (index <= C_RCV_HDR_OVF_LAST)) {
11653                 /* We do not want to bother for disabled contexts */
11654                 return 0;
11655         }
11656
11657         return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
11658 }
11659
11660 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
11661 {
11662         struct cntr_entry *entry;
11663         u64 *sval;
11664
11665         entry = &port_cntrs[index];
11666         sval = ppd->scntrs + entry->offset;
11667
11668         if (vl != CNTR_INVALID_VL)
11669                 sval += vl;
11670
11671         if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11672             (index <= C_RCV_HDR_OVF_LAST)) {
11673                 /* We do not want to bother for disabled contexts */
11674                 return 0;
11675         }
11676
11677         return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
11678 }
11679
11680 static void update_synth_timer(unsigned long opaque)
11681 {
11682         u64 cur_tx;
11683         u64 cur_rx;
11684         u64 total_flits;
11685         u8 update = 0;
11686         int i, j, vl;
11687         struct hfi1_pportdata *ppd;
11688         struct cntr_entry *entry;
11689
11690         struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
11691
11692         /*
11693          * Rather than keep beating on the CSRs pick a minimal set that we can
11694          * check to watch for potential roll over. We can do this by looking at
11695          * the number of flits sent/recv. If the total flits exceeds 32bits then
11696          * we have to iterate all the counters and update.
11697          */
11698         entry = &dev_cntrs[C_DC_RCV_FLITS];
11699         cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11700
11701         entry = &dev_cntrs[C_DC_XMIT_FLITS];
11702         cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11703
11704         hfi1_cdbg(
11705             CNTR,
11706             "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
11707             dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
11708
11709         if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
11710                 /*
11711                  * May not be strictly necessary to update but it won't hurt and
11712                  * simplifies the logic here.
11713                  */
11714                 update = 1;
11715                 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
11716                           dd->unit);
11717         } else {
11718                 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
11719                 hfi1_cdbg(CNTR,
11720                           "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
11721                           total_flits, (u64)CNTR_32BIT_MAX);
11722                 if (total_flits >= CNTR_32BIT_MAX) {
11723                         hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
11724                                   dd->unit);
11725                         update = 1;
11726                 }
11727         }
11728
11729         if (update) {
11730                 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
11731                 for (i = 0; i < DEV_CNTR_LAST; i++) {
11732                         entry = &dev_cntrs[i];
11733                         if (entry->flags & CNTR_VL) {
11734                                 for (vl = 0; vl < C_VL_COUNT; vl++)
11735                                         read_dev_cntr(dd, i, vl);
11736                         } else {
11737                                 read_dev_cntr(dd, i, CNTR_INVALID_VL);
11738                         }
11739                 }
11740                 ppd = (struct hfi1_pportdata *)(dd + 1);
11741                 for (i = 0; i < dd->num_pports; i++, ppd++) {
11742                         for (j = 0; j < PORT_CNTR_LAST; j++) {
11743                                 entry = &port_cntrs[j];
11744                                 if (entry->flags & CNTR_VL) {
11745                                         for (vl = 0; vl < C_VL_COUNT; vl++)
11746                                                 read_port_cntr(ppd, j, vl);
11747                                 } else {
11748                                         read_port_cntr(ppd, j, CNTR_INVALID_VL);
11749                                 }
11750                         }
11751                 }
11752
11753                 /*
11754                  * We want the value in the register. The goal is to keep track
11755                  * of the number of "ticks" not the counter value. In other
11756                  * words if the register rolls we want to notice it and go ahead
11757                  * and force an update.
11758                  */
11759                 entry = &dev_cntrs[C_DC_XMIT_FLITS];
11760                 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
11761                                                 CNTR_MODE_R, 0);
11762
11763                 entry = &dev_cntrs[C_DC_RCV_FLITS];
11764                 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
11765                                                 CNTR_MODE_R, 0);
11766
11767                 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
11768                           dd->unit, dd->last_tx, dd->last_rx);
11769
11770         } else {
11771                 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
11772         }
11773
11774 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
11775 }
11776
11777 #define C_MAX_NAME 13 /* 12 chars + one for /0 */
11778 static int init_cntrs(struct hfi1_devdata *dd)
11779 {
11780         int i, rcv_ctxts, j;
11781         size_t sz;
11782         char *p;
11783         char name[C_MAX_NAME];
11784         struct hfi1_pportdata *ppd;
11785         const char *bit_type_32 = ",32";
11786         const int bit_type_32_sz = strlen(bit_type_32);
11787
11788         /* set up the stats timer; the add_timer is done at the end */
11789         setup_timer(&dd->synth_stats_timer, update_synth_timer,
11790                     (unsigned long)dd);
11791
11792         /***********************/
11793         /* per device counters */
11794         /***********************/
11795
11796         /* size names and determine how many we have*/
11797         dd->ndevcntrs = 0;
11798         sz = 0;
11799
11800         for (i = 0; i < DEV_CNTR_LAST; i++) {
11801                 if (dev_cntrs[i].flags & CNTR_DISABLED) {
11802                         hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
11803                         continue;
11804                 }
11805
11806                 if (dev_cntrs[i].flags & CNTR_VL) {
11807                         dev_cntrs[i].offset = dd->ndevcntrs;
11808                         for (j = 0; j < C_VL_COUNT; j++) {
11809                                 snprintf(name, C_MAX_NAME, "%s%d",
11810                                          dev_cntrs[i].name, vl_from_idx(j));
11811                                 sz += strlen(name);
11812                                 /* Add ",32" for 32-bit counters */
11813                                 if (dev_cntrs[i].flags & CNTR_32BIT)
11814                                         sz += bit_type_32_sz;
11815                                 sz++;
11816                                 dd->ndevcntrs++;
11817                         }
11818                 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
11819                         dev_cntrs[i].offset = dd->ndevcntrs;
11820                         for (j = 0; j < dd->chip_sdma_engines; j++) {
11821                                 snprintf(name, C_MAX_NAME, "%s%d",
11822                                          dev_cntrs[i].name, j);
11823                                 sz += strlen(name);
11824                                 /* Add ",32" for 32-bit counters */
11825                                 if (dev_cntrs[i].flags & CNTR_32BIT)
11826                                         sz += bit_type_32_sz;
11827                                 sz++;
11828                                 dd->ndevcntrs++;
11829                         }
11830                 } else {
11831                         /* +1 for newline. */
11832                         sz += strlen(dev_cntrs[i].name) + 1;
11833                         /* Add ",32" for 32-bit counters */
11834                         if (dev_cntrs[i].flags & CNTR_32BIT)
11835                                 sz += bit_type_32_sz;
11836                         dev_cntrs[i].offset = dd->ndevcntrs;
11837                         dd->ndevcntrs++;
11838                 }
11839         }
11840
11841         /* allocate space for the counter values */
11842         dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
11843         if (!dd->cntrs)
11844                 goto bail;
11845
11846         dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
11847         if (!dd->scntrs)
11848                 goto bail;
11849
11850         /* allocate space for the counter names */
11851         dd->cntrnameslen = sz;
11852         dd->cntrnames = kmalloc(sz, GFP_KERNEL);
11853         if (!dd->cntrnames)
11854                 goto bail;
11855
11856         /* fill in the names */
11857         for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
11858                 if (dev_cntrs[i].flags & CNTR_DISABLED) {
11859                         /* Nothing */
11860                 } else if (dev_cntrs[i].flags & CNTR_VL) {
11861                         for (j = 0; j < C_VL_COUNT; j++) {
11862                                 snprintf(name, C_MAX_NAME, "%s%d",
11863                                          dev_cntrs[i].name,
11864                                          vl_from_idx(j));
11865                                 memcpy(p, name, strlen(name));
11866                                 p += strlen(name);
11867
11868                                 /* Counter is 32 bits */
11869                                 if (dev_cntrs[i].flags & CNTR_32BIT) {
11870                                         memcpy(p, bit_type_32, bit_type_32_sz);
11871                                         p += bit_type_32_sz;
11872                                 }
11873
11874                                 *p++ = '\n';
11875                         }
11876                 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
11877                         for (j = 0; j < dd->chip_sdma_engines; j++) {
11878                                 snprintf(name, C_MAX_NAME, "%s%d",
11879                                          dev_cntrs[i].name, j);
11880                                 memcpy(p, name, strlen(name));
11881                                 p += strlen(name);
11882
11883                                 /* Counter is 32 bits */
11884                                 if (dev_cntrs[i].flags & CNTR_32BIT) {
11885                                         memcpy(p, bit_type_32, bit_type_32_sz);
11886                                         p += bit_type_32_sz;
11887                                 }
11888
11889                                 *p++ = '\n';
11890                         }
11891                 } else {
11892                         memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
11893                         p += strlen(dev_cntrs[i].name);
11894
11895                         /* Counter is 32 bits */
11896                         if (dev_cntrs[i].flags & CNTR_32BIT) {
11897                                 memcpy(p, bit_type_32, bit_type_32_sz);
11898                                 p += bit_type_32_sz;
11899                         }
11900
11901                         *p++ = '\n';
11902                 }
11903         }
11904
11905         /*********************/
11906         /* per port counters */
11907         /*********************/
11908
11909         /*
11910          * Go through the counters for the overflows and disable the ones we
11911          * don't need. This varies based on platform so we need to do it
11912          * dynamically here.
11913          */
11914         rcv_ctxts = dd->num_rcv_contexts;
11915         for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
11916              i <= C_RCV_HDR_OVF_LAST; i++) {
11917                 port_cntrs[i].flags |= CNTR_DISABLED;
11918         }
11919
11920         /* size port counter names and determine how many we have*/
11921         sz = 0;
11922         dd->nportcntrs = 0;
11923         for (i = 0; i < PORT_CNTR_LAST; i++) {
11924                 if (port_cntrs[i].flags & CNTR_DISABLED) {
11925                         hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
11926                         continue;
11927                 }
11928
11929                 if (port_cntrs[i].flags & CNTR_VL) {
11930                         port_cntrs[i].offset = dd->nportcntrs;
11931                         for (j = 0; j < C_VL_COUNT; j++) {
11932                                 snprintf(name, C_MAX_NAME, "%s%d",
11933                                          port_cntrs[i].name, vl_from_idx(j));
11934                                 sz += strlen(name);
11935                                 /* Add ",32" for 32-bit counters */
11936                                 if (port_cntrs[i].flags & CNTR_32BIT)
11937                                         sz += bit_type_32_sz;
11938                                 sz++;
11939                                 dd->nportcntrs++;
11940                         }
11941                 } else {
11942                         /* +1 for newline */
11943                         sz += strlen(port_cntrs[i].name) + 1;
11944                         /* Add ",32" for 32-bit counters */
11945                         if (port_cntrs[i].flags & CNTR_32BIT)
11946                                 sz += bit_type_32_sz;
11947                         port_cntrs[i].offset = dd->nportcntrs;
11948                         dd->nportcntrs++;
11949                 }
11950         }
11951
11952         /* allocate space for the counter names */
11953         dd->portcntrnameslen = sz;
11954         dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
11955         if (!dd->portcntrnames)
11956                 goto bail;
11957
11958         /* fill in port cntr names */
11959         for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
11960                 if (port_cntrs[i].flags & CNTR_DISABLED)
11961                         continue;
11962
11963                 if (port_cntrs[i].flags & CNTR_VL) {
11964                         for (j = 0; j < C_VL_COUNT; j++) {
11965                                 snprintf(name, C_MAX_NAME, "%s%d",
11966                                          port_cntrs[i].name, vl_from_idx(j));
11967                                 memcpy(p, name, strlen(name));
11968                                 p += strlen(name);
11969
11970                                 /* Counter is 32 bits */
11971                                 if (port_cntrs[i].flags & CNTR_32BIT) {
11972                                         memcpy(p, bit_type_32, bit_type_32_sz);
11973                                         p += bit_type_32_sz;
11974                                 }
11975
11976                                 *p++ = '\n';
11977                         }
11978                 } else {
11979                         memcpy(p, port_cntrs[i].name,
11980                                strlen(port_cntrs[i].name));
11981                         p += strlen(port_cntrs[i].name);
11982
11983                         /* Counter is 32 bits */
11984                         if (port_cntrs[i].flags & CNTR_32BIT) {
11985                                 memcpy(p, bit_type_32, bit_type_32_sz);
11986                                 p += bit_type_32_sz;
11987                         }
11988
11989                         *p++ = '\n';
11990                 }
11991         }
11992
11993         /* allocate per port storage for counter values */
11994         ppd = (struct hfi1_pportdata *)(dd + 1);
11995         for (i = 0; i < dd->num_pports; i++, ppd++) {
11996                 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
11997                 if (!ppd->cntrs)
11998                         goto bail;
11999
12000                 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12001                 if (!ppd->scntrs)
12002                         goto bail;
12003         }
12004
12005         /* CPU counters need to be allocated and zeroed */
12006         if (init_cpu_counters(dd))
12007                 goto bail;
12008
12009         mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12010         return 0;
12011 bail:
12012         free_cntrs(dd);
12013         return -ENOMEM;
12014 }
12015
12016 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12017 {
12018         switch (chip_lstate) {
12019         default:
12020                 dd_dev_err(dd,
12021                            "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12022                            chip_lstate);
12023                 /* fall through */
12024         case LSTATE_DOWN:
12025                 return IB_PORT_DOWN;
12026         case LSTATE_INIT:
12027                 return IB_PORT_INIT;
12028         case LSTATE_ARMED:
12029                 return IB_PORT_ARMED;
12030         case LSTATE_ACTIVE:
12031                 return IB_PORT_ACTIVE;
12032         }
12033 }
12034
12035 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12036 {
12037         /* look at the HFI meta-states only */
12038         switch (chip_pstate & 0xf0) {
12039         default:
12040                 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
12041                            chip_pstate);
12042                 /* fall through */
12043         case PLS_DISABLED:
12044                 return IB_PORTPHYSSTATE_DISABLED;
12045         case PLS_OFFLINE:
12046                 return OPA_PORTPHYSSTATE_OFFLINE;
12047         case PLS_POLLING:
12048                 return IB_PORTPHYSSTATE_POLLING;
12049         case PLS_CONFIGPHY:
12050                 return IB_PORTPHYSSTATE_TRAINING;
12051         case PLS_LINKUP:
12052                 return IB_PORTPHYSSTATE_LINKUP;
12053         case PLS_PHYTEST:
12054                 return IB_PORTPHYSSTATE_PHY_TEST;
12055         }
12056 }
12057
12058 /* return the OPA port logical state name */
12059 const char *opa_lstate_name(u32 lstate)
12060 {
12061         static const char * const port_logical_names[] = {
12062                 "PORT_NOP",
12063                 "PORT_DOWN",
12064                 "PORT_INIT",
12065                 "PORT_ARMED",
12066                 "PORT_ACTIVE",
12067                 "PORT_ACTIVE_DEFER",
12068         };
12069         if (lstate < ARRAY_SIZE(port_logical_names))
12070                 return port_logical_names[lstate];
12071         return "unknown";
12072 }
12073
12074 /* return the OPA port physical state name */
12075 const char *opa_pstate_name(u32 pstate)
12076 {
12077         static const char * const port_physical_names[] = {
12078                 "PHYS_NOP",
12079                 "reserved1",
12080                 "PHYS_POLL",
12081                 "PHYS_DISABLED",
12082                 "PHYS_TRAINING",
12083                 "PHYS_LINKUP",
12084                 "PHYS_LINK_ERR_RECOVER",
12085                 "PHYS_PHY_TEST",
12086                 "reserved8",
12087                 "PHYS_OFFLINE",
12088                 "PHYS_GANGED",
12089                 "PHYS_TEST",
12090         };
12091         if (pstate < ARRAY_SIZE(port_physical_names))
12092                 return port_physical_names[pstate];
12093         return "unknown";
12094 }
12095
12096 /*
12097  * Read the hardware link state and set the driver's cached value of it.
12098  * Return the (new) current value.
12099  */
12100 u32 get_logical_state(struct hfi1_pportdata *ppd)
12101 {
12102         u32 new_state;
12103
12104         new_state = chip_to_opa_lstate(ppd->dd, read_logical_state(ppd->dd));
12105         if (new_state != ppd->lstate) {
12106                 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
12107                             opa_lstate_name(new_state), new_state);
12108                 ppd->lstate = new_state;
12109         }
12110         /*
12111          * Set port status flags in the page mapped into userspace
12112          * memory. Do it here to ensure a reliable state - this is
12113          * the only function called by all state handling code.
12114          * Always set the flags due to the fact that the cache value
12115          * might have been changed explicitly outside of this
12116          * function.
12117          */
12118         if (ppd->statusp) {
12119                 switch (ppd->lstate) {
12120                 case IB_PORT_DOWN:
12121                 case IB_PORT_INIT:
12122                         *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12123                                            HFI1_STATUS_IB_READY);
12124                         break;
12125                 case IB_PORT_ARMED:
12126                         *ppd->statusp |= HFI1_STATUS_IB_CONF;
12127                         break;
12128                 case IB_PORT_ACTIVE:
12129                         *ppd->statusp |= HFI1_STATUS_IB_READY;
12130                         break;
12131                 }
12132         }
12133         return ppd->lstate;
12134 }
12135
12136 /**
12137  * wait_logical_linkstate - wait for an IB link state change to occur
12138  * @ppd: port device
12139  * @state: the state to wait for
12140  * @msecs: the number of milliseconds to wait
12141  *
12142  * Wait up to msecs milliseconds for IB link state change to occur.
12143  * For now, take the easy polling route.
12144  * Returns 0 if state reached, otherwise -ETIMEDOUT.
12145  */
12146 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12147                                   int msecs)
12148 {
12149         unsigned long timeout;
12150
12151         timeout = jiffies + msecs_to_jiffies(msecs);
12152         while (1) {
12153                 if (get_logical_state(ppd) == state)
12154                         return 0;
12155                 if (time_after(jiffies, timeout))
12156                         break;
12157                 msleep(20);
12158         }
12159         dd_dev_err(ppd->dd, "timeout waiting for link state 0x%x\n", state);
12160
12161         return -ETIMEDOUT;
12162 }
12163
12164 u8 hfi1_ibphys_portstate(struct hfi1_pportdata *ppd)
12165 {
12166         u32 pstate;
12167         u32 ib_pstate;
12168
12169         pstate = read_physical_state(ppd->dd);
12170         ib_pstate = chip_to_opa_pstate(ppd->dd, pstate);
12171         if (ppd->last_pstate != ib_pstate) {
12172                 dd_dev_info(ppd->dd,
12173                             "%s: physical state changed to %s (0x%x), phy 0x%x\n",
12174                             __func__, opa_pstate_name(ib_pstate), ib_pstate,
12175                             pstate);
12176                 ppd->last_pstate = ib_pstate;
12177         }
12178         return ib_pstate;
12179 }
12180
12181 /*
12182  * Read/modify/write ASIC_QSFP register bits as selected by mask
12183  * data: 0 or 1 in the positions depending on what needs to be written
12184  * dir: 0 for read, 1 for write
12185  * mask: select by setting
12186  *      I2CCLK  (bit 0)
12187  *      I2CDATA (bit 1)
12188  */
12189 u64 hfi1_gpio_mod(struct hfi1_devdata *dd, u32 target, u32 data, u32 dir,
12190                   u32 mask)
12191 {
12192         u64 qsfp_oe, target_oe;
12193
12194         target_oe = target ? ASIC_QSFP2_OE : ASIC_QSFP1_OE;
12195         if (mask) {
12196                 /* We are writing register bits, so lock access */
12197                 dir &= mask;
12198                 data &= mask;
12199
12200                 qsfp_oe = read_csr(dd, target_oe);
12201                 qsfp_oe = (qsfp_oe & ~(u64)mask) | (u64)dir;
12202                 write_csr(dd, target_oe, qsfp_oe);
12203         }
12204         /* We are exclusively reading bits here, but it is unlikely
12205          * we'll get valid data when we set the direction of the pin
12206          * in the same call, so read should call this function again
12207          * to get valid data
12208          */
12209         return read_csr(dd, target ? ASIC_QSFP2_IN : ASIC_QSFP1_IN);
12210 }
12211
12212 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12213 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12214
12215 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
12216 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12217
12218 int hfi1_init_ctxt(struct send_context *sc)
12219 {
12220         if (sc) {
12221                 struct hfi1_devdata *dd = sc->dd;
12222                 u64 reg;
12223                 u8 set = (sc->type == SC_USER ?
12224                           HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
12225                           HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
12226                 reg = read_kctxt_csr(dd, sc->hw_context,
12227                                      SEND_CTXT_CHECK_ENABLE);
12228                 if (set)
12229                         CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
12230                 else
12231                         SET_STATIC_RATE_CONTROL_SMASK(reg);
12232                 write_kctxt_csr(dd, sc->hw_context,
12233                                 SEND_CTXT_CHECK_ENABLE, reg);
12234         }
12235         return 0;
12236 }
12237
12238 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12239 {
12240         int ret = 0;
12241         u64 reg;
12242
12243         if (dd->icode != ICODE_RTL_SILICON) {
12244                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
12245                         dd_dev_info(dd, "%s: tempsense not supported by HW\n",
12246                                     __func__);
12247                 return -EINVAL;
12248         }
12249         reg = read_csr(dd, ASIC_STS_THERM);
12250         temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
12251                       ASIC_STS_THERM_CURR_TEMP_MASK);
12252         temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
12253                         ASIC_STS_THERM_LO_TEMP_MASK);
12254         temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
12255                         ASIC_STS_THERM_HI_TEMP_MASK);
12256         temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
12257                           ASIC_STS_THERM_CRIT_TEMP_MASK);
12258         /* triggers is a 3-bit value - 1 bit per trigger. */
12259         temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
12260
12261         return ret;
12262 }
12263
12264 /* ========================================================================= */
12265
12266 /*
12267  * Enable/disable chip from delivering interrupts.
12268  */
12269 void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12270 {
12271         int i;
12272
12273         /*
12274          * In HFI, the mask needs to be 1 to allow interrupts.
12275          */
12276         if (enable) {
12277                 /* enable all interrupts */
12278                 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12279                         write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0);
12280
12281                 init_qsfp_int(dd);
12282         } else {
12283                 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12284                         write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
12285         }
12286 }
12287
12288 /*
12289  * Clear all interrupt sources on the chip.
12290  */
12291 static void clear_all_interrupts(struct hfi1_devdata *dd)
12292 {
12293         int i;
12294
12295         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12296                 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
12297
12298         write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
12299         write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
12300         write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
12301         write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
12302         write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
12303         write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
12304         write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
12305         for (i = 0; i < dd->chip_send_contexts; i++)
12306                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
12307         for (i = 0; i < dd->chip_sdma_engines; i++)
12308                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
12309
12310         write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
12311         write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
12312         write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
12313 }
12314
12315 /* Move to pcie.c? */
12316 static void disable_intx(struct pci_dev *pdev)
12317 {
12318         pci_intx(pdev, 0);
12319 }
12320
12321 static void clean_up_interrupts(struct hfi1_devdata *dd)
12322 {
12323         int i;
12324
12325         /* remove irqs - must happen before disabling/turning off */
12326         if (dd->num_msix_entries) {
12327                 /* MSI-X */
12328                 struct hfi1_msix_entry *me = dd->msix_entries;
12329
12330                 for (i = 0; i < dd->num_msix_entries; i++, me++) {
12331                         if (!me->arg) /* => no irq, no affinity */
12332                                 continue;
12333                         hfi1_put_irq_affinity(dd, &dd->msix_entries[i]);
12334                         free_irq(me->msix.vector, me->arg);
12335                 }
12336         } else {
12337                 /* INTx */
12338                 if (dd->requested_intx_irq) {
12339                         free_irq(dd->pcidev->irq, dd);
12340                         dd->requested_intx_irq = 0;
12341                 }
12342         }
12343
12344         /* turn off interrupts */
12345         if (dd->num_msix_entries) {
12346                 /* MSI-X */
12347                 pci_disable_msix(dd->pcidev);
12348         } else {
12349                 /* INTx */
12350                 disable_intx(dd->pcidev);
12351         }
12352
12353         /* clean structures */
12354         kfree(dd->msix_entries);
12355         dd->msix_entries = NULL;
12356         dd->num_msix_entries = 0;
12357 }
12358
12359 /*
12360  * Remap the interrupt source from the general handler to the given MSI-X
12361  * interrupt.
12362  */
12363 static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
12364 {
12365         u64 reg;
12366         int m, n;
12367
12368         /* clear from the handled mask of the general interrupt */
12369         m = isrc / 64;
12370         n = isrc % 64;
12371         dd->gi_mask[m] &= ~((u64)1 << n);
12372
12373         /* direct the chip source to the given MSI-X interrupt */
12374         m = isrc / 8;
12375         n = isrc % 8;
12376         reg = read_csr(dd, CCE_INT_MAP + (8 * m));
12377         reg &= ~((u64)0xff << (8 * n));
12378         reg |= ((u64)msix_intr & 0xff) << (8 * n);
12379         write_csr(dd, CCE_INT_MAP + (8 * m), reg);
12380 }
12381
12382 static void remap_sdma_interrupts(struct hfi1_devdata *dd,
12383                                   int engine, int msix_intr)
12384 {
12385         /*
12386          * SDMA engine interrupt sources grouped by type, rather than
12387          * engine.  Per-engine interrupts are as follows:
12388          *      SDMA
12389          *      SDMAProgress
12390          *      SDMAIdle
12391          */
12392         remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine,
12393                    msix_intr);
12394         remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine,
12395                    msix_intr);
12396         remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine,
12397                    msix_intr);
12398 }
12399
12400 static int request_intx_irq(struct hfi1_devdata *dd)
12401 {
12402         int ret;
12403
12404         snprintf(dd->intx_name, sizeof(dd->intx_name), DRIVER_NAME "_%d",
12405                  dd->unit);
12406         ret = request_irq(dd->pcidev->irq, general_interrupt,
12407                           IRQF_SHARED, dd->intx_name, dd);
12408         if (ret)
12409                 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
12410                            ret);
12411         else
12412                 dd->requested_intx_irq = 1;
12413         return ret;
12414 }
12415
12416 static int request_msix_irqs(struct hfi1_devdata *dd)
12417 {
12418         int first_general, last_general;
12419         int first_sdma, last_sdma;
12420         int first_rx, last_rx;
12421         int i, ret = 0;
12422
12423         /* calculate the ranges we are going to use */
12424         first_general = 0;
12425         last_general = first_general + 1;
12426         first_sdma = last_general;
12427         last_sdma = first_sdma + dd->num_sdma;
12428         first_rx = last_sdma;
12429         last_rx = first_rx + dd->n_krcv_queues;
12430
12431         /*
12432          * Sanity check - the code expects all SDMA chip source
12433          * interrupts to be in the same CSR, starting at bit 0.  Verify
12434          * that this is true by checking the bit location of the start.
12435          */
12436         BUILD_BUG_ON(IS_SDMA_START % 64);
12437
12438         for (i = 0; i < dd->num_msix_entries; i++) {
12439                 struct hfi1_msix_entry *me = &dd->msix_entries[i];
12440                 const char *err_info;
12441                 irq_handler_t handler;
12442                 irq_handler_t thread = NULL;
12443                 void *arg;
12444                 int idx;
12445                 struct hfi1_ctxtdata *rcd = NULL;
12446                 struct sdma_engine *sde = NULL;
12447
12448                 /* obtain the arguments to request_irq */
12449                 if (first_general <= i && i < last_general) {
12450                         idx = i - first_general;
12451                         handler = general_interrupt;
12452                         arg = dd;
12453                         snprintf(me->name, sizeof(me->name),
12454                                  DRIVER_NAME "_%d", dd->unit);
12455                         err_info = "general";
12456                         me->type = IRQ_GENERAL;
12457                 } else if (first_sdma <= i && i < last_sdma) {
12458                         idx = i - first_sdma;
12459                         sde = &dd->per_sdma[idx];
12460                         handler = sdma_interrupt;
12461                         arg = sde;
12462                         snprintf(me->name, sizeof(me->name),
12463                                  DRIVER_NAME "_%d sdma%d", dd->unit, idx);
12464                         err_info = "sdma";
12465                         remap_sdma_interrupts(dd, idx, i);
12466                         me->type = IRQ_SDMA;
12467                 } else if (first_rx <= i && i < last_rx) {
12468                         idx = i - first_rx;
12469                         rcd = dd->rcd[idx];
12470                         /* no interrupt if no rcd */
12471                         if (!rcd)
12472                                 continue;
12473                         /*
12474                          * Set the interrupt register and mask for this
12475                          * context's interrupt.
12476                          */
12477                         rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
12478                         rcd->imask = ((u64)1) <<
12479                                         ((IS_RCVAVAIL_START + idx) % 64);
12480                         handler = receive_context_interrupt;
12481                         thread = receive_context_thread;
12482                         arg = rcd;
12483                         snprintf(me->name, sizeof(me->name),
12484                                  DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
12485                         err_info = "receive context";
12486                         remap_intr(dd, IS_RCVAVAIL_START + idx, i);
12487                         me->type = IRQ_RCVCTXT;
12488                 } else {
12489                         /* not in our expected range - complain, then
12490                          * ignore it
12491                          */
12492                         dd_dev_err(dd,
12493                                    "Unexpected extra MSI-X interrupt %d\n", i);
12494                         continue;
12495                 }
12496                 /* no argument, no interrupt */
12497                 if (!arg)
12498                         continue;
12499                 /* make sure the name is terminated */
12500                 me->name[sizeof(me->name) - 1] = 0;
12501
12502                 ret = request_threaded_irq(me->msix.vector, handler, thread, 0,
12503                                            me->name, arg);
12504                 if (ret) {
12505                         dd_dev_err(dd,
12506                                    "unable to allocate %s interrupt, vector %d, index %d, err %d\n",
12507                                    err_info, me->msix.vector, idx, ret);
12508                         return ret;
12509                 }
12510                 /*
12511                  * assign arg after request_irq call, so it will be
12512                  * cleaned up
12513                  */
12514                 me->arg = arg;
12515
12516                 ret = hfi1_get_irq_affinity(dd, me);
12517                 if (ret)
12518                         dd_dev_err(dd,
12519                                    "unable to pin IRQ %d\n", ret);
12520         }
12521
12522         return ret;
12523 }
12524
12525 /*
12526  * Set the general handler to accept all interrupts, remap all
12527  * chip interrupts back to MSI-X 0.
12528  */
12529 static void reset_interrupts(struct hfi1_devdata *dd)
12530 {
12531         int i;
12532
12533         /* all interrupts handled by the general handler */
12534         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12535                 dd->gi_mask[i] = ~(u64)0;
12536
12537         /* all chip interrupts map to MSI-X 0 */
12538         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
12539                 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
12540 }
12541
12542 static int set_up_interrupts(struct hfi1_devdata *dd)
12543 {
12544         struct hfi1_msix_entry *entries;
12545         u32 total, request;
12546         int i, ret;
12547         int single_interrupt = 0; /* we expect to have all the interrupts */
12548
12549         /*
12550          * Interrupt count:
12551          *      1 general, "slow path" interrupt (includes the SDMA engines
12552          *              slow source, SDMACleanupDone)
12553          *      N interrupts - one per used SDMA engine
12554          *      M interrupt - one per kernel receive context
12555          */
12556         total = 1 + dd->num_sdma + dd->n_krcv_queues;
12557
12558         entries = kcalloc(total, sizeof(*entries), GFP_KERNEL);
12559         if (!entries) {
12560                 ret = -ENOMEM;
12561                 goto fail;
12562         }
12563         /* 1-1 MSI-X entry assignment */
12564         for (i = 0; i < total; i++)
12565                 entries[i].msix.entry = i;
12566
12567         /* ask for MSI-X interrupts */
12568         request = total;
12569         request_msix(dd, &request, entries);
12570
12571         if (request == 0) {
12572                 /* using INTx */
12573                 /* dd->num_msix_entries already zero */
12574                 kfree(entries);
12575                 single_interrupt = 1;
12576                 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n");
12577         } else {
12578                 /* using MSI-X */
12579                 dd->num_msix_entries = request;
12580                 dd->msix_entries = entries;
12581
12582                 if (request != total) {
12583                         /* using MSI-X, with reduced interrupts */
12584                         dd_dev_err(
12585                                 dd,
12586                                 "cannot handle reduced interrupt case, want %u, got %u\n",
12587                                 total, request);
12588                         ret = -EINVAL;
12589                         goto fail;
12590                 }
12591                 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
12592         }
12593
12594         /* mask all interrupts */
12595         set_intr_state(dd, 0);
12596         /* clear all pending interrupts */
12597         clear_all_interrupts(dd);
12598
12599         /* reset general handler mask, chip MSI-X mappings */
12600         reset_interrupts(dd);
12601
12602         if (single_interrupt)
12603                 ret = request_intx_irq(dd);
12604         else
12605                 ret = request_msix_irqs(dd);
12606         if (ret)
12607                 goto fail;
12608
12609         return 0;
12610
12611 fail:
12612         clean_up_interrupts(dd);
12613         return ret;
12614 }
12615
12616 /*
12617  * Set up context values in dd.  Sets:
12618  *
12619  *      num_rcv_contexts - number of contexts being used
12620  *      n_krcv_queues - number of kernel contexts
12621  *      first_user_ctxt - first non-kernel context in array of contexts
12622  *      freectxts  - number of free user contexts
12623  *      num_send_contexts - number of PIO send contexts being used
12624  */
12625 static int set_up_context_variables(struct hfi1_devdata *dd)
12626 {
12627         int num_kernel_contexts;
12628         int total_contexts;
12629         int ret;
12630         unsigned ngroups;
12631
12632         /*
12633          * Kernel receive contexts:
12634          * - min of 2 or 1 context/numa (excluding control context)
12635          * - Context 0 - control context (VL15/multicast/error)
12636          * - Context 1 - first kernel context
12637          * - Context 2 - second kernel context
12638          * ...
12639          */
12640         if (n_krcvqs)
12641                 /*
12642                  * n_krcvqs is the sum of module parameter kernel receive
12643                  * contexts, krcvqs[].  It does not include the control
12644                  * context, so add that.
12645                  */
12646                 num_kernel_contexts = n_krcvqs + 1;
12647         else
12648                 num_kernel_contexts = num_online_nodes() + 1;
12649         num_kernel_contexts =
12650                 max_t(int, MIN_KERNEL_KCTXTS, num_kernel_contexts);
12651         /*
12652          * Every kernel receive context needs an ACK send context.
12653          * one send context is allocated for each VL{0-7} and VL15
12654          */
12655         if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) {
12656                 dd_dev_err(dd,
12657                            "Reducing # kernel rcv contexts to: %d, from %d\n",
12658                            (int)(dd->chip_send_contexts - num_vls - 1),
12659                            (int)num_kernel_contexts);
12660                 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
12661         }
12662         /*
12663          * User contexts:
12664          *      - default to 1 user context per real (non-HT) CPU core if
12665          *        num_user_contexts is negative
12666          */
12667         if (num_user_contexts < 0)
12668                 num_user_contexts =
12669                         cpumask_weight(&dd->affinity->real_cpu_mask);
12670
12671         total_contexts = num_kernel_contexts + num_user_contexts;
12672
12673         /*
12674          * Adjust the counts given a global max.
12675          */
12676         if (total_contexts > dd->chip_rcv_contexts) {
12677                 dd_dev_err(dd,
12678                            "Reducing # user receive contexts to: %d, from %d\n",
12679                            (int)(dd->chip_rcv_contexts - num_kernel_contexts),
12680                            (int)num_user_contexts);
12681                 num_user_contexts = dd->chip_rcv_contexts - num_kernel_contexts;
12682                 /* recalculate */
12683                 total_contexts = num_kernel_contexts + num_user_contexts;
12684         }
12685
12686         /* the first N are kernel contexts, the rest are user contexts */
12687         dd->num_rcv_contexts = total_contexts;
12688         dd->n_krcv_queues = num_kernel_contexts;
12689         dd->first_user_ctxt = num_kernel_contexts;
12690         dd->num_user_contexts = num_user_contexts;
12691         dd->freectxts = num_user_contexts;
12692         dd_dev_info(dd,
12693                     "rcv contexts: chip %d, used %d (kernel %d, user %d)\n",
12694                     (int)dd->chip_rcv_contexts,
12695                     (int)dd->num_rcv_contexts,
12696                     (int)dd->n_krcv_queues,
12697                     (int)dd->num_rcv_contexts - dd->n_krcv_queues);
12698
12699         /*
12700          * Receive array allocation:
12701          *   All RcvArray entries are divided into groups of 8. This
12702          *   is required by the hardware and will speed up writes to
12703          *   consecutive entries by using write-combining of the entire
12704          *   cacheline.
12705          *
12706          *   The number of groups are evenly divided among all contexts.
12707          *   any left over groups will be given to the first N user
12708          *   contexts.
12709          */
12710         dd->rcv_entries.group_size = RCV_INCREMENT;
12711         ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size;
12712         dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
12713         dd->rcv_entries.nctxt_extra = ngroups -
12714                 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
12715         dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
12716                     dd->rcv_entries.ngroups,
12717                     dd->rcv_entries.nctxt_extra);
12718         if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
12719             MAX_EAGER_ENTRIES * 2) {
12720                 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
12721                         dd->rcv_entries.group_size;
12722                 dd_dev_info(dd,
12723                             "RcvArray group count too high, change to %u\n",
12724                             dd->rcv_entries.ngroups);
12725                 dd->rcv_entries.nctxt_extra = 0;
12726         }
12727         /*
12728          * PIO send contexts
12729          */
12730         ret = init_sc_pools_and_sizes(dd);
12731         if (ret >= 0) { /* success */
12732                 dd->num_send_contexts = ret;
12733                 dd_dev_info(
12734                         dd,
12735                         "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
12736                         dd->chip_send_contexts,
12737                         dd->num_send_contexts,
12738                         dd->sc_sizes[SC_KERNEL].count,
12739                         dd->sc_sizes[SC_ACK].count,
12740                         dd->sc_sizes[SC_USER].count,
12741                         dd->sc_sizes[SC_VL15].count);
12742                 ret = 0;        /* success */
12743         }
12744
12745         return ret;
12746 }
12747
12748 /*
12749  * Set the device/port partition key table. The MAD code
12750  * will ensure that, at least, the partial management
12751  * partition key is present in the table.
12752  */
12753 static void set_partition_keys(struct hfi1_pportdata *ppd)
12754 {
12755         struct hfi1_devdata *dd = ppd->dd;
12756         u64 reg = 0;
12757         int i;
12758
12759         dd_dev_info(dd, "Setting partition keys\n");
12760         for (i = 0; i < hfi1_get_npkeys(dd); i++) {
12761                 reg |= (ppd->pkeys[i] &
12762                         RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
12763                         ((i % 4) *
12764                          RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
12765                 /* Each register holds 4 PKey values. */
12766                 if ((i % 4) == 3) {
12767                         write_csr(dd, RCV_PARTITION_KEY +
12768                                   ((i - 3) * 2), reg);
12769                         reg = 0;
12770                 }
12771         }
12772
12773         /* Always enable HW pkeys check when pkeys table is set */
12774         add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
12775 }
12776
12777 /*
12778  * These CSRs and memories are uninitialized on reset and must be
12779  * written before reading to set the ECC/parity bits.
12780  *
12781  * NOTE: All user context CSRs that are not mmaped write-only
12782  * (e.g. the TID flows) must be initialized even if the driver never
12783  * reads them.
12784  */
12785 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
12786 {
12787         int i, j;
12788
12789         /* CceIntMap */
12790         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
12791                 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
12792
12793         /* SendCtxtCreditReturnAddr */
12794         for (i = 0; i < dd->chip_send_contexts; i++)
12795                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
12796
12797         /* PIO Send buffers */
12798         /* SDMA Send buffers */
12799         /*
12800          * These are not normally read, and (presently) have no method
12801          * to be read, so are not pre-initialized
12802          */
12803
12804         /* RcvHdrAddr */
12805         /* RcvHdrTailAddr */
12806         /* RcvTidFlowTable */
12807         for (i = 0; i < dd->chip_rcv_contexts; i++) {
12808                 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
12809                 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
12810                 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
12811                         write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
12812         }
12813
12814         /* RcvArray */
12815         for (i = 0; i < dd->chip_rcv_array_count; i++)
12816                 write_csr(dd, RCV_ARRAY + (8 * i),
12817                           RCV_ARRAY_RT_WRITE_ENABLE_SMASK);
12818
12819         /* RcvQPMapTable */
12820         for (i = 0; i < 32; i++)
12821                 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
12822 }
12823
12824 /*
12825  * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
12826  */
12827 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
12828                              u64 ctrl_bits)
12829 {
12830         unsigned long timeout;
12831         u64 reg;
12832
12833         /* is the condition present? */
12834         reg = read_csr(dd, CCE_STATUS);
12835         if ((reg & status_bits) == 0)
12836                 return;
12837
12838         /* clear the condition */
12839         write_csr(dd, CCE_CTRL, ctrl_bits);
12840
12841         /* wait for the condition to clear */
12842         timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
12843         while (1) {
12844                 reg = read_csr(dd, CCE_STATUS);
12845                 if ((reg & status_bits) == 0)
12846                         return;
12847                 if (time_after(jiffies, timeout)) {
12848                         dd_dev_err(dd,
12849                                    "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
12850                                    status_bits, reg & status_bits);
12851                         return;
12852                 }
12853                 udelay(1);
12854         }
12855 }
12856
12857 /* set CCE CSRs to chip reset defaults */
12858 static void reset_cce_csrs(struct hfi1_devdata *dd)
12859 {
12860         int i;
12861
12862         /* CCE_REVISION read-only */
12863         /* CCE_REVISION2 read-only */
12864         /* CCE_CTRL - bits clear automatically */
12865         /* CCE_STATUS read-only, use CceCtrl to clear */
12866         clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
12867         clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
12868         clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
12869         for (i = 0; i < CCE_NUM_SCRATCH; i++)
12870                 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
12871         /* CCE_ERR_STATUS read-only */
12872         write_csr(dd, CCE_ERR_MASK, 0);
12873         write_csr(dd, CCE_ERR_CLEAR, ~0ull);
12874         /* CCE_ERR_FORCE leave alone */
12875         for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
12876                 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
12877         write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
12878         /* CCE_PCIE_CTRL leave alone */
12879         for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
12880                 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
12881                 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
12882                           CCE_MSIX_TABLE_UPPER_RESETCSR);
12883         }
12884         for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
12885                 /* CCE_MSIX_PBA read-only */
12886                 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
12887                 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
12888         }
12889         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
12890                 write_csr(dd, CCE_INT_MAP, 0);
12891         for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
12892                 /* CCE_INT_STATUS read-only */
12893                 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
12894                 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
12895                 /* CCE_INT_FORCE leave alone */
12896                 /* CCE_INT_BLOCKED read-only */
12897         }
12898         for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
12899                 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
12900 }
12901
12902 /* set MISC CSRs to chip reset defaults */
12903 static void reset_misc_csrs(struct hfi1_devdata *dd)
12904 {
12905         int i;
12906
12907         for (i = 0; i < 32; i++) {
12908                 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
12909                 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
12910                 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
12911         }
12912         /*
12913          * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
12914          * only be written 128-byte chunks
12915          */
12916         /* init RSA engine to clear lingering errors */
12917         write_csr(dd, MISC_CFG_RSA_CMD, 1);
12918         write_csr(dd, MISC_CFG_RSA_MU, 0);
12919         write_csr(dd, MISC_CFG_FW_CTRL, 0);
12920         /* MISC_STS_8051_DIGEST read-only */
12921         /* MISC_STS_SBM_DIGEST read-only */
12922         /* MISC_STS_PCIE_DIGEST read-only */
12923         /* MISC_STS_FAB_DIGEST read-only */
12924         /* MISC_ERR_STATUS read-only */
12925         write_csr(dd, MISC_ERR_MASK, 0);
12926         write_csr(dd, MISC_ERR_CLEAR, ~0ull);
12927         /* MISC_ERR_FORCE leave alone */
12928 }
12929
12930 /* set TXE CSRs to chip reset defaults */
12931 static void reset_txe_csrs(struct hfi1_devdata *dd)
12932 {
12933         int i;
12934
12935         /*
12936          * TXE Kernel CSRs
12937          */
12938         write_csr(dd, SEND_CTRL, 0);
12939         __cm_reset(dd, 0);      /* reset CM internal state */
12940         /* SEND_CONTEXTS read-only */
12941         /* SEND_DMA_ENGINES read-only */
12942         /* SEND_PIO_MEM_SIZE read-only */
12943         /* SEND_DMA_MEM_SIZE read-only */
12944         write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
12945         pio_reset_all(dd);      /* SEND_PIO_INIT_CTXT */
12946         /* SEND_PIO_ERR_STATUS read-only */
12947         write_csr(dd, SEND_PIO_ERR_MASK, 0);
12948         write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
12949         /* SEND_PIO_ERR_FORCE leave alone */
12950         /* SEND_DMA_ERR_STATUS read-only */
12951         write_csr(dd, SEND_DMA_ERR_MASK, 0);
12952         write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
12953         /* SEND_DMA_ERR_FORCE leave alone */
12954         /* SEND_EGRESS_ERR_STATUS read-only */
12955         write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
12956         write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
12957         /* SEND_EGRESS_ERR_FORCE leave alone */
12958         write_csr(dd, SEND_BTH_QP, 0);
12959         write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
12960         write_csr(dd, SEND_SC2VLT0, 0);
12961         write_csr(dd, SEND_SC2VLT1, 0);
12962         write_csr(dd, SEND_SC2VLT2, 0);
12963         write_csr(dd, SEND_SC2VLT3, 0);
12964         write_csr(dd, SEND_LEN_CHECK0, 0);
12965         write_csr(dd, SEND_LEN_CHECK1, 0);
12966         /* SEND_ERR_STATUS read-only */
12967         write_csr(dd, SEND_ERR_MASK, 0);
12968         write_csr(dd, SEND_ERR_CLEAR, ~0ull);
12969         /* SEND_ERR_FORCE read-only */
12970         for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
12971                 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
12972         for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
12973                 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
12974         for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++)
12975                 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
12976         for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
12977                 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
12978         for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
12979                 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
12980         write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
12981         write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
12982         /* SEND_CM_CREDIT_USED_STATUS read-only */
12983         write_csr(dd, SEND_CM_TIMER_CTRL, 0);
12984         write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
12985         write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
12986         write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
12987         write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
12988         for (i = 0; i < TXE_NUM_DATA_VL; i++)
12989                 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
12990         write_csr(dd, SEND_CM_CREDIT_VL15, 0);
12991         /* SEND_CM_CREDIT_USED_VL read-only */
12992         /* SEND_CM_CREDIT_USED_VL15 read-only */
12993         /* SEND_EGRESS_CTXT_STATUS read-only */
12994         /* SEND_EGRESS_SEND_DMA_STATUS read-only */
12995         write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
12996         /* SEND_EGRESS_ERR_INFO read-only */
12997         /* SEND_EGRESS_ERR_SOURCE read-only */
12998
12999         /*
13000          * TXE Per-Context CSRs
13001          */
13002         for (i = 0; i < dd->chip_send_contexts; i++) {
13003                 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13004                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13005                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13006                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13007                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13008                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13009                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13010                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13011                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13012                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13013                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13014                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13015         }
13016
13017         /*
13018          * TXE Per-SDMA CSRs
13019          */
13020         for (i = 0; i < dd->chip_sdma_engines; i++) {
13021                 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13022                 /* SEND_DMA_STATUS read-only */
13023                 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13024                 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13025                 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13026                 /* SEND_DMA_HEAD read-only */
13027                 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13028                 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13029                 /* SEND_DMA_IDLE_CNT read-only */
13030                 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13031                 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13032                 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13033                 /* SEND_DMA_ENG_ERR_STATUS read-only */
13034                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13035                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13036                 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13037                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13038                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13039                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13040                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13041                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13042                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13043                 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13044         }
13045 }
13046
13047 /*
13048  * Expect on entry:
13049  * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13050  */
13051 static void init_rbufs(struct hfi1_devdata *dd)
13052 {
13053         u64 reg;
13054         int count;
13055
13056         /*
13057          * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13058          * clear.
13059          */
13060         count = 0;
13061         while (1) {
13062                 reg = read_csr(dd, RCV_STATUS);
13063                 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13064                             | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13065                         break;
13066                 /*
13067                  * Give up after 1ms - maximum wait time.
13068                  *
13069                  * RBuf size is 148KiB.  Slowest possible is PCIe Gen1 x1 at
13070                  * 250MB/s bandwidth.  Lower rate to 66% for overhead to get:
13071                  *      148 KB / (66% * 250MB/s) = 920us
13072                  */
13073                 if (count++ > 500) {
13074                         dd_dev_err(dd,
13075                                    "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13076                                    __func__, reg);
13077                         break;
13078                 }
13079                 udelay(2); /* do not busy-wait the CSR */
13080         }
13081
13082         /* start the init - expect RcvCtrl to be 0 */
13083         write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13084
13085         /*
13086          * Read to force the write of Rcvtrl.RxRbufInit.  There is a brief
13087          * period after the write before RcvStatus.RxRbufInitDone is valid.
13088          * The delay in the first run through the loop below is sufficient and
13089          * required before the first read of RcvStatus.RxRbufInintDone.
13090          */
13091         read_csr(dd, RCV_CTRL);
13092
13093         /* wait for the init to finish */
13094         count = 0;
13095         while (1) {
13096                 /* delay is required first time through - see above */
13097                 udelay(2); /* do not busy-wait the CSR */
13098                 reg = read_csr(dd, RCV_STATUS);
13099                 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13100                         break;
13101
13102                 /* give up after 100us - slowest possible at 33MHz is 73us */
13103                 if (count++ > 50) {
13104                         dd_dev_err(dd,
13105                                    "%s: RcvStatus.RxRbufInit not set, continuing\n",
13106                                    __func__);
13107                         break;
13108                 }
13109         }
13110 }
13111
13112 /* set RXE CSRs to chip reset defaults */
13113 static void reset_rxe_csrs(struct hfi1_devdata *dd)
13114 {
13115         int i, j;
13116
13117         /*
13118          * RXE Kernel CSRs
13119          */
13120         write_csr(dd, RCV_CTRL, 0);
13121         init_rbufs(dd);
13122         /* RCV_STATUS read-only */
13123         /* RCV_CONTEXTS read-only */
13124         /* RCV_ARRAY_CNT read-only */
13125         /* RCV_BUF_SIZE read-only */
13126         write_csr(dd, RCV_BTH_QP, 0);
13127         write_csr(dd, RCV_MULTICAST, 0);
13128         write_csr(dd, RCV_BYPASS, 0);
13129         write_csr(dd, RCV_VL15, 0);
13130         /* this is a clear-down */
13131         write_csr(dd, RCV_ERR_INFO,
13132                   RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13133         /* RCV_ERR_STATUS read-only */
13134         write_csr(dd, RCV_ERR_MASK, 0);
13135         write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13136         /* RCV_ERR_FORCE leave alone */
13137         for (i = 0; i < 32; i++)
13138                 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13139         for (i = 0; i < 4; i++)
13140                 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13141         for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13142                 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13143         for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13144                 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13145         for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) {
13146                 write_csr(dd, RCV_RSM_CFG + (8 * i), 0);
13147                 write_csr(dd, RCV_RSM_SELECT + (8 * i), 0);
13148                 write_csr(dd, RCV_RSM_MATCH + (8 * i), 0);
13149         }
13150         for (i = 0; i < 32; i++)
13151                 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13152
13153         /*
13154          * RXE Kernel and User Per-Context CSRs
13155          */
13156         for (i = 0; i < dd->chip_rcv_contexts; i++) {
13157                 /* kernel */
13158                 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13159                 /* RCV_CTXT_STATUS read-only */
13160                 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13161                 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13162                 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13163                 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13164                 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13165                 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13166                 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13167                 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13168                 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13169                 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13170
13171                 /* user */
13172                 /* RCV_HDR_TAIL read-only */
13173                 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13174                 /* RCV_EGR_INDEX_TAIL read-only */
13175                 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13176                 /* RCV_EGR_OFFSET_TAIL read-only */
13177                 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
13178                         write_uctxt_csr(dd, i,
13179                                         RCV_TID_FLOW_TABLE + (8 * j), 0);
13180                 }
13181         }
13182 }
13183
13184 /*
13185  * Set sc2vl tables.
13186  *
13187  * They power on to zeros, so to avoid send context errors
13188  * they need to be set:
13189  *
13190  * SC 0-7 -> VL 0-7 (respectively)
13191  * SC 15  -> VL 15
13192  * otherwise
13193  *        -> VL 0
13194  */
13195 static void init_sc2vl_tables(struct hfi1_devdata *dd)
13196 {
13197         int i;
13198         /* init per architecture spec, constrained by hardware capability */
13199
13200         /* HFI maps sent packets */
13201         write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13202                 0,
13203                 0, 0, 1, 1,
13204                 2, 2, 3, 3,
13205                 4, 4, 5, 5,
13206                 6, 6, 7, 7));
13207         write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13208                 1,
13209                 8, 0, 9, 0,
13210                 10, 0, 11, 0,
13211                 12, 0, 13, 0,
13212                 14, 0, 15, 15));
13213         write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
13214                 2,
13215                 16, 0, 17, 0,
13216                 18, 0, 19, 0,
13217                 20, 0, 21, 0,
13218                 22, 0, 23, 0));
13219         write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
13220                 3,
13221                 24, 0, 25, 0,
13222                 26, 0, 27, 0,
13223                 28, 0, 29, 0,
13224                 30, 0, 31, 0));
13225
13226         /* DC maps received packets */
13227         write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
13228                 15_0,
13229                 0, 0, 1, 1,  2, 2,  3, 3,  4, 4,  5, 5,  6, 6,  7,  7,
13230                 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
13231         write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
13232                 31_16,
13233                 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
13234                 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
13235
13236         /* initialize the cached sc2vl values consistently with h/w */
13237         for (i = 0; i < 32; i++) {
13238                 if (i < 8 || i == 15)
13239                         *((u8 *)(dd->sc2vl) + i) = (u8)i;
13240                 else
13241                         *((u8 *)(dd->sc2vl) + i) = 0;
13242         }
13243 }
13244
13245 /*
13246  * Read chip sizes and then reset parts to sane, disabled, values.  We cannot
13247  * depend on the chip going through a power-on reset - a driver may be loaded
13248  * and unloaded many times.
13249  *
13250  * Do not write any CSR values to the chip in this routine - there may be
13251  * a reset following the (possible) FLR in this routine.
13252  *
13253  */
13254 static void init_chip(struct hfi1_devdata *dd)
13255 {
13256         int i;
13257
13258         /*
13259          * Put the HFI CSRs in a known state.
13260          * Combine this with a DC reset.
13261          *
13262          * Stop the device from doing anything while we do a
13263          * reset.  We know there are no other active users of
13264          * the device since we are now in charge.  Turn off
13265          * off all outbound and inbound traffic and make sure
13266          * the device does not generate any interrupts.
13267          */
13268
13269         /* disable send contexts and SDMA engines */
13270         write_csr(dd, SEND_CTRL, 0);
13271         for (i = 0; i < dd->chip_send_contexts; i++)
13272                 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13273         for (i = 0; i < dd->chip_sdma_engines; i++)
13274                 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13275         /* disable port (turn off RXE inbound traffic) and contexts */
13276         write_csr(dd, RCV_CTRL, 0);
13277         for (i = 0; i < dd->chip_rcv_contexts; i++)
13278                 write_csr(dd, RCV_CTXT_CTRL, 0);
13279         /* mask all interrupt sources */
13280         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
13281                 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
13282
13283         /*
13284          * DC Reset: do a full DC reset before the register clear.
13285          * A recommended length of time to hold is one CSR read,
13286          * so reread the CceDcCtrl.  Then, hold the DC in reset
13287          * across the clear.
13288          */
13289         write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
13290         (void)read_csr(dd, CCE_DC_CTRL);
13291
13292         if (use_flr) {
13293                 /*
13294                  * A FLR will reset the SPC core and part of the PCIe.
13295                  * The parts that need to be restored have already been
13296                  * saved.
13297                  */
13298                 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13299
13300                 /* do the FLR, the DC reset will remain */
13301                 hfi1_pcie_flr(dd);
13302
13303                 /* restore command and BARs */
13304                 restore_pci_variables(dd);
13305
13306                 if (is_ax(dd)) {
13307                         dd_dev_info(dd, "Resetting CSRs with FLR\n");
13308                         hfi1_pcie_flr(dd);
13309                         restore_pci_variables(dd);
13310                 }
13311         } else {
13312                 dd_dev_info(dd, "Resetting CSRs with writes\n");
13313                 reset_cce_csrs(dd);
13314                 reset_txe_csrs(dd);
13315                 reset_rxe_csrs(dd);
13316                 reset_misc_csrs(dd);
13317         }
13318         /* clear the DC reset */
13319         write_csr(dd, CCE_DC_CTRL, 0);
13320
13321         /* Set the LED off */
13322         setextled(dd, 0);
13323
13324         /*
13325          * Clear the QSFP reset.
13326          * An FLR enforces a 0 on all out pins. The driver does not touch
13327          * ASIC_QSFPn_OUT otherwise.  This leaves RESET_N low and
13328          * anything plugged constantly in reset, if it pays attention
13329          * to RESET_N.
13330          * Prime examples of this are optical cables. Set all pins high.
13331          * I2CCLK and I2CDAT will change per direction, and INT_N and
13332          * MODPRS_N are input only and their value is ignored.
13333          */
13334         write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
13335         write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
13336         init_chip_resources(dd);
13337 }
13338
13339 static void init_early_variables(struct hfi1_devdata *dd)
13340 {
13341         int i;
13342
13343         /* assign link credit variables */
13344         dd->vau = CM_VAU;
13345         dd->link_credits = CM_GLOBAL_CREDITS;
13346         if (is_ax(dd))
13347                 dd->link_credits--;
13348         dd->vcu = cu_to_vcu(hfi1_cu);
13349         /* enough room for 8 MAD packets plus header - 17K */
13350         dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
13351         if (dd->vl15_init > dd->link_credits)
13352                 dd->vl15_init = dd->link_credits;
13353
13354         write_uninitialized_csrs_and_memories(dd);
13355
13356         if (HFI1_CAP_IS_KSET(PKEY_CHECK))
13357                 for (i = 0; i < dd->num_pports; i++) {
13358                         struct hfi1_pportdata *ppd = &dd->pport[i];
13359
13360                         set_partition_keys(ppd);
13361                 }
13362         init_sc2vl_tables(dd);
13363 }
13364
13365 static void init_kdeth_qp(struct hfi1_devdata *dd)
13366 {
13367         /* user changed the KDETH_QP */
13368         if (kdeth_qp != 0 && kdeth_qp >= 0xff) {
13369                 /* out of range or illegal value */
13370                 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring");
13371                 kdeth_qp = 0;
13372         }
13373         if (kdeth_qp == 0)      /* not set, or failed range check */
13374                 kdeth_qp = DEFAULT_KDETH_QP;
13375
13376         write_csr(dd, SEND_BTH_QP,
13377                   (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) <<
13378                   SEND_BTH_QP_KDETH_QP_SHIFT);
13379
13380         write_csr(dd, RCV_BTH_QP,
13381                   (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) <<
13382                   RCV_BTH_QP_KDETH_QP_SHIFT);
13383 }
13384
13385 /**
13386  * init_qpmap_table
13387  * @dd - device data
13388  * @first_ctxt - first context
13389  * @last_ctxt - first context
13390  *
13391  * This return sets the qpn mapping table that
13392  * is indexed by qpn[8:1].
13393  *
13394  * The routine will round robin the 256 settings
13395  * from first_ctxt to last_ctxt.
13396  *
13397  * The first/last looks ahead to having specialized
13398  * receive contexts for mgmt and bypass.  Normal
13399  * verbs traffic will assumed to be on a range
13400  * of receive contexts.
13401  */
13402 static void init_qpmap_table(struct hfi1_devdata *dd,
13403                              u32 first_ctxt,
13404                              u32 last_ctxt)
13405 {
13406         u64 reg = 0;
13407         u64 regno = RCV_QP_MAP_TABLE;
13408         int i;
13409         u64 ctxt = first_ctxt;
13410
13411         for (i = 0; i < 256; i++) {
13412                 reg |= ctxt << (8 * (i % 8));
13413                 ctxt++;
13414                 if (ctxt > last_ctxt)
13415                         ctxt = first_ctxt;
13416                 if (i % 8 == 7) {
13417                         write_csr(dd, regno, reg);
13418                         reg = 0;
13419                         regno += 8;
13420                 }
13421         }
13422
13423         add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
13424                         | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
13425 }
13426
13427 struct rsm_map_table {
13428         u64 map[NUM_MAP_REGS];
13429         unsigned int used;
13430 };
13431
13432 /*
13433  * Return an initialized RMT map table for users to fill in.  OK if it
13434  * returns NULL, indicating no table.
13435  */
13436 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd)
13437 {
13438         struct rsm_map_table *rmt;
13439         u8 rxcontext = is_ax(dd) ? 0 : 0xff;  /* 0 is default if a0 ver. */
13440
13441         rmt = kmalloc(sizeof(*rmt), GFP_KERNEL);
13442         if (rmt) {
13443                 memset(rmt->map, rxcontext, sizeof(rmt->map));
13444                 rmt->used = 0;
13445         }
13446
13447         return rmt;
13448 }
13449
13450 /*
13451  * Write the final RMT map table to the chip and free the table.  OK if
13452  * table is NULL.
13453  */
13454 static void complete_rsm_map_table(struct hfi1_devdata *dd,
13455                                    struct rsm_map_table *rmt)
13456 {
13457         int i;
13458
13459         if (rmt) {
13460                 /* write table to chip */
13461                 for (i = 0; i < NUM_MAP_REGS; i++)
13462                         write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
13463
13464                 /* enable RSM */
13465                 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
13466         }
13467 }
13468
13469 /**
13470  * init_qos - init RX qos
13471  * @dd - device data
13472  * @rmt - RSM map table
13473  *
13474  * This routine initializes Rule 0 and the RSM map table to implement
13475  * quality of service (qos).
13476  *
13477  * If all of the limit tests succeed, qos is applied based on the array
13478  * interpretation of krcvqs where entry 0 is VL0.
13479  *
13480  * The number of vl bits (n) and the number of qpn bits (m) are computed to
13481  * feed both the RSM map table and the single rule.
13482  */
13483 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt)
13484 {
13485         u8 max_by_vl = 0;
13486         unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
13487         unsigned int rmt_entries;
13488         u64 reg;
13489
13490         /* validate */
13491         if (!rmt ||
13492             dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
13493             num_vls == 1 ||
13494             krcvqsset <= 1)
13495                 goto bail;
13496         for (i = 0; i < min_t(unsigned, num_vls, krcvqsset); i++)
13497                 if (krcvqs[i] > max_by_vl)
13498                         max_by_vl = krcvqs[i];
13499         if (max_by_vl > 32)
13500                 goto bail;
13501         qpns_per_vl = __roundup_pow_of_two(max_by_vl);
13502         /* determine bits vl */
13503         n = ilog2(__roundup_pow_of_two(num_vls));
13504         /* determine bits for qpn */
13505         m = ilog2(qpns_per_vl);
13506         if ((m + n) > 7)
13507                 goto bail;
13508         /* enough room in the map table? */
13509         rmt_entries = 1 << (m + n);
13510         if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES)
13511                 goto bail;
13512         /* add qos entries to the the RSM map table */
13513         for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
13514                 unsigned tctxt;
13515
13516                 for (qpn = 0, tctxt = ctxt;
13517                      krcvqs[i] && qpn < qpns_per_vl; qpn++) {
13518                         unsigned idx, regoff, regidx;
13519
13520                         /* generate the index the hardware will produce */
13521                         idx = rmt->used + ((qpn << n) ^ i);
13522                         regoff = (idx % 8) * 8;
13523                         regidx = idx / 8;
13524                         /* replace default with context number */
13525                         reg = rmt->map[regidx];
13526                         reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
13527                                 << regoff);
13528                         reg |= (u64)(tctxt++) << regoff;
13529                         rmt->map[regidx] = reg;
13530                         if (tctxt == ctxt + krcvqs[i])
13531                                 tctxt = ctxt;
13532                 }
13533                 ctxt += krcvqs[i];
13534         }
13535         /* add rule0 */
13536         write_csr(dd, RCV_RSM_CFG /* + (8 * 0) */,
13537                   (u64)rmt->used << RCV_RSM_CFG_OFFSET_SHIFT |
13538                   RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_MASK <<
13539                         RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_SHIFT |
13540                   2ull << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
13541         write_csr(dd, RCV_RSM_SELECT /* + (8 * 0) */,
13542                   LRH_BTH_MATCH_OFFSET << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
13543                   LRH_SC_MATCH_OFFSET << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
13544                   LRH_SC_SELECT_OFFSET << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
13545                   ((u64)n) << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
13546                   QPN_SELECT_OFFSET << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
13547                   ((u64)m + (u64)n) << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
13548         write_csr(dd, RCV_RSM_MATCH /* + (8 * 0) */,
13549                   LRH_BTH_MASK << RCV_RSM_MATCH_MASK1_SHIFT |
13550                   LRH_BTH_VALUE << RCV_RSM_MATCH_VALUE1_SHIFT |
13551                   LRH_SC_MASK << RCV_RSM_MATCH_MASK2_SHIFT |
13552                   LRH_SC_VALUE << RCV_RSM_MATCH_VALUE2_SHIFT);
13553         /* mark RSM map entries as used */
13554         rmt->used += rmt_entries;
13555         /* map everything else to the mcast/err/vl15 context */
13556         init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT);
13557         dd->qos_shift = n + 1;
13558         return;
13559 bail:
13560         dd->qos_shift = 1;
13561         init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
13562 }
13563
13564 static void init_rxe(struct hfi1_devdata *dd)
13565 {
13566         struct rsm_map_table *rmt;
13567
13568         /* enable all receive errors */
13569         write_csr(dd, RCV_ERR_MASK, ~0ull);
13570
13571         rmt = alloc_rsm_map_table(dd);
13572         /* set up QOS, including the QPN map table */
13573         init_qos(dd, rmt);
13574         complete_rsm_map_table(dd, rmt);
13575         kfree(rmt);
13576
13577         /*
13578          * make sure RcvCtrl.RcvWcb <= PCIe Device Control
13579          * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
13580          * space, PciCfgCap2.MaxPayloadSize in HFI).  There is only one
13581          * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
13582          * Max_PayLoad_Size set to its minimum of 128.
13583          *
13584          * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
13585          * (64 bytes).  Max_Payload_Size is possibly modified upward in
13586          * tune_pcie_caps() which is called after this routine.
13587          */
13588 }
13589
13590 static void init_other(struct hfi1_devdata *dd)
13591 {
13592         /* enable all CCE errors */
13593         write_csr(dd, CCE_ERR_MASK, ~0ull);
13594         /* enable *some* Misc errors */
13595         write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
13596         /* enable all DC errors, except LCB */
13597         write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
13598         write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
13599 }
13600
13601 /*
13602  * Fill out the given AU table using the given CU.  A CU is defined in terms
13603  * AUs.  The table is a an encoding: given the index, how many AUs does that
13604  * represent?
13605  *
13606  * NOTE: Assumes that the register layout is the same for the
13607  * local and remote tables.
13608  */
13609 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
13610                                u32 csr0to3, u32 csr4to7)
13611 {
13612         write_csr(dd, csr0to3,
13613                   0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT |
13614                   1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT |
13615                   2ull * cu <<
13616                   SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
13617                   4ull * cu <<
13618                   SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
13619         write_csr(dd, csr4to7,
13620                   8ull * cu <<
13621                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
13622                   16ull * cu <<
13623                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
13624                   32ull * cu <<
13625                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
13626                   64ull * cu <<
13627                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
13628 }
13629
13630 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
13631 {
13632         assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
13633                            SEND_CM_LOCAL_AU_TABLE4_TO7);
13634 }
13635
13636 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
13637 {
13638         assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
13639                            SEND_CM_REMOTE_AU_TABLE4_TO7);
13640 }
13641
13642 static void init_txe(struct hfi1_devdata *dd)
13643 {
13644         int i;
13645
13646         /* enable all PIO, SDMA, general, and Egress errors */
13647         write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
13648         write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
13649         write_csr(dd, SEND_ERR_MASK, ~0ull);
13650         write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
13651
13652         /* enable all per-context and per-SDMA engine errors */
13653         for (i = 0; i < dd->chip_send_contexts; i++)
13654                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
13655         for (i = 0; i < dd->chip_sdma_engines; i++)
13656                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
13657
13658         /* set the local CU to AU mapping */
13659         assign_local_cm_au_table(dd, dd->vcu);
13660
13661         /*
13662          * Set reasonable default for Credit Return Timer
13663          * Don't set on Simulator - causes it to choke.
13664          */
13665         if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
13666                 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
13667 }
13668
13669 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey)
13670 {
13671         struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
13672         unsigned sctxt;
13673         int ret = 0;
13674         u64 reg;
13675
13676         if (!rcd || !rcd->sc) {
13677                 ret = -EINVAL;
13678                 goto done;
13679         }
13680         sctxt = rcd->sc->hw_context;
13681         reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
13682                 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
13683                  SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
13684         /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
13685         if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
13686                 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
13687         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
13688         /*
13689          * Enable send-side J_KEY integrity check, unless this is A0 h/w
13690          */
13691         if (!is_ax(dd)) {
13692                 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13693                 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
13694                 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13695         }
13696
13697         /* Enable J_KEY check on receive context. */
13698         reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
13699                 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
13700                  RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
13701         write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, reg);
13702 done:
13703         return ret;
13704 }
13705
13706 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt)
13707 {
13708         struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
13709         unsigned sctxt;
13710         int ret = 0;
13711         u64 reg;
13712
13713         if (!rcd || !rcd->sc) {
13714                 ret = -EINVAL;
13715                 goto done;
13716         }
13717         sctxt = rcd->sc->hw_context;
13718         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
13719         /*
13720          * Disable send-side J_KEY integrity check, unless this is A0 h/w.
13721          * This check would not have been enabled for A0 h/w, see
13722          * set_ctxt_jkey().
13723          */
13724         if (!is_ax(dd)) {
13725                 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13726                 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
13727                 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13728         }
13729         /* Turn off the J_KEY on the receive side */
13730         write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, 0);
13731 done:
13732         return ret;
13733 }
13734
13735 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey)
13736 {
13737         struct hfi1_ctxtdata *rcd;
13738         unsigned sctxt;
13739         int ret = 0;
13740         u64 reg;
13741
13742         if (ctxt < dd->num_rcv_contexts) {
13743                 rcd = dd->rcd[ctxt];
13744         } else {
13745                 ret = -EINVAL;
13746                 goto done;
13747         }
13748         if (!rcd || !rcd->sc) {
13749                 ret = -EINVAL;
13750                 goto done;
13751         }
13752         sctxt = rcd->sc->hw_context;
13753         reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
13754                 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
13755         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
13756         reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13757         reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
13758         reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK;
13759         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13760 done:
13761         return ret;
13762 }
13763
13764 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt)
13765 {
13766         struct hfi1_ctxtdata *rcd;
13767         unsigned sctxt;
13768         int ret = 0;
13769         u64 reg;
13770
13771         if (ctxt < dd->num_rcv_contexts) {
13772                 rcd = dd->rcd[ctxt];
13773         } else {
13774                 ret = -EINVAL;
13775                 goto done;
13776         }
13777         if (!rcd || !rcd->sc) {
13778                 ret = -EINVAL;
13779                 goto done;
13780         }
13781         sctxt = rcd->sc->hw_context;
13782         reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13783         reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
13784         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13785         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13786 done:
13787         return ret;
13788 }
13789
13790 /*
13791  * Start doing the clean up the the chip. Our clean up happens in multiple
13792  * stages and this is just the first.
13793  */
13794 void hfi1_start_cleanup(struct hfi1_devdata *dd)
13795 {
13796         aspm_exit(dd);
13797         free_cntrs(dd);
13798         free_rcverr(dd);
13799         clean_up_interrupts(dd);
13800         finish_chip_resources(dd);
13801 }
13802
13803 #define HFI_BASE_GUID(dev) \
13804         ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
13805
13806 /*
13807  * Information can be shared between the two HFIs on the same ASIC
13808  * in the same OS.  This function finds the peer device and sets
13809  * up a shared structure.
13810  */
13811 static int init_asic_data(struct hfi1_devdata *dd)
13812 {
13813         unsigned long flags;
13814         struct hfi1_devdata *tmp, *peer = NULL;
13815         int ret = 0;
13816
13817         spin_lock_irqsave(&hfi1_devs_lock, flags);
13818         /* Find our peer device */
13819         list_for_each_entry(tmp, &hfi1_dev_list, list) {
13820                 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) &&
13821                     dd->unit != tmp->unit) {
13822                         peer = tmp;
13823                         break;
13824                 }
13825         }
13826
13827         if (peer) {
13828                 dd->asic_data = peer->asic_data;
13829         } else {
13830                 dd->asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL);
13831                 if (!dd->asic_data) {
13832                         ret = -ENOMEM;
13833                         goto done;
13834                 }
13835                 mutex_init(&dd->asic_data->asic_resource_mutex);
13836         }
13837         dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */
13838
13839 done:
13840         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
13841         return ret;
13842 }
13843
13844 /*
13845  * Set dd->boardname.  Use a generic name if a name is not returned from
13846  * EFI variable space.
13847  *
13848  * Return 0 on success, -ENOMEM if space could not be allocated.
13849  */
13850 static int obtain_boardname(struct hfi1_devdata *dd)
13851 {
13852         /* generic board description */
13853         const char generic[] =
13854                 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
13855         unsigned long size;
13856         int ret;
13857
13858         ret = read_hfi1_efi_var(dd, "description", &size,
13859                                 (void **)&dd->boardname);
13860         if (ret) {
13861                 dd_dev_info(dd, "Board description not found\n");
13862                 /* use generic description */
13863                 dd->boardname = kstrdup(generic, GFP_KERNEL);
13864                 if (!dd->boardname)
13865                         return -ENOMEM;
13866         }
13867         return 0;
13868 }
13869
13870 /*
13871  * Check the interrupt registers to make sure that they are mapped correctly.
13872  * It is intended to help user identify any mismapping by VMM when the driver
13873  * is running in a VM. This function should only be called before interrupt
13874  * is set up properly.
13875  *
13876  * Return 0 on success, -EINVAL on failure.
13877  */
13878 static int check_int_registers(struct hfi1_devdata *dd)
13879 {
13880         u64 reg;
13881         u64 all_bits = ~(u64)0;
13882         u64 mask;
13883
13884         /* Clear CceIntMask[0] to avoid raising any interrupts */
13885         mask = read_csr(dd, CCE_INT_MASK);
13886         write_csr(dd, CCE_INT_MASK, 0ull);
13887         reg = read_csr(dd, CCE_INT_MASK);
13888         if (reg)
13889                 goto err_exit;
13890
13891         /* Clear all interrupt status bits */
13892         write_csr(dd, CCE_INT_CLEAR, all_bits);
13893         reg = read_csr(dd, CCE_INT_STATUS);
13894         if (reg)
13895                 goto err_exit;
13896
13897         /* Set all interrupt status bits */
13898         write_csr(dd, CCE_INT_FORCE, all_bits);
13899         reg = read_csr(dd, CCE_INT_STATUS);
13900         if (reg != all_bits)
13901                 goto err_exit;
13902
13903         /* Restore the interrupt mask */
13904         write_csr(dd, CCE_INT_CLEAR, all_bits);
13905         write_csr(dd, CCE_INT_MASK, mask);
13906
13907         return 0;
13908 err_exit:
13909         write_csr(dd, CCE_INT_MASK, mask);
13910         dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n");
13911         return -EINVAL;
13912 }
13913
13914 /**
13915  * Allocate and initialize the device structure for the hfi.
13916  * @dev: the pci_dev for hfi1_ib device
13917  * @ent: pci_device_id struct for this dev
13918  *
13919  * Also allocates, initializes, and returns the devdata struct for this
13920  * device instance
13921  *
13922  * This is global, and is called directly at init to set up the
13923  * chip-specific function pointers for later use.
13924  */
13925 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
13926                                   const struct pci_device_id *ent)
13927 {
13928         struct hfi1_devdata *dd;
13929         struct hfi1_pportdata *ppd;
13930         u64 reg;
13931         int i, ret;
13932         static const char * const inames[] = { /* implementation names */
13933                 "RTL silicon",
13934                 "RTL VCS simulation",
13935                 "RTL FPGA emulation",
13936                 "Functional simulator"
13937         };
13938         struct pci_dev *parent = pdev->bus->self;
13939
13940         dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
13941                                 sizeof(struct hfi1_pportdata));
13942         if (IS_ERR(dd))
13943                 goto bail;
13944         ppd = dd->pport;
13945         for (i = 0; i < dd->num_pports; i++, ppd++) {
13946                 int vl;
13947                 /* init common fields */
13948                 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
13949                 /* DC supports 4 link widths */
13950                 ppd->link_width_supported =
13951                         OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
13952                         OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
13953                 ppd->link_width_downgrade_supported =
13954                         ppd->link_width_supported;
13955                 /* start out enabling only 4X */
13956                 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
13957                 ppd->link_width_downgrade_enabled =
13958                                         ppd->link_width_downgrade_supported;
13959                 /* link width active is 0 when link is down */
13960                 /* link width downgrade active is 0 when link is down */
13961
13962                 if (num_vls < HFI1_MIN_VLS_SUPPORTED ||
13963                     num_vls > HFI1_MAX_VLS_SUPPORTED) {
13964                         hfi1_early_err(&pdev->dev,
13965                                        "Invalid num_vls %u, using %u VLs\n",
13966                                     num_vls, HFI1_MAX_VLS_SUPPORTED);
13967                         num_vls = HFI1_MAX_VLS_SUPPORTED;
13968                 }
13969                 ppd->vls_supported = num_vls;
13970                 ppd->vls_operational = ppd->vls_supported;
13971                 ppd->actual_vls_operational = ppd->vls_supported;
13972                 /* Set the default MTU. */
13973                 for (vl = 0; vl < num_vls; vl++)
13974                         dd->vld[vl].mtu = hfi1_max_mtu;
13975                 dd->vld[15].mtu = MAX_MAD_PACKET;
13976                 /*
13977                  * Set the initial values to reasonable default, will be set
13978                  * for real when link is up.
13979                  */
13980                 ppd->lstate = IB_PORT_DOWN;
13981                 ppd->overrun_threshold = 0x4;
13982                 ppd->phy_error_threshold = 0xf;
13983                 ppd->port_crc_mode_enabled = link_crc_mask;
13984                 /* initialize supported LTP CRC mode */
13985                 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
13986                 /* initialize enabled LTP CRC mode */
13987                 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
13988                 /* start in offline */
13989                 ppd->host_link_state = HLS_DN_OFFLINE;
13990                 init_vl_arb_caches(ppd);
13991                 ppd->last_pstate = 0xff; /* invalid value */
13992         }
13993
13994         dd->link_default = HLS_DN_POLL;
13995
13996         /*
13997          * Do remaining PCIe setup and save PCIe values in dd.
13998          * Any error printing is already done by the init code.
13999          * On return, we have the chip mapped.
14000          */
14001         ret = hfi1_pcie_ddinit(dd, pdev, ent);
14002         if (ret < 0)
14003                 goto bail_free;
14004
14005         /* verify that reads actually work, save revision for reset check */
14006         dd->revision = read_csr(dd, CCE_REVISION);
14007         if (dd->revision == ~(u64)0) {
14008                 dd_dev_err(dd, "cannot read chip CSRs\n");
14009                 ret = -EINVAL;
14010                 goto bail_cleanup;
14011         }
14012         dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
14013                         & CCE_REVISION_CHIP_REV_MAJOR_MASK;
14014         dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
14015                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
14016
14017         /*
14018          * Check interrupt registers mapping if the driver has no access to
14019          * the upstream component. In this case, it is likely that the driver
14020          * is running in a VM.
14021          */
14022         if (!parent) {
14023                 ret = check_int_registers(dd);
14024                 if (ret)
14025                         goto bail_cleanup;
14026         }
14027
14028         /*
14029          * obtain the hardware ID - NOT related to unit, which is a
14030          * software enumeration
14031          */
14032         reg = read_csr(dd, CCE_REVISION2);
14033         dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
14034                                         & CCE_REVISION2_HFI_ID_MASK;
14035         /* the variable size will remove unwanted bits */
14036         dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
14037         dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
14038         dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
14039                     dd->icode < ARRAY_SIZE(inames) ?
14040                     inames[dd->icode] : "unknown", (int)dd->irev);
14041
14042         /* speeds the hardware can support */
14043         dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
14044         /* speeds allowed to run at */
14045         dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
14046         /* give a reasonable active value, will be set on link up */
14047         dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
14048
14049         dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);
14050         dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);
14051         dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);
14052         dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);
14053         dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);
14054         /* fix up link widths for emulation _p */
14055         ppd = dd->pport;
14056         if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
14057                 ppd->link_width_supported =
14058                         ppd->link_width_enabled =
14059                         ppd->link_width_downgrade_supported =
14060                         ppd->link_width_downgrade_enabled =
14061                                 OPA_LINK_WIDTH_1X;
14062         }
14063         /* insure num_vls isn't larger than number of sdma engines */
14064         if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
14065                 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
14066                            num_vls, dd->chip_sdma_engines);
14067                 num_vls = dd->chip_sdma_engines;
14068                 ppd->vls_supported = dd->chip_sdma_engines;
14069                 ppd->vls_operational = ppd->vls_supported;
14070         }
14071
14072         /*
14073          * Convert the ns parameter to the 64 * cclocks used in the CSR.
14074          * Limit the max if larger than the field holds.  If timeout is
14075          * non-zero, then the calculated field will be at least 1.
14076          *
14077          * Must be after icode is set up - the cclock rate depends
14078          * on knowing the hardware being used.
14079          */
14080         dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
14081         if (dd->rcv_intr_timeout_csr >
14082                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
14083                 dd->rcv_intr_timeout_csr =
14084                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
14085         else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
14086                 dd->rcv_intr_timeout_csr = 1;
14087
14088         /* needs to be done before we look for the peer device */
14089         read_guid(dd);
14090
14091         /* set up shared ASIC data with peer device */
14092         ret = init_asic_data(dd);
14093         if (ret)
14094                 goto bail_cleanup;
14095
14096         /* obtain chip sizes, reset chip CSRs */
14097         init_chip(dd);
14098
14099         /* read in the PCIe link speed information */
14100         ret = pcie_speeds(dd);
14101         if (ret)
14102                 goto bail_cleanup;
14103
14104         /* Needs to be called before hfi1_firmware_init */
14105         get_platform_config(dd);
14106
14107         /* read in firmware */
14108         ret = hfi1_firmware_init(dd);
14109         if (ret)
14110                 goto bail_cleanup;
14111
14112         /*
14113          * In general, the PCIe Gen3 transition must occur after the
14114          * chip has been idled (so it won't initiate any PCIe transactions
14115          * e.g. an interrupt) and before the driver changes any registers
14116          * (the transition will reset the registers).
14117          *
14118          * In particular, place this call after:
14119          * - init_chip()     - the chip will not initiate any PCIe transactions
14120          * - pcie_speeds()   - reads the current link speed
14121          * - hfi1_firmware_init() - the needed firmware is ready to be
14122          *                          downloaded
14123          */
14124         ret = do_pcie_gen3_transition(dd);
14125         if (ret)
14126                 goto bail_cleanup;
14127
14128         /* start setting dd values and adjusting CSRs */
14129         init_early_variables(dd);
14130
14131         parse_platform_config(dd);
14132
14133         ret = obtain_boardname(dd);
14134         if (ret)
14135                 goto bail_cleanup;
14136
14137         snprintf(dd->boardversion, BOARD_VERS_MAX,
14138                  "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
14139                  HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
14140                  (u32)dd->majrev,
14141                  (u32)dd->minrev,
14142                  (dd->revision >> CCE_REVISION_SW_SHIFT)
14143                     & CCE_REVISION_SW_MASK);
14144
14145         /*
14146          * The real cpu mask is part of the affinity struct but has to be
14147          * initialized earlier than the rest of the affinity struct because it
14148          * is needed to calculate the number of user contexts in
14149          * set_up_context_variables(). However, hfi1_dev_affinity_init(),
14150          * which initializes the rest of the affinity struct members,
14151          * depends on set_up_context_variables() for the number of kernel
14152          * contexts, so it cannot be called before set_up_context_variables().
14153          */
14154         ret = init_real_cpu_mask(dd);
14155         if (ret)
14156                 goto bail_cleanup;
14157
14158         ret = set_up_context_variables(dd);
14159         if (ret)
14160                 goto bail_cleanup;
14161
14162         /* set initial RXE CSRs */
14163         init_rxe(dd);
14164         /* set initial TXE CSRs */
14165         init_txe(dd);
14166         /* set initial non-RXE, non-TXE CSRs */
14167         init_other(dd);
14168         /* set up KDETH QP prefix in both RX and TX CSRs */
14169         init_kdeth_qp(dd);
14170
14171         hfi1_dev_affinity_init(dd);
14172
14173         /* send contexts must be set up before receive contexts */
14174         ret = init_send_contexts(dd);
14175         if (ret)
14176                 goto bail_cleanup;
14177
14178         ret = hfi1_create_ctxts(dd);
14179         if (ret)
14180                 goto bail_cleanup;
14181
14182         dd->rcvhdrsize = DEFAULT_RCVHDRSIZE;
14183         /*
14184          * rcd[0] is guaranteed to be valid by this point. Also, all
14185          * context are using the same value, as per the module parameter.
14186          */
14187         dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
14188
14189         ret = init_pervl_scs(dd);
14190         if (ret)
14191                 goto bail_cleanup;
14192
14193         /* sdma init */
14194         for (i = 0; i < dd->num_pports; ++i) {
14195                 ret = sdma_init(dd, i);
14196                 if (ret)
14197                         goto bail_cleanup;
14198         }
14199
14200         /* use contexts created by hfi1_create_ctxts */
14201         ret = set_up_interrupts(dd);
14202         if (ret)
14203                 goto bail_cleanup;
14204
14205         /* set up LCB access - must be after set_up_interrupts() */
14206         init_lcb_access(dd);
14207
14208         snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
14209                  dd->base_guid & 0xFFFFFF);
14210
14211         dd->oui1 = dd->base_guid >> 56 & 0xFF;
14212         dd->oui2 = dd->base_guid >> 48 & 0xFF;
14213         dd->oui3 = dd->base_guid >> 40 & 0xFF;
14214
14215         ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
14216         if (ret)
14217                 goto bail_clear_intr;
14218         check_fabric_firmware_versions(dd);
14219
14220         thermal_init(dd);
14221
14222         ret = init_cntrs(dd);
14223         if (ret)
14224                 goto bail_clear_intr;
14225
14226         ret = init_rcverr(dd);
14227         if (ret)
14228                 goto bail_free_cntrs;
14229
14230         ret = eprom_init(dd);
14231         if (ret)
14232                 goto bail_free_rcverr;
14233
14234         goto bail;
14235
14236 bail_free_rcverr:
14237         free_rcverr(dd);
14238 bail_free_cntrs:
14239         free_cntrs(dd);
14240 bail_clear_intr:
14241         clean_up_interrupts(dd);
14242 bail_cleanup:
14243         hfi1_pcie_ddcleanup(dd);
14244 bail_free:
14245         hfi1_free_devdata(dd);
14246         dd = ERR_PTR(ret);
14247 bail:
14248         return dd;
14249 }
14250
14251 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
14252                         u32 dw_len)
14253 {
14254         u32 delta_cycles;
14255         u32 current_egress_rate = ppd->current_egress_rate;
14256         /* rates here are in units of 10^6 bits/sec */
14257
14258         if (desired_egress_rate == -1)
14259                 return 0; /* shouldn't happen */
14260
14261         if (desired_egress_rate >= current_egress_rate)
14262                 return 0; /* we can't help go faster, only slower */
14263
14264         delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
14265                         egress_cycles(dw_len * 4, current_egress_rate);
14266
14267         return (u16)delta_cycles;
14268 }
14269
14270 /**
14271  * create_pbc - build a pbc for transmission
14272  * @flags: special case flags or-ed in built pbc
14273  * @srate: static rate
14274  * @vl: vl
14275  * @dwlen: dword length (header words + data words + pbc words)
14276  *
14277  * Create a PBC with the given flags, rate, VL, and length.
14278  *
14279  * NOTE: The PBC created will not insert any HCRC - all callers but one are
14280  * for verbs, which does not use this PSM feature.  The lone other caller
14281  * is for the diagnostic interface which calls this if the user does not
14282  * supply their own PBC.
14283  */
14284 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
14285                u32 dw_len)
14286 {
14287         u64 pbc, delay = 0;
14288
14289         if (unlikely(srate_mbs))
14290                 delay = delay_cycles(ppd, srate_mbs, dw_len);
14291
14292         pbc = flags
14293                 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
14294                 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
14295                 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
14296                 | (dw_len & PBC_LENGTH_DWS_MASK)
14297                         << PBC_LENGTH_DWS_SHIFT;
14298
14299         return pbc;
14300 }
14301
14302 #define SBUS_THERMAL    0x4f
14303 #define SBUS_THERM_MONITOR_MODE 0x1
14304
14305 #define THERM_FAILURE(dev, ret, reason) \
14306         dd_dev_err((dd),                                                \
14307                    "Thermal sensor initialization failed: %s (%d)\n",   \
14308                    (reason), (ret))
14309
14310 /*
14311  * Initialize the Avago Thermal sensor.
14312  *
14313  * After initialization, enable polling of thermal sensor through
14314  * SBus interface. In order for this to work, the SBus Master
14315  * firmware has to be loaded due to the fact that the HW polling
14316  * logic uses SBus interrupts, which are not supported with
14317  * default firmware. Otherwise, no data will be returned through
14318  * the ASIC_STS_THERM CSR.
14319  */
14320 static int thermal_init(struct hfi1_devdata *dd)
14321 {
14322         int ret = 0;
14323
14324         if (dd->icode != ICODE_RTL_SILICON ||
14325             check_chip_resource(dd, CR_THERM_INIT, NULL))
14326                 return ret;
14327
14328         ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
14329         if (ret) {
14330                 THERM_FAILURE(dd, ret, "Acquire SBus");
14331                 return ret;
14332         }
14333
14334         dd_dev_info(dd, "Initializing thermal sensor\n");
14335         /* Disable polling of thermal readings */
14336         write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
14337         msleep(100);
14338         /* Thermal Sensor Initialization */
14339         /*    Step 1: Reset the Thermal SBus Receiver */
14340         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14341                                 RESET_SBUS_RECEIVER, 0);
14342         if (ret) {
14343                 THERM_FAILURE(dd, ret, "Bus Reset");
14344                 goto done;
14345         }
14346         /*    Step 2: Set Reset bit in Thermal block */
14347         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14348                                 WRITE_SBUS_RECEIVER, 0x1);
14349         if (ret) {
14350                 THERM_FAILURE(dd, ret, "Therm Block Reset");
14351                 goto done;
14352         }
14353         /*    Step 3: Write clock divider value (100MHz -> 2MHz) */
14354         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
14355                                 WRITE_SBUS_RECEIVER, 0x32);
14356         if (ret) {
14357                 THERM_FAILURE(dd, ret, "Write Clock Div");
14358                 goto done;
14359         }
14360         /*    Step 4: Select temperature mode */
14361         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
14362                                 WRITE_SBUS_RECEIVER,
14363                                 SBUS_THERM_MONITOR_MODE);
14364         if (ret) {
14365                 THERM_FAILURE(dd, ret, "Write Mode Sel");
14366                 goto done;
14367         }
14368         /*    Step 5: De-assert block reset and start conversion */
14369         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14370                                 WRITE_SBUS_RECEIVER, 0x2);
14371         if (ret) {
14372                 THERM_FAILURE(dd, ret, "Write Reset Deassert");
14373                 goto done;
14374         }
14375         /*    Step 5.1: Wait for first conversion (21.5ms per spec) */
14376         msleep(22);
14377
14378         /* Enable polling of thermal readings */
14379         write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
14380
14381         /* Set initialized flag */
14382         ret = acquire_chip_resource(dd, CR_THERM_INIT, 0);
14383         if (ret)
14384                 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");
14385
14386 done:
14387         release_chip_resource(dd, CR_SBUS);
14388         return ret;
14389 }
14390
14391 static void handle_temp_err(struct hfi1_devdata *dd)
14392 {
14393         struct hfi1_pportdata *ppd = &dd->pport[0];
14394         /*
14395          * Thermal Critical Interrupt
14396          * Put the device into forced freeze mode, take link down to
14397          * offline, and put DC into reset.
14398          */
14399         dd_dev_emerg(dd,
14400                      "Critical temperature reached! Forcing device into freeze mode!\n");
14401         dd->flags |= HFI1_FORCED_FREEZE;
14402         start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
14403         /*
14404          * Shut DC down as much and as quickly as possible.
14405          *
14406          * Step 1: Take the link down to OFFLINE. This will cause the
14407          *         8051 to put the Serdes in reset. However, we don't want to
14408          *         go through the entire link state machine since we want to
14409          *         shutdown ASAP. Furthermore, this is not a graceful shutdown
14410          *         but rather an attempt to save the chip.
14411          *         Code below is almost the same as quiet_serdes() but avoids
14412          *         all the extra work and the sleeps.
14413          */
14414         ppd->driver_link_ready = 0;
14415         ppd->link_enabled = 0;
14416         set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) |
14417                                 PLS_OFFLINE);
14418         /*
14419          * Step 2: Shutdown LCB and 8051
14420          *         After shutdown, do not restore DC_CFG_RESET value.
14421          */
14422         dc_shutdown(dd);
14423 }