drivers/staging/rdma/hfi1/init.c

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #include <linux/pci.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/vmalloc.h>
  51 #include <linux/delay.h>
  52 #include <linux/idr.h>
  53 #include <linux/module.h>
  54 #include <linux/printk.h>
  55 #include <linux/hrtimer.h>
  56 #include <rdma/rdma_vt.h>
  57
  58 #include "hfi.h"
  59 #include "device.h"
  60 #include "common.h"
  61 #include "trace.h"
  62 #include "mad.h"
  63 #include "sdma.h"
  64 #include "debugfs.h"
  65 #include "verbs.h"
  66 #include "aspm.h"
  67
  68 #undef pr_fmt
  69 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
  70
  71 /*
  72  * min buffers we want to have per context, after driver
  73  */
  74 #define HFI1_MIN_USER_CTXT_BUFCNT 7
  75
  76 #define HFI1_MIN_HDRQ_EGRBUF_CNT 2
  77 #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352
  78 #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
  79 #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
  80
  81 /*
  82  * Number of user receive contexts we are configured to use (to allow for more
  83  * pio buffers per ctxt, etc.)  Zero means use one user context per CPU.
  84  */
  85 int num_user_contexts = -1;
  86 module_param_named(num_user_contexts, num_user_contexts, uint, S_IRUGO);
  87 MODULE_PARM_DESC(
  88         num_user_contexts, "Set max number of user contexts to use");
  89
  90 uint krcvqs[RXE_NUM_DATA_VL];
  91 int krcvqsset;
  92 module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO);
  93 MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL");
  94
  95 /* computed based on above array */
  96 unsigned n_krcvqs;
  97
  98 static unsigned hfi1_rcvarr_split = 25;
  99 module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO);
 100 MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers");
 101
 102 static uint eager_buffer_size = (2 << 20); /* 2MB */
 103 module_param(eager_buffer_size, uint, S_IRUGO);
 104 MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 2MB");
 105
 106 static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */
 107 module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO);
 108 MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)");
 109
 110 static uint hfi1_hdrq_entsize = 32;
 111 module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, S_IRUGO);
 112 MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B");
 113
 114 unsigned int user_credit_return_threshold = 33; /* default is 33% */
 115 module_param(user_credit_return_threshold, uint, S_IRUGO);
 116 MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
 117
 118 static inline u64 encode_rcv_header_entry_size(u16);
 119
 120 static struct idr hfi1_unit_table;
 121 u32 hfi1_cpulist_count;
 122 unsigned long *hfi1_cpulist;
 123
 124 /*
 125  * Common code for creating the receive context array.
 126  */
 127 int hfi1_create_ctxts(struct hfi1_devdata *dd)
 128 {
 129         unsigned i;
 130         int ret;
 131
 132         /* Control context has to be always 0 */
 133         BUILD_BUG_ON(HFI1_CTRL_CTXT != 0);
 134
 135         dd->rcd = kzalloc_node(dd->num_rcv_contexts * sizeof(*dd->rcd),
 136                                GFP_KERNEL, dd->node);
 137         if (!dd->rcd)
 138                 goto nomem;
 139
 140         /* create one or more kernel contexts */
 141         for (i = 0; i < dd->first_user_ctxt; ++i) {
 142                 struct hfi1_pportdata *ppd;
 143                 struct hfi1_ctxtdata *rcd;
 144
 145                 ppd = dd->pport + (i % dd->num_pports);
 146                 rcd = hfi1_create_ctxtdata(ppd, i, dd->node);
 147                 if (!rcd) {
 148                         dd_dev_err(dd,
 149                                    "Unable to allocate kernel receive context, failing\n");
 150                         goto nomem;
 151                 }
 152                 /*
 153                  * Set up the kernel context flags here and now because they
 154                  * use default values for all receive side memories.  User
 155                  * contexts will be handled as they are created.
 156                  */
 157                 rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) |
 158                         HFI1_CAP_KGET(NODROP_RHQ_FULL) |
 159                         HFI1_CAP_KGET(NODROP_EGR_FULL) |
 160                         HFI1_CAP_KGET(DMA_RTAIL);
 161
 162                 /* Control context must use DMA_RTAIL */
 163                 if (rcd->ctxt == HFI1_CTRL_CTXT)
 164                         rcd->flags |= HFI1_CAP_DMA_RTAIL;
 165                 rcd->seq_cnt = 1;
 166
 167                 rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node);
 168                 if (!rcd->sc) {
 169                         dd_dev_err(dd,
 170                                    "Unable to allocate kernel send context, failing\n");
 171                         dd->rcd[rcd->ctxt] = NULL;
 172                         hfi1_free_ctxtdata(dd, rcd);
 173                         goto nomem;
 174                 }
 175
 176                 ret = hfi1_init_ctxt(rcd->sc);
 177                 if (ret < 0) {
 178                         dd_dev_err(dd,
 179                                    "Failed to setup kernel receive context, failing\n");
 180                         sc_free(rcd->sc);
 181                         dd->rcd[rcd->ctxt] = NULL;
 182                         hfi1_free_ctxtdata(dd, rcd);
 183                         ret = -EFAULT;
 184                         goto bail;
 185                 }
 186         }
 187
 188         /*
 189          * Initialize aspm, to be done after gen3 transition and setting up
 190          * contexts and before enabling interrupts
 191          */
 192         aspm_init(dd);
 193
 194         return 0;
 195 nomem:
 196         ret = -ENOMEM;
 197 bail:
 198         kfree(dd->rcd);
 199         dd->rcd = NULL;
 200         return ret;
 201 }
 202
 203 /*
 204  * Common code for user and kernel context setup.
 205  */
 206 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt,
 207                                            int numa)
 208 {
 209         struct hfi1_devdata *dd = ppd->dd;
 210         struct hfi1_ctxtdata *rcd;
 211         unsigned kctxt_ngroups = 0;
 212         u32 base;
 213
 214         if (dd->rcv_entries.nctxt_extra >
 215             dd->num_rcv_contexts - dd->first_user_ctxt)
 216                 kctxt_ngroups = (dd->rcv_entries.nctxt_extra -
 217                                  (dd->num_rcv_contexts - dd->first_user_ctxt));
 218         rcd = kzalloc(sizeof(*rcd), GFP_KERNEL);
 219         if (rcd) {
 220                 u32 rcvtids, max_entries;
 221
 222                 hfi1_cdbg(PROC, "setting up context %u\n", ctxt);
 223
 224                 INIT_LIST_HEAD(&rcd->qp_wait_list);
 225                 rcd->ppd = ppd;
 226                 rcd->dd = dd;
 227                 rcd->cnt = 1;
 228                 rcd->ctxt = ctxt;
 229                 dd->rcd[ctxt] = rcd;
 230                 rcd->numa_id = numa;
 231                 rcd->rcv_array_groups = dd->rcv_entries.ngroups;
 232
 233                 mutex_init(&rcd->exp_lock);
 234
 235                 /*
 236                  * Calculate the context's RcvArray entry starting point.
 237                  * We do this here because we have to take into account all
 238                  * the RcvArray entries that previous context would have
 239                  * taken and we have to account for any extra groups
 240                  * assigned to the kernel or user contexts.
 241                  */
 242                 if (ctxt < dd->first_user_ctxt) {
 243                         if (ctxt < kctxt_ngroups) {
 244                                 base = ctxt * (dd->rcv_entries.ngroups + 1);
 245                                 rcd->rcv_array_groups++;
 246                         } else
 247                                 base = kctxt_ngroups +
 248                                         (ctxt * dd->rcv_entries.ngroups);
 249                 } else {
 250                         u16 ct = ctxt - dd->first_user_ctxt;
 251
 252                         base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) +
 253                                 kctxt_ngroups);
 254                         if (ct < dd->rcv_entries.nctxt_extra) {
 255                                 base += ct * (dd->rcv_entries.ngroups + 1);
 256                                 rcd->rcv_array_groups++;
 257                         } else
 258                                 base += dd->rcv_entries.nctxt_extra +
 259                                         (ct * dd->rcv_entries.ngroups);
 260                 }
 261                 rcd->eager_base = base * dd->rcv_entries.group_size;
 262
 263                 /* Validate and initialize Rcv Hdr Q variables */
 264                 if (rcvhdrcnt % HDRQ_INCREMENT) {
 265                         dd_dev_err(dd,
 266                                    "ctxt%u: header queue count %d must be divisible by %lu\n",
 267                                    rcd->ctxt, rcvhdrcnt, HDRQ_INCREMENT);
 268                         goto bail;
 269                 }
 270                 rcd->rcvhdrq_cnt = rcvhdrcnt;
 271                 rcd->rcvhdrqentsize = hfi1_hdrq_entsize;
 272                 /*
 273                  * Simple Eager buffer allocation: we have already pre-allocated
 274                  * the number of RcvArray entry groups. Each ctxtdata structure
 275                  * holds the number of groups for that context.
 276                  *
 277                  * To follow CSR requirements and maintain cacheline alignment,
 278                  * make sure all sizes and bases are multiples of group_size.
 279                  *
 280                  * The expected entry count is what is left after assigning
 281                  * eager.
 282                  */
 283                 max_entries = rcd->rcv_array_groups *
 284                         dd->rcv_entries.group_size;
 285                 rcvtids = ((max_entries * hfi1_rcvarr_split) / 100);
 286                 rcd->egrbufs.count = round_down(rcvtids,
 287                                                 dd->rcv_entries.group_size);
 288                 if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) {
 289                         dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n",
 290                                    rcd->ctxt);
 291                         rcd->egrbufs.count = MAX_EAGER_ENTRIES;
 292                 }
 293                 hfi1_cdbg(PROC,
 294                           "ctxt%u: max Eager buffer RcvArray entries: %u\n",
 295                           rcd->ctxt, rcd->egrbufs.count);
 296
 297                 /*
 298                  * Allocate array that will hold the eager buffer accounting
 299                  * data.
 300                  * This will allocate the maximum possible buffer count based
 301                  * on the value of the RcvArray split parameter.
 302                  * The resulting value will be rounded down to the closest
 303                  * multiple of dd->rcv_entries.group_size.
 304                  */
 305                 rcd->egrbufs.buffers = kcalloc(rcd->egrbufs.count,
 306                                                sizeof(*rcd->egrbufs.buffers),
 307                                                GFP_KERNEL);
 308                 if (!rcd->egrbufs.buffers)
 309                         goto bail;
 310                 rcd->egrbufs.rcvtids = kcalloc(rcd->egrbufs.count,
 311                                                sizeof(*rcd->egrbufs.rcvtids),
 312                                                GFP_KERNEL);
 313                 if (!rcd->egrbufs.rcvtids)
 314                         goto bail;
 315                 rcd->egrbufs.size = eager_buffer_size;
 316                 /*
 317                  * The size of the buffers programmed into the RcvArray
 318                  * entries needs to be big enough to handle the highest
 319                  * MTU supported.
 320                  */
 321                 if (rcd->egrbufs.size < hfi1_max_mtu) {
 322                         rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu);
 323                         hfi1_cdbg(PROC,
 324                                   "ctxt%u: eager bufs size too small. Adjusting to %zu\n",
 325                                     rcd->ctxt, rcd->egrbufs.size);
 326                 }
 327                 rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE;
 328
 329                 if (ctxt < dd->first_user_ctxt) { /* N/A for PSM contexts */
 330                         rcd->opstats = kzalloc(sizeof(*rcd->opstats),
 331                                 GFP_KERNEL);
 332                         if (!rcd->opstats)
 333                                 goto bail;
 334                 }
 335         }
 336         return rcd;
 337 bail:
 338         kfree(rcd->egrbufs.rcvtids);
 339         kfree(rcd->egrbufs.buffers);
 340         kfree(rcd);
 341         return NULL;
 342 }
 343
 344 /*
 345  * Convert a receive header entry size that to the encoding used in the CSR.
 346  *
 347  * Return a zero if the given size is invalid.
 348  */
 349 static inline u64 encode_rcv_header_entry_size(u16 size)
 350 {
 351         /* there are only 3 valid receive header entry sizes */
 352         if (size == 2)
 353                 return 1;
 354         if (size == 16)
 355                 return 2;
 356         else if (size == 32)
 357                 return 4;
 358         return 0; /* invalid */
 359 }
 360
 361 /*
 362  * Select the largest ccti value over all SLs to determine the intra-
 363  * packet gap for the link.
 364  *
 365  * called with cca_timer_lock held (to protect access to cca_timer
 366  * array), and rcu_read_lock() (to protect access to cc_state).
 367  */
 368 void set_link_ipg(struct hfi1_pportdata *ppd)
 369 {
 370         struct hfi1_devdata *dd = ppd->dd;
 371         struct cc_state *cc_state;
 372         int i;
 373         u16 cce, ccti_limit, max_ccti = 0;
 374         u16 shift, mult;
 375         u64 src;
 376         u32 current_egress_rate; /* Mbits /sec */
 377         u32 max_pkt_time;
 378         /*
 379          * max_pkt_time is the maximum packet egress time in units
 380          * of the fabric clock period 1/(805 MHz).
 381          */
 382
 383         cc_state = get_cc_state(ppd);
 384
 385         if (!cc_state)
 386                 /*
 387                  * This should _never_ happen - rcu_read_lock() is held,
 388                  * and set_link_ipg() should not be called if cc_state
 389                  * is NULL.
 390                  */
 391                 return;
 392
 393         for (i = 0; i < OPA_MAX_SLS; i++) {
 394                 u16 ccti = ppd->cca_timer[i].ccti;
 395
 396                 if (ccti > max_ccti)
 397                         max_ccti = ccti;
 398         }
 399
 400         ccti_limit = cc_state->cct.ccti_limit;
 401         if (max_ccti > ccti_limit)
 402                 max_ccti = ccti_limit;
 403
 404         cce = cc_state->cct.entries[max_ccti].entry;
 405         shift = (cce & 0xc000) >> 14;
 406         mult = (cce & 0x3fff);
 407
 408         current_egress_rate = active_egress_rate(ppd);
 409
 410         max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate);
 411
 412         src = (max_pkt_time >> shift) * mult;
 413
 414         src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK;
 415         src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT;
 416
 417         write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
 418 }
 419
 420 static enum hrtimer_restart cca_timer_fn(struct hrtimer *t)
 421 {
 422         struct cca_timer *cca_timer;
 423         struct hfi1_pportdata *ppd;
 424         int sl;
 425         u16 ccti, ccti_timer, ccti_min;
 426         struct cc_state *cc_state;
 427         unsigned long flags;
 428
 429         cca_timer = container_of(t, struct cca_timer, hrtimer);
 430         ppd = cca_timer->ppd;
 431         sl = cca_timer->sl;
 432
 433         rcu_read_lock();
 434
 435         cc_state = get_cc_state(ppd);
 436
 437         if (!cc_state) {
 438                 rcu_read_unlock();
 439                 return HRTIMER_NORESTART;
 440         }
 441
 442         /*
 443          * 1) decrement ccti for SL
 444          * 2) calculate IPG for link (set_link_ipg())
 445          * 3) restart timer, unless ccti is at min value
 446          */
 447
 448         ccti_min = cc_state->cong_setting.entries[sl].ccti_min;
 449         ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
 450
 451         spin_lock_irqsave(&ppd->cca_timer_lock, flags);
 452
 453         ccti = cca_timer->ccti;
 454
 455         if (ccti > ccti_min) {
 456                 cca_timer->ccti--;
 457                 set_link_ipg(ppd);
 458         }
 459
 460         spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
 461
 462         rcu_read_unlock();
 463
 464         if (ccti > ccti_min) {
 465                 unsigned long nsec = 1024 * ccti_timer;
 466                 /* ccti_timer is in units of 1.024 usec */
 467                 hrtimer_forward_now(t, ns_to_ktime(nsec));
 468                 return HRTIMER_RESTART;
 469         }
 470         return HRTIMER_NORESTART;
 471 }
 472
 473 /*
 474  * Common code for initializing the physical port structure.
 475  */
 476 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
 477                          struct hfi1_devdata *dd, u8 hw_pidx, u8 port)
 478 {
 479         int i, size;
 480         uint default_pkey_idx;
 481
 482         ppd->dd = dd;
 483         ppd->hw_pidx = hw_pidx;
 484         ppd->port = port; /* IB port number, not index */
 485
 486         default_pkey_idx = 1;
 487
 488         ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY;
 489         if (loopback) {
 490                 hfi1_early_err(&pdev->dev,
 491                                "Faking data partition 0x8001 in idx %u\n",
 492                                !default_pkey_idx);
 493                 ppd->pkeys[!default_pkey_idx] = 0x8001;
 494         }
 495
 496         INIT_WORK(&ppd->link_vc_work, handle_verify_cap);
 497         INIT_WORK(&ppd->link_up_work, handle_link_up);
 498         INIT_WORK(&ppd->link_down_work, handle_link_down);
 499         INIT_WORK(&ppd->dc_host_req_work, handle_8051_request);
 500         INIT_WORK(&ppd->freeze_work, handle_freeze);
 501         INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade);
 502         INIT_WORK(&ppd->sma_message_work, handle_sma_message);
 503         INIT_WORK(&ppd->link_bounce_work, handle_link_bounce);
 504         INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work);
 505         INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);
 506
 507         mutex_init(&ppd->hls_lock);
 508         spin_lock_init(&ppd->sdma_alllock);
 509         spin_lock_init(&ppd->qsfp_info.qsfp_lock);
 510
 511         ppd->qsfp_info.ppd = ppd;
 512         ppd->sm_trap_qp = 0x0;
 513         ppd->sa_qp = 0x1;
 514
 515         ppd->hfi1_wq = NULL;
 516
 517         spin_lock_init(&ppd->cca_timer_lock);
 518
 519         for (i = 0; i < OPA_MAX_SLS; i++) {
 520                 hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC,
 521                              HRTIMER_MODE_REL);
 522                 ppd->cca_timer[i].ppd = ppd;
 523                 ppd->cca_timer[i].sl = i;
 524                 ppd->cca_timer[i].ccti = 0;
 525                 ppd->cca_timer[i].hrtimer.function = cca_timer_fn;
 526         }
 527
 528         ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT;
 529
 530         spin_lock_init(&ppd->cc_state_lock);
 531         spin_lock_init(&ppd->cc_log_lock);
 532         size = sizeof(struct cc_state);
 533         RCU_INIT_POINTER(ppd->cc_state, kzalloc(size, GFP_KERNEL));
 534         if (!rcu_dereference(ppd->cc_state))
 535                 goto bail;
 536         return;
 537
 538 bail:
 539
 540         hfi1_early_err(&pdev->dev,
 541                        "Congestion Control Agent disabled for port %d\n", port);
 542 }
 543
 544 /*
 545  * Do initialization for device that is only needed on
 546  * first detect, not on resets.
 547  */
 548 static int loadtime_init(struct hfi1_devdata *dd)
 549 {
 550         return 0;
 551 }
 552
 553 /**
 554  * init_after_reset - re-initialize after a reset
 555  * @dd: the hfi1_ib device
 556  *
 557  * sanity check at least some of the values after reset, and
 558  * ensure no receive or transmit (explicitly, in case reset
 559  * failed
 560  */
 561 static int init_after_reset(struct hfi1_devdata *dd)
 562 {
 563         int i;
 564
 565         /*
 566          * Ensure chip does no sends or receives, tail updates, or
 567          * pioavail updates while we re-initialize.  This is mostly
 568          * for the driver data structures, not chip registers.
 569          */
 570         for (i = 0; i < dd->num_rcv_contexts; i++)
 571                 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS |
 572                                   HFI1_RCVCTRL_INTRAVAIL_DIS |
 573                                   HFI1_RCVCTRL_TAILUPD_DIS, i);
 574         pio_send_control(dd, PSC_GLOBAL_DISABLE);
 575         for (i = 0; i < dd->num_send_contexts; i++)
 576                 sc_disable(dd->send_contexts[i].sc);
 577
 578         return 0;
 579 }
 580
 581 static void enable_chip(struct hfi1_devdata *dd)
 582 {
 583         u32 rcvmask;
 584         u32 i;
 585
 586         /* enable PIO send */
 587         pio_send_control(dd, PSC_GLOBAL_ENABLE);
 588
 589         /*
 590          * Enable kernel ctxts' receive and receive interrupt.
 591          * Other ctxts done as user opens and initializes them.
 592          */
 593         for (i = 0; i < dd->first_user_ctxt; ++i) {
 594                 rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB;
 595                 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
 596                         HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
 597                 if (!HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, MULTI_PKT_EGR))
 598                         rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB;
 599                 if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_RHQ_FULL))
 600                         rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB;
 601                 if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_EGR_FULL))
 602                         rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB;
 603                 hfi1_rcvctrl(dd, rcvmask, i);
 604                 sc_enable(dd->rcd[i]->sc);
 605         }
 606 }
 607
 608 /**
 609  * create_workqueues - create per port workqueues
 610  * @dd: the hfi1_ib device
 611  */
 612 static int create_workqueues(struct hfi1_devdata *dd)
 613 {
 614         int pidx;
 615         struct hfi1_pportdata *ppd;
 616
 617         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 618                 ppd = dd->pport + pidx;
 619                 if (!ppd->hfi1_wq) {
 620                         ppd->hfi1_wq =
 621                                 alloc_workqueue(
 622                                     "hfi%d_%d",
 623                                     WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE,
 624                                     dd->num_sdma,
 625                                     dd->unit, pidx);
 626                         if (!ppd->hfi1_wq)
 627                                 goto wq_error;
 628                 }
 629         }
 630         return 0;
 631 wq_error:
 632         pr_err("alloc_workqueue failed for port %d\n", pidx + 1);
 633         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 634                 ppd = dd->pport + pidx;
 635                 if (ppd->hfi1_wq) {
 636                         destroy_workqueue(ppd->hfi1_wq);
 637                         ppd->hfi1_wq = NULL;
 638                 }
 639         }
 640         return -ENOMEM;
 641 }
 642
 643 /**
 644  * hfi1_init - do the actual initialization sequence on the chip
 645  * @dd: the hfi1_ib device
 646  * @reinit: re-initializing, so don't allocate new memory
 647  *
 648  * Do the actual initialization sequence on the chip.  This is done
 649  * both from the init routine called from the PCI infrastructure, and
 650  * when we reset the chip, or detect that it was reset internally,
 651  * or it's administratively re-enabled.
 652  *
 653  * Memory allocation here and in called routines is only done in
 654  * the first case (reinit == 0).  We have to be careful, because even
 655  * without memory allocation, we need to re-write all the chip registers
 656  * TIDs, etc. after the reset or enable has completed.
 657  */
 658 int hfi1_init(struct hfi1_devdata *dd, int reinit)
 659 {
 660         int ret = 0, pidx, lastfail = 0;
 661         unsigned i, len;
 662         struct hfi1_ctxtdata *rcd;
 663         struct hfi1_pportdata *ppd;
 664
 665         /* Set up recv low level handlers */
 666         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EXPECTED] =
 667                                                 kdeth_process_expected;
 668         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EAGER] =
 669                                                 kdeth_process_eager;
 670         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_IB] = process_receive_ib;
 671         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_ERROR] =
 672                                                 process_receive_error;
 673         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_BYPASS] =
 674                                                 process_receive_bypass;
 675         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID5] =
 676                                                 process_receive_invalid;
 677         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID6] =
 678                                                 process_receive_invalid;
 679         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID7] =
 680                                                 process_receive_invalid;
 681         dd->rhf_rcv_function_map = dd->normal_rhf_rcv_functions;
 682
 683         /* Set up send low level handlers */
 684         dd->process_pio_send = hfi1_verbs_send_pio;
 685         dd->process_dma_send = hfi1_verbs_send_dma;
 686         dd->pio_inline_send = pio_copy;
 687
 688         if (is_ax(dd)) {
 689                 atomic_set(&dd->drop_packet, DROP_PACKET_ON);
 690                 dd->do_drop = 1;
 691         } else {
 692                 atomic_set(&dd->drop_packet, DROP_PACKET_OFF);
 693                 dd->do_drop = 0;
 694         }
 695
 696         /* make sure the link is not "up" */
 697         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 698                 ppd = dd->pport + pidx;
 699                 ppd->linkup = 0;
 700         }
 701
 702         if (reinit)
 703                 ret = init_after_reset(dd);
 704         else
 705                 ret = loadtime_init(dd);
 706         if (ret)
 707                 goto done;
 708
 709         /* allocate dummy tail memory for all receive contexts */
 710         dd->rcvhdrtail_dummy_kvaddr = dma_zalloc_coherent(
 711                 &dd->pcidev->dev, sizeof(u64),
 712                 &dd->rcvhdrtail_dummy_physaddr,
 713                 GFP_KERNEL);
 714
 715         if (!dd->rcvhdrtail_dummy_kvaddr) {
 716                 dd_dev_err(dd, "cannot allocate dummy tail memory\n");
 717                 ret = -ENOMEM;
 718                 goto done;
 719         }
 720
 721         /* dd->rcd can be NULL if early initialization failed */
 722         for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
 723                 /*
 724                  * Set up the (kernel) rcvhdr queue and egr TIDs.  If doing
 725                  * re-init, the simplest way to handle this is to free
 726                  * existing, and re-allocate.
 727                  * Need to re-create rest of ctxt 0 ctxtdata as well.
 728                  */
 729                 rcd = dd->rcd[i];
 730                 if (!rcd)
 731                         continue;
 732
 733                 rcd->do_interrupt = &handle_receive_interrupt;
 734
 735                 lastfail = hfi1_create_rcvhdrq(dd, rcd);
 736                 if (!lastfail)
 737                         lastfail = hfi1_setup_eagerbufs(rcd);
 738                 if (lastfail)
 739                         dd_dev_err(dd,
 740                                    "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
 741         }
 742         if (lastfail)
 743                 ret = lastfail;
 744
 745         /* Allocate enough memory for user event notification. */
 746         len = PAGE_ALIGN(dd->chip_rcv_contexts * HFI1_MAX_SHARED_CTXTS *
 747                          sizeof(*dd->events));
 748         dd->events = vmalloc_user(len);
 749         if (!dd->events)
 750                 dd_dev_err(dd, "Failed to allocate user events page\n");
 751         /*
 752          * Allocate a page for device and port status.
 753          * Page will be shared amongst all user processes.
 754          */
 755         dd->status = vmalloc_user(PAGE_SIZE);
 756         if (!dd->status)
 757                 dd_dev_err(dd, "Failed to allocate dev status page\n");
 758         else
 759                 dd->freezelen = PAGE_SIZE - (sizeof(*dd->status) -
 760                                              sizeof(dd->status->freezemsg));
 761         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 762                 ppd = dd->pport + pidx;
 763                 if (dd->status)
 764                         /* Currently, we only have one port */
 765                         ppd->statusp = &dd->status->port;
 766
 767                 set_mtu(ppd);
 768         }
 769
 770         /* enable chip even if we have an error, so we can debug cause */
 771         enable_chip(dd);
 772
 773 done:
 774         /*
 775          * Set status even if port serdes is not initialized
 776          * so that diags will work.
 777          */
 778         if (dd->status)
 779                 dd->status->dev |= HFI1_STATUS_CHIP_PRESENT |
 780                         HFI1_STATUS_INITTED;
 781         if (!ret) {
 782                 /* enable all interrupts from the chip */
 783                 set_intr_state(dd, 1);
 784
 785                 /* chip is OK for user apps; mark it as initialized */
 786                 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 787                         ppd = dd->pport + pidx;
 788
 789                         /*
 790                          * start the serdes - must be after interrupts are
 791                          * enabled so we are notified when the link goes up
 792                          */
 793                         lastfail = bringup_serdes(ppd);
 794                         if (lastfail)
 795                                 dd_dev_info(dd,
 796                                             "Failed to bring up port %u\n",
 797                                             ppd->port);
 798
 799                         /*
 800                          * Set status even if port serdes is not initialized
 801                          * so that diags will work.
 802                          */
 803                         if (ppd->statusp)
 804                                 *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT |
 805                                                         HFI1_STATUS_INITTED;
 806                         if (!ppd->link_speed_enabled)
 807                                 continue;
 808                 }
 809         }
 810
 811         /* if ret is non-zero, we probably should do some cleanup here... */
 812         return ret;
 813 }
 814
 815 static inline struct hfi1_devdata *__hfi1_lookup(int unit)
 816 {
 817         return idr_find(&hfi1_unit_table, unit);
 818 }
 819
 820 struct hfi1_devdata *hfi1_lookup(int unit)
 821 {
 822         struct hfi1_devdata *dd;
 823         unsigned long flags;
 824
 825         spin_lock_irqsave(&hfi1_devs_lock, flags);
 826         dd = __hfi1_lookup(unit);
 827         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
 828
 829         return dd;
 830 }
 831
 832 /*
 833  * Stop the timers during unit shutdown, or after an error late
 834  * in initialization.
 835  */
 836 static void stop_timers(struct hfi1_devdata *dd)
 837 {
 838         struct hfi1_pportdata *ppd;
 839         int pidx;
 840
 841         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 842                 ppd = dd->pport + pidx;
 843                 if (ppd->led_override_timer.data) {
 844                         del_timer_sync(&ppd->led_override_timer);
 845                         atomic_set(&ppd->led_override_timer_active, 0);
 846                 }
 847         }
 848 }
 849
 850 /**
 851  * shutdown_device - shut down a device
 852  * @dd: the hfi1_ib device
 853  *
 854  * This is called to make the device quiet when we are about to
 855  * unload the driver, and also when the device is administratively
 856  * disabled.   It does not free any data structures.
 857  * Everything it does has to be setup again by hfi1_init(dd, 1)
 858  */
 859 static void shutdown_device(struct hfi1_devdata *dd)
 860 {
 861         struct hfi1_pportdata *ppd;
 862         unsigned pidx;
 863         int i;
 864
 865         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 866                 ppd = dd->pport + pidx;
 867
 868                 ppd->linkup = 0;
 869                 if (ppd->statusp)
 870                         *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
 871                                            HFI1_STATUS_IB_READY);
 872         }
 873         dd->flags &= ~HFI1_INITTED;
 874
 875         /* mask interrupts, but not errors */
 876         set_intr_state(dd, 0);
 877
 878         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 879                 ppd = dd->pport + pidx;
 880                 for (i = 0; i < dd->num_rcv_contexts; i++)
 881                         hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS |
 882                                           HFI1_RCVCTRL_CTXT_DIS |
 883                                           HFI1_RCVCTRL_INTRAVAIL_DIS |
 884                                           HFI1_RCVCTRL_PKEY_DIS |
 885                                           HFI1_RCVCTRL_ONE_PKT_EGR_DIS, i);
 886                 /*
 887                  * Gracefully stop all sends allowing any in progress to
 888                  * trickle out first.
 889                  */
 890                 for (i = 0; i < dd->num_send_contexts; i++)
 891                         sc_flush(dd->send_contexts[i].sc);
 892         }
 893
 894         /*
 895          * Enough for anything that's going to trickle out to have actually
 896          * done so.
 897          */
 898         udelay(20);
 899
 900         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 901                 ppd = dd->pport + pidx;
 902
 903                 /* disable all contexts */
 904                 for (i = 0; i < dd->num_send_contexts; i++)
 905                         sc_disable(dd->send_contexts[i].sc);
 906                 /* disable the send device */
 907                 pio_send_control(dd, PSC_GLOBAL_DISABLE);
 908
 909                 shutdown_led_override(ppd);
 910
 911                 /*
 912                  * Clear SerdesEnable.
 913                  * We can't count on interrupts since we are stopping.
 914                  */
 915                 hfi1_quiet_serdes(ppd);
 916
 917                 if (ppd->hfi1_wq) {
 918                         destroy_workqueue(ppd->hfi1_wq);
 919                         ppd->hfi1_wq = NULL;
 920                 }
 921         }
 922         sdma_exit(dd);
 923 }
 924
 925 /**
 926  * hfi1_free_ctxtdata - free a context's allocated data
 927  * @dd: the hfi1_ib device
 928  * @rcd: the ctxtdata structure
 929  *
 930  * free up any allocated data for a context
 931  * This should not touch anything that would affect a simultaneous
 932  * re-allocation of context data, because it is called after hfi1_mutex
 933  * is released (and can be called from reinit as well).
 934  * It should never change any chip state, or global driver state.
 935  */
 936 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
 937 {
 938         unsigned e;
 939
 940         if (!rcd)
 941                 return;
 942
 943         if (rcd->rcvhdrq) {
 944                 dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size,
 945                                   rcd->rcvhdrq, rcd->rcvhdrq_phys);
 946                 rcd->rcvhdrq = NULL;
 947                 if (rcd->rcvhdrtail_kvaddr) {
 948                         dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
 949                                           (void *)rcd->rcvhdrtail_kvaddr,
 950                                           rcd->rcvhdrqtailaddr_phys);
 951                         rcd->rcvhdrtail_kvaddr = NULL;
 952                 }
 953         }
 954
 955         /* all the RcvArray entries should have been cleared by now */
 956         kfree(rcd->egrbufs.rcvtids);
 957
 958         for (e = 0; e < rcd->egrbufs.alloced; e++) {
 959                 if (rcd->egrbufs.buffers[e].phys)
 960                         dma_free_coherent(&dd->pcidev->dev,
 961                                           rcd->egrbufs.buffers[e].len,
 962                                           rcd->egrbufs.buffers[e].addr,
 963                                           rcd->egrbufs.buffers[e].phys);
 964         }
 965         kfree(rcd->egrbufs.buffers);
 966
 967         sc_free(rcd->sc);
 968         vfree(rcd->user_event_mask);
 969         vfree(rcd->subctxt_uregbase);
 970         vfree(rcd->subctxt_rcvegrbuf);
 971         vfree(rcd->subctxt_rcvhdr_base);
 972         kfree(rcd->opstats);
 973         kfree(rcd);
 974 }
 975
 976 /*
 977  * Release our hold on the shared asic data.  If we are the last one,
 978  * free the structure.  Must be holding hfi1_devs_lock.
 979  */
 980 static void release_asic_data(struct hfi1_devdata *dd)
 981 {
 982         int other;
 983
 984         if (!dd->asic_data)
 985                 return;
 986         dd->asic_data->dds[dd->hfi1_id] = NULL;
 987         other = dd->hfi1_id ? 0 : 1;
 988         if (!dd->asic_data->dds[other]) {
 989                 /* we are the last holder, free it */
 990                 kfree(dd->asic_data);
 991         }
 992         dd->asic_data = NULL;
 993 }
 994
 995 void hfi1_free_devdata(struct hfi1_devdata *dd)
 996 {
 997         unsigned long flags;
 998
 999         spin_lock_irqsave(&hfi1_devs_lock, flags);
1000         idr_remove(&hfi1_unit_table, dd->unit);
1001         list_del(&dd->list);
1002         release_asic_data(dd);
1003         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1004         free_platform_config(dd);
1005         rcu_barrier(); /* wait for rcu callbacks to complete */
1006         free_percpu(dd->int_counter);
1007         free_percpu(dd->rcv_limit);
1008         hfi1_dev_affinity_free(dd);
1009         free_percpu(dd->send_schedule);
1010         ib_dealloc_device(&dd->verbs_dev.rdi.ibdev);
1011 }
1012
1013 /*
1014  * Allocate our primary per-unit data structure.  Must be done via verbs
1015  * allocator, because the verbs cleanup process both does cleanup and
1016  * free of the data structure.
1017  * "extra" is for chip-specific data.
1018  *
1019  * Use the idr mechanism to get a unit number for this unit.
1020  */
1021 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra)
1022 {
1023         unsigned long flags;
1024         struct hfi1_devdata *dd;
1025         int ret, nports;
1026
1027         /* extra is * number of ports */
1028         nports = extra / sizeof(struct hfi1_pportdata);
1029
1030         dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1031                                                      nports);
1032         if (!dd)
1033                 return ERR_PTR(-ENOMEM);
1034         dd->num_pports = nports;
1035         dd->pport = (struct hfi1_pportdata *)(dd + 1);
1036
1037         INIT_LIST_HEAD(&dd->list);
1038         idr_preload(GFP_KERNEL);
1039         spin_lock_irqsave(&hfi1_devs_lock, flags);
1040
1041         ret = idr_alloc(&hfi1_unit_table, dd, 0, 0, GFP_NOWAIT);
1042         if (ret >= 0) {
1043                 dd->unit = ret;
1044                 list_add(&dd->list, &hfi1_dev_list);
1045         }
1046
1047         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1048         idr_preload_end();
1049
1050         if (ret < 0) {
1051                 hfi1_early_err(&pdev->dev,
1052                                "Could not allocate unit ID: error %d\n", -ret);
1053                 goto bail;
1054         }
1055         /*
1056          * Initialize all locks for the device. This needs to be as early as
1057          * possible so locks are usable.
1058          */
1059         spin_lock_init(&dd->sc_lock);
1060         spin_lock_init(&dd->sendctrl_lock);
1061         spin_lock_init(&dd->rcvctrl_lock);
1062         spin_lock_init(&dd->uctxt_lock);
1063         spin_lock_init(&dd->hfi1_diag_trans_lock);
1064         spin_lock_init(&dd->sc_init_lock);
1065         spin_lock_init(&dd->dc8051_lock);
1066         spin_lock_init(&dd->dc8051_memlock);
1067         seqlock_init(&dd->sc2vl_lock);
1068         spin_lock_init(&dd->sde_map_lock);
1069         spin_lock_init(&dd->pio_map_lock);
1070         init_waitqueue_head(&dd->event_queue);
1071
1072         dd->int_counter = alloc_percpu(u64);
1073         if (!dd->int_counter) {
1074                 ret = -ENOMEM;
1075                 hfi1_early_err(&pdev->dev,
1076                                "Could not allocate per-cpu int_counter\n");
1077                 goto bail;
1078         }
1079
1080         dd->rcv_limit = alloc_percpu(u64);
1081         if (!dd->rcv_limit) {
1082                 ret = -ENOMEM;
1083                 hfi1_early_err(&pdev->dev,
1084                                "Could not allocate per-cpu rcv_limit\n");
1085                 goto bail;
1086         }
1087
1088         dd->send_schedule = alloc_percpu(u64);
1089         if (!dd->send_schedule) {
1090                 ret = -ENOMEM;
1091                 hfi1_early_err(&pdev->dev,
1092                                "Could not allocate per-cpu int_counter\n");
1093                 goto bail;
1094         }
1095
1096         if (!hfi1_cpulist_count) {
1097                 u32 count = num_online_cpus();
1098
1099                 hfi1_cpulist = kcalloc(BITS_TO_LONGS(count), sizeof(long),
1100                                        GFP_KERNEL);
1101                 if (hfi1_cpulist)
1102                         hfi1_cpulist_count = count;
1103                 else
1104                         hfi1_early_err(
1105                         &pdev->dev,
1106                         "Could not alloc cpulist info, cpu affinity might be wrong\n");
1107         }
1108         return dd;
1109
1110 bail:
1111         if (!list_empty(&dd->list))
1112                 list_del_init(&dd->list);
1113         ib_dealloc_device(&dd->verbs_dev.rdi.ibdev);
1114         return ERR_PTR(ret);
1115 }
1116
1117 /*
1118  * Called from freeze mode handlers, and from PCI error
1119  * reporting code.  Should be paranoid about state of
1120  * system and data structures.
1121  */
1122 void hfi1_disable_after_error(struct hfi1_devdata *dd)
1123 {
1124         if (dd->flags & HFI1_INITTED) {
1125                 u32 pidx;
1126
1127                 dd->flags &= ~HFI1_INITTED;
1128                 if (dd->pport)
1129                         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1130                                 struct hfi1_pportdata *ppd;
1131
1132                                 ppd = dd->pport + pidx;
1133                                 if (dd->flags & HFI1_PRESENT)
1134                                         set_link_state(ppd, HLS_DN_DISABLE);
1135
1136                                 if (ppd->statusp)
1137                                         *ppd->statusp &= ~HFI1_STATUS_IB_READY;
1138                         }
1139         }
1140
1141         /*
1142          * Mark as having had an error for driver, and also
1143          * for /sys and status word mapped to user programs.
1144          * This marks unit as not usable, until reset.
1145          */
1146         if (dd->status)
1147                 dd->status->dev |= HFI1_STATUS_HWERROR;
1148 }
1149
1150 static void remove_one(struct pci_dev *);
1151 static int init_one(struct pci_dev *, const struct pci_device_id *);
1152
1153 #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1154 #define PFX DRIVER_NAME ": "
1155
1156 static const struct pci_device_id hfi1_pci_tbl[] = {
1157         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) },
1158         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) },
1159         { 0, }
1160 };
1161
1162 MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl);
1163
1164 static struct pci_driver hfi1_pci_driver = {
1165         .name = DRIVER_NAME,
1166         .probe = init_one,
1167         .remove = remove_one,
1168         .id_table = hfi1_pci_tbl,
1169         .err_handler = &hfi1_pci_err_handler,
1170 };
1171
1172 static void __init compute_krcvqs(void)
1173 {
1174         int i;
1175
1176         for (i = 0; i < krcvqsset; i++)
1177                 n_krcvqs += krcvqs[i];
1178 }
1179
1180 /*
1181  * Do all the generic driver unit- and chip-independent memory
1182  * allocation and initialization.
1183  */
1184 static int __init hfi1_mod_init(void)
1185 {
1186         int ret;
1187
1188         ret = dev_init();
1189         if (ret)
1190                 goto bail;
1191
1192         /* validate max MTU before any devices start */
1193         if (!valid_opa_max_mtu(hfi1_max_mtu)) {
1194                 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1195                        hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU);
1196                 hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU;
1197         }
1198         /* valid CUs run from 1-128 in powers of 2 */
1199         if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu))
1200                 hfi1_cu = 1;
1201         /* valid credit return threshold is 0-100, variable is unsigned */
1202         if (user_credit_return_threshold > 100)
1203                 user_credit_return_threshold = 100;
1204
1205         compute_krcvqs();
1206         /*
1207          * sanitize receive interrupt count, time must wait until after
1208          * the hardware type is known
1209          */
1210         if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK)
1211                 rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK;
1212         /* reject invalid combinations */
1213         if (rcv_intr_count == 0 && rcv_intr_timeout == 0) {
1214                 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1215                 rcv_intr_count = 1;
1216         }
1217         if (rcv_intr_count > 1 && rcv_intr_timeout == 0) {
1218                 /*
1219                  * Avoid indefinite packet delivery by requiring a timeout
1220                  * if count is > 1.
1221                  */
1222                 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1223                 rcv_intr_timeout = 1;
1224         }
1225         if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) {
1226                 /*
1227                  * The dynamic algorithm expects a non-zero timeout
1228                  * and a count > 1.
1229                  */
1230                 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1231                 rcv_intr_dynamic = 0;
1232         }
1233
1234         /* sanitize link CRC options */
1235         link_crc_mask &= SUPPORTED_CRCS;
1236
1237         /*
1238          * These must be called before the driver is registered with
1239          * the PCI subsystem.
1240          */
1241         idr_init(&hfi1_unit_table);
1242
1243         hfi1_dbg_init();
1244         ret = hfi1_wss_init();
1245         if (ret < 0)
1246                 goto bail_wss;
1247         ret = pci_register_driver(&hfi1_pci_driver);
1248         if (ret < 0) {
1249                 pr_err("Unable to register driver: error %d\n", -ret);
1250                 goto bail_dev;
1251         }
1252         goto bail; /* all OK */
1253
1254 bail_dev:
1255         hfi1_wss_exit();
1256 bail_wss:
1257         hfi1_dbg_exit();
1258         idr_destroy(&hfi1_unit_table);
1259         dev_cleanup();
1260 bail:
1261         return ret;
1262 }
1263
1264 module_init(hfi1_mod_init);
1265
1266 /*
1267  * Do the non-unit driver cleanup, memory free, etc. at unload.
1268  */
1269 static void __exit hfi1_mod_cleanup(void)
1270 {
1271         pci_unregister_driver(&hfi1_pci_driver);
1272         hfi1_wss_exit();
1273         hfi1_dbg_exit();
1274         hfi1_cpulist_count = 0;
1275         kfree(hfi1_cpulist);
1276
1277         idr_destroy(&hfi1_unit_table);
1278         dispose_firmware();     /* asymmetric with obtain_firmware() */
1279         dev_cleanup();
1280 }
1281
1282 module_exit(hfi1_mod_cleanup);
1283
1284 /* this can only be called after a successful initialization */
1285 static void cleanup_device_data(struct hfi1_devdata *dd)
1286 {
1287         int ctxt;
1288         int pidx;
1289         struct hfi1_ctxtdata **tmp;
1290         unsigned long flags;
1291
1292         /* users can't do anything more with chip */
1293         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1294                 struct hfi1_pportdata *ppd = &dd->pport[pidx];
1295                 struct cc_state *cc_state;
1296                 int i;
1297
1298                 if (ppd->statusp)
1299                         *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT;
1300
1301                 for (i = 0; i < OPA_MAX_SLS; i++)
1302                         hrtimer_cancel(&ppd->cca_timer[i].hrtimer);
1303
1304                 spin_lock(&ppd->cc_state_lock);
1305                 cc_state = get_cc_state(ppd);
1306                 rcu_assign_pointer(ppd->cc_state, NULL);
1307                 spin_unlock(&ppd->cc_state_lock);
1308
1309                 if (cc_state)
1310                         call_rcu(&cc_state->rcu, cc_state_reclaim);
1311         }
1312
1313         free_credit_return(dd);
1314
1315         /*
1316          * Free any resources still in use (usually just kernel contexts)
1317          * at unload; we do for ctxtcnt, because that's what we allocate.
1318          * We acquire lock to be really paranoid that rcd isn't being
1319          * accessed from some interrupt-related code (that should not happen,
1320          * but best to be sure).
1321          */
1322         spin_lock_irqsave(&dd->uctxt_lock, flags);
1323         tmp = dd->rcd;
1324         dd->rcd = NULL;
1325         spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1326
1327         if (dd->rcvhdrtail_dummy_kvaddr) {
1328                 dma_free_coherent(&dd->pcidev->dev, sizeof(u64),
1329                                   (void *)dd->rcvhdrtail_dummy_kvaddr,
1330                                   dd->rcvhdrtail_dummy_physaddr);
1331                                   dd->rcvhdrtail_dummy_kvaddr = NULL;
1332         }
1333
1334         for (ctxt = 0; tmp && ctxt < dd->num_rcv_contexts; ctxt++) {
1335                 struct hfi1_ctxtdata *rcd = tmp[ctxt];
1336
1337                 tmp[ctxt] = NULL; /* debugging paranoia */
1338                 if (rcd) {
1339                         hfi1_clear_tids(rcd);
1340                         hfi1_free_ctxtdata(dd, rcd);
1341                 }
1342         }
1343         kfree(tmp);
1344         free_pio_map(dd);
1345         /* must follow rcv context free - need to remove rcv's hooks */
1346         for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++)
1347                 sc_free(dd->send_contexts[ctxt].sc);
1348         dd->num_send_contexts = 0;
1349         kfree(dd->send_contexts);
1350         dd->send_contexts = NULL;
1351         kfree(dd->hw_to_sw);
1352         dd->hw_to_sw = NULL;
1353         kfree(dd->boardname);
1354         vfree(dd->events);
1355         vfree(dd->status);
1356 }
1357
1358 /*
1359  * Clean up on unit shutdown, or error during unit load after
1360  * successful initialization.
1361  */
1362 static void postinit_cleanup(struct hfi1_devdata *dd)
1363 {
1364         hfi1_start_cleanup(dd);
1365
1366         hfi1_pcie_ddcleanup(dd);
1367         hfi1_pcie_cleanup(dd->pcidev);
1368
1369         cleanup_device_data(dd);
1370
1371         hfi1_free_devdata(dd);
1372 }
1373
1374 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1375 {
1376         int ret = 0, j, pidx, initfail;
1377         struct hfi1_devdata *dd = NULL;
1378         struct hfi1_pportdata *ppd;
1379
1380         /* First, lock the non-writable module parameters */
1381         HFI1_CAP_LOCK();
1382
1383         /* Validate some global module parameters */
1384         if (rcvhdrcnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) {
1385                 hfi1_early_err(&pdev->dev, "Header queue  count too small\n");
1386                 ret = -EINVAL;
1387                 goto bail;
1388         }
1389         if (rcvhdrcnt > HFI1_MAX_HDRQ_EGRBUF_CNT) {
1390                 hfi1_early_err(&pdev->dev,
1391                                "Receive header queue count cannot be greater than %u\n",
1392                                HFI1_MAX_HDRQ_EGRBUF_CNT);
1393                 ret = -EINVAL;
1394                 goto bail;
1395         }
1396         /* use the encoding function as a sanitization check */
1397         if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {
1398                 hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n",
1399                                hfi1_hdrq_entsize);
1400                 ret = -EINVAL;
1401                 goto bail;
1402         }
1403
1404         /* The receive eager buffer size must be set before the receive
1405          * contexts are created.
1406          *
1407          * Set the eager buffer size.  Validate that it falls in a range
1408          * allowed by the hardware - all powers of 2 between the min and
1409          * max.  The maximum valid MTU is within the eager buffer range
1410          * so we do not need to cap the max_mtu by an eager buffer size
1411          * setting.
1412          */
1413         if (eager_buffer_size) {
1414                 if (!is_power_of_2(eager_buffer_size))
1415                         eager_buffer_size =
1416                                 roundup_pow_of_two(eager_buffer_size);
1417                 eager_buffer_size =
1418                         clamp_val(eager_buffer_size,
1419                                   MIN_EAGER_BUFFER * 8,
1420                                   MAX_EAGER_BUFFER_TOTAL);
1421                 hfi1_early_info(&pdev->dev, "Eager buffer size %u\n",
1422                                 eager_buffer_size);
1423         } else {
1424                 hfi1_early_err(&pdev->dev, "Invalid Eager buffer size of 0\n");
1425                 ret = -EINVAL;
1426                 goto bail;
1427         }
1428
1429         /* restrict value of hfi1_rcvarr_split */
1430         hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100);
1431
1432         ret = hfi1_pcie_init(pdev, ent);
1433         if (ret)
1434                 goto bail;
1435
1436         /*
1437          * Do device-specific initialization, function table setup, dd
1438          * allocation, etc.
1439          */
1440         switch (ent->device) {
1441         case PCI_DEVICE_ID_INTEL0:
1442         case PCI_DEVICE_ID_INTEL1:
1443                 dd = hfi1_init_dd(pdev, ent);
1444                 break;
1445         default:
1446                 hfi1_early_err(&pdev->dev,
1447                                "Failing on unknown Intel deviceid 0x%x\n",
1448                                ent->device);
1449                 ret = -ENODEV;
1450         }
1451
1452         if (IS_ERR(dd))
1453                 ret = PTR_ERR(dd);
1454         if (ret)
1455                 goto clean_bail; /* error already printed */
1456
1457         ret = create_workqueues(dd);
1458         if (ret)
1459                 goto clean_bail;
1460
1461         /* do the generic initialization */
1462         initfail = hfi1_init(dd, 0);
1463
1464         ret = hfi1_register_ib_device(dd);
1465
1466         /*
1467          * Now ready for use.  this should be cleared whenever we
1468          * detect a reset, or initiate one.  If earlier failure,
1469          * we still create devices, so diags, etc. can be used
1470          * to determine cause of problem.
1471          */
1472         if (!initfail && !ret) {
1473                 dd->flags |= HFI1_INITTED;
1474                 /* create debufs files after init and ib register */
1475                 hfi1_dbg_ibdev_init(&dd->verbs_dev);
1476         }
1477
1478         j = hfi1_device_create(dd);
1479         if (j)
1480                 dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1481
1482         if (initfail || ret) {
1483                 stop_timers(dd);
1484                 flush_workqueue(ib_wq);
1485                 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1486                         hfi1_quiet_serdes(dd->pport + pidx);
1487                         ppd = dd->pport + pidx;
1488                         if (ppd->hfi1_wq) {
1489                                 destroy_workqueue(ppd->hfi1_wq);
1490                                 ppd->hfi1_wq = NULL;
1491                         }
1492                 }
1493                 if (!j)
1494                         hfi1_device_remove(dd);
1495                 if (!ret)
1496                         hfi1_unregister_ib_device(dd);
1497                 postinit_cleanup(dd);
1498                 if (initfail)
1499                         ret = initfail;
1500                 goto bail;      /* everything already cleaned */
1501         }
1502
1503         sdma_start(dd);
1504
1505         return 0;
1506
1507 clean_bail:
1508         hfi1_pcie_cleanup(pdev);
1509 bail:
1510         return ret;
1511 }
1512
1513 static void remove_one(struct pci_dev *pdev)
1514 {
1515         struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1516
1517         /* close debugfs files before ib unregister */
1518         hfi1_dbg_ibdev_exit(&dd->verbs_dev);
1519         /* unregister from IB core */
1520         hfi1_unregister_ib_device(dd);
1521
1522         /*
1523          * Disable the IB link, disable interrupts on the device,
1524          * clear dma engines, etc.
1525          */
1526         shutdown_device(dd);
1527
1528         stop_timers(dd);
1529
1530         /* wait until all of our (qsfp) queue_work() calls complete */
1531         flush_workqueue(ib_wq);
1532
1533         hfi1_device_remove(dd);
1534
1535         postinit_cleanup(dd);
1536 }
1537
1538 /**
1539  * hfi1_create_rcvhdrq - create a receive header queue
1540  * @dd: the hfi1_ib device
1541  * @rcd: the context data
1542  *
1543  * This must be contiguous memory (from an i/o perspective), and must be
1544  * DMA'able (which means for some systems, it will go through an IOMMU,
1545  * or be forced into a low address range).
1546  */
1547 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1548 {
1549         unsigned amt;
1550         u64 reg;
1551
1552         if (!rcd->rcvhdrq) {
1553                 dma_addr_t phys_hdrqtail;
1554                 gfp_t gfp_flags;
1555
1556                 /*
1557                  * rcvhdrqentsize is in DWs, so we have to convert to bytes
1558                  * (* sizeof(u32)).
1559                  */
1560                 amt = PAGE_ALIGN(rcd->rcvhdrq_cnt * rcd->rcvhdrqentsize *
1561                                  sizeof(u32));
1562
1563                 gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ?
1564                         GFP_USER : GFP_KERNEL;
1565                 rcd->rcvhdrq = dma_zalloc_coherent(
1566                         &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys,
1567                         gfp_flags | __GFP_COMP);
1568
1569                 if (!rcd->rcvhdrq) {
1570                         dd_dev_err(dd,
1571                                    "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1572                                    amt, rcd->ctxt);
1573                         goto bail;
1574                 }
1575
1576                 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL)) {
1577                         rcd->rcvhdrtail_kvaddr = dma_zalloc_coherent(
1578                                 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1579                                 gfp_flags);
1580                         if (!rcd->rcvhdrtail_kvaddr)
1581                                 goto bail_free;
1582                         rcd->rcvhdrqtailaddr_phys = phys_hdrqtail;
1583                 }
1584
1585                 rcd->rcvhdrq_size = amt;
1586         }
1587         /*
1588          * These values are per-context:
1589          *      RcvHdrCnt
1590          *      RcvHdrEntSize
1591          *      RcvHdrSize
1592          */
1593         reg = ((u64)(rcd->rcvhdrq_cnt >> HDRQ_SIZE_SHIFT)
1594                         & RCV_HDR_CNT_CNT_MASK)
1595                 << RCV_HDR_CNT_CNT_SHIFT;
1596         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_CNT, reg);
1597         reg = (encode_rcv_header_entry_size(rcd->rcvhdrqentsize)
1598                         & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK)
1599                 << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT;
1600         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_ENT_SIZE, reg);
1601         reg = (dd->rcvhdrsize & RCV_HDR_SIZE_HDR_SIZE_MASK)
1602                 << RCV_HDR_SIZE_HDR_SIZE_SHIFT;
1603         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_SIZE, reg);
1604
1605         /*
1606          * Program dummy tail address for every receive context
1607          * before enabling any receive context
1608          */
1609         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_TAIL_ADDR,
1610                         dd->rcvhdrtail_dummy_physaddr);
1611
1612         return 0;
1613
1614 bail_free:
1615         dd_dev_err(dd,
1616                    "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1617                    rcd->ctxt);
1618         vfree(rcd->user_event_mask);
1619         rcd->user_event_mask = NULL;
1620         dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1621                           rcd->rcvhdrq_phys);
1622         rcd->rcvhdrq = NULL;
1623 bail:
1624         return -ENOMEM;
1625 }
1626
1627 /**
1628  * allocate eager buffers, both kernel and user contexts.
1629  * @rcd: the context we are setting up.
1630  *
1631  * Allocate the eager TID buffers and program them into hip.
1632  * They are no longer completely contiguous, we do multiple allocation
1633  * calls.  Otherwise we get the OOM code involved, by asking for too
1634  * much per call, with disastrous results on some kernels.
1635  */
1636 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
1637 {
1638         struct hfi1_devdata *dd = rcd->dd;
1639         u32 max_entries, egrtop, alloced_bytes = 0, idx = 0;
1640         gfp_t gfp_flags;
1641         u16 order;
1642         int ret = 0;
1643         u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu);
1644
1645         /*
1646          * GFP_USER, but without GFP_FS, so buffer cache can be
1647          * coalesced (we hope); otherwise, even at order 4,
1648          * heavy filesystem activity makes these fail, and we can
1649          * use compound pages.
1650          */
1651         gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
1652
1653         /*
1654          * The minimum size of the eager buffers is a groups of MTU-sized
1655          * buffers.
1656          * The global eager_buffer_size parameter is checked against the
1657          * theoretical lower limit of the value. Here, we check against the
1658          * MTU.
1659          */
1660         if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size))
1661                 rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size;
1662         /*
1663          * If using one-pkt-per-egr-buffer, lower the eager buffer
1664          * size to the max MTU (page-aligned).
1665          */
1666         if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
1667                 rcd->egrbufs.rcvtid_size = round_mtu;
1668
1669         /*
1670          * Eager buffers sizes of 1MB or less require smaller TID sizes
1671          * to satisfy the "multiple of 8 RcvArray entries" requirement.
1672          */
1673         if (rcd->egrbufs.size <= (1 << 20))
1674                 rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu,
1675                         rounddown_pow_of_two(rcd->egrbufs.size / 8));
1676
1677         while (alloced_bytes < rcd->egrbufs.size &&
1678                rcd->egrbufs.alloced < rcd->egrbufs.count) {
1679                 rcd->egrbufs.buffers[idx].addr =
1680                         dma_zalloc_coherent(&dd->pcidev->dev,
1681                                             rcd->egrbufs.rcvtid_size,
1682                                             &rcd->egrbufs.buffers[idx].phys,
1683                                             gfp_flags);
1684                 if (rcd->egrbufs.buffers[idx].addr) {
1685                         rcd->egrbufs.buffers[idx].len =
1686                                 rcd->egrbufs.rcvtid_size;
1687                         rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr =
1688                                 rcd->egrbufs.buffers[idx].addr;
1689                         rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].phys =
1690                                 rcd->egrbufs.buffers[idx].phys;
1691                         rcd->egrbufs.alloced++;
1692                         alloced_bytes += rcd->egrbufs.rcvtid_size;
1693                         idx++;
1694                 } else {
1695                         u32 new_size, i, j;
1696                         u64 offset = 0;
1697
1698                         /*
1699                          * Fail the eager buffer allocation if:
1700                          *   - we are already using the lowest acceptable size
1701                          *   - we are using one-pkt-per-egr-buffer (this implies
1702                          *     that we are accepting only one size)
1703                          */
1704                         if (rcd->egrbufs.rcvtid_size == round_mtu ||
1705                             !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) {
1706                                 dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n",
1707                                            rcd->ctxt);
1708                                 goto bail_rcvegrbuf_phys;
1709                         }
1710
1711                         new_size = rcd->egrbufs.rcvtid_size / 2;
1712
1713                         /*
1714                          * If the first attempt to allocate memory failed, don't
1715                          * fail everything but continue with the next lower
1716                          * size.
1717                          */
1718                         if (idx == 0) {
1719                                 rcd->egrbufs.rcvtid_size = new_size;
1720                                 continue;
1721                         }
1722
1723                         /*
1724                          * Re-partition already allocated buffers to a smaller
1725                          * size.
1726                          */
1727                         rcd->egrbufs.alloced = 0;
1728                         for (i = 0, j = 0, offset = 0; j < idx; i++) {
1729                                 if (i >= rcd->egrbufs.count)
1730                                         break;
1731                                 rcd->egrbufs.rcvtids[i].phys =
1732                                         rcd->egrbufs.buffers[j].phys + offset;
1733                                 rcd->egrbufs.rcvtids[i].addr =
1734                                         rcd->egrbufs.buffers[j].addr + offset;
1735                                 rcd->egrbufs.alloced++;
1736                                 if ((rcd->egrbufs.buffers[j].phys + offset +
1737                                      new_size) ==
1738                                     (rcd->egrbufs.buffers[j].phys +
1739                                      rcd->egrbufs.buffers[j].len)) {
1740                                         j++;
1741                                         offset = 0;
1742                                 } else {
1743                                         offset += new_size;
1744                                 }
1745                         }
1746                         rcd->egrbufs.rcvtid_size = new_size;
1747                 }
1748         }
1749         rcd->egrbufs.numbufs = idx;
1750         rcd->egrbufs.size = alloced_bytes;
1751
1752         hfi1_cdbg(PROC,
1753                   "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n",
1754                   rcd->ctxt, rcd->egrbufs.alloced, rcd->egrbufs.rcvtid_size,
1755                   rcd->egrbufs.size);
1756
1757         /*
1758          * Set the contexts rcv array head update threshold to the closest
1759          * power of 2 (so we can use a mask instead of modulo) below half
1760          * the allocated entries.
1761          */
1762         rcd->egrbufs.threshold =
1763                 rounddown_pow_of_two(rcd->egrbufs.alloced / 2);
1764         /*
1765          * Compute the expected RcvArray entry base. This is done after
1766          * allocating the eager buffers in order to maximize the
1767          * expected RcvArray entries for the context.
1768          */
1769         max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size;
1770         egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size);
1771         rcd->expected_count = max_entries - egrtop;
1772         if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2)
1773                 rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2;
1774
1775         rcd->expected_base = rcd->eager_base + egrtop;
1776         hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
1777                   rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count,
1778                   rcd->eager_base, rcd->expected_base);
1779
1780         if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) {
1781                 hfi1_cdbg(PROC,
1782                           "ctxt%u: current Eager buffer size is invalid %u\n",
1783                           rcd->ctxt, rcd->egrbufs.rcvtid_size);
1784                 ret = -EINVAL;
1785                 goto bail;
1786         }
1787
1788         for (idx = 0; idx < rcd->egrbufs.alloced; idx++) {
1789                 hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER,
1790                              rcd->egrbufs.rcvtids[idx].phys, order);
1791                 cond_resched();
1792         }
1793         goto bail;
1794
1795 bail_rcvegrbuf_phys:
1796         for (idx = 0; idx < rcd->egrbufs.alloced &&
1797              rcd->egrbufs.buffers[idx].addr;
1798              idx++) {
1799                 dma_free_coherent(&dd->pcidev->dev,
1800                                   rcd->egrbufs.buffers[idx].len,
1801                                   rcd->egrbufs.buffers[idx].addr,
1802                                   rcd->egrbufs.buffers[idx].phys);
1803                 rcd->egrbufs.buffers[idx].addr = NULL;
1804                 rcd->egrbufs.buffers[idx].phys = 0;
1805                 rcd->egrbufs.buffers[idx].len = 0;
1806         }
1807 bail:
1808         return ret;
1809 }