4 * Copyright(c) 2015, 2016 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
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16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
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23 * modification, are permitted provided that the following conditions
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50 /* send context types */
56 /* invalid send context index */
57 #define INVALID_SCI 0xff
59 /* PIO buffer release callback function */
60 typedef void (*pio_release_cb)(void *arg, int code);
62 /* PIO release codes - in bits, as there could more than one that apply */
63 #define PRC_OK 0 /* no known error */
64 #define PRC_STATUS_ERR 0x01 /* credit return due to status error */
65 #define PRC_PBC 0x02 /* credit return due to PBC */
66 #define PRC_THRESHOLD 0x04 /* credit return due to threshold */
67 #define PRC_FILL_ERR 0x08 /* credit return due fill error */
68 #define PRC_FORCE 0x10 /* credit return due credit force */
69 #define PRC_SC_DISABLE 0x20 /* clean-up after a context disable */
78 /* an allocated PIO buffer */
80 struct send_context *sc;/* back pointer to owning send context */
81 pio_release_cb cb; /* called when the buffer is released */
82 void *arg; /* argument for cb */
83 void __iomem *start; /* buffer start address */
84 void __iomem *end; /* context end address */
85 unsigned long size; /* context size, in bytes */
86 unsigned long sent_at; /* buffer is sent when <= free */
87 u32 block_count; /* size of buffer, in blocks */
88 u32 qw_written; /* QW written so far */
89 u32 carry_bytes; /* number of valid bytes in carry */
90 union mix carry; /* pending unwritten bytes */
93 /* cache line aligned pio buffer array */
94 union pio_shadow_ring {
96 u64 unused[16]; /* cache line spacer */
97 } ____cacheline_aligned;
99 /* per-NUMA send context */
100 struct send_context {
101 /* read-only after init */
102 struct hfi1_devdata *dd; /* device */
103 void __iomem *base_addr; /* start of PIO memory */
104 union pio_shadow_ring *sr; /* shadow ring */
106 volatile __le64 *hw_free; /* HW free counter */
107 struct work_struct halt_work; /* halted context work queue entry */
108 unsigned long flags; /* flags */
109 int node; /* context home node */
110 int type; /* context type */
111 u32 sw_index; /* software index number */
112 u32 hw_context; /* hardware context number */
113 u32 credits; /* number of blocks in context */
114 u32 sr_size; /* size of the shadow ring */
115 u32 group; /* credit return group */
116 /* allocator fields */
117 spinlock_t alloc_lock ____cacheline_aligned_in_smp;
118 unsigned long fill; /* official alloc count */
119 unsigned long alloc_free; /* copy of free (less cache thrash) */
120 u32 sr_head; /* shadow ring head */
121 /* releaser fields */
122 spinlock_t release_lock ____cacheline_aligned_in_smp;
123 unsigned long free; /* official free count */
124 u32 sr_tail; /* shadow ring tail */
125 /* list for PIO waiters */
126 struct list_head piowait ____cacheline_aligned_in_smp;
127 spinlock_t credit_ctrl_lock ____cacheline_aligned_in_smp;
128 u64 credit_ctrl; /* cache for credit control */
129 u32 credit_intr_count; /* count of credit intr users */
130 u32 __percpu *buffers_allocated;/* count of buffers allocated */
131 wait_queue_head_t halt_wait; /* wait until kernel sees interrupt */
134 /* send context flags */
135 #define SCF_ENABLED 0x01
136 #define SCF_IN_FREE 0x02
137 #define SCF_HALTED 0x04
138 #define SCF_FROZEN 0x08
140 struct send_context_info {
141 struct send_context *sc; /* allocated working context */
142 u16 allocated; /* has this been allocated? */
143 u16 type; /* context type */
144 u16 base; /* base in PIO array */
145 u16 credits; /* size in PIO array */
148 /* DMA credit return, index is always (context & 0x7) */
149 struct credit_return {
150 volatile __le64 cr[8];
153 /* NUMA indexed credit return array */
154 struct credit_return_base {
155 struct credit_return *va;
159 /* send context configuration sizes (one per type) */
160 struct sc_config_sizes {
166 * The diagram below details the relationship of the mapping structures
168 * Since the mapping now allows for non-uniform send contexts per vl, the
169 * number of send contexts for a vl is either the vl_scontexts[vl] or
170 * a computation based on num_kernel_send_contexts/num_vls:
173 * nactual = vl_scontexts ? vl_scontexts[vl] : num_kernel_send_contexts/num_vls
175 * n = roundup to next highest power of 2 using nactual
177 * In the case where there are num_kernel_send_contexts/num_vls doesn't divide
178 * evenly, the extras are added from the last vl downward.
180 * For the case where n > nactual, the send contexts are assigned
181 * in a round robin fashion wrapping back to the first send context
182 * for a particular vl.
186 * | +--------------------+
188 * pio_vl_map |--------------------|
189 * +--------------------------+ | ksc[0] -> sc 1 |
190 * | list (RCU) | |--------------------|
191 * |--------------------------| ->| ksc[1] -> sc 2 |
192 * | mask | --/ |--------------------|
193 * |--------------------------| -/ | * |
194 * | actual_vls (max 8) | -/ |--------------------|
195 * |--------------------------| --/ | ksc[n] -> sc n |
196 * | vls (max 8) | -/ +--------------------+
197 * |--------------------------| --/
199 * |--------------------------| +--------------------+
200 * | map[1] |--- | mask |
201 * |--------------------------| \---- |--------------------|
202 * | * | \-- | ksc[0] -> sc 1+n |
203 * | * | \---- |--------------------|
204 * | * | \->| ksc[1] -> sc 2+n |
205 * |--------------------------| |--------------------|
206 * | map[vls - 1] |- | * |
207 * +--------------------------+ \- |--------------------|
208 * \- | ksc[m] -> sc m+n |
209 * \ +--------------------+
212 * \- +--------------------+
214 * \ |--------------------|
215 * \- | ksc[0] -> sc 1+m+n |
216 * \- |--------------------|
217 * >| ksc[1] -> sc 2+m+n |
218 * |--------------------|
220 * |--------------------|
221 * | ksc[o] -> sc o+m+n |
222 * +--------------------+
226 /* Initial number of send contexts per VL */
227 #define INIT_SC_PER_VL 2
230 * struct pio_map_elem - mapping for a vl
231 * @mask - selector mask
232 * @ksc - array of kernel send contexts for this vl
234 * The mask is used to "mod" the selector to
235 * produce index into the trailing array of
238 struct pio_map_elem {
240 struct send_context *ksc[0];
244 * struct pio_vl_map - mapping for a vl
245 * @list - rcu head for free callback
246 * @mask - vl mask to "mod" the vl to produce an index to map array
247 * @actual_vls - number of vls
248 * @vls - numbers of vls rounded to next power of 2
249 * @map - array of pio_map_elem entries
251 * This is the parent mapping structure. The trailing members of the
252 * struct point to pio_map_elem entries, which in turn point to an
253 * array of kscs for that vl.
256 struct rcu_head list;
260 struct pio_map_elem *map[0];
263 int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls,
265 void free_pio_map(struct hfi1_devdata *dd);
266 struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
267 u32 selector, u8 vl);
268 struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
269 u32 selector, u8 sc5);
271 /* send context functions */
272 int init_credit_return(struct hfi1_devdata *dd);
273 void free_credit_return(struct hfi1_devdata *dd);
274 int init_sc_pools_and_sizes(struct hfi1_devdata *dd);
275 int init_send_contexts(struct hfi1_devdata *dd);
276 int init_credit_return(struct hfi1_devdata *dd);
277 int init_pervl_scs(struct hfi1_devdata *dd);
278 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
279 uint hdrqentsize, int numa);
280 void sc_free(struct send_context *sc);
281 int sc_enable(struct send_context *sc);
282 void sc_disable(struct send_context *sc);
283 int sc_restart(struct send_context *sc);
284 void sc_return_credits(struct send_context *sc);
285 void sc_flush(struct send_context *sc);
286 void sc_drop(struct send_context *sc);
287 void sc_stop(struct send_context *sc, int bit);
288 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
289 pio_release_cb cb, void *arg);
290 void sc_release_update(struct send_context *sc);
291 void sc_return_credits(struct send_context *sc);
292 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context);
293 void sc_add_credit_return_intr(struct send_context *sc);
294 void sc_del_credit_return_intr(struct send_context *sc);
295 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold);
296 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize);
297 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint);
298 void sc_wait(struct hfi1_devdata *dd);
299 void set_pio_integrity(struct send_context *sc);
301 /* support functions */
302 void pio_reset_all(struct hfi1_devdata *dd);
303 void pio_freeze(struct hfi1_devdata *dd);
304 void pio_kernel_unfreeze(struct hfi1_devdata *dd);
306 /* global PIO send control operations */
307 #define PSC_GLOBAL_ENABLE 0
308 #define PSC_GLOBAL_DISABLE 1
309 #define PSC_GLOBAL_VLARB_ENABLE 2
310 #define PSC_GLOBAL_VLARB_DISABLE 3
311 #define PSC_CM_RESET 4
312 #define PSC_DATA_VL_ENABLE 5
313 #define PSC_DATA_VL_DISABLE 6
315 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl);
316 void pio_send_control(struct hfi1_devdata *dd, int op);
318 /* PIO copy routines */
319 void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
320 const void *from, size_t count);
321 void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
322 const void *from, size_t nbytes);
323 void seg_pio_copy_mid(struct pio_buf *pbuf, const void *from, size_t nbytes);
324 void seg_pio_copy_end(struct pio_buf *pbuf);