2 * Copyright(c) 2015, 2016 Intel Corporation.
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48 #include <linux/delay.h>
49 #include <linux/pci.h>
50 #include <linux/vmalloc.h>
56 * "Two Wire Serial Interface" support.
58 * Originally written for a not-quite-i2c serial eeprom, which is
59 * still used on some supported boards. Later boards have added a
60 * variety of other uses, most board-specific, so the bit-boffing
61 * part has been split off to this file, while the other parts
62 * have been moved to chip-specific files.
64 * We have also dropped all pretense of fully generic (e.g. pretend
65 * we don't know whether '1' is the higher voltage) interface, as
66 * the restrictions of the generic i2c interface (e.g. no access from
67 * driver itself) make it unsuitable for this use.
74 * i2c_wait_for_writes - wait for a write
75 * @dd: the hfi1_ib device
77 * We use this instead of udelay directly, so we can make sure
78 * that previous register writes have been flushed all the way
79 * to the chip. Since we are delaying anyway, the cost doesn't
80 * hurt, and makes the bit twiddling more regular
82 static void i2c_wait_for_writes(struct hfi1_devdata *dd, u32 target)
85 * implicit read of EXTStatus is as good as explicit
86 * read of scratch, if all we want to do is flush
89 hfi1_gpio_mod(dd, target, 0, 0, 0);
90 rmb(); /* inlined, so prevent compiler reordering */
94 * QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that
95 * for "almost compliant" modules
97 #define SCL_WAIT_USEC 1000
99 /* BUF_WAIT is time bus must be free between STOP or ACK and to next START.
100 * Should be 20, but some chips need more.
102 #define TWSI_BUF_WAIT_USEC 60
104 static void scl_out(struct hfi1_devdata *dd, u32 target, u8 bit)
110 mask = QSFP_HFI0_I2CCLK;
112 /* SCL is meant to be bare-drain, so never set "OUT", just DIR */
113 hfi1_gpio_mod(dd, target, 0, bit ? 0 : mask, mask);
116 * Allow for slow slaves by simple
117 * delay for falling edge, sampling on rise.
124 for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
125 if (mask & hfi1_gpio_mod(dd, target, 0, 0, 0))
130 dd_dev_err(dd, "SCL interface stuck low > %d uSec\n",
133 i2c_wait_for_writes(dd, target);
136 static u8 scl_in(struct hfi1_devdata *dd, u32 target, int wait)
140 mask = QSFP_HFI0_I2CCLK;
141 /* SCL is meant to be bare-drain, so never set "OUT", just DIR */
142 hfi1_gpio_mod(dd, target, 0, 0, mask);
143 read_val = hfi1_gpio_mod(dd, target, 0, 0, 0);
145 i2c_wait_for_writes(dd, target);
146 return (read_val & mask) >> GPIO_SCL_NUM;
149 static void sda_out(struct hfi1_devdata *dd, u32 target, u8 bit)
153 mask = QSFP_HFI0_I2CDAT;
155 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
156 hfi1_gpio_mod(dd, target, 0, bit ? 0 : mask, mask);
158 i2c_wait_for_writes(dd, target);
162 static u8 sda_in(struct hfi1_devdata *dd, u32 target, int wait)
166 mask = QSFP_HFI0_I2CDAT;
167 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
168 hfi1_gpio_mod(dd, target, 0, 0, mask);
169 read_val = hfi1_gpio_mod(dd, target, 0, 0, 0);
171 i2c_wait_for_writes(dd, target);
172 return (read_val & mask) >> GPIO_SDA_NUM;
176 * i2c_ackrcv - see if ack following write is true
177 * @dd: the hfi1_ib device
179 static int i2c_ackrcv(struct hfi1_devdata *dd, u32 target)
183 /* AT ENTRY SCL = LOW */
184 /* change direction, ignore data */
185 ack_received = sda_in(dd, target, 1);
186 scl_out(dd, target, 1);
187 ack_received = sda_in(dd, target, 1) == 0;
188 scl_out(dd, target, 0);
192 static void stop_cmd(struct hfi1_devdata *dd, u32 target);
195 * rd_byte - read a byte, sending STOP on last, else ACK
196 * @dd: the hfi1_ib device
198 * Returns byte shifted out of device
200 static int rd_byte(struct hfi1_devdata *dd, u32 target, int last)
206 for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
208 scl_out(dd, target, 1);
209 data |= sda_in(dd, target, 0);
210 scl_out(dd, target, 0);
213 scl_out(dd, target, 1);
214 stop_cmd(dd, target);
216 sda_out(dd, target, 0);
217 scl_out(dd, target, 1);
218 scl_out(dd, target, 0);
219 sda_out(dd, target, 1);
225 * wr_byte - write a byte, one bit at a time
226 * @dd: the hfi1_ib device
227 * @data: the byte to write
229 * Returns 0 if we got the following ack, otherwise 1
231 static int wr_byte(struct hfi1_devdata *dd, u32 target, u8 data)
236 for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
237 bit = (data >> bit_cntr) & 1;
238 sda_out(dd, target, bit);
239 scl_out(dd, target, 1);
240 scl_out(dd, target, 0);
242 return (!i2c_ackrcv(dd, target)) ? 1 : 0;
246 * issue TWSI start sequence:
247 * (both clock/data high, clock high, data low while clock is high)
249 static void start_seq(struct hfi1_devdata *dd, u32 target)
251 sda_out(dd, target, 1);
252 scl_out(dd, target, 1);
253 sda_out(dd, target, 0);
255 scl_out(dd, target, 0);
259 * stop_seq - transmit the stop sequence
260 * @dd: the hfi1_ib device
262 * (both clock/data low, clock high, data high while clock is high)
264 static void stop_seq(struct hfi1_devdata *dd, u32 target)
266 scl_out(dd, target, 0);
267 sda_out(dd, target, 0);
268 scl_out(dd, target, 1);
269 sda_out(dd, target, 1);
273 * stop_cmd - transmit the stop condition
274 * @dd: the hfi1_ib device
276 * (both clock/data low, clock high, data high while clock is high)
278 static void stop_cmd(struct hfi1_devdata *dd, u32 target)
280 stop_seq(dd, target);
281 udelay(TWSI_BUF_WAIT_USEC);
285 * hfi1_twsi_reset - reset I2C communication
286 * @dd: the hfi1_ib device
287 * returns 0 if ok, -EIO on error
289 int hfi1_twsi_reset(struct hfi1_devdata *dd, u32 target)
291 int clock_cycles_left = 9;
294 /* Both SCL and SDA should be high. If not, there
295 * is something wrong.
297 mask = QSFP_HFI0_I2CCLK | QSFP_HFI0_I2CDAT;
300 * Force pins to desired innocuous state.
301 * This is the default power-on state with out=0 and dir=0,
302 * So tri-stated and should be floating high (barring HW problems)
304 hfi1_gpio_mod(dd, target, 0, 0, mask);
306 /* Check if SCL is low, if it is low then we have a slave device
307 * misbehaving and there is not much we can do.
309 if (!scl_in(dd, target, 0))
312 /* Check if SDA is low, if it is low then we have to clock SDA
313 * up to 9 times for the device to release the bus
315 while (clock_cycles_left--) {
316 if (sda_in(dd, target, 0))
318 scl_out(dd, target, 0);
319 scl_out(dd, target, 1);
325 #define HFI1_TWSI_START 0x100
326 #define HFI1_TWSI_STOP 0x200
328 /* Write byte to TWSI, optionally prefixed with START or suffixed with
330 * returns 0 if OK (ACK received), else != 0
332 static int twsi_wr(struct hfi1_devdata *dd, u32 target, int data, int flags)
336 if (flags & HFI1_TWSI_START)
337 start_seq(dd, target);
339 /* Leaves SCL low (from i2c_ackrcv()) */
340 ret = wr_byte(dd, target, data);
342 if (flags & HFI1_TWSI_STOP)
343 stop_cmd(dd, target);
347 /* Added functionality for IBA7220-based cards */
348 #define HFI1_TEMP_DEV 0x98
352 * General interface for data transfer from twsi devices.
353 * One vestige of its former role is that it recognizes a device
354 * HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
355 * which responded to all TWSI device codes, interpreting them as
356 * address within device. On all other devices found on board handled by
357 * this driver, the device is followed by a N-byte "address" which selects
358 * the "register" or "offset" within the device from which data should
361 int hfi1_twsi_blk_rd(struct hfi1_devdata *dd, u32 target, int dev, int addr,
362 void *buffer, int len)
369 /* obtain the offset size, strip it from the device address */
370 offset_size = (dev >> 8) & 0xff;
373 /* allow at most a 2 byte offset */
377 if (dev == HFI1_TWSI_NO_DEV) {
378 /* legacy not-really-I2C */
379 addr = (addr << 1) | READ_CMD;
380 ret = twsi_wr(dd, target, addr, HFI1_TWSI_START);
384 ret = twsi_wr(dd, target,
385 dev | WRITE_CMD, HFI1_TWSI_START);
387 stop_cmd(dd, target);
391 for (i = 0; i < offset_size; i++) {
392 ret = twsi_wr(dd, target,
393 (addr >> (i * 8)) & 0xff, 0);
394 udelay(TWSI_BUF_WAIT_USEC);
396 dd_dev_err(dd, "Failed to write byte %d of offset 0x%04X\n",
402 ret = twsi_wr(dd, target, dev | READ_CMD, HFI1_TWSI_START);
405 stop_cmd(dd, target);
410 * block devices keeps clocking data out as long as we ack,
411 * automatically incrementing the address. Some have "pages"
412 * whose boundaries will not be crossed, but the handling
413 * of these is left to the caller, who is in a better
418 * Get and store data, sending ACK if length remaining,
421 *bp++ = rd_byte(dd, target, !len);
432 * General interface for data transfer to twsi devices.
433 * One vestige of its former role is that it recognizes a device
434 * HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
435 * which responded to all TWSI device codes, interpreting them as
436 * address within device. On all other devices found on board handled by
437 * this driver, the device is followed by a N-byte "address" which selects
438 * the "register" or "offset" within the device to which data should
441 int hfi1_twsi_blk_wr(struct hfi1_devdata *dd, u32 target, int dev, int addr,
442 const void *buffer, int len)
444 const u8 *bp = buffer;
449 /* obtain the offset size, strip it from the device address */
450 offset_size = (dev >> 8) & 0xff;
453 /* allow at most a 2 byte offset */
457 if (dev == HFI1_TWSI_NO_DEV) {
458 if (twsi_wr(dd, target, (addr << 1) | WRITE_CMD,
464 if (twsi_wr(dd, target, dev | WRITE_CMD, HFI1_TWSI_START))
468 for (i = 0; i < offset_size; i++) {
469 ret = twsi_wr(dd, target, (addr >> (i * 8)) & 0xff, 0);
470 udelay(TWSI_BUF_WAIT_USEC);
472 dd_dev_err(dd, "Failed to write byte %d of offset 0x%04X\n",
478 for (i = 0; i < len; i++)
479 if (twsi_wr(dd, target, *bp++, 0))
485 stop_cmd(dd, target);