3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2015 Intel Corporation.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
21 * Copyright(c) 2015 Intel Corporation.
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
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34 * contributors may be used to endorse or promote products derived
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37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 #include <rdma/ib_mad.h>
52 #include <rdma/ib_user_verbs.h>
54 #include <linux/module.h>
55 #include <linux/utsname.h>
56 #include <linux/rculist.h>
58 #include <linux/random.h>
59 #include <linux/vmalloc.h>
68 unsigned int hfi1_lkey_table_size = 16;
69 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
71 MODULE_PARM_DESC(lkey_table_size,
72 "LKEY table size in bits (2^n, 1 <= n <= 23)");
74 static unsigned int hfi1_max_pds = 0xFFFF;
75 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
76 MODULE_PARM_DESC(max_pds,
77 "Maximum number of protection domains to support");
79 static unsigned int hfi1_max_ahs = 0xFFFF;
80 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
81 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
83 unsigned int hfi1_max_cqes = 0x2FFFF;
84 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
85 MODULE_PARM_DESC(max_cqes,
86 "Maximum number of completion queue entries to support");
88 unsigned int hfi1_max_cqs = 0x1FFFF;
89 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
90 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
92 unsigned int hfi1_max_qp_wrs = 0x3FFF;
93 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
94 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
96 unsigned int hfi1_max_qps = 16384;
97 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
98 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
100 unsigned int hfi1_max_sges = 0x60;
101 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
102 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
104 unsigned int hfi1_max_mcast_grps = 16384;
105 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
106 MODULE_PARM_DESC(max_mcast_grps,
107 "Maximum number of multicast groups to support");
109 unsigned int hfi1_max_mcast_qp_attached = 16;
110 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
112 MODULE_PARM_DESC(max_mcast_qp_attached,
113 "Maximum number of attached QPs to support");
115 unsigned int hfi1_max_srqs = 1024;
116 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
117 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
119 unsigned int hfi1_max_srq_sges = 128;
120 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
121 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
123 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
124 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
125 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
127 static void verbs_sdma_complete(
128 struct sdma_txreq *cookie,
132 /* Length of buffer to create verbs txreq cache name */
133 #define TXREQ_NAME_LEN 24
136 * Note that it is OK to post send work requests in the SQE and ERR
137 * states; hfi1_do_send() will process them and generate error
138 * completions as per IB 1.2 C10-96.
140 const int ib_hfi1_state_ops[IB_QPS_ERR + 1] = {
142 [IB_QPS_INIT] = HFI1_POST_RECV_OK,
143 [IB_QPS_RTR] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK,
144 [IB_QPS_RTS] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
145 HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK |
146 HFI1_PROCESS_NEXT_SEND_OK,
147 [IB_QPS_SQD] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
148 HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK,
149 [IB_QPS_SQE] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
150 HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
151 [IB_QPS_ERR] = HFI1_POST_RECV_OK | HFI1_FLUSH_RECV |
152 HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
155 struct hfi1_ucontext {
156 struct ib_ucontext ibucontext;
159 static inline struct hfi1_ucontext *to_iucontext(struct ib_ucontext
162 return container_of(ibucontext, struct hfi1_ucontext, ibucontext);
165 static inline void _hfi1_schedule_send(struct hfi1_qp *qp);
168 * Translate ib_wr_opcode into ib_wc_opcode.
170 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
171 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
172 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
173 [IB_WR_SEND] = IB_WC_SEND,
174 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
175 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
176 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
177 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
181 * Length of header by opcode, 0 --> not supported
183 const u8 hdr_len_by_opcode[256] = {
185 [IB_OPCODE_RC_SEND_FIRST] = 12 + 8,
186 [IB_OPCODE_RC_SEND_MIDDLE] = 12 + 8,
187 [IB_OPCODE_RC_SEND_LAST] = 12 + 8,
188 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
189 [IB_OPCODE_RC_SEND_ONLY] = 12 + 8,
190 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4,
191 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = 12 + 8 + 16,
192 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = 12 + 8,
193 [IB_OPCODE_RC_RDMA_WRITE_LAST] = 12 + 8,
194 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
195 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = 12 + 8 + 16,
196 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
197 [IB_OPCODE_RC_RDMA_READ_REQUEST] = 12 + 8 + 16,
198 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = 12 + 8 + 4,
199 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = 12 + 8,
200 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = 12 + 8 + 4,
201 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = 12 + 8 + 4,
202 [IB_OPCODE_RC_ACKNOWLEDGE] = 12 + 8 + 4,
203 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = 12 + 8 + 4,
204 [IB_OPCODE_RC_COMPARE_SWAP] = 12 + 8 + 28,
205 [IB_OPCODE_RC_FETCH_ADD] = 12 + 8 + 28,
207 [IB_OPCODE_UC_SEND_FIRST] = 12 + 8,
208 [IB_OPCODE_UC_SEND_MIDDLE] = 12 + 8,
209 [IB_OPCODE_UC_SEND_LAST] = 12 + 8,
210 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
211 [IB_OPCODE_UC_SEND_ONLY] = 12 + 8,
212 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4,
213 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = 12 + 8 + 16,
214 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = 12 + 8,
215 [IB_OPCODE_UC_RDMA_WRITE_LAST] = 12 + 8,
216 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
217 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = 12 + 8 + 16,
218 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
220 [IB_OPCODE_UD_SEND_ONLY] = 12 + 8 + 8,
221 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 12
224 static const opcode_handler opcode_handler_tbl[256] = {
226 [IB_OPCODE_RC_SEND_FIRST] = &hfi1_rc_rcv,
227 [IB_OPCODE_RC_SEND_MIDDLE] = &hfi1_rc_rcv,
228 [IB_OPCODE_RC_SEND_LAST] = &hfi1_rc_rcv,
229 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
230 [IB_OPCODE_RC_SEND_ONLY] = &hfi1_rc_rcv,
231 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
232 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = &hfi1_rc_rcv,
233 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = &hfi1_rc_rcv,
234 [IB_OPCODE_RC_RDMA_WRITE_LAST] = &hfi1_rc_rcv,
235 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
236 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = &hfi1_rc_rcv,
237 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
238 [IB_OPCODE_RC_RDMA_READ_REQUEST] = &hfi1_rc_rcv,
239 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = &hfi1_rc_rcv,
240 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = &hfi1_rc_rcv,
241 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = &hfi1_rc_rcv,
242 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = &hfi1_rc_rcv,
243 [IB_OPCODE_RC_ACKNOWLEDGE] = &hfi1_rc_rcv,
244 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = &hfi1_rc_rcv,
245 [IB_OPCODE_RC_COMPARE_SWAP] = &hfi1_rc_rcv,
246 [IB_OPCODE_RC_FETCH_ADD] = &hfi1_rc_rcv,
248 [IB_OPCODE_UC_SEND_FIRST] = &hfi1_uc_rcv,
249 [IB_OPCODE_UC_SEND_MIDDLE] = &hfi1_uc_rcv,
250 [IB_OPCODE_UC_SEND_LAST] = &hfi1_uc_rcv,
251 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
252 [IB_OPCODE_UC_SEND_ONLY] = &hfi1_uc_rcv,
253 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
254 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = &hfi1_uc_rcv,
255 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = &hfi1_uc_rcv,
256 [IB_OPCODE_UC_RDMA_WRITE_LAST] = &hfi1_uc_rcv,
257 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
258 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = &hfi1_uc_rcv,
259 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
261 [IB_OPCODE_UD_SEND_ONLY] = &hfi1_ud_rcv,
262 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_ud_rcv,
264 [IB_OPCODE_CNP] = &hfi1_cnp_rcv
270 __be64 ib_hfi1_sys_image_guid;
273 * hfi1_copy_sge - copy data to SGE memory
275 * @data: the data to copy
276 * @length: the length of the data
279 struct hfi1_sge_state *ss,
280 void *data, u32 length,
283 struct hfi1_sge *sge = &ss->sge;
286 u32 len = sge->length;
290 if (len > sge->sge_length)
291 len = sge->sge_length;
292 WARN_ON_ONCE(len == 0);
293 memcpy(sge->vaddr, data, len);
296 sge->sge_length -= len;
297 if (sge->sge_length == 0) {
299 hfi1_put_mr(sge->mr);
301 *sge = *ss->sg_list++;
302 } else if (sge->length == 0 && sge->mr->lkey) {
303 if (++sge->n >= HFI1_SEGSZ) {
304 if (++sge->m >= sge->mr->mapsz)
309 sge->mr->map[sge->m]->segs[sge->n].vaddr;
311 sge->mr->map[sge->m]->segs[sge->n].length;
319 * hfi1_skip_sge - skip over SGE memory
321 * @length: the number of bytes to skip
323 void hfi1_skip_sge(struct hfi1_sge_state *ss, u32 length, int release)
325 struct hfi1_sge *sge = &ss->sge;
328 u32 len = sge->length;
332 if (len > sge->sge_length)
333 len = sge->sge_length;
334 WARN_ON_ONCE(len == 0);
337 sge->sge_length -= len;
338 if (sge->sge_length == 0) {
340 hfi1_put_mr(sge->mr);
342 *sge = *ss->sg_list++;
343 } else if (sge->length == 0 && sge->mr->lkey) {
344 if (++sge->n >= HFI1_SEGSZ) {
345 if (++sge->m >= sge->mr->mapsz)
350 sge->mr->map[sge->m]->segs[sge->n].vaddr;
352 sge->mr->map[sge->m]->segs[sge->n].length;
359 * post_one_send - post one RC, UC, or UD send work request
360 * @qp: the QP to post on
361 * @wr: the work request to send
363 static int post_one_send(struct hfi1_qp *qp, struct ib_send_wr *wr)
365 struct hfi1_swqe *wqe;
370 struct hfi1_lkey_table *rkt;
372 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
373 struct hfi1_pportdata *ppd;
374 struct hfi1_ibport *ibp;
376 /* IB spec says that num_sge == 0 is OK. */
377 if (unlikely(wr->num_sge > qp->s_max_sge))
380 ppd = &dd->pport[qp->port_num - 1];
381 ibp = &ppd->ibport_data;
384 * Don't allow RDMA reads or atomic operations on UC or
385 * undefined operations.
386 * Make sure buffer is large enough to hold the result for atomics.
388 if (qp->ibqp.qp_type == IB_QPT_UC) {
389 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
391 } else if (qp->ibqp.qp_type != IB_QPT_RC) {
392 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
393 if (wr->opcode != IB_WR_SEND &&
394 wr->opcode != IB_WR_SEND_WITH_IMM)
396 /* Check UD destination address PD */
397 if (qp->ibqp.pd != ud_wr(wr)->ah->pd)
399 } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
401 else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
403 wr->sg_list[0].length < sizeof(u64) ||
404 wr->sg_list[0].addr & (sizeof(u64) - 1)))
406 else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
409 next = qp->s_head + 1;
410 if (next >= qp->s_size)
412 if (next == qp->s_last)
415 rkt = &to_idev(qp->ibqp.device)->lk_table;
416 pd = to_ipd(qp->ibqp.pd);
417 wqe = get_swqe_ptr(qp, qp->s_head);
420 if (qp->ibqp.qp_type != IB_QPT_UC &&
421 qp->ibqp.qp_type != IB_QPT_RC)
422 memcpy(&wqe->ud_wr, ud_wr(wr), sizeof(wqe->ud_wr));
423 else if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM ||
424 wr->opcode == IB_WR_RDMA_WRITE ||
425 wr->opcode == IB_WR_RDMA_READ)
426 memcpy(&wqe->rdma_wr, rdma_wr(wr), sizeof(wqe->rdma_wr));
427 else if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
428 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
429 memcpy(&wqe->atomic_wr, atomic_wr(wr), sizeof(wqe->atomic_wr));
431 memcpy(&wqe->wr, wr, sizeof(wqe->wr));
436 acc = wr->opcode >= IB_WR_RDMA_READ ?
437 IB_ACCESS_LOCAL_WRITE : 0;
438 for (i = 0; i < wr->num_sge; i++) {
439 u32 length = wr->sg_list[i].length;
444 ok = hfi1_lkey_ok(rkt, pd, &wqe->sg_list[j],
445 &wr->sg_list[i], acc);
447 goto bail_inval_free;
448 wqe->length += length;
453 if (qp->ibqp.qp_type == IB_QPT_UC ||
454 qp->ibqp.qp_type == IB_QPT_RC) {
455 if (wqe->length > 0x80000000U)
456 goto bail_inval_free;
458 struct hfi1_ah *ah = to_iah(ud_wr(wr)->ah);
460 atomic_inc(&ah->refcount);
462 wqe->ssn = qp->s_ssn++;
468 /* release mr holds */
470 struct hfi1_sge *sge = &wqe->sg_list[--j];
472 hfi1_put_mr(sge->mr);
478 * post_send - post a send on a QP
479 * @ibqp: the QP to post the send on
480 * @wr: the list of work requests to post
481 * @bad_wr: the first bad WR is put here
483 * This may be called from interrupt context.
485 static int post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
486 struct ib_send_wr **bad_wr)
488 struct hfi1_qp *qp = to_iqp(ibqp);
494 spin_lock_irqsave(&qp->s_lock, flags);
496 /* Check that state is OK to post send. */
497 if (unlikely(!(ib_hfi1_state_ops[qp->state] & HFI1_POST_SEND_OK))) {
498 spin_unlock_irqrestore(&qp->s_lock, flags);
502 /* sq empty and not list -> call send */
503 call_send = qp->s_head == qp->s_last && !wr->next;
505 for (; wr; wr = wr->next) {
506 err = post_one_send(qp, wr);
514 spin_unlock_irqrestore(&qp->s_lock, flags);
515 if (nreq && !call_send)
516 _hfi1_schedule_send(qp);
517 if (nreq && call_send)
518 hfi1_do_send(&qp->s_iowait.iowork);
523 * post_receive - post a receive on a QP
524 * @ibqp: the QP to post the receive on
525 * @wr: the WR to post
526 * @bad_wr: the first bad WR is put here
528 * This may be called from interrupt context.
530 static int post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
531 struct ib_recv_wr **bad_wr)
533 struct hfi1_qp *qp = to_iqp(ibqp);
534 struct hfi1_rwq *wq = qp->r_rq.wq;
538 /* Check that state is OK to post receive. */
539 if (!(ib_hfi1_state_ops[qp->state] & HFI1_POST_RECV_OK) || !wq) {
545 for (; wr; wr = wr->next) {
546 struct hfi1_rwqe *wqe;
550 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
556 spin_lock_irqsave(&qp->r_rq.lock, flags);
558 if (next >= qp->r_rq.size)
560 if (next == wq->tail) {
561 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
567 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
568 wqe->wr_id = wr->wr_id;
569 wqe->num_sge = wr->num_sge;
570 for (i = 0; i < wr->num_sge; i++)
571 wqe->sg_list[i] = wr->sg_list[i];
572 /* Make sure queue entry is written before the head index. */
575 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
584 * Make sure the QP is ready and able to accept the given opcode.
586 static inline int qp_ok(int opcode, struct hfi1_packet *packet)
588 struct hfi1_ibport *ibp;
590 if (!(ib_hfi1_state_ops[packet->qp->state] & HFI1_PROCESS_RECV_OK))
592 if (((opcode & OPCODE_QP_MASK) == packet->qp->allowed_ops) ||
593 (opcode == IB_OPCODE_CNP))
596 ibp = &packet->rcd->ppd->ibport_data;
603 * hfi1_ib_rcv - process an incoming packet
604 * @packet: data packet information
606 * This is called to process an incoming packet at interrupt level.
608 * Tlen is the length of the header + data + CRC in bytes.
610 void hfi1_ib_rcv(struct hfi1_packet *packet)
612 struct hfi1_ctxtdata *rcd = packet->rcd;
613 struct hfi1_ib_header *hdr = packet->hdr;
614 u32 tlen = packet->tlen;
615 struct hfi1_pportdata *ppd = rcd->ppd;
616 struct hfi1_ibport *ibp = &ppd->ibport_data;
624 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
625 if (lnh == HFI1_LRH_BTH)
626 packet->ohdr = &hdr->u.oth;
627 else if (lnh == HFI1_LRH_GRH) {
630 packet->ohdr = &hdr->u.l.oth;
631 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
633 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
634 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
636 packet->rcv_flags |= HFI1_HAS_GRH;
640 trace_input_ibhdr(rcd->dd, hdr);
642 opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
643 inc_opstats(tlen, &rcd->opstats->stats[opcode]);
645 /* Get the destination QP number. */
646 qp_num = be32_to_cpu(packet->ohdr->bth[1]) & HFI1_QPN_MASK;
647 lid = be16_to_cpu(hdr->lrh[1]);
648 if (unlikely((lid >= HFI1_MULTICAST_LID_BASE) &&
649 (lid != HFI1_PERMISSIVE_LID))) {
650 struct hfi1_mcast *mcast;
651 struct hfi1_mcast_qp *p;
653 if (lnh != HFI1_LRH_GRH)
655 mcast = hfi1_mcast_find(ibp, &hdr->u.l.grh.dgid);
658 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
660 spin_lock_irqsave(&packet->qp->r_lock, flags);
661 if (likely((qp_ok(opcode, packet))))
662 opcode_handler_tbl[opcode](packet);
663 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
666 * Notify hfi1_multicast_detach() if it is waiting for us
669 if (atomic_dec_return(&mcast->refcount) <= 1)
670 wake_up(&mcast->wait);
673 packet->qp = hfi1_lookup_qpn(ibp, qp_num);
678 spin_lock_irqsave(&packet->qp->r_lock, flags);
679 if (likely((qp_ok(opcode, packet))))
680 opcode_handler_tbl[opcode](packet);
681 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
691 * This is called from a timer to check for QPs
692 * which need kernel memory in order to send a packet.
694 static void mem_timer(unsigned long data)
696 struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data;
697 struct list_head *list = &dev->memwait;
698 struct hfi1_qp *qp = NULL;
702 write_seqlock_irqsave(&dev->iowait_lock, flags);
703 if (!list_empty(list)) {
704 wait = list_first_entry(list, struct iowait, list);
705 qp = container_of(wait, struct hfi1_qp, s_iowait);
706 list_del_init(&qp->s_iowait.list);
707 /* refcount held until actual wake up */
708 if (!list_empty(list))
709 mod_timer(&dev->mem_timer, jiffies + 1);
711 write_sequnlock_irqrestore(&dev->iowait_lock, flags);
714 hfi1_qp_wakeup(qp, HFI1_S_WAIT_KMEM);
717 void update_sge(struct hfi1_sge_state *ss, u32 length)
719 struct hfi1_sge *sge = &ss->sge;
721 sge->vaddr += length;
722 sge->length -= length;
723 sge->sge_length -= length;
724 if (sge->sge_length == 0) {
726 *sge = *ss->sg_list++;
727 } else if (sge->length == 0 && sge->mr->lkey) {
728 if (++sge->n >= HFI1_SEGSZ) {
729 if (++sge->m >= sge->mr->mapsz)
733 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
734 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
738 static noinline struct verbs_txreq *__get_txreq(struct hfi1_ibdev *dev,
741 struct verbs_txreq *tx;
744 tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
746 spin_lock_irqsave(&qp->s_lock, flags);
747 write_seqlock(&dev->iowait_lock);
748 if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK &&
749 list_empty(&qp->s_iowait.list)) {
751 qp->s_flags |= HFI1_S_WAIT_TX;
752 list_add_tail(&qp->s_iowait.list, &dev->txwait);
753 trace_hfi1_qpsleep(qp, HFI1_S_WAIT_TX);
754 atomic_inc(&qp->refcount);
756 qp->s_flags &= ~HFI1_S_BUSY;
757 write_sequnlock(&dev->iowait_lock);
758 spin_unlock_irqrestore(&qp->s_lock, flags);
759 tx = ERR_PTR(-EBUSY);
764 static inline struct verbs_txreq *get_txreq(struct hfi1_ibdev *dev,
767 struct verbs_txreq *tx;
769 tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
771 /* call slow path to get the lock */
772 tx = __get_txreq(dev, qp);
780 void hfi1_put_txreq(struct verbs_txreq *tx)
782 struct hfi1_ibdev *dev;
788 dev = to_idev(qp->ibqp.device);
794 sdma_txclean(dd_from_dev(dev), &tx->txreq);
796 /* Free verbs_txreq and return to slab cache */
797 kmem_cache_free(dev->verbs_txreq_cache, tx);
800 seq = read_seqbegin(&dev->iowait_lock);
801 if (!list_empty(&dev->txwait)) {
804 write_seqlock_irqsave(&dev->iowait_lock, flags);
805 /* Wake up first QP wanting a free struct */
806 wait = list_first_entry(&dev->txwait, struct iowait,
808 qp = container_of(wait, struct hfi1_qp, s_iowait);
809 list_del_init(&qp->s_iowait.list);
810 /* refcount held until actual wake up */
811 write_sequnlock_irqrestore(&dev->iowait_lock, flags);
812 hfi1_qp_wakeup(qp, HFI1_S_WAIT_TX);
815 } while (read_seqretry(&dev->iowait_lock, seq));
819 * This is called with progress side lock held.
822 static void verbs_sdma_complete(
823 struct sdma_txreq *cookie,
827 struct verbs_txreq *tx =
828 container_of(cookie, struct verbs_txreq, txreq);
829 struct hfi1_qp *qp = tx->qp;
831 spin_lock(&qp->s_lock);
833 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
834 else if (qp->ibqp.qp_type == IB_QPT_RC) {
835 struct hfi1_ib_header *hdr;
838 hfi1_rc_send_complete(qp, hdr);
842 * This happens when the send engine notes
843 * a QP in the error state and cannot
844 * do the flush work until that QP's
845 * sdma work has finished.
847 if (qp->s_flags & HFI1_S_WAIT_DMA) {
848 qp->s_flags &= ~HFI1_S_WAIT_DMA;
849 hfi1_schedule_send(qp);
852 spin_unlock(&qp->s_lock);
857 static int wait_kmem(struct hfi1_ibdev *dev, struct hfi1_qp *qp)
862 spin_lock_irqsave(&qp->s_lock, flags);
863 if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
864 write_seqlock(&dev->iowait_lock);
865 if (list_empty(&qp->s_iowait.list)) {
866 if (list_empty(&dev->memwait))
867 mod_timer(&dev->mem_timer, jiffies + 1);
868 qp->s_flags |= HFI1_S_WAIT_KMEM;
869 list_add_tail(&qp->s_iowait.list, &dev->memwait);
870 trace_hfi1_qpsleep(qp, HFI1_S_WAIT_KMEM);
871 atomic_inc(&qp->refcount);
873 write_sequnlock(&dev->iowait_lock);
874 qp->s_flags &= ~HFI1_S_BUSY;
877 spin_unlock_irqrestore(&qp->s_lock, flags);
883 * This routine calls txadds for each sg entry.
885 * Add failures will revert the sge cursor
887 static int build_verbs_ulp_payload(
888 struct sdma_engine *sde,
889 struct hfi1_sge_state *ss,
891 struct verbs_txreq *tx)
893 struct hfi1_sge *sg_list = ss->sg_list;
894 struct hfi1_sge sge = ss->sge;
895 u8 num_sge = ss->num_sge;
900 len = ss->sge.length;
903 if (len > ss->sge.sge_length)
904 len = ss->sge.sge_length;
905 WARN_ON_ONCE(len == 0);
906 ret = sdma_txadd_kvaddr(
920 ss->num_sge = num_sge;
921 ss->sg_list = sg_list;
926 * Build the number of DMA descriptors needed to send length bytes of data.
928 * NOTE: DMA mapping is held in the tx until completed in the ring or
929 * the tx desc is freed without having been submitted to the ring
931 * This routine insures the following all the helper routine
935 static int build_verbs_tx_desc(
936 struct sdma_engine *sde,
937 struct hfi1_sge_state *ss,
939 struct verbs_txreq *tx,
940 struct ahg_ib_header *ahdr,
944 struct hfi1_pio_header *phdr;
945 u16 hdrbytes = tx->hdr_dwords << 2;
948 if (!ahdr->ahgcount) {
949 ret = sdma_txinit_ahg(
957 verbs_sdma_complete);
960 phdr->pbc = cpu_to_le64(pbc);
961 memcpy(&phdr->hdr, &ahdr->ibh, hdrbytes - sizeof(phdr->pbc));
963 ret = sdma_txadd_kvaddr(
967 tx->hdr_dwords << 2);
971 struct hfi1_other_headers *sohdr = &ahdr->ibh.u.oth;
972 struct hfi1_other_headers *dohdr = &phdr->hdr.u.oth;
974 /* needed in rc_send_complete() */
975 phdr->hdr.lrh[0] = ahdr->ibh.lrh[0];
976 if ((be16_to_cpu(phdr->hdr.lrh[0]) & 3) == HFI1_LRH_GRH) {
977 sohdr = &ahdr->ibh.u.l.oth;
978 dohdr = &phdr->hdr.u.l.oth;
981 dohdr->bth[0] = sohdr->bth[0];
983 dohdr->bth[2] = sohdr->bth[2];
984 ret = sdma_txinit_ahg(
992 verbs_sdma_complete);
997 /* add the ulp payload - if any. ss can be NULL for acks */
999 ret = build_verbs_ulp_payload(sde, ss, length, tx);
1004 int hfi1_verbs_send_dma(struct hfi1_qp *qp, struct hfi1_pkt_state *ps,
1007 struct ahg_ib_header *ahdr = qp->s_hdr;
1008 u32 hdrwords = qp->s_hdrwords;
1009 struct hfi1_sge_state *ss = qp->s_cur_sge;
1010 u32 len = qp->s_cur_size;
1011 u32 plen = hdrwords + ((len + 3) >> 2) + 2; /* includes pbc */
1012 struct hfi1_ibdev *dev = ps->dev;
1013 struct hfi1_pportdata *ppd = ps->ppd;
1014 struct verbs_txreq *tx;
1015 struct sdma_txreq *stx;
1020 if (!list_empty(&qp->s_iowait.tx_head)) {
1021 stx = list_first_entry(
1022 &qp->s_iowait.tx_head,
1025 list_del_init(&stx->list);
1026 tx = container_of(stx, struct verbs_txreq, txreq);
1027 ret = sdma_send_txreq(tx->sde, &qp->s_iowait, stx);
1028 if (unlikely(ret == -ECOMM))
1033 tx = get_txreq(dev, qp);
1037 tx->sde = qp->s_sde;
1039 if (likely(pbc == 0)) {
1040 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1042 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1043 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1045 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1047 tx->wqe = qp->s_wqe;
1048 tx->mr = qp->s_rdma_mr;
1050 qp->s_rdma_mr = NULL;
1051 tx->hdr_dwords = hdrwords + 2;
1052 ret = build_verbs_tx_desc(tx->sde, ss, len, tx, ahdr, pbc);
1055 trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1056 ret = sdma_send_txreq(tx->sde, &qp->s_iowait, &tx->txreq);
1057 if (unlikely(ret == -ECOMM))
1062 /* The current one got "sent" */
1065 /* kmalloc or mapping fail */
1067 return wait_kmem(dev, qp);
1073 * If we are now in the error state, return zero to flush the
1074 * send work request.
1076 static int no_bufs_available(struct hfi1_qp *qp, struct send_context *sc)
1078 struct hfi1_devdata *dd = sc->dd;
1079 struct hfi1_ibdev *dev = &dd->verbs_dev;
1080 unsigned long flags;
1084 * Note that as soon as want_buffer() is called and
1085 * possibly before it returns, sc_piobufavail()
1086 * could be called. Therefore, put QP on the I/O wait list before
1087 * enabling the PIO avail interrupt.
1089 spin_lock_irqsave(&qp->s_lock, flags);
1090 if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
1091 write_seqlock(&dev->iowait_lock);
1092 if (list_empty(&qp->s_iowait.list)) {
1093 struct hfi1_ibdev *dev = &dd->verbs_dev;
1097 qp->s_flags |= HFI1_S_WAIT_PIO;
1098 was_empty = list_empty(&sc->piowait);
1099 list_add_tail(&qp->s_iowait.list, &sc->piowait);
1100 trace_hfi1_qpsleep(qp, HFI1_S_WAIT_PIO);
1101 atomic_inc(&qp->refcount);
1102 /* counting: only call wantpiobuf_intr if first user */
1104 hfi1_sc_wantpiobuf_intr(sc, 1);
1106 write_sequnlock(&dev->iowait_lock);
1107 qp->s_flags &= ~HFI1_S_BUSY;
1110 spin_unlock_irqrestore(&qp->s_lock, flags);
1114 struct send_context *qp_to_send_context(struct hfi1_qp *qp, u8 sc5)
1116 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1117 struct hfi1_pportdata *ppd = dd->pport + (qp->port_num - 1);
1120 vl = sc_to_vlt(dd, sc5);
1121 if (vl >= ppd->vls_supported && vl != 15)
1123 return dd->vld[vl].sc;
1126 int hfi1_verbs_send_pio(struct hfi1_qp *qp, struct hfi1_pkt_state *ps,
1129 struct ahg_ib_header *ahdr = qp->s_hdr;
1130 u32 hdrwords = qp->s_hdrwords;
1131 struct hfi1_sge_state *ss = qp->s_cur_sge;
1132 u32 len = qp->s_cur_size;
1133 u32 dwords = (len + 3) >> 2;
1134 u32 plen = hdrwords + dwords + 2; /* includes pbc */
1135 struct hfi1_pportdata *ppd = ps->ppd;
1136 u32 *hdr = (u32 *)&ahdr->ibh;
1139 unsigned long flags = 0;
1140 struct send_context *sc;
1141 struct pio_buf *pbuf;
1142 int wc_status = IB_WC_SUCCESS;
1144 /* vl15 special case taken care of in ud.c */
1146 sc = qp_to_send_context(qp, sc5);
1150 if (likely(pbc == 0)) {
1151 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1152 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1153 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1154 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1156 pbuf = sc_buffer_alloc(sc, plen, NULL, NULL);
1157 if (unlikely(pbuf == NULL)) {
1158 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1160 * If we have filled the PIO buffers to capacity and are
1161 * not in an active state this request is not going to
1162 * go out to so just complete it with an error or else a
1163 * ULP or the core may be stuck waiting.
1167 "alloc failed. state not active, completing");
1168 wc_status = IB_WC_GENERAL_ERR;
1172 * This is a normal occurrence. The PIO buffs are full
1173 * up but we are still happily sending, well we could be
1174 * so lets continue to queue the request.
1176 hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1177 return no_bufs_available(qp, sc);
1182 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1185 seg_pio_copy_start(pbuf, pbc, hdr, hdrwords*4);
1187 void *addr = ss->sge.vaddr;
1188 u32 slen = ss->sge.length;
1192 update_sge(ss, slen);
1193 seg_pio_copy_mid(pbuf, addr, slen);
1196 seg_pio_copy_end(pbuf);
1200 trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1202 if (qp->s_rdma_mr) {
1203 hfi1_put_mr(qp->s_rdma_mr);
1204 qp->s_rdma_mr = NULL;
1209 spin_lock_irqsave(&qp->s_lock, flags);
1210 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1211 spin_unlock_irqrestore(&qp->s_lock, flags);
1212 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1213 spin_lock_irqsave(&qp->s_lock, flags);
1214 hfi1_rc_send_complete(qp, &ahdr->ibh);
1215 spin_unlock_irqrestore(&qp->s_lock, flags);
1221 * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1222 * being an entry from the ingress partition key table), return 0
1223 * otherwise. Use the matching criteria for egress partition keys
1224 * specified in the OPAv1 spec., section 9.1l.7.
1226 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1228 u16 mkey = pkey & PKEY_LOW_15_MASK;
1229 u16 ment = ent & PKEY_LOW_15_MASK;
1233 * If pkey[15] is set (full partition member),
1234 * is bit 15 in the corresponding table element
1235 * clear (limited member)?
1237 if (pkey & PKEY_MEMBER_MASK)
1238 return !!(ent & PKEY_MEMBER_MASK);
1245 * egress_pkey_check - return 0 if hdr's pkey matches according to the
1246 * criteria in the OPAv1 spec., section 9.11.7.
1248 static inline int egress_pkey_check(struct hfi1_pportdata *ppd,
1249 struct hfi1_ib_header *hdr,
1252 struct hfi1_other_headers *ohdr;
1253 struct hfi1_devdata *dd;
1256 u8 lnh, sc5 = qp->s_sc;
1258 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1261 /* locate the pkey within the headers */
1262 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
1263 if (lnh == HFI1_LRH_GRH)
1264 ohdr = &hdr->u.l.oth;
1268 pkey = (u16)be32_to_cpu(ohdr->bth[0]);
1270 /* If SC15, pkey[0:14] must be 0x7fff */
1271 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1275 /* Is the pkey = 0x0, or 0x8000? */
1276 if ((pkey & PKEY_LOW_15_MASK) == 0)
1279 /* The most likely matching pkey has index qp->s_pkey_index */
1280 if (unlikely(!egress_pkey_matches_entry(pkey,
1281 ppd->pkeys[qp->s_pkey_index]))) {
1282 /* no match - try the entire table */
1283 for (; i < MAX_PKEY_VALUES; i++) {
1284 if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1289 if (i < MAX_PKEY_VALUES)
1292 incr_cntr64(&ppd->port_xmit_constraint_errors);
1294 if (!(dd->err_info_xmit_constraint.status & OPA_EI_STATUS_SMASK)) {
1295 u16 slid = be16_to_cpu(hdr->lrh[3]);
1297 dd->err_info_xmit_constraint.status |= OPA_EI_STATUS_SMASK;
1298 dd->err_info_xmit_constraint.slid = slid;
1299 dd->err_info_xmit_constraint.pkey = pkey;
1305 * hfi1_verbs_send - send a packet
1306 * @qp: the QP to send on
1307 * @ps: the state of the packet to send
1309 * Return zero if packet is sent or queued OK.
1310 * Return non-zero and clear qp->s_flags HFI1_S_BUSY otherwise.
1312 int hfi1_verbs_send(struct hfi1_qp *qp, struct hfi1_pkt_state *ps)
1314 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1315 struct ahg_ib_header *ahdr = qp->s_hdr;
1318 unsigned long flags = 0;
1321 * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1322 * can defer SDMA restart until link goes ACTIVE without
1323 * worrying about just how we got there.
1325 if ((qp->ibqp.qp_type == IB_QPT_SMI) ||
1326 !(dd->flags & HFI1_HAS_SEND_DMA))
1329 ret = egress_pkey_check(dd->pport, &ahdr->ibh, qp);
1330 if (unlikely(ret)) {
1332 * The value we are returning here does not get propagated to
1333 * the verbs caller. Thus we need to complete the request with
1334 * error otherwise the caller could be sitting waiting on the
1335 * completion event. Only do this for PIO. SDMA has its own
1336 * mechanism for handling the errors. So for SDMA we can just
1340 hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1342 spin_lock_irqsave(&qp->s_lock, flags);
1343 hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1344 spin_unlock_irqrestore(&qp->s_lock, flags);
1350 ret = dd->process_pio_send(qp, ps, 0);
1352 #ifdef CONFIG_SDMA_VERBOSITY
1353 dd_dev_err(dd, "CONFIG SDMA %s:%d %s()\n",
1354 slashstrip(__FILE__), __LINE__, __func__);
1355 dd_dev_err(dd, "SDMA hdrwords = %u, len = %u\n", qp->s_hdrwords,
1358 ret = dd->process_dma_send(qp, ps, 0);
1364 static int query_device(struct ib_device *ibdev,
1365 struct ib_device_attr *props,
1366 struct ib_udata *uhw)
1368 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1369 struct hfi1_ibdev *dev = to_idev(ibdev);
1371 if (uhw->inlen || uhw->outlen)
1373 memset(props, 0, sizeof(*props));
1375 props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1376 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1377 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1378 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1380 props->page_size_cap = PAGE_SIZE;
1382 dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1383 props->vendor_part_id = dd->pcidev->device;
1384 props->hw_ver = dd->minrev;
1385 props->sys_image_guid = ib_hfi1_sys_image_guid;
1386 props->max_mr_size = ~0ULL;
1387 props->max_qp = hfi1_max_qps;
1388 props->max_qp_wr = hfi1_max_qp_wrs;
1389 props->max_sge = hfi1_max_sges;
1390 props->max_sge_rd = hfi1_max_sges;
1391 props->max_cq = hfi1_max_cqs;
1392 props->max_ah = hfi1_max_ahs;
1393 props->max_cqe = hfi1_max_cqes;
1394 props->max_mr = dev->lk_table.max;
1395 props->max_fmr = dev->lk_table.max;
1396 props->max_map_per_fmr = 32767;
1397 props->max_pd = hfi1_max_pds;
1398 props->max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1399 props->max_qp_init_rd_atom = 255;
1400 /* props->max_res_rd_atom */
1401 props->max_srq = hfi1_max_srqs;
1402 props->max_srq_wr = hfi1_max_srq_wrs;
1403 props->max_srq_sge = hfi1_max_srq_sges;
1404 /* props->local_ca_ack_delay */
1405 props->atomic_cap = IB_ATOMIC_GLOB;
1406 props->max_pkeys = hfi1_get_npkeys(dd);
1407 props->max_mcast_grp = hfi1_max_mcast_grps;
1408 props->max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1409 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1410 props->max_mcast_grp;
1415 static inline u16 opa_speed_to_ib(u16 in)
1419 if (in & OPA_LINK_SPEED_25G)
1420 out |= IB_SPEED_EDR;
1421 if (in & OPA_LINK_SPEED_12_5G)
1422 out |= IB_SPEED_FDR;
1428 * Convert a single OPA link width (no multiple flags) to an IB value.
1429 * A zero OPA link width means link down, which means the IB width value
1432 static inline u16 opa_width_to_ib(u16 in)
1435 case OPA_LINK_WIDTH_1X:
1436 /* map 2x and 3x to 1x as they don't exist in IB */
1437 case OPA_LINK_WIDTH_2X:
1438 case OPA_LINK_WIDTH_3X:
1440 default: /* link down or unknown, return our largest width */
1441 case OPA_LINK_WIDTH_4X:
1446 static int query_port(struct ib_device *ibdev, u8 port,
1447 struct ib_port_attr *props)
1449 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1450 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1451 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1454 memset(props, 0, sizeof(*props));
1455 props->lid = lid ? lid : 0;
1456 props->lmc = ppd->lmc;
1457 props->sm_lid = ibp->sm_lid;
1458 props->sm_sl = ibp->sm_sl;
1459 /* OPA logical states match IB logical states */
1460 props->state = driver_lstate(ppd);
1461 props->phys_state = hfi1_ibphys_portstate(ppd);
1462 props->port_cap_flags = ibp->port_cap_flags;
1463 props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1464 props->max_msg_sz = 0x80000000;
1465 props->pkey_tbl_len = hfi1_get_npkeys(dd);
1466 props->bad_pkey_cntr = ibp->pkey_violations;
1467 props->qkey_viol_cntr = ibp->qkey_violations;
1468 props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1469 /* see rate_show() in ib core/sysfs.c */
1470 props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1471 props->max_vl_num = ppd->vls_supported;
1472 props->init_type_reply = 0;
1474 /* Once we are a "first class" citizen and have added the OPA MTUs to
1475 * the core we can advertise the larger MTU enum to the ULPs, for now
1476 * advertise only 4K.
1478 * Those applications which are either OPA aware or pass the MTU enum
1479 * from the Path Records to us will get the new 8k MTU. Those that
1480 * attempt to process the MTU enum may fail in various ways.
1482 props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1483 4096 : hfi1_max_mtu), IB_MTU_4096);
1484 props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1485 mtu_to_enum(ppd->ibmtu, IB_MTU_2048);
1486 props->subnet_timeout = ibp->subnet_timeout;
1491 static int port_immutable(struct ib_device *ibdev, u8 port_num,
1492 struct ib_port_immutable *immutable)
1494 struct ib_port_attr attr;
1497 err = query_port(ibdev, port_num, &attr);
1501 memset(immutable, 0, sizeof(*immutable));
1503 immutable->pkey_tbl_len = attr.pkey_tbl_len;
1504 immutable->gid_tbl_len = attr.gid_tbl_len;
1505 immutable->core_cap_flags = RDMA_CORE_PORT_INTEL_OPA;
1506 immutable->max_mad_size = OPA_MGMT_MAD_SIZE;
1511 static int modify_device(struct ib_device *device,
1512 int device_modify_mask,
1513 struct ib_device_modify *device_modify)
1515 struct hfi1_devdata *dd = dd_from_ibdev(device);
1519 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1520 IB_DEVICE_MODIFY_NODE_DESC)) {
1525 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1526 memcpy(device->node_desc, device_modify->node_desc, 64);
1527 for (i = 0; i < dd->num_pports; i++) {
1528 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1530 hfi1_node_desc_chg(ibp);
1534 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1535 ib_hfi1_sys_image_guid =
1536 cpu_to_be64(device_modify->sys_image_guid);
1537 for (i = 0; i < dd->num_pports; i++) {
1538 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1540 hfi1_sys_guid_chg(ibp);
1550 static int modify_port(struct ib_device *ibdev, u8 port,
1551 int port_modify_mask, struct ib_port_modify *props)
1553 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1554 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1557 ibp->port_cap_flags |= props->set_port_cap_mask;
1558 ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1559 if (props->set_port_cap_mask || props->clr_port_cap_mask)
1560 hfi1_cap_mask_chg(ibp);
1561 if (port_modify_mask & IB_PORT_SHUTDOWN) {
1562 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1563 OPA_LINKDOWN_REASON_UNKNOWN);
1564 ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1566 if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1567 ibp->qkey_violations = 0;
1571 static int query_gid(struct ib_device *ibdev, u8 port,
1572 int index, union ib_gid *gid)
1574 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1577 if (!port || port > dd->num_pports)
1580 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1581 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1583 gid->global.subnet_prefix = ibp->gid_prefix;
1585 gid->global.interface_id = cpu_to_be64(ppd->guid);
1586 else if (index < HFI1_GUIDS_PER_PORT)
1587 gid->global.interface_id = ibp->guids[index - 1];
1595 static struct ib_pd *alloc_pd(struct ib_device *ibdev,
1596 struct ib_ucontext *context,
1597 struct ib_udata *udata)
1599 struct hfi1_ibdev *dev = to_idev(ibdev);
1604 * This is actually totally arbitrary. Some correctness tests
1605 * assume there's a maximum number of PDs that can be allocated.
1606 * We don't actually have this limit, but we fail the test if
1607 * we allow allocations of more than we report for this value.
1610 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1612 ret = ERR_PTR(-ENOMEM);
1616 spin_lock(&dev->n_pds_lock);
1617 if (dev->n_pds_allocated == hfi1_max_pds) {
1618 spin_unlock(&dev->n_pds_lock);
1620 ret = ERR_PTR(-ENOMEM);
1624 dev->n_pds_allocated++;
1625 spin_unlock(&dev->n_pds_lock);
1627 /* ib_alloc_pd() will initialize pd->ibpd. */
1628 pd->user = udata != NULL;
1636 static int dealloc_pd(struct ib_pd *ibpd)
1638 struct hfi1_pd *pd = to_ipd(ibpd);
1639 struct hfi1_ibdev *dev = to_idev(ibpd->device);
1641 spin_lock(&dev->n_pds_lock);
1642 dev->n_pds_allocated--;
1643 spin_unlock(&dev->n_pds_lock);
1651 * convert ah port,sl to sc
1653 u8 ah_to_sc(struct ib_device *ibdev, struct ib_ah_attr *ah)
1655 struct hfi1_ibport *ibp = to_iport(ibdev, ah->port_num);
1657 return ibp->sl_to_sc[ah->sl];
1660 int hfi1_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1662 struct hfi1_ibport *ibp;
1663 struct hfi1_pportdata *ppd;
1664 struct hfi1_devdata *dd;
1667 /* A multicast address requires a GRH (see ch. 8.4.1). */
1668 if (ah_attr->dlid >= HFI1_MULTICAST_LID_BASE &&
1669 ah_attr->dlid != HFI1_PERMISSIVE_LID &&
1670 !(ah_attr->ah_flags & IB_AH_GRH))
1672 if ((ah_attr->ah_flags & IB_AH_GRH) &&
1673 ah_attr->grh.sgid_index >= HFI1_GUIDS_PER_PORT)
1675 if (ah_attr->dlid == 0)
1677 if (ah_attr->port_num < 1 ||
1678 ah_attr->port_num > ibdev->phys_port_cnt)
1680 if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1681 ib_rate_to_mbps(ah_attr->static_rate) < 0)
1683 if (ah_attr->sl >= OPA_MAX_SLS)
1685 /* test the mapping for validity */
1686 ibp = to_iport(ibdev, ah_attr->port_num);
1687 ppd = ppd_from_ibp(ibp);
1688 sc5 = ibp->sl_to_sc[ah_attr->sl];
1689 dd = dd_from_ppd(ppd);
1690 if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1698 * create_ah - create an address handle
1699 * @pd: the protection domain
1700 * @ah_attr: the attributes of the AH
1702 * This may be called from interrupt context.
1704 static struct ib_ah *create_ah(struct ib_pd *pd,
1705 struct ib_ah_attr *ah_attr)
1709 struct hfi1_ibdev *dev = to_idev(pd->device);
1710 unsigned long flags;
1712 if (hfi1_check_ah(pd->device, ah_attr)) {
1713 ret = ERR_PTR(-EINVAL);
1717 ah = kmalloc(sizeof(*ah), GFP_ATOMIC);
1719 ret = ERR_PTR(-ENOMEM);
1723 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1724 if (dev->n_ahs_allocated == hfi1_max_ahs) {
1725 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1727 ret = ERR_PTR(-ENOMEM);
1731 dev->n_ahs_allocated++;
1732 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1734 /* ib_create_ah() will initialize ah->ibah. */
1735 ah->attr = *ah_attr;
1736 atomic_set(&ah->refcount, 0);
1744 struct ib_ah *hfi1_create_qp0_ah(struct hfi1_ibport *ibp, u16 dlid)
1746 struct ib_ah_attr attr;
1747 struct ib_ah *ah = ERR_PTR(-EINVAL);
1748 struct hfi1_qp *qp0;
1750 memset(&attr, 0, sizeof(attr));
1752 attr.port_num = ppd_from_ibp(ibp)->port;
1754 qp0 = rcu_dereference(ibp->qp[0]);
1756 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1762 * destroy_ah - destroy an address handle
1763 * @ibah: the AH to destroy
1765 * This may be called from interrupt context.
1767 static int destroy_ah(struct ib_ah *ibah)
1769 struct hfi1_ibdev *dev = to_idev(ibah->device);
1770 struct hfi1_ah *ah = to_iah(ibah);
1771 unsigned long flags;
1773 if (atomic_read(&ah->refcount) != 0)
1776 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1777 dev->n_ahs_allocated--;
1778 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1785 static int modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1787 struct hfi1_ah *ah = to_iah(ibah);
1789 if (hfi1_check_ah(ibah->device, ah_attr))
1792 ah->attr = *ah_attr;
1797 static int query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1799 struct hfi1_ah *ah = to_iah(ibah);
1801 *ah_attr = ah->attr;
1807 * hfi1_get_npkeys - return the size of the PKEY table for context 0
1808 * @dd: the hfi1_ib device
1810 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1812 return ARRAY_SIZE(dd->pport[0].pkeys);
1815 static int query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1818 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1821 if (index >= hfi1_get_npkeys(dd)) {
1826 *pkey = hfi1_get_pkey(to_iport(ibdev, port), index);
1834 * alloc_ucontext - allocate a ucontest
1835 * @ibdev: the infiniband device
1836 * @udata: not used by the driver
1839 static struct ib_ucontext *alloc_ucontext(struct ib_device *ibdev,
1840 struct ib_udata *udata)
1842 struct hfi1_ucontext *context;
1843 struct ib_ucontext *ret;
1845 context = kmalloc(sizeof(*context), GFP_KERNEL);
1847 ret = ERR_PTR(-ENOMEM);
1851 ret = &context->ibucontext;
1857 static int dealloc_ucontext(struct ib_ucontext *context)
1859 kfree(to_iucontext(context));
1863 static void init_ibport(struct hfi1_pportdata *ppd)
1865 struct hfi1_ibport *ibp = &ppd->ibport_data;
1866 size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1869 for (i = 0; i < sz; i++) {
1870 ibp->sl_to_sc[i] = i;
1871 ibp->sc_to_sl[i] = i;
1874 spin_lock_init(&ibp->lock);
1875 /* Set the prefix to the default value (see ch. 4.1.1) */
1876 ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
1878 /* Below should only set bits defined in OPA PortInfo.CapabilityMask */
1879 ibp->port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1880 IB_PORT_CAP_MASK_NOTICE_SUP;
1881 ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1882 ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1883 ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1884 ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1885 ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1887 RCU_INIT_POINTER(ibp->qp[0], NULL);
1888 RCU_INIT_POINTER(ibp->qp[1], NULL);
1891 static void verbs_txreq_kmem_cache_ctor(void *obj)
1893 struct verbs_txreq *tx = obj;
1895 memset(tx, 0, sizeof(*tx));
1899 * hfi1_register_ib_device - register our device with the infiniband core
1900 * @dd: the device data structure
1901 * Return 0 if successful, errno if unsuccessful.
1903 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1905 struct hfi1_ibdev *dev = &dd->verbs_dev;
1906 struct ib_device *ibdev = &dev->ibdev;
1907 struct hfi1_pportdata *ppd = dd->pport;
1908 unsigned i, lk_tab_size;
1910 size_t lcpysz = IB_DEVICE_NAME_MAX;
1912 char buf[TXREQ_NAME_LEN];
1914 ret = hfi1_qp_init(dev);
1919 for (i = 0; i < dd->num_pports; i++)
1920 init_ibport(ppd + i);
1922 /* Only need to initialize non-zero fields. */
1923 spin_lock_init(&dev->n_pds_lock);
1924 spin_lock_init(&dev->n_ahs_lock);
1925 spin_lock_init(&dev->n_cqs_lock);
1926 spin_lock_init(&dev->n_qps_lock);
1927 spin_lock_init(&dev->n_srqs_lock);
1928 spin_lock_init(&dev->n_mcast_grps_lock);
1929 init_timer(&dev->mem_timer);
1930 dev->mem_timer.function = mem_timer;
1931 dev->mem_timer.data = (unsigned long) dev;
1934 * The top hfi1_lkey_table_size bits are used to index the
1935 * table. The lower 8 bits can be owned by the user (copied from
1936 * the LKEY). The remaining bits act as a generation number or tag.
1938 spin_lock_init(&dev->lk_table.lock);
1939 dev->lk_table.max = 1 << hfi1_lkey_table_size;
1940 /* ensure generation is at least 4 bits (keys.c) */
1941 if (hfi1_lkey_table_size > MAX_LKEY_TABLE_BITS) {
1942 dd_dev_warn(dd, "lkey bits %u too large, reduced to %u\n",
1943 hfi1_lkey_table_size, MAX_LKEY_TABLE_BITS);
1944 hfi1_lkey_table_size = MAX_LKEY_TABLE_BITS;
1946 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
1947 dev->lk_table.table = (struct hfi1_mregion __rcu **)
1948 vmalloc(lk_tab_size);
1949 if (dev->lk_table.table == NULL) {
1953 RCU_INIT_POINTER(dev->dma_mr, NULL);
1954 for (i = 0; i < dev->lk_table.max; i++)
1955 RCU_INIT_POINTER(dev->lk_table.table[i], NULL);
1956 INIT_LIST_HEAD(&dev->pending_mmaps);
1957 spin_lock_init(&dev->pending_lock);
1958 seqlock_init(&dev->iowait_lock);
1959 dev->mmap_offset = PAGE_SIZE;
1960 spin_lock_init(&dev->mmap_offset_lock);
1961 INIT_LIST_HEAD(&dev->txwait);
1962 INIT_LIST_HEAD(&dev->memwait);
1964 descq_cnt = sdma_get_descq_cnt();
1966 snprintf(buf, sizeof(buf), "hfi1_%u_vtxreq_cache", dd->unit);
1967 /* SLAB_HWCACHE_ALIGN for AHG */
1968 dev->verbs_txreq_cache = kmem_cache_create(buf,
1969 sizeof(struct verbs_txreq),
1970 0, SLAB_HWCACHE_ALIGN,
1971 verbs_txreq_kmem_cache_ctor);
1972 if (!dev->verbs_txreq_cache) {
1974 goto err_verbs_txreq;
1978 * The system image GUID is supposed to be the same for all
1979 * HFIs in a single system but since there can be other
1980 * device types in the system, we can't be sure this is unique.
1982 if (!ib_hfi1_sys_image_guid)
1983 ib_hfi1_sys_image_guid = cpu_to_be64(ppd->guid);
1984 lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1985 strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1986 ibdev->owner = THIS_MODULE;
1987 ibdev->node_guid = cpu_to_be64(ppd->guid);
1988 ibdev->uverbs_abi_ver = HFI1_UVERBS_ABI_VERSION;
1989 ibdev->uverbs_cmd_mask =
1990 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
1991 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
1992 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
1993 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
1994 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
1995 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
1996 (1ull << IB_USER_VERBS_CMD_MODIFY_AH) |
1997 (1ull << IB_USER_VERBS_CMD_QUERY_AH) |
1998 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
1999 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2000 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2001 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2002 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2003 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2004 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2005 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
2006 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
2007 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2008 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2009 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2010 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2011 (1ull << IB_USER_VERBS_CMD_POST_SEND) |
2012 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2013 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2014 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2015 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2016 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2017 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2018 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2019 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2020 ibdev->node_type = RDMA_NODE_IB_CA;
2021 ibdev->phys_port_cnt = dd->num_pports;
2022 ibdev->num_comp_vectors = 1;
2023 ibdev->dma_device = &dd->pcidev->dev;
2024 ibdev->query_device = query_device;
2025 ibdev->modify_device = modify_device;
2026 ibdev->query_port = query_port;
2027 ibdev->modify_port = modify_port;
2028 ibdev->query_pkey = query_pkey;
2029 ibdev->query_gid = query_gid;
2030 ibdev->alloc_ucontext = alloc_ucontext;
2031 ibdev->dealloc_ucontext = dealloc_ucontext;
2032 ibdev->alloc_pd = alloc_pd;
2033 ibdev->dealloc_pd = dealloc_pd;
2034 ibdev->create_ah = create_ah;
2035 ibdev->destroy_ah = destroy_ah;
2036 ibdev->modify_ah = modify_ah;
2037 ibdev->query_ah = query_ah;
2038 ibdev->create_srq = hfi1_create_srq;
2039 ibdev->modify_srq = hfi1_modify_srq;
2040 ibdev->query_srq = hfi1_query_srq;
2041 ibdev->destroy_srq = hfi1_destroy_srq;
2042 ibdev->create_qp = hfi1_create_qp;
2043 ibdev->modify_qp = hfi1_modify_qp;
2044 ibdev->query_qp = hfi1_query_qp;
2045 ibdev->destroy_qp = hfi1_destroy_qp;
2046 ibdev->post_send = post_send;
2047 ibdev->post_recv = post_receive;
2048 ibdev->post_srq_recv = hfi1_post_srq_receive;
2049 ibdev->create_cq = hfi1_create_cq;
2050 ibdev->destroy_cq = hfi1_destroy_cq;
2051 ibdev->resize_cq = hfi1_resize_cq;
2052 ibdev->poll_cq = hfi1_poll_cq;
2053 ibdev->req_notify_cq = hfi1_req_notify_cq;
2054 ibdev->get_dma_mr = hfi1_get_dma_mr;
2055 ibdev->reg_user_mr = hfi1_reg_user_mr;
2056 ibdev->dereg_mr = hfi1_dereg_mr;
2057 ibdev->alloc_mr = hfi1_alloc_mr;
2058 ibdev->alloc_fmr = hfi1_alloc_fmr;
2059 ibdev->map_phys_fmr = hfi1_map_phys_fmr;
2060 ibdev->unmap_fmr = hfi1_unmap_fmr;
2061 ibdev->dealloc_fmr = hfi1_dealloc_fmr;
2062 ibdev->attach_mcast = hfi1_multicast_attach;
2063 ibdev->detach_mcast = hfi1_multicast_detach;
2064 ibdev->process_mad = hfi1_process_mad;
2065 ibdev->mmap = hfi1_mmap;
2066 ibdev->dma_ops = &hfi1_dma_mapping_ops;
2067 ibdev->get_port_immutable = port_immutable;
2069 strncpy(ibdev->node_desc, init_utsname()->nodename,
2070 sizeof(ibdev->node_desc));
2072 ret = ib_register_device(ibdev, hfi1_create_port_files);
2076 ret = hfi1_create_agents(dev);
2080 ret = hfi1_verbs_register_sysfs(dd);
2087 hfi1_free_agents(dev);
2089 ib_unregister_device(ibdev);
2092 kmem_cache_destroy(dev->verbs_txreq_cache);
2093 vfree(dev->lk_table.table);
2097 dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2102 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
2104 struct hfi1_ibdev *dev = &dd->verbs_dev;
2105 struct ib_device *ibdev = &dev->ibdev;
2107 hfi1_verbs_unregister_sysfs(dd);
2109 hfi1_free_agents(dev);
2111 ib_unregister_device(ibdev);
2113 if (!list_empty(&dev->txwait))
2114 dd_dev_err(dd, "txwait list not empty!\n");
2115 if (!list_empty(&dev->memwait))
2116 dd_dev_err(dd, "memwait list not empty!\n");
2118 dd_dev_err(dd, "DMA MR not NULL!\n");
2121 del_timer_sync(&dev->mem_timer);
2122 kmem_cache_destroy(dev->verbs_txreq_cache);
2123 vfree(dev->lk_table.table);
2126 void hfi1_cnp_rcv(struct hfi1_packet *packet)
2128 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2129 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2130 struct hfi1_ib_header *hdr = packet->hdr;
2131 struct hfi1_qp *qp = packet->qp;
2134 u8 sl, sc5, sc4_bit, svc_type;
2135 bool sc4_set = has_sc4_bit(packet);
2137 switch (packet->qp->ibqp.qp_type) {
2139 rlid = qp->remote_ah_attr.dlid;
2140 rqpn = qp->remote_qpn;
2141 svc_type = IB_CC_SVCTYPE_UC;
2144 rlid = qp->remote_ah_attr.dlid;
2145 rqpn = qp->remote_qpn;
2146 svc_type = IB_CC_SVCTYPE_RC;
2151 svc_type = IB_CC_SVCTYPE_UD;
2158 sc4_bit = sc4_set << 4;
2159 sc5 = (be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf;
2161 sl = ibp->sc_to_sl[sc5];
2162 lqpn = qp->ibqp.qp_num;
2164 process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);