1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
36 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
37 enum radio_path rfpath, u32 offset);
38 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
39 enum radio_path rfpath, u32 offset,
41 static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask);
42 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw);
43 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
44 static bool _rtl92ee_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
46 static bool _rtl92ee_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
48 static void _rtl92ee_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
49 static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
50 u32 cmdtableidx, u32 cmdtablesz,
51 enum swchnlcmd_id cmdid,
54 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
55 u8 channel, u8 *stage,
56 u8 *step, u32 *delay);
57 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
58 enum wireless_mode wirelessmode,
60 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw);
61 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw);
63 u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
65 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 u32 returnvalue, originalvalue, bitshift;
68 RT_TRACE(COMP_RF, DBG_TRACE,
69 ("regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask));
70 originalvalue = rtl_read_dword(rtlpriv, regaddr);
71 bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
72 returnvalue = (originalvalue & bitmask) >> bitshift;
74 RT_TRACE(COMP_RF, DBG_TRACE,
75 ("BBR MASK = 0x%x Addr[0x%x]= 0x%x\n",
76 bitmask, regaddr, originalvalue));
81 void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
82 u32 bitmask, u32 data)
84 struct rtl_priv *rtlpriv = rtl_priv(hw);
85 u32 originalvalue, bitshift;
87 RT_TRACE(COMP_RF, DBG_TRACE,
88 ("regaddr(%#x), bitmask(%#x), data(%#x)\n",
89 regaddr, bitmask, data));
91 if (bitmask != MASKDWORD) {
92 originalvalue = rtl_read_dword(rtlpriv, regaddr);
93 bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
94 data = ((originalvalue & (~bitmask)) | (data << bitshift));
97 rtl_write_dword(rtlpriv, regaddr, data);
99 RT_TRACE(COMP_RF, DBG_TRACE,
100 ("regaddr(%#x), bitmask(%#x), data(%#x)\n",
101 regaddr, bitmask, data));
104 u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
105 enum radio_path rfpath, u32 regaddr, u32 bitmask)
107 struct rtl_priv *rtlpriv = rtl_priv(hw);
108 u32 original_value, readback_value, bitshift;
111 RT_TRACE(COMP_RF, DBG_TRACE,
112 ("regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
113 regaddr, rfpath, bitmask));
115 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
118 original_value = _rtl92ee_phy_rf_serial_read(hw , rfpath, regaddr);
119 bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
120 readback_value = (original_value & bitmask) >> bitshift;
122 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
124 RT_TRACE(COMP_RF, DBG_TRACE,
125 ("regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
126 regaddr, rfpath, bitmask, original_value));
128 return readback_value;
131 void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
132 enum radio_path rfpath,
133 u32 addr, u32 bitmask, u32 data)
135 struct rtl_priv *rtlpriv = rtl_priv(hw);
136 u32 original_value, bitshift;
139 RT_TRACE(COMP_RF, DBG_TRACE,
140 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
141 addr, bitmask, data, rfpath));
143 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
145 if (bitmask != RFREG_OFFSET_MASK) {
146 original_value = _rtl92ee_phy_rf_serial_read(hw, rfpath, addr);
147 bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
148 data = (original_value & (~bitmask)) | (data << bitshift);
151 _rtl92ee_phy_rf_serial_write(hw, rfpath, addr, data);
153 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
155 RT_TRACE(COMP_RF, DBG_TRACE,
156 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
157 addr, bitmask, data, rfpath));
160 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
161 enum radio_path rfpath, u32 offset)
163 struct rtl_priv *rtlpriv = rtl_priv(hw);
164 struct rtl_phy *rtlphy = &(rtlpriv->phy);
165 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
167 u32 tmplong, tmplong2;
173 if (RT_CANNOT_IO(hw)) {
174 RT_TRACE(COMP_ERR, DBG_EMERG, ("return all one\n"));
177 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
178 if (rfpath == RF90_PATH_A)
181 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
182 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
183 (newoffset << 23) | BLSSIREADEDGE;
184 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
185 tmplong & (~BLSSIREADEDGE));
187 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
190 if (rfpath == RF90_PATH_A)
191 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
193 else if (rfpath == RF90_PATH_B)
194 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
197 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
200 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
202 RT_TRACE(COMP_RF, DBG_TRACE,
203 ("RFR-%d Addr[0x%x]= 0x%x\n",
204 rfpath, pphyreg->rflssi_readback, retvalue));
208 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
209 enum radio_path rfpath, u32 offset,
214 struct rtl_priv *rtlpriv = rtl_priv(hw);
215 struct rtl_phy *rtlphy = &(rtlpriv->phy);
216 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
218 if (RT_CANNOT_IO(hw)) {
219 RT_TRACE(COMP_ERR, DBG_EMERG, ("stop\n"));
224 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
225 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
226 RT_TRACE(COMP_RF, DBG_TRACE,
227 ("RFW-%d Addr[0x%x]= 0x%x\n", rfpath,
228 pphyreg->rf3wire_offset, data_and_addr));
231 static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask)
235 for (i = 0; i <= 31; i++) {
236 if (((bitmask >> i) & 0x1) == 1)
242 bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw)
244 bool rtstatus = _rtl92ee_phy_config_mac_with_headerfile(hw);
249 bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw)
251 bool rtstatus = true;
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
257 _rtl92ee_phy_init_bb_rf_register_definition(hw);
258 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
259 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
260 regval | BIT(13) | BIT(0) | BIT(1));
262 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
263 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
264 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
265 FEN_BB_GLB_RSTn | FEN_BBRSTB);
267 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
269 tmp = rtl_read_dword(rtlpriv, 0x4c);
270 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
272 rtstatus = _rtl92ee_phy_bb8192ee_config_parafile(hw);
274 crystal_cap = rtlpriv->efuse.eeprom_crystalcap & 0x3F;
275 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
276 (crystal_cap | (crystal_cap << 6)));
280 bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw)
282 return rtl92ee_phy_rf6052_config(hw);
285 static bool _check_condition(struct ieee80211_hw *hw,
288 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
289 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
290 u32 _board = rtlefuse->board_type; /*need efuse define*/
291 u32 _interface = rtlhal->interface;
292 u32 _platform = 0x08;/*SupportPlatform */
293 u32 cond = condition;
295 if (condition == 0xCDCDCDCD)
297 cond = condition & 0xFF;
298 if ((_board != cond) && (cond != 0xFF))
300 cond = condition & 0xFF00;
302 if ((_interface & cond) == 0 && cond != 0x07)
304 cond = condition & 0xFF0000;
306 if ((_platform & cond) == 0 && cond != 0x0F)
311 static void _rtl92ee_config_rf_reg(struct ieee80211_hw *hw, u32 addr, u32 data,
312 enum radio_path rfpath, u32 regaddr)
314 if (addr == 0xfe || addr == 0xffe) {
317 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
323 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);
326 while ((getvalue >> 8) != (data >> 8)) {
328 rtl_set_rfreg(hw, rfpath, regaddr,
329 RFREG_OFFSET_MASK, data);
331 getvalue = rtl_get_rfreg(hw, rfpath, addr,
341 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);
345 while (getvalue != data) {
347 rtl_set_rfreg(hw, rfpath, regaddr,
348 RFREG_OFFSET_MASK, data);
350 rtl_set_rfreg(hw, rfpath, 0x18,
351 RFREG_OFFSET_MASK, 0x0fc07);
353 getvalue = rtl_get_rfreg(hw, rfpath, addr,
362 static void _rtl92ee_config_rf_radio_a(struct ieee80211_hw *hw,
365 u32 content = 0x1000; /*RF Content: radio_a_txt*/
366 u32 maskforphyset = (u32)(content & 0xE000);
368 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_A,
369 addr | maskforphyset);
372 static void _rtl92ee_config_rf_radio_b(struct ieee80211_hw *hw,
375 u32 content = 0x1001; /*RF Content: radio_b_txt*/
376 u32 maskforphyset = (u32)(content & 0xE000);
378 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_B,
379 addr | maskforphyset);
382 static void _rtl92ee_config_bb_reg(struct ieee80211_hw *hw,
387 else if (addr == 0xfd)
389 else if (addr == 0xfc)
391 else if (addr == 0xfb)
393 else if (addr == 0xfa)
395 else if (addr == 0xf9)
398 rtl_set_bbreg(hw, addr, MASKDWORD , data);
403 static void _rtl92ee_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
405 struct rtl_priv *rtlpriv = rtl_priv(hw);
406 struct rtl_phy *rtlphy = &(rtlpriv->phy);
408 u8 band = BAND_ON_2_4G, rf = 0, txnum = 0, sec = 0;
410 for (; band <= BAND_ON_5G; ++band)
411 for (; rf < TX_PWR_BY_RATE_NUM_RF; ++rf)
412 for (; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
413 for (; sec < TX_PWR_BY_RATE_NUM_SECTION; ++sec)
414 rtlphy->tx_power_by_rate_offset
415 [band][rf][txnum][sec] = 0;
418 static void _rtl92ee_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
420 u8 rate_section, u8 txnum, u8 value)
422 struct rtl_priv *rtlpriv = rtl_priv(hw);
423 struct rtl_phy *rtlphy = &(rtlpriv->phy);
425 if (path > RF90_PATH_D) {
426 RT_TRACE(COMP_INIT, DBG_LOUD, ("Invalid Rf Path %d\n", path));
429 if (band == BAND_ON_2_4G) {
430 switch (rate_section) {
432 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
435 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
438 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
441 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
444 RT_TRACE(COMP_INIT, DBG_LOUD,
445 ("Invalid RateSection %d in 2.4G, Rf %d,%dTx\n",
446 rate_section, path, txnum));
450 RT_TRACE(COMP_INIT, DBG_LOUD, ("Invalid Band %d\n", band));
454 static u8 _rtl92ee_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw, u8 band,
455 u8 path, u8 txnum, u8 rate_section)
457 struct rtl_priv *rtlpriv = rtl_priv(hw);
458 struct rtl_phy *rtlphy = &(rtlpriv->phy);
460 if (path > RF90_PATH_D) {
461 RT_TRACE(COMP_INIT, DBG_LOUD, ("Invalid Rf Path %d\n", path));
464 if (band == BAND_ON_2_4G) {
465 switch (rate_section) {
467 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
470 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
473 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
476 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
479 RT_TRACE(COMP_INIT, DBG_LOUD,
480 ("Invalid RateSection %d in 2.4G, Rf %d,%dTx\n",
481 rate_section, path, txnum));
485 RT_TRACE(COMP_INIT, DBG_LOUD, ("Invalid Band %d()\n", band));
490 static void _rtl92ee_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
492 struct rtl_priv *rtlpriv = rtl_priv(hw);
493 struct rtl_phy *rtlphy = &(rtlpriv->phy);
495 u8 base = 0, path = 0;
497 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
498 if (path == RF90_PATH_A) {
499 raw = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][3] >> 24) & 0xFF;
500 base = (raw >> 4) * 10 + (raw & 0xF);
501 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
504 } else if (path == RF90_PATH_B) {
505 raw = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][3] >> 0) & 0xFF;
506 base = (raw >> 4) * 10 + (raw & 0xF);
507 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
511 raw = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF;
512 base = (raw >> 4) * 10 + (raw & 0xF);
513 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
516 raw = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF;
517 base = (raw >> 4) * 10 + (raw & 0xF);
518 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
519 HT_MCS0_MCS7, RF_1TX,
522 raw = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF;
523 base = (raw >> 4) * 10 + (raw & 0xF);
524 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
525 HT_MCS8_MCS15, RF_2TX,
530 static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
537 for (i = 3; i >= 0; --i) {
538 if (i >= start && i <= end) {
539 /* Get the exact value */
540 tmp = (u8) (*data >> (i * 8)) & 0xF;
541 tmp += ((u8) ((*data >> (i * 8 + 4)) & 0xF)) * 10;
543 /* Change the value to a relative value */
544 tmp = (tmp > base) ? tmp - base : base - tmp;
546 tmp = (u8) (*data >> (i * 8)) & 0xFF;
554 static void _rtl92ee_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw)
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 struct rtl_phy *rtlphy = &(rtlpriv->phy);
558 u8 base = 0, rf = 0, band = BAND_ON_2_4G;
560 for (rf = RF90_PATH_A; rf <= RF90_PATH_B; ++rf) {
561 if (rf == RF90_PATH_A) {
562 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band,
565 _phy_convert_txpower_dbm_to_relative_value(
566 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][2]),
568 _phy_convert_txpower_dbm_to_relative_value(
569 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][3]),
571 } else if (rf == RF90_PATH_B) {
572 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band,
575 _phy_convert_txpower_dbm_to_relative_value(
576 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][3]),
578 _phy_convert_txpower_dbm_to_relative_value(
579 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][2]),
582 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
584 _phy_convert_txpower_dbm_to_relative_value(
585 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][0]),
587 _phy_convert_txpower_dbm_to_relative_value(
588 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][1]),
591 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
594 _phy_convert_txpower_dbm_to_relative_value(
595 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][4]),
597 _phy_convert_txpower_dbm_to_relative_value(
598 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][5]),
600 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
603 _phy_convert_txpower_dbm_to_relative_value(
604 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][6]),
606 _phy_convert_txpower_dbm_to_relative_value(
607 &(rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][7]),
610 RT_TRACE(COMP_POWER, DBG_TRACE,
611 ("<== _rtl92ee_phy_convert_txpower_dbm_to_relative_value()\n"));
614 static void _rtl92ee_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
616 _rtl92ee_phy_store_txpower_by_rate_base(hw);
617 _rtl92ee_phy_convert_txpower_dbm_to_relative_value(hw);
620 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw)
622 struct rtl_priv *rtlpriv = rtl_priv(hw);
623 struct rtl_phy *rtlphy = &(rtlpriv->phy);
624 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
627 rtstatus = _rtl92ee_phy_config_bb_with_headerfile(hw,
628 BASEBAND_CONFIG_PHY_REG);
630 RT_TRACE(COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
634 _rtl92ee_phy_init_tx_power_by_rate(hw);
635 if (rtlefuse->autoload_failflag == false) {
636 rtlphy->pwrgroup_cnt = 0;
637 rtstatus = _rtl92ee_phy_config_bb_with_pgheaderfile(hw,
638 BASEBAND_CONFIG_PHY_REG);
640 _rtl92ee_phy_txpower_by_rate_configuration(hw);
642 RT_TRACE(COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
645 rtstatus = _rtl92ee_phy_config_bb_with_headerfile(hw,
646 BASEBAND_CONFIG_AGC_TAB);
648 RT_TRACE(COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
651 rtlphy->bcck_high_power = (bool) (rtl_get_bbreg(hw,
652 RFPGA0_XA_HSSIPARAMETER2,
658 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
660 struct rtl_priv *rtlpriv = rtl_priv(hw);
665 RT_TRACE(COMP_INIT, DBG_TRACE, ("Read Rtl8192EMACPHY_Array\n"));
666 arraylength = RTL8192EE_MAC_ARRAY_LEN;
667 ptrarray = RTL8192EE_MAC_ARRAY;
668 RT_TRACE(COMP_INIT, DBG_LOUD,
669 ("Img:RTL8192EE_MAC_ARRAY LEN %d\n" , arraylength));
670 for (i = 0; i < arraylength; i = i + 2)
671 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
675 static bool _rtl92ee_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
678 #define READ_NEXT_PAIR(v1, v2, i) \
688 struct rtl_priv *rtlpriv = rtl_priv(hw);
691 if (configtype == BASEBAND_CONFIG_PHY_REG) {
692 len = RTL8192EE_PHY_REG_ARRAY_LEN;
693 array = RTL8192EE_PHY_REG_ARRAY;
695 for (i = 0; i < len; i = i + 2) {
698 if (v1 < 0xcdcdcdcd) {
699 _rtl92ee_config_bb_reg(hw, v1, v2);
700 } else {/*This line is the start line of branch.*/
701 /* to protect READ_NEXT_PAIR not overrun */
705 if (!_check_condition(hw , array[i])) {
706 /*Discard the following pairs*/
707 READ_NEXT_PAIR(v1, v2, i);
708 while (v2 != 0xDEAD &&
710 v2 != 0xCDCD && i < len - 2)
711 READ_NEXT_PAIR(v1, v2, i);
712 i -= 2; /* prevent from for-loop += 2*/
713 } else{/* Configure matched pairs and
714 * skip to end of if-else. */
715 READ_NEXT_PAIR(v1, v2, i);
716 while (v2 != 0xDEAD &&
718 v2 != 0xCDCD && i < len - 2) {
719 _rtl92ee_config_bb_reg(hw, v1,
721 READ_NEXT_PAIR(v1, v2, i);
724 while (v2 != 0xDEAD && i < len - 2)
725 READ_NEXT_PAIR(v1, v2, i);
729 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
730 len = RTL8192EE_AGC_TAB_ARRAY_LEN;
731 array = RTL8192EE_AGC_TAB_ARRAY;
733 for (i = 0; i < len; i = i + 2) {
736 if (v1 < 0xCDCDCDCD) {
737 rtl_set_bbreg(hw, array[i], MASKDWORD,
741 } else{/*This line is the start line of branch.*/
742 /* to protect READ_NEXT_PAIR not overrun */
746 if (!_check_condition(hw , array[i])) {
747 /*Discard the following pairs*/
748 READ_NEXT_PAIR(v1, v2, i);
749 while (v2 != 0xDEAD &&
753 READ_NEXT_PAIR(v1, v2, i);
754 i -= 2; /* prevent from for-loop += 2*/
755 } else {/* Configure matched pairs and
756 * skip to end of if-else.*/
757 READ_NEXT_PAIR(v1, v2, i);
758 while (v2 != 0xDEAD &&
767 READ_NEXT_PAIR(v1 , v2 , i);
770 while (v2 != 0xDEAD &&
772 READ_NEXT_PAIR(v1 , v2 , i);
775 RT_TRACE(COMP_INIT, DBG_TRACE,
776 ("The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
784 static u8 _rtl92ee_get_rate_section_index(u32 regaddr)
789 case RTXAGC_A_RATE18_06:
792 case RTXAGC_A_RATE54_24:
795 case RTXAGC_A_CCK1_MCS32:
798 case RTXAGC_B_CCK11_A_CCK2_11:
801 case RTXAGC_A_MCS03_MCS00:
804 case RTXAGC_A_MCS07_MCS04:
807 case RTXAGC_A_MCS11_MCS08:
810 case RTXAGC_A_MCS15_MCS12:
813 case RTXAGC_B_RATE18_06:
816 case RTXAGC_B_RATE54_24:
819 case RTXAGC_B_CCK1_55_MCS32:
822 case RTXAGC_B_MCS03_MCS00:
825 case RTXAGC_B_MCS07_MCS04:
828 case RTXAGC_B_MCS11_MCS08:
831 case RTXAGC_B_MCS15_MCS12:
836 if (regaddr >= 0xC20 && regaddr <= 0xC4C)
837 index = (u8) ((regaddr - 0xC20) / 4);
838 else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
839 index = (u8) ((regaddr - 0xE20) / 4);
845 static void _rtl92ee_store_tx_power_by_rate(struct ieee80211_hw *hw,
847 enum radio_path rfpath,
848 u32 txnum, u32 regaddr,
849 u32 bitmask, u32 data)
851 struct rtl_priv *rtlpriv = rtl_priv(hw);
852 struct rtl_phy *rtlphy = &(rtlpriv->phy);
853 u8 section = _rtl92ee_get_rate_section_index(regaddr);
855 if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
856 RT_TRACE(FPHY, PHY_TXPWR, ("Invalid Band %d\n", band));
860 if (rfpath > MAX_RF_PATH - 1) {
861 RT_TRACE(FPHY, PHY_TXPWR, ("Invalid RfPath %d\n", rfpath));
864 if (txnum > MAX_RF_PATH - 1) {
865 RT_TRACE(FPHY, PHY_TXPWR, ("Invalid TxNum %d\n", txnum));
869 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][section] = data;
872 static bool _rtl92ee_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
875 struct rtl_priv *rtlpriv = rtl_priv(hw);
877 u32 *phy_regarray_table_pg;
878 u16 phy_regarray_pg_len;
879 u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0;
881 phy_regarray_pg_len = RTL8192EE_PHY_REG_ARRAY_PG_LEN;
882 phy_regarray_table_pg = RTL8192EE_PHY_REG_ARRAY_PG;
884 if (configtype == BASEBAND_CONFIG_PHY_REG) {
885 for (i = 0; i < phy_regarray_pg_len; i = i + 6) {
886 v1 = phy_regarray_table_pg[i];
887 v2 = phy_regarray_table_pg[i+1];
888 v3 = phy_regarray_table_pg[i+2];
889 v4 = phy_regarray_table_pg[i+3];
890 v5 = phy_regarray_table_pg[i+4];
891 v6 = phy_regarray_table_pg[i+5];
893 if (v1 < 0xcdcdcdcd) {
894 _rtl92ee_store_tx_power_by_rate(hw, v1, v2, v3,
900 RT_TRACE(COMP_SEND, DBG_TRACE,
901 ("configtype != BaseBand_Config_PHY_REG\n"));
906 bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
907 enum radio_path rfpath)
909 #define READ_NEXT_RF_PAIR(v1, v2, i) \
919 struct rtl_priv *rtlpriv = rtl_priv(hw);
924 len = RTL8192EE_RADIOA_ARRAY_LEN;
925 array = RTL8192EE_RADIOA_ARRAY;
926 RT_TRACE(COMP_INIT, DBG_LOUD,
927 ("Radio_A:RTL8192EE_RADIOA_ARRAY %d\n" , len));
928 RT_TRACE(COMP_INIT, DBG_LOUD, ("Radio No %x\n", rfpath));
929 for (i = 0; i < len; i = i + 2) {
932 if (v1 < 0xcdcdcdcd) {
933 _rtl92ee_config_rf_radio_a(hw, v1, v2);
935 } else {/*This line is the start line of branch.*/
936 /* to protect READ_NEXT_PAIR not overrun */
940 if (!_check_condition(hw , array[i])) {
941 /*Discard the following pairs*/
942 READ_NEXT_RF_PAIR(v1, v2, i);
943 while (v2 != 0xDEAD &&
945 v2 != 0xCDCD && i < len - 2)
946 READ_NEXT_RF_PAIR(v1, v2, i);
947 i -= 2; /* prevent from for-loop += 2*/
948 } else {/* Configure matched pairs and
949 * skip to end of if-else.*/
950 READ_NEXT_RF_PAIR(v1, v2, i);
951 while (v2 != 0xDEAD &&
953 v2 != 0xCDCD && i < len - 2) {
954 _rtl92ee_config_rf_radio_a(hw,
957 READ_NEXT_RF_PAIR(v1, v2, i);
960 while (v2 != 0xDEAD && i < len - 2)
961 READ_NEXT_RF_PAIR(v1, v2, i);
968 len = RTL8192EE_RADIOB_ARRAY_LEN;
969 array = RTL8192EE_RADIOB_ARRAY;
970 RT_TRACE(COMP_INIT, DBG_LOUD,
971 ("Radio_A:RTL8192EE_RADIOB_ARRAY %d\n" , len));
972 RT_TRACE(COMP_INIT, DBG_LOUD, ("Radio No %x\n", rfpath));
973 for (i = 0; i < len; i = i + 2) {
976 if (v1 < 0xcdcdcdcd) {
977 _rtl92ee_config_rf_radio_b(hw, v1, v2);
979 } else {/*This line is the start line of branch.*/
980 /* to protect READ_NEXT_PAIR not overrun */
984 if (!_check_condition(hw , array[i])) {
985 /*Discard the following pairs*/
986 READ_NEXT_RF_PAIR(v1, v2, i);
987 while (v2 != 0xDEAD &&
989 v2 != 0xCDCD && i < len - 2)
990 READ_NEXT_RF_PAIR(v1, v2, i);
991 i -= 2; /* prevent from for-loop += 2*/
992 } else {/* Configure matched pairs and
993 * skip to end of if-else.*/
994 READ_NEXT_RF_PAIR(v1, v2, i);
995 while (v2 != 0xDEAD &&
997 v2 != 0xCDCD && i < len - 2) {
998 _rtl92ee_config_rf_radio_b(hw,
1001 READ_NEXT_RF_PAIR(v1, v2, i);
1004 while (v2 != 0xDEAD && i < len - 2)
1005 READ_NEXT_RF_PAIR(v1, v2, i);
1011 RT_TRACE(COMP_ERR, DBG_EMERG,
1012 ("switch case not process\n"));
1015 RT_TRACE(COMP_ERR, DBG_EMERG,
1016 ("switch case not process\n"));
1022 void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1024 struct rtl_priv *rtlpriv = rtl_priv(hw);
1025 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1027 rtlphy->default_initialgain[0] =
1028 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
1029 rtlphy->default_initialgain[1] =
1030 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
1031 rtlphy->default_initialgain[2] =
1032 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
1033 rtlphy->default_initialgain[3] =
1034 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
1036 RT_TRACE(COMP_INIT, DBG_TRACE,
1037 ("Default initial gain (c50 = 0x%x, c58 = 0x%x, c60 = 0x%x, c68 = 0x%x\n",
1038 rtlphy->default_initialgain[0],
1039 rtlphy->default_initialgain[1],
1040 rtlphy->default_initialgain[2],
1041 rtlphy->default_initialgain[3]));
1043 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
1044 ROFDM0_RXDETECTOR3, MASKBYTE0);
1045 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
1046 ROFDM0_RXDETECTOR2, MASKDWORD);
1048 RT_TRACE(COMP_INIT, DBG_TRACE,
1049 ("Default framesync (0x%x) = 0x%x\n",
1050 ROFDM0_RXDETECTOR3, rtlphy->framesync));
1053 static void _rtl92ee_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
1055 struct rtl_priv *rtlpriv = rtl_priv(hw);
1056 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1058 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1059 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1061 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
1062 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
1064 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
1065 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
1067 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
1068 RFPGA0_XA_LSSIPARAMETER;
1069 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
1070 RFPGA0_XB_LSSIPARAMETER;
1072 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
1073 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
1075 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
1076 RFPGA0_XA_LSSIREADBACK;
1077 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
1078 RFPGA0_XB_LSSIREADBACK;
1080 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
1081 TRANSCEIVEA_HSPI_READBACK;
1082 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
1083 TRANSCEIVEB_HSPI_READBACK;
1086 void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
1088 struct rtl_priv *rtlpriv = rtl_priv(hw);
1089 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1093 txpwr_level = rtlphy->cur_cck_txpwridx;
1094 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
1096 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1097 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) >
1099 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
1101 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1102 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
1103 txpwr_level) > txpwr_dbm)
1104 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw,
1105 WIRELESS_MODE_N_24G,
1107 *powerlevel = txpwr_dbm;
1110 static u8 _rtl92ee_phy_get_ratesection_intxpower_byrate(enum radio_path path,
1113 u8 rate_section = 0;
1116 case DESC92C_RATE1M:
1120 case DESC92C_RATE2M:
1121 case DESC92C_RATE5_5M:
1122 if (path == RF90_PATH_A)
1124 else if (path == RF90_PATH_B)
1128 case DESC92C_RATE11M:
1132 case DESC92C_RATE6M:
1133 case DESC92C_RATE9M:
1134 case DESC92C_RATE12M:
1135 case DESC92C_RATE18M:
1139 case DESC92C_RATE24M:
1140 case DESC92C_RATE36M:
1141 case DESC92C_RATE48M:
1142 case DESC92C_RATE54M:
1146 case DESC92C_RATEMCS0:
1147 case DESC92C_RATEMCS1:
1148 case DESC92C_RATEMCS2:
1149 case DESC92C_RATEMCS3:
1153 case DESC92C_RATEMCS4:
1154 case DESC92C_RATEMCS5:
1155 case DESC92C_RATEMCS6:
1156 case DESC92C_RATEMCS7:
1160 case DESC92C_RATEMCS8:
1161 case DESC92C_RATEMCS9:
1162 case DESC92C_RATEMCS10:
1163 case DESC92C_RATEMCS11:
1167 case DESC92C_RATEMCS12:
1168 case DESC92C_RATEMCS13:
1169 case DESC92C_RATEMCS14:
1170 case DESC92C_RATEMCS15:
1175 RT_ASSERT(true, ("Rate_Section is Illegal\n"));
1179 return rate_section;
1182 static u8 _rtl92ee_get_txpower_by_rate(struct ieee80211_hw *hw,
1183 enum band_type band,
1184 enum radio_path rf, u8 rate)
1186 struct rtl_priv *rtlpriv = rtl_priv(hw);
1187 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1188 u8 shift = 0, sec, tx_num;
1191 sec = _rtl92ee_phy_get_ratesection_intxpower_byrate(rf, rate);
1192 tx_num = RF_TX_NUM_NONIMPLEMENT;
1194 if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
1195 if ((rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS15))
1202 case DESC92C_RATE1M:
1205 case DESC92C_RATE2M:
1208 case DESC92C_RATE5_5M:
1211 case DESC92C_RATE11M:
1215 case DESC92C_RATE6M:
1218 case DESC92C_RATE9M:
1221 case DESC92C_RATE12M:
1224 case DESC92C_RATE18M:
1228 case DESC92C_RATE24M:
1231 case DESC92C_RATE36M:
1234 case DESC92C_RATE48M:
1237 case DESC92C_RATE54M:
1241 case DESC92C_RATEMCS0:
1244 case DESC92C_RATEMCS1:
1247 case DESC92C_RATEMCS2:
1250 case DESC92C_RATEMCS3:
1254 case DESC92C_RATEMCS4:
1257 case DESC92C_RATEMCS5:
1260 case DESC92C_RATEMCS6:
1263 case DESC92C_RATEMCS7:
1267 case DESC92C_RATEMCS8:
1270 case DESC92C_RATEMCS9:
1273 case DESC92C_RATEMCS10:
1276 case DESC92C_RATEMCS11:
1280 case DESC92C_RATEMCS12:
1283 case DESC92C_RATEMCS13:
1286 case DESC92C_RATEMCS14:
1289 case DESC92C_RATEMCS15:
1294 RT_ASSERT(true, ("Rate_Section is Illegal\n"));
1298 diff = (u8) (rtlphy->tx_power_by_rate_offset[band][rf][tx_num][sec] >>
1304 static u8 _rtl92ee_get_txpower_index(struct ieee80211_hw *hw,
1305 enum radio_path rfpath, u8 rate,
1308 struct rtl_priv *rtlpriv = rtl_priv(hw);
1309 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
1310 u8 index = (channel - 1);
1314 if (channel < 1 || channel > 14) {
1316 RT_TRACE(COMP_POWER_TRACKING, DBG_DMESG,
1317 ("Illegal channel!!\n"));
1320 if (IS_CCK_RATE(rate))
1321 tx_power = rtlefuse->txpwrlevel_cck[rfpath][index];
1322 else if (DESC92C_RATE6M <= rate)
1323 tx_power = rtlefuse->txpwrlevel_ht40_1s[rfpath][index];
1326 if (DESC92C_RATE6M <= rate && rate <= DESC92C_RATE54M &&
1328 tx_power += rtlefuse->txpwr_legacyhtdiff[rfpath][TX_1S];
1330 /* BW20-1S, BW20-2S */
1331 if (bw == HT_CHANNEL_WIDTH_20) {
1332 if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1333 tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_1S];
1334 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1335 tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_2S];
1336 } else if (bw == HT_CHANNEL_WIDTH_20_40) {/* BW40-1S, BW40-2S */
1337 if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1338 tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_1S];
1339 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1340 tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_2S];
1343 if (rtlefuse->eeprom_regulatory != 2)
1344 diff = _rtl92ee_get_txpower_by_rate(hw, BAND_ON_2_4G,
1349 if (tx_power > MAX_POWER_INDEX)
1350 tx_power = MAX_POWER_INDEX;
1355 static void _rtl92ee_set_txpower_index(struct ieee80211_hw *hw, u8 pwr_idx,
1356 enum radio_path rfpath, u8 rate)
1358 struct rtl_priv *rtlpriv = rtl_priv(hw);
1360 if (rfpath == RF90_PATH_A) {
1362 case DESC92C_RATE1M:
1363 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32,
1364 MASKBYTE1, pwr_idx);
1366 case DESC92C_RATE2M:
1367 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11,
1368 MASKBYTE1, pwr_idx);
1370 case DESC92C_RATE5_5M:
1371 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11,
1372 MASKBYTE2, pwr_idx);
1374 case DESC92C_RATE11M:
1375 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11,
1376 MASKBYTE3, pwr_idx);
1378 case DESC92C_RATE6M:
1379 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06,
1380 MASKBYTE0, pwr_idx);
1382 case DESC92C_RATE9M:
1383 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06,
1384 MASKBYTE1, pwr_idx);
1386 case DESC92C_RATE12M:
1387 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06,
1388 MASKBYTE2, pwr_idx);
1390 case DESC92C_RATE18M:
1391 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06,
1392 MASKBYTE3, pwr_idx);
1394 case DESC92C_RATE24M:
1395 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24,
1396 MASKBYTE0, pwr_idx);
1398 case DESC92C_RATE36M:
1399 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24,
1400 MASKBYTE1, pwr_idx);
1402 case DESC92C_RATE48M:
1403 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24,
1404 MASKBYTE2, pwr_idx);
1406 case DESC92C_RATE54M:
1407 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24,
1408 MASKBYTE3, pwr_idx);
1410 case DESC92C_RATEMCS0:
1411 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
1412 MASKBYTE0, pwr_idx);
1414 case DESC92C_RATEMCS1:
1415 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
1416 MASKBYTE1, pwr_idx);
1418 case DESC92C_RATEMCS2:
1419 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
1420 MASKBYTE2, pwr_idx);
1422 case DESC92C_RATEMCS3:
1423 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
1424 MASKBYTE3, pwr_idx);
1426 case DESC92C_RATEMCS4:
1427 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
1428 MASKBYTE0, pwr_idx);
1430 case DESC92C_RATEMCS5:
1431 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
1432 MASKBYTE1, pwr_idx);
1434 case DESC92C_RATEMCS6:
1435 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
1436 MASKBYTE2, pwr_idx);
1438 case DESC92C_RATEMCS7:
1439 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
1440 MASKBYTE3, pwr_idx);
1442 case DESC92C_RATEMCS8:
1443 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
1444 MASKBYTE0, pwr_idx);
1446 case DESC92C_RATEMCS9:
1447 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
1448 MASKBYTE1, pwr_idx);
1450 case DESC92C_RATEMCS10:
1451 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
1452 MASKBYTE2, pwr_idx);
1454 case DESC92C_RATEMCS11:
1455 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
1456 MASKBYTE3, pwr_idx);
1458 case DESC92C_RATEMCS12:
1459 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
1460 MASKBYTE0, pwr_idx);
1462 case DESC92C_RATEMCS13:
1463 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
1464 MASKBYTE1, pwr_idx);
1466 case DESC92C_RATEMCS14:
1467 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
1468 MASKBYTE2, pwr_idx);
1470 case DESC92C_RATEMCS15:
1471 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
1472 MASKBYTE3, pwr_idx);
1475 RT_TRACE(COMP_POWER, DBG_LOUD, ("Invalid Rate!!\n"));
1478 } else if (rfpath == RF90_PATH_B) {
1480 case DESC92C_RATE1M:
1481 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32,
1482 MASKBYTE1, pwr_idx);
1484 case DESC92C_RATE2M:
1485 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32,
1486 MASKBYTE2, pwr_idx);
1488 case DESC92C_RATE5_5M:
1489 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32,
1490 MASKBYTE3, pwr_idx);
1492 case DESC92C_RATE11M:
1493 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11,
1494 MASKBYTE0, pwr_idx);
1496 case DESC92C_RATE6M:
1497 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06,
1498 MASKBYTE0, pwr_idx);
1500 case DESC92C_RATE9M:
1501 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06,
1502 MASKBYTE1, pwr_idx);
1504 case DESC92C_RATE12M:
1505 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06,
1506 MASKBYTE2, pwr_idx);
1508 case DESC92C_RATE18M:
1509 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06,
1510 MASKBYTE3, pwr_idx);
1512 case DESC92C_RATE24M:
1513 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24,
1514 MASKBYTE0, pwr_idx);
1516 case DESC92C_RATE36M:
1517 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24,
1518 MASKBYTE1, pwr_idx);
1520 case DESC92C_RATE48M:
1521 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24,
1522 MASKBYTE2, pwr_idx);
1524 case DESC92C_RATE54M:
1525 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24,
1526 MASKBYTE3, pwr_idx);
1528 case DESC92C_RATEMCS0:
1529 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
1530 MASKBYTE0, pwr_idx);
1532 case DESC92C_RATEMCS1:
1533 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
1534 MASKBYTE1, pwr_idx);
1536 case DESC92C_RATEMCS2:
1537 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
1538 MASKBYTE2, pwr_idx);
1540 case DESC92C_RATEMCS3:
1541 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
1542 MASKBYTE3, pwr_idx);
1544 case DESC92C_RATEMCS4:
1545 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
1546 MASKBYTE0, pwr_idx);
1548 case DESC92C_RATEMCS5:
1549 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
1550 MASKBYTE1, pwr_idx);
1552 case DESC92C_RATEMCS6:
1553 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
1554 MASKBYTE2, pwr_idx);
1556 case DESC92C_RATEMCS7:
1557 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
1558 MASKBYTE3, pwr_idx);
1560 case DESC92C_RATEMCS8:
1561 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
1562 MASKBYTE0, pwr_idx);
1564 case DESC92C_RATEMCS9:
1565 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
1566 MASKBYTE1, pwr_idx);
1568 case DESC92C_RATEMCS10:
1569 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
1570 MASKBYTE2, pwr_idx);
1572 case DESC92C_RATEMCS11:
1573 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
1574 MASKBYTE3, pwr_idx);
1576 case DESC92C_RATEMCS12:
1577 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
1578 MASKBYTE0, pwr_idx);
1580 case DESC92C_RATEMCS13:
1581 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
1582 MASKBYTE1, pwr_idx);
1584 case DESC92C_RATEMCS14:
1585 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
1586 MASKBYTE2, pwr_idx);
1588 case DESC92C_RATEMCS15:
1589 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
1590 MASKBYTE3, pwr_idx);
1593 RT_TRACE(COMP_POWER, DBG_LOUD, ("Invalid Rate!!\n"));
1597 RT_TRACE(COMP_POWER, DBG_LOUD, ("Invalid RFPath!!\n"));
1601 static void rtl92ee_phy_set_txpower_index_by_rate_array(struct ieee80211_hw *hw,
1602 enum radio_path rfpath, u8 bw,
1603 u8 channel, u8 *rates, u8 size)
1607 for (i = 0; i < size; i++) {
1608 power_index = _rtl92ee_get_txpower_index(hw, rfpath, rates[i],
1610 _rtl92ee_set_txpower_index(hw, power_index, rfpath, rates[i]);
1614 static void rtl92ee_phy_set_txpower_index_by_rate_section(struct ieee80211_hw *hw,
1615 enum radio_path rfpath,
1617 enum rate_section section)
1619 struct rtl_priv *rtlpriv = rtl_priv(hw);
1620 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1621 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1623 if (section == CCK) {
1624 u8 cck_rates[] = {DESC92C_RATE1M, DESC92C_RATE2M,
1625 DESC92C_RATE5_5M, DESC92C_RATE11M};
1626 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1627 rtl92ee_phy_set_txpower_index_by_rate_array(hw, rfpath,
1628 rtlphy->current_chan_bw,
1629 channel, cck_rates, 4);
1630 } else if (section == OFDM) {
1631 u8 ofdm_rates[] = {DESC92C_RATE6M, DESC92C_RATE9M,
1632 DESC92C_RATE12M, DESC92C_RATE18M,
1633 DESC92C_RATE24M, DESC92C_RATE36M,
1634 DESC92C_RATE48M, DESC92C_RATE54M};
1635 rtl92ee_phy_set_txpower_index_by_rate_array(hw, rfpath,
1636 rtlphy->current_chan_bw,
1637 channel, ofdm_rates, 8);
1638 } else if (section == HT_MCS0_MCS7) {
1639 u8 ht_rates1t[] = {DESC92C_RATEMCS0, DESC92C_RATEMCS1,
1640 DESC92C_RATEMCS2, DESC92C_RATEMCS3,
1641 DESC92C_RATEMCS4, DESC92C_RATEMCS5,
1642 DESC92C_RATEMCS6, DESC92C_RATEMCS7};
1643 rtl92ee_phy_set_txpower_index_by_rate_array(hw, rfpath,
1644 rtlphy->current_chan_bw,
1645 channel, ht_rates1t, 8);
1646 } else if (section == HT_MCS8_MCS15) {
1647 u8 ht_rates2t[] = {DESC92C_RATEMCS8, DESC92C_RATEMCS9,
1648 DESC92C_RATEMCS10, DESC92C_RATEMCS11,
1649 DESC92C_RATEMCS12, DESC92C_RATEMCS13,
1650 DESC92C_RATEMCS14, DESC92C_RATEMCS15};
1651 rtl92ee_phy_set_txpower_index_by_rate_array(hw, rfpath,
1652 rtlphy->current_chan_bw,
1653 channel, ht_rates2t, 8);
1655 RT_TRACE(FPHY, PHY_TXPWR,
1656 ("Invalid RateSection %d\n", section));
1659 void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1661 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1662 struct rtl_phy *rtlphy = &(rtl_priv(hw)->phy);
1663 enum radio_path rfpath;
1665 if (rtlefuse->b_txpwr_fromeprom == false)
1667 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1669 rtl92ee_phy_set_txpower_index_by_rate_section(hw, rfpath,
1671 rtl92ee_phy_set_txpower_index_by_rate_section(hw, rfpath,
1673 rtl92ee_phy_set_txpower_index_by_rate_section(hw, rfpath,
1676 if (rtlphy->num_total_rfpath >= 2)
1677 rtl92ee_phy_set_txpower_index_by_rate_section(hw,
1683 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1684 enum wireless_mode wirelessmode,
1690 switch (wirelessmode) {
1691 case WIRELESS_MODE_B:
1694 case WIRELESS_MODE_G:
1695 case WIRELESS_MODE_N_24G:
1702 pwrout_dbm = txpwridx / 2 + offset;
1706 void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1708 struct rtl_priv *rtlpriv = rtl_priv(hw);
1709 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1710 enum io_type iotype;
1712 if (!is_hal_stop(rtlhal)) {
1713 switch (operation) {
1714 case SCAN_OPT_BACKUP_BAND0:
1715 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
1716 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1720 case SCAN_OPT_RESTORE:
1721 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1722 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1726 RT_TRACE(COMP_ERR, DBG_EMERG,
1727 ("Unknown Scan Backup operation.\n"));
1733 void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1735 struct rtl_priv *rtlpriv = rtl_priv(hw);
1736 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1737 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1738 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1742 RT_TRACE(COMP_SCAN, DBG_TRACE,
1743 ("Switch to %s bandwidth\n",
1744 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1745 "20MHz" : "40MHz"));
1747 if (is_hal_stop(rtlhal)) {
1748 rtlphy->set_bwmode_inprogress = false;
1752 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1753 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1755 switch (rtlphy->current_chan_bw) {
1756 case HT_CHANNEL_WIDTH_20:
1757 reg_bw_opmode |= BW_OPMODE_20MHZ;
1758 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1760 case HT_CHANNEL_WIDTH_20_40:
1761 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1762 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1763 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1764 (mac->cur_40_prime_sc << 5);
1765 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1768 RT_TRACE(COMP_ERR, DBG_EMERG,
1769 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1773 switch (rtlphy->current_chan_bw) {
1774 case HT_CHANNEL_WIDTH_20:
1775 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1776 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1777 rtl_set_bbreg(hw, ROFDM0_TXPSEUDONOISEWGT,
1778 (BIT(31) | BIT(30)), 0);
1780 case HT_CHANNEL_WIDTH_20_40:
1781 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1782 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1783 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1784 (mac->cur_40_prime_sc >> 1));
1785 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00,
1786 mac->cur_40_prime_sc);
1788 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1789 (mac->cur_40_prime_sc ==
1790 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1793 RT_TRACE(COMP_ERR, DBG_EMERG,
1794 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1797 rtl92ee_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1798 rtlphy->set_bwmode_inprogress = false;
1799 RT_TRACE(COMP_SCAN, DBG_LOUD, ("\n"));
1802 void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
1803 enum nl80211_channel_type ch_type)
1805 struct rtl_priv *rtlpriv = rtl_priv(hw);
1806 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1807 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1808 u8 tmp_bw = rtlphy->current_chan_bw;
1810 if (rtlphy->set_bwmode_inprogress)
1812 rtlphy->set_bwmode_inprogress = true;
1813 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1814 rtl92ee_phy_set_bw_mode_callback(hw);
1816 RT_TRACE(COMP_ERR, DBG_WARNING,
1817 ("false driver sleep or unload\n"));
1818 rtlphy->set_bwmode_inprogress = false;
1819 rtlphy->current_chan_bw = tmp_bw;
1823 void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1825 struct rtl_priv *rtlpriv = rtl_priv(hw);
1826 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1827 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1830 RT_TRACE(COMP_SCAN, DBG_TRACE,
1831 ("switch to channel%d\n", rtlphy->current_channel));
1832 if (is_hal_stop(rtlhal))
1835 if (!rtlphy->sw_chnl_inprogress)
1837 if (!_rtl92ee_phy_sw_chnl_step_by_step
1838 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1839 &rtlphy->sw_chnl_step, &delay)) {
1845 rtlphy->sw_chnl_inprogress = false;
1849 RT_TRACE(COMP_SCAN, DBG_TRACE, ("\n"));
1852 u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw)
1854 struct rtl_priv *rtlpriv = rtl_priv(hw);
1855 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1856 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1858 if (rtlphy->sw_chnl_inprogress)
1860 if (rtlphy->set_bwmode_inprogress)
1862 RT_ASSERT((rtlphy->current_channel <= 14),
1863 ("WIRELESS_MODE_G but channel>14"));
1864 rtlphy->sw_chnl_inprogress = true;
1865 rtlphy->sw_chnl_stage = 0;
1866 rtlphy->sw_chnl_step = 0;
1867 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1868 rtl92ee_phy_sw_chnl_callback(hw);
1869 RT_TRACE(COMP_CHAN, DBG_LOUD,
1870 ("sw_chnl_inprogress false schdule workitem current channel %d\n",
1871 rtlphy->current_channel));
1872 rtlphy->sw_chnl_inprogress = false;
1874 RT_TRACE(COMP_CHAN, DBG_LOUD,
1875 ("sw_chnl_inprogress false driver sleep or unload\n"));
1876 rtlphy->sw_chnl_inprogress = false;
1881 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1882 u8 channel, u8 *stage, u8 *step,
1885 struct rtl_priv *rtlpriv = rtl_priv(hw);
1886 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1887 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1888 u32 precommoncmdcnt;
1889 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1890 u32 postcommoncmdcnt;
1891 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1893 struct swchnlcmd *currentcmd = NULL;
1895 u8 num_total_rfpath = rtlphy->num_total_rfpath;
1897 precommoncmdcnt = 0;
1898 _rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1900 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
1901 _rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1902 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1904 postcommoncmdcnt = 0;
1906 _rtl92ee_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1907 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1911 RT_ASSERT((channel >= 1 && channel <= 14),
1912 ("illegal channel for Zebra: %d\n", channel));
1914 _rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1915 MAX_RFDEPENDCMD_CNT,
1917 RF_CHNLBW, channel, 10);
1919 _rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1920 MAX_RFDEPENDCMD_CNT, CMDID_END,
1926 currentcmd = &precommoncmd[*step];
1929 currentcmd = &rfdependcmd[*step];
1932 currentcmd = &postcommoncmd[*step];
1935 RT_TRACE(COMP_ERR, DBG_EMERG,
1936 ("Invalid 'stage' = %d, Check it!\n" ,
1942 if (currentcmd->cmdid == CMDID_END) {
1943 if ((*stage) == 2) {
1952 switch (currentcmd->cmdid) {
1953 case CMDID_SET_TXPOWEROWER_LEVEL:
1954 rtl92ee_phy_set_txpower_level(hw, channel);
1956 case CMDID_WRITEPORT_ULONG:
1957 rtl_write_dword(rtlpriv, currentcmd->para1,
1960 case CMDID_WRITEPORT_USHORT:
1961 rtl_write_word(rtlpriv, currentcmd->para1,
1962 (u16) currentcmd->para2);
1964 case CMDID_WRITEPORT_UCHAR:
1965 rtl_write_byte(rtlpriv, currentcmd->para1,
1966 (u8) currentcmd->para2);
1968 case CMDID_RF_WRITEREG:
1969 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1970 rtlphy->rfreg_chnlval[rfpath] =
1971 ((rtlphy->rfreg_chnlval[rfpath] &
1972 0xfffff00) | currentcmd->para2);
1974 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1977 rtlphy->rfreg_chnlval[rfpath]);
1981 RT_TRACE(COMP_ERR, DBG_EMERG,
1982 ("switch case not process\n"));
1989 (*delay) = currentcmd->msdelay;
1994 static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1995 u32 cmdtableidx, u32 cmdtablesz,
1996 enum swchnlcmd_id cmdid,
1997 u32 para1, u32 para2, u32 msdelay)
1999 struct swchnlcmd *pcmd;
2001 if (cmdtable == NULL) {
2002 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
2006 if (cmdtableidx >= cmdtablesz)
2009 pcmd = cmdtable + cmdtableidx;
2010 pcmd->cmdid = cmdid;
2011 pcmd->para1 = para1;
2012 pcmd->para2 = para2;
2013 pcmd->msdelay = msdelay;
2017 static u8 _rtl92ee_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
2019 u32 reg_eac, reg_e94, reg_e9c;
2021 /* path-A IQK setting */
2022 /* PA/PAD controlled by 0x0 */
2023 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2024 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
2025 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2027 rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x18008c1c);
2028 rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x38008c1c);
2029 rtl_set_bbreg(hw, RTx_IQK_Tone_B, MASKDWORD, 0x38008c1c);
2030 rtl_set_bbreg(hw, RRx_IQK_Tone_B, MASKDWORD, 0x38008c1c);
2032 rtl_set_bbreg(hw, RTx_IQK_PI_A, MASKDWORD, 0x82140303);
2033 rtl_set_bbreg(hw, RRx_IQK_PI_A, MASKDWORD, 0x68160000);
2035 /*LO calibration setting*/
2036 rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x00462911);
2038 /*One shot, path A LOK & IQK*/
2039 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf9000000);
2040 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
2042 mdelay(IQK_DELAY_TIME);
2044 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
2045 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
2046 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
2048 if (!(reg_eac & BIT(28)) &&
2049 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
2050 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
2058 static u8 _rtl92ee_phy_path_b_iqk(struct ieee80211_hw *hw)
2060 u32 reg_eac, reg_eb4, reg_ebc;
2063 /* PA/PAD controlled by 0x0 */
2064 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2065 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2066 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2068 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
2069 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2071 rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x38008c1c);
2072 rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x38008c1c);
2073 rtl_set_bbreg(hw, RTx_IQK_Tone_B, MASKDWORD, 0x18008c1c);
2074 rtl_set_bbreg(hw, RRx_IQK_Tone_B, MASKDWORD, 0x38008c1c);
2076 rtl_set_bbreg(hw, RTx_IQK_PI_B, MASKDWORD, 0x821403e2);
2077 rtl_set_bbreg(hw, RRx_IQK_PI_B, MASKDWORD, 0x68160000);
2079 /* LO calibration setting */
2080 rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x00462911);
2082 /*One shot, path B LOK & IQK*/
2083 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xfa000000);
2084 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
2086 mdelay(IQK_DELAY_TIME);
2088 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
2089 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
2090 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
2092 if (!(reg_eac & BIT(31)) &&
2093 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
2094 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
2102 static u8 _rtl92ee_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
2104 u32 reg_eac, reg_e94, reg_e9c, reg_ea4 , u32temp;
2107 /*Get TXIMR Setting*/
2108 /*Modify RX IQK mode table*/
2109 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2111 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2112 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2113 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2114 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
2116 /*PA/PAD control by 0x56, and set = 0x0*/
2117 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);
2118 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);
2121 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2124 rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, 0x01007c00);
2125 rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x01004800);
2127 /*path a IQK setting*/
2128 rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x18008c1c);
2129 rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x38008c1c);
2130 rtl_set_bbreg(hw, RTx_IQK_Tone_B, MASKDWORD, 0x38008c1c);
2131 rtl_set_bbreg(hw, RRx_IQK_Tone_B, MASKDWORD, 0x38008c1c);
2133 rtl_set_bbreg(hw, RTx_IQK_PI_A, MASKDWORD, 0x82160c1f);
2134 rtl_set_bbreg(hw, RRx_IQK_PI_A, MASKDWORD, 0x68160c1f);
2136 /*LO calibration Setting*/
2137 rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x0046a911);
2139 /*one shot, path A LOK & iqk*/
2140 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xfa000000);
2141 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
2143 mdelay(IQK_DELAY_TIME);
2146 reg_eac = rtl_get_bbreg(hw, RRx_Power_After_IQK_A_2, MASKDWORD);
2147 reg_e94 = rtl_get_bbreg(hw, RTx_Power_Before_IQK_A, MASKDWORD);
2148 reg_e9c = rtl_get_bbreg(hw, RTx_Power_After_IQK_A, MASKDWORD);
2150 if (!(reg_eac & BIT(28)) &&
2151 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
2152 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) {
2155 /* PA/PAD controlled by 0x0 */
2156 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2157 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
2161 u32temp = 0x80007C00 | (reg_e94 & 0x3FF0000) |
2162 ((reg_e9c & 0x3FF0000) >> 16);
2163 rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, u32temp);
2165 /*Modify RX IQK mode table*/
2166 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2168 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2170 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2171 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2172 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
2174 /*PA/PAD control by 0x56, and set = 0x0*/
2175 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);
2176 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);
2179 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2182 rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x01004800);
2184 /*path a IQK setting*/
2185 rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x38008c1c);
2186 rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x18008c1c);
2187 rtl_set_bbreg(hw, RTx_IQK_Tone_B, MASKDWORD, 0x38008c1c);
2188 rtl_set_bbreg(hw, RRx_IQK_Tone_B, MASKDWORD, 0x38008c1c);
2190 rtl_set_bbreg(hw, RTx_IQK_PI_A, MASKDWORD, 0x82160c1f);
2191 rtl_set_bbreg(hw, RRx_IQK_PI_A, MASKDWORD, 0x28160c1f);
2193 /*LO calibration Setting*/
2194 rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x0046a891);
2195 /*one shot, path A LOK & iqk*/
2196 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xfa000000);
2197 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
2199 mdelay(IQK_DELAY_TIME);
2201 reg_eac = rtl_get_bbreg(hw, RRx_Power_After_IQK_A_2, MASKDWORD);
2202 reg_ea4 = rtl_get_bbreg(hw, RRx_Power_Before_IQK_A_2, MASKDWORD);
2204 /*PA/PAD controlled by 0x0*/
2206 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2207 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
2208 /*if Tx is OK, check whether Rx is OK*/
2209 if (!(reg_eac & BIT(27)) &&
2210 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
2211 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
2217 static u8 _rtl92ee_phy_path_b_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
2219 struct rtl_priv *rtlpriv = rtl_priv(hw);
2220 u32 reg_eac, reg_eb4, reg_ebc, reg_ecc, reg_ec4, u32temp;
2223 /*Get TXIMR Setting*/
2224 /*Modify RX IQK mode table*/
2225 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2227 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2228 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2229 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2230 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
2233 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);
2234 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);
2236 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2239 rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, 0x01007c00);
2240 rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x01004800);
2242 /*path a IQK setting*/
2243 rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x38008c1c);
2244 rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x38008c1c);
2245 rtl_set_bbreg(hw, RTx_IQK_Tone_B, MASKDWORD, 0x18008c1c);
2246 rtl_set_bbreg(hw, RRx_IQK_Tone_B, MASKDWORD, 0x38008c1c);
2248 rtl_set_bbreg(hw, RTx_IQK_PI_B, MASKDWORD, 0x82160c1f);
2249 rtl_set_bbreg(hw, RRx_IQK_PI_B, MASKDWORD, 0x68160c1f);
2251 /*LO calibration Setting*/
2252 rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x0046a911);
2254 /*one shot, path A LOK & iqk*/
2255 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xfa000000);
2256 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
2258 mdelay(IQK_DELAY_TIME);
2261 reg_eac = rtl_get_bbreg(hw, RRx_Power_After_IQK_A_2, MASKDWORD);
2262 reg_eb4 = rtl_get_bbreg(hw, RTx_Power_Before_IQK_B, MASKDWORD);
2263 reg_ebc = rtl_get_bbreg(hw, RTx_Power_After_IQK_B, MASKDWORD);
2265 if (!(reg_eac & BIT(31)) &&
2266 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
2267 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) {
2270 /* PA/PAD controlled by 0x0 */
2271 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2272 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2276 u32temp = 0x80007C00 | (reg_eb4 & 0x3FF0000) |
2277 ((reg_ebc & 0x3FF0000) >> 16);
2278 rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, u32temp);
2280 /*Modify RX IQK mode table*/
2281 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2282 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2284 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2285 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2286 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
2289 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);
2290 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);
2293 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2296 rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x01004800);
2298 /*path b IQK setting*/
2299 rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x38008c1c);
2300 rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x38008c1c);
2301 rtl_set_bbreg(hw, RTx_IQK_Tone_B, MASKDWORD, 0x38008c1c);
2302 rtl_set_bbreg(hw, RRx_IQK_Tone_B, MASKDWORD, 0x18008c1c);
2304 rtl_set_bbreg(hw, RTx_IQK_PI_B, MASKDWORD, 0x82160c1f);
2305 rtl_set_bbreg(hw, RRx_IQK_PI_B, MASKDWORD, 0x28160c1f);
2307 /*LO calibration Setting*/
2308 rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x0046a891);
2309 /*one shot, path A LOK & iqk*/
2310 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xfa000000);
2311 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
2313 mdelay(IQK_DELAY_TIME);
2315 reg_eac = rtl_get_bbreg(hw, RRx_Power_After_IQK_A_2, MASKDWORD);
2316 reg_ec4 = rtl_get_bbreg(hw, RRx_Power_Before_IQK_B_2, MASKDWORD);
2317 reg_ecc = rtl_get_bbreg(hw, RRx_Power_After_IQK_B_2, MASKDWORD);
2318 /*PA/PAD controlled by 0x0*/
2320 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2321 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2322 /*if Tx is OK, check whether Rx is OK*/
2323 if (!(reg_eac & BIT(30)) &&
2324 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
2325 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
2328 RT_TRACE(COMP_RF, DBG_LOUD, ("Path B Rx IQK fail!!\n"));
2333 static void _rtl92ee_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
2334 bool b_iqk_ok, long result[][8],
2338 u32 oldval_0, x, tx0_a, reg;
2341 if (final_candidate == 0xFF) {
2343 } else if (b_iqk_ok) {
2344 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2345 MASKDWORD) >> 22) & 0x3FF;
2346 x = result[final_candidate][0];
2347 if ((x & 0x00000200) != 0)
2349 tx0_a = (x * oldval_0) >> 8;
2350 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2351 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
2352 ((x * oldval_0 >> 7) & 0x1));
2353 y = result[final_candidate][1];
2354 if ((y & 0x00000200) != 0)
2356 tx0_c = (y * oldval_0) >> 8;
2357 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2358 ((tx0_c & 0x3C0) >> 6));
2359 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2361 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
2362 ((y * oldval_0 >> 7) & 0x1));
2367 reg = result[final_candidate][2];
2368 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2370 reg = result[final_candidate][3] & 0x3F;
2371 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2373 reg = (result[final_candidate][3] >> 6) & 0xF;
2374 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg);
2378 static void _rtl92ee_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
2379 bool b_iqk_ok, long result[][8],
2383 u32 oldval_1, x, tx1_a, reg;
2386 if (final_candidate == 0xFF) {
2388 } else if (b_iqk_ok) {
2389 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2390 MASKDWORD) >> 22) & 0x3FF;
2391 x = result[final_candidate][4];
2392 if ((x & 0x00000200) != 0)
2394 tx1_a = (x * oldval_1) >> 8;
2395 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a);
2396 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
2397 ((x * oldval_1 >> 7) & 0x1));
2398 y = result[final_candidate][5];
2399 if ((y & 0x00000200) != 0)
2401 tx1_c = (y * oldval_1) >> 8;
2402 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2403 ((tx1_c & 0x3C0) >> 6));
2404 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2406 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
2407 ((y * oldval_1 >> 7) & 0x1));
2412 reg = result[final_candidate][6];
2413 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2415 reg = result[final_candidate][7] & 0x3F;
2416 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2418 reg = (result[final_candidate][7] >> 6) & 0xF;
2419 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg);
2423 static void _rtl92ee_phy_save_adda_registers(struct ieee80211_hw *hw,
2424 u32 *addareg, u32 *addabackup,
2429 for (i = 0; i < registernum; i++)
2430 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
2433 static void _rtl92ee_phy_save_mac_registers(struct ieee80211_hw *hw,
2434 u32 *macreg, u32 *macbackup)
2436 struct rtl_priv *rtlpriv = rtl_priv(hw);
2439 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
2440 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
2442 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
2445 static void _rtl92ee_phy_reload_adda_registers(struct ieee80211_hw *hw,
2446 u32 *addareg, u32 *addabackup,
2451 for (i = 0; i < regiesternum; i++)
2452 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
2455 static void _rtl92ee_phy_reload_mac_registers(struct ieee80211_hw *hw,
2456 u32 *macreg, u32 *macbackup)
2458 struct rtl_priv *rtlpriv = rtl_priv(hw);
2461 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
2462 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
2463 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
2466 static void _rtl92ee_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
2467 bool is_patha_on, bool is2t)
2472 pathon = is_patha_on ? 0x0fc01616 : 0x0fc01616;
2474 pathon = 0x0fc01616;
2475 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0fc01616);
2477 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
2480 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
2481 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
2484 static void _rtl92ee_phy_mac_setting_calibration(struct ieee80211_hw *hw,
2485 u32 *macreg, u32 *macbackup)
2487 rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff);
2490 static void _rtl92ee_phy_path_a_standby(struct ieee80211_hw *hw)
2492 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
2493 rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000);
2494 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2497 static bool _rtl92ee_phy_simularity_compare(struct ieee80211_hw *hw,
2498 long result[][8], u8 c1, u8 c2)
2500 u32 i, j, diff, simularity_bitmap, bound;
2502 u8 final_candidate[2] = { 0xFF, 0xFF };
2503 bool bresult = true/*, is2t = true*/;
2508 simularity_bitmap = 0;
2510 for (i = 0; i < bound; i++) {
2511 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
2512 if ((result[c1][i] & 0x00000200) != 0)
2513 tmp1 = result[c1][i] | 0xFFFFFC00;
2515 tmp1 = result[c1][i];
2517 if ((result[c2][i] & 0x00000200) != 0)
2518 tmp2 = result[c2][i] | 0xFFFFFC00;
2520 tmp2 = result[c2][i];
2522 tmp1 = result[c1][i];
2523 tmp2 = result[c2][i];
2526 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2528 if (diff > MAX_TOLERANCE) {
2529 if ((i == 2 || i == 6) && !simularity_bitmap) {
2530 if (result[c1][i] + result[c1][i + 1] == 0)
2531 final_candidate[(i / 4)] = c2;
2532 else if (result[c2][i] + result[c2][i + 1] == 0)
2533 final_candidate[(i / 4)] = c1;
2535 simularity_bitmap |= (1 << i);
2537 simularity_bitmap |= (1 << i);
2542 if (simularity_bitmap == 0) {
2543 for (i = 0; i < (bound / 4); i++) {
2544 if (final_candidate[i] != 0xFF) {
2545 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2547 result[final_candidate[i]][j];
2553 if (!(simularity_bitmap & 0x03)) {/*path A TX OK*/
2554 for (i = 0; i < 2; i++)
2555 result[3][i] = result[c1][i];
2557 if (!(simularity_bitmap & 0x0c)) {/*path A RX OK*/
2558 for (i = 2; i < 4; i++)
2559 result[3][i] = result[c1][i];
2561 if (!(simularity_bitmap & 0x30)) {/*path B TX OK*/
2562 for (i = 4; i < 6; i++)
2563 result[3][i] = result[c1][i];
2565 if (!(simularity_bitmap & 0xc0)) {/*path B RX OK*/
2566 for (i = 6; i < 8; i++)
2567 result[3][i] = result[c1][i];
2573 static void _rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw,
2574 long result[][8], u8 t, bool is2t)
2576 struct rtl_priv *rtlpriv = rtl_priv(hw);
2577 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2579 u8 patha_ok, pathb_ok;
2580 u8 tmp_0xc50 = (u8) rtl_get_bbreg(hw, 0xc50, MASKBYTE0);
2581 u8 tmp_0xc58 = (u8) rtl_get_bbreg(hw, 0xc58, MASKBYTE0);
2582 u32 adda_reg[IQK_ADDA_REG_NUM] = {
2583 0x85c, 0xe6c, 0xe70, 0xe74,
2584 0xe78, 0xe7c, 0xe80, 0xe84,
2585 0xe88, 0xe8c, 0xed0, 0xed4,
2586 0xed8, 0xedc, 0xee0, 0xeec
2589 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2590 0x522, 0x550, 0x551, 0x040
2593 u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2594 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
2595 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
2600 const u32 retrycount = 2;
2604 _rtl92ee_phy_save_adda_registers(hw, adda_reg,
2605 rtlphy->adda_backup,
2607 _rtl92ee_phy_save_mac_registers(hw, iqk_mac_reg,
2608 rtlphy->iqk_mac_backup);
2609 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg,
2610 rtlphy->iqk_bb_backup,
2614 _rtl92ee_phy_path_adda_on(hw, adda_reg, true, is2t);
2617 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2618 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
2619 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
2620 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200);
2622 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01);
2623 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01);
2624 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01);
2625 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01);
2627 _rtl92ee_phy_mac_setting_calibration(hw, iqk_mac_reg,
2628 rtlphy->iqk_mac_backup);
2630 /* IQ calibration setting*/
2631 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2632 rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, 0x01007c00);
2633 rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x01004800);
2635 for (i = 0; i < retrycount; i++) {
2636 patha_ok = _rtl92ee_phy_path_a_iqk(hw, is2t);
2638 if (patha_ok == 0x01) {
2639 RT_TRACE(COMP_RF, DBG_LOUD,
2640 ("Path A Tx IQK Success!!\n"));
2641 result[t][0] = (rtl_get_bbreg(hw,
2642 RTx_Power_Before_IQK_A,
2643 MASKDWORD) & 0x3FF0000)
2645 result[t][1] = (rtl_get_bbreg(hw, RTx_Power_After_IQK_A,
2646 MASKDWORD) & 0x3FF0000)
2650 RT_TRACE(COMP_RF, DBG_LOUD,
2651 ("Path A Tx IQK Fail!!, ret = 0x%x\n",
2656 for (i = 0 ; i < retrycount ; i++) {
2657 patha_ok = _rtl92ee_phy_path_a_rx_iqk(hw, is2t);
2659 if (patha_ok == 0x03) {
2660 RT_TRACE(COMP_RF, DBG_LOUD,
2661 ("Path A Rx IQK Success!!\n"));
2662 result[t][2] = (rtl_get_bbreg(hw,
2663 RRx_Power_Before_IQK_A_2,
2664 MASKDWORD) & 0x3FF0000)
2666 result[t][3] = (rtl_get_bbreg(hw,
2667 RRx_Power_After_IQK_A_2,
2668 MASKDWORD) & 0x3FF0000)
2672 RT_TRACE(COMP_RF, DBG_LOUD,
2673 ("Path A Rx IQK Fail!!, ret = 0x%x\n",
2678 if (0x00 == patha_ok)
2679 RT_TRACE(COMP_RF, DBG_LOUD, ("Path A IQK failed!!, ret = 0\n"));
2682 _rtl92ee_phy_path_a_standby(hw);
2683 /* Turn Path B ADDA on */
2684 _rtl92ee_phy_path_adda_on(hw, adda_reg, false, is2t);
2686 /* IQ calibration setting */
2687 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2688 rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, 0x01007c00);
2689 rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x01004800);
2691 for (i = 0 ; i < retrycount ; i++) {
2692 pathb_ok = _rtl92ee_phy_path_b_iqk(hw);
2693 if (pathb_ok == 0x01) {
2694 RT_TRACE(COMP_RF, DBG_LOUD,
2695 ("Path B Tx IQK Success!!\n"));
2696 result[t][4] = (rtl_get_bbreg(hw,
2697 RTx_Power_Before_IQK_B,
2698 MASKDWORD) & 0x3FF0000)
2700 result[t][5] = (rtl_get_bbreg(hw,
2701 RTx_Power_After_IQK_B,
2702 MASKDWORD) & 0x3FF0000)
2706 RT_TRACE(COMP_RF, DBG_LOUD,
2707 ("Path B Tx IQK Fail!!, ret = 0x%x\n",
2712 for (i = 0 ; i < retrycount ; i++) {
2713 pathb_ok = _rtl92ee_phy_path_b_rx_iqk(hw, is2t);
2714 if (pathb_ok == 0x03) {
2715 RT_TRACE(COMP_RF, DBG_LOUD,
2716 ("Path B Rx IQK Success!!\n"));
2717 result[t][6] = (rtl_get_bbreg(hw,
2718 RRx_Power_Before_IQK_B_2,
2719 MASKDWORD) & 0x3FF0000)
2721 result[t][7] = (rtl_get_bbreg(hw,
2722 RRx_Power_After_IQK_B_2,
2723 MASKDWORD) & 0x3FF0000)
2727 RT_TRACE(COMP_RF, DBG_LOUD,
2728 ("Path B Rx IQK Fail!!, ret = 0x%x\n",
2733 if (0x00 == pathb_ok)
2734 RT_TRACE(COMP_RF, DBG_LOUD,
2735 ("Path B IQK failed!!, ret = 0\n"));
2737 /* Back to BB mode, load original value */
2738 RT_TRACE(COMP_RF, DBG_LOUD,
2739 ("IQK:Back to BB mode, load original value!\n"));
2740 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);
2743 /* Reload ADDA power saving parameters */
2744 _rtl92ee_phy_reload_adda_registers(hw, adda_reg,
2745 rtlphy->adda_backup,
2748 /* Reload MAC parameters */
2749 _rtl92ee_phy_reload_mac_registers(hw, iqk_mac_reg,
2750 rtlphy->iqk_mac_backup);
2752 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg,
2753 rtlphy->iqk_bb_backup,
2756 /* Restore RX initial gain */
2757 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2758 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50);
2760 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2761 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58);
2764 /* load 0xe30 IQC default value */
2765 rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x01008c00);
2766 rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x01008c00);
2768 RT_TRACE(COMP_RF, DBG_LOUD, ("_rtl92ee_phy_iq_calibrate() <==\n"));
2771 static void _rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2774 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
2775 struct rtl_priv *rtlpriv = rtl_priv(hw);
2777 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2779 if ((tmpreg & 0x70) != 0)
2780 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2782 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2784 if ((tmpreg & 0x70) != 0) {
2785 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
2788 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
2791 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
2792 (rf_a_mode & 0x8FFFF) | 0x10000);
2795 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
2796 (rf_b_mode & 0x8FFFF) | 0x10000);
2798 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
2800 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
2804 if ((tmpreg & 0x70) != 0) {
2805 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2806 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
2809 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
2812 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2814 RT_TRACE(COMP_INIT , DBG_LOUD , ("\n"));
2817 static void _rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw,
2818 bool bmain, bool is2t)
2820 struct rtl_priv *rtlpriv = rtl_priv(hw);
2821 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2822 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2823 RT_TRACE(COMP_INIT , DBG_LOUD , ("\n"));
2825 if (is_hal_stop(rtlhal)) {
2827 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0);
2828 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7));
2829 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
2833 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2834 BIT(5) | BIT(6), 0x1);
2836 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2837 BIT(5) | BIT(6), 0x2);
2839 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
2840 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
2842 /* We use the RF definition of MAIN and AUX,
2843 * left antenna and right antenna repectively.
2844 * Default output at AUX.*/
2846 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
2847 BIT(14) | BIT(13) | BIT(12), 0);
2848 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2849 BIT(5) | BIT(4) | BIT(3), 0);
2850 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
2851 rtl_set_bbreg(hw, rConfig_ram64x16, BIT(31), 0);
2853 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
2854 BIT(14) | BIT(13) | BIT(12), 1);
2855 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2856 BIT(5) | BIT(4) | BIT(3), 1);
2857 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
2858 rtl_set_bbreg(hw, rConfig_ram64x16, BIT(31), 1);
2863 #undef IQK_ADDA_REG_NUM
2864 #undef IQK_DELAY_TIME
2866 static u8 rtl92ee_get_rightchnlplace_for_iqk(u8 chnl)
2868 u8 channel_all[59] = {
2869 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
2870 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2871 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2872 114, 116, 118, 120, 122, 124, 126, 128, 130,
2873 132, 134, 136, 138, 140, 149, 151, 153, 155,
2874 157, 159, 161, 163, 165
2879 for (place = 14; place < sizeof(channel_all); place++) {
2880 if (channel_all[place] == chnl)
2888 void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
2890 struct rtl_priv *rtlpriv = rtl_priv(hw);
2891 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2893 u8 i, final_candidate;
2894 bool b_patha_ok, b_pathb_ok;
2895 long reg_e94, reg_e9c, reg_ea4, reg_eac;
2896 long reg_eb4, reg_ebc, reg_ec4, reg_ecc;
2897 bool is12simular, is13simular, is23simular;
2899 u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2900 ROFDM0_XARXIQIMBALANCE,
2901 ROFDM0_XBRXIQIMBALANCE,
2902 ROFDM0_ECCATHRESHOLD,
2903 ROFDM0_AGCRSSITABLE,
2904 ROFDM0_XATXIQIMBALANCE,
2905 ROFDM0_XBTXIQIMBALANCE,
2912 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg,
2913 rtlphy->iqk_bb_backup, 9);
2917 for (i = 0; i < 8; i++) {
2922 if ((i == 0) || (i == 2) || (i == 4) || (i == 6))
2923 result[3][i] = 0x100;
2927 final_candidate = 0xff;
2930 is12simular = false;
2931 is23simular = false;
2932 is13simular = false;
2933 for (i = 0; i < 3; i++) {
2934 _rtl92ee_phy_iq_calibrate(hw, result, i, true);
2936 is12simular = _rtl92ee_phy_simularity_compare(hw,
2940 final_candidate = 0;
2946 is13simular = _rtl92ee_phy_simularity_compare(hw,
2950 final_candidate = 0;
2953 is23simular = _rtl92ee_phy_simularity_compare(hw,
2957 final_candidate = 1;
2959 final_candidate = 3;
2962 for (i = 0; i < 4; i++) {
2963 reg_e94 = result[i][0];
2964 reg_e9c = result[i][1];
2965 reg_ea4 = result[i][2];
2966 reg_eac = result[i][3];
2967 reg_eb4 = result[i][4];
2968 reg_ebc = result[i][5];
2969 reg_ec4 = result[i][6];
2970 reg_ecc = result[i][7];
2972 if (final_candidate != 0xff) {
2973 reg_e94 = result[final_candidate][0];
2974 rtlphy->reg_e94 = reg_e94;
2975 reg_e9c = result[final_candidate][1];
2976 rtlphy->reg_e9c = reg_e9c;
2977 reg_ea4 = result[final_candidate][2];
2978 reg_eac = result[final_candidate][3];
2979 reg_eb4 = result[final_candidate][4];
2980 rtlphy->reg_eb4 = reg_eb4;
2981 reg_ebc = result[final_candidate][5];
2982 rtlphy->reg_ebc = reg_ebc;
2983 reg_ec4 = result[final_candidate][6];
2984 reg_ecc = result[final_candidate][7];
2988 rtlphy->reg_e94 = 0x100;
2989 rtlphy->reg_eb4 = 0x100;
2990 rtlphy->reg_e9c = 0x0;
2991 rtlphy->reg_ebc = 0x0;
2994 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
2995 _rtl92ee_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2999 _rtl92ee_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result,
3003 idx = rtl92ee_get_rightchnlplace_for_iqk(rtlphy->current_channel);
3005 /* To Fix BSOD when final_candidate is 0xff
3006 * by sherry 20120321 */
3007 if (final_candidate < 4) {
3008 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
3009 rtlphy->iqk_matrix_regsetting[idx].value[0][i] =
3010 result[final_candidate][i];
3012 rtlphy->iqk_matrix_regsetting[idx].b_iqk_done = true;
3014 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg,
3015 rtlphy->iqk_bb_backup, 9);
3018 void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw)
3020 struct rtl_priv *rtlpriv = rtl_priv(hw);
3021 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3022 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
3023 u32 timeout = 2000, timecount = 0;
3025 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
3030 rtlphy->lck_inprogress = true;
3031 RTPRINT(rtlpriv, FINIT, INIT_IQK,
3032 "LCK:Start!!! currentband %x delay %d ms\n",
3033 rtlhal->current_bandtype, timecount);
3035 _rtl92ee_phy_lc_calibrate(hw, false);
3037 rtlphy->lck_inprogress = false;
3040 void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
3042 struct rtl_priv *rtlpriv = rtl_priv(hw);
3043 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3045 if (rtlphy->b_apk_done)
3051 void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
3053 _rtl92ee_phy_set_rfpath_switch(hw, bmain, false);
3056 bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
3058 struct rtl_priv *rtlpriv = rtl_priv(hw);
3059 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3060 bool b_postprocessing = false;
3062 RT_TRACE(COMP_CMD, DBG_TRACE,
3063 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
3064 iotype, rtlphy->set_io_inprogress));
3067 case IO_CMD_RESUME_DM_BY_SCAN:
3068 RT_TRACE(COMP_CMD, DBG_TRACE,
3069 ("[IO CMD] Resume DM after scan.\n"));
3070 b_postprocessing = true;
3072 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
3073 RT_TRACE(COMP_CMD, DBG_TRACE,
3074 ("[IO CMD] Pause DM before scan.\n"));
3075 b_postprocessing = true;
3078 RT_TRACE(COMP_ERR, DBG_EMERG,
3079 ("switch case not process\n"));
3083 if (b_postprocessing && !rtlphy->set_io_inprogress) {
3084 rtlphy->set_io_inprogress = true;
3085 rtlphy->current_io_type = iotype;
3089 rtl92ee_phy_set_io(hw);
3090 RT_TRACE(COMP_CMD, DBG_TRACE, ("IO Type(%#x)\n", iotype));
3094 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw)
3096 struct rtl_priv *rtlpriv = rtl_priv(hw);
3097 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3099 RT_TRACE(COMP_CMD, DBG_TRACE,
3100 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
3101 rtlphy->current_io_type, rtlphy->set_io_inprogress));
3102 switch (rtlphy->current_io_type) {
3103 case IO_CMD_RESUME_DM_BY_SCAN:
3104 rtl92ee_dm_write_dig(hw , rtlphy->initgain_backup.xaagccore1);
3105 rtl92ee_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca);
3106 RT_TRACE(COMP_CMD, DBG_TRACE , ("no set txpower\n"));
3107 rtl92ee_phy_set_txpower_level(hw, rtlphy->current_channel);
3109 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
3111 rtlphy->initgain_backup.xaagccore1 = dm_dig.cur_igvalue;
3112 rtl92ee_dm_write_dig(hw, 0x17);
3113 rtlphy->initgain_backup.cca = dm_dig.cur_cck_cca_thres;
3114 rtl92ee_dm_write_cck_cca_thres(hw, 0x40);
3117 RT_TRACE(COMP_ERR, DBG_EMERG,
3118 ("switch case not process\n"));
3121 rtlphy->set_io_inprogress = false;
3122 RT_TRACE(COMP_CMD, DBG_TRACE,
3123 ("(%#x)\n", rtlphy->current_io_type));
3126 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw)
3128 struct rtl_priv *rtlpriv = rtl_priv(hw);
3130 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3131 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3132 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/
3133 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3134 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3135 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3138 static void _rtl92ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
3140 struct rtl_priv *rtlpriv = rtl_priv(hw);
3142 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3143 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3145 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3146 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3149 static bool _rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
3150 enum rf_pwrstate rfpwr_state)
3152 struct rtl_priv *rtlpriv = rtl_priv(hw);
3153 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3154 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3155 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3156 bool bresult = true;
3158 struct rtl8192_tx_ring *ring = NULL;
3160 switch (rfpwr_state) {
3162 if ((ppsc->rfpwr_state == ERFOFF) &&
3163 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3168 RT_TRACE(COMP_RF, DBG_DMESG,
3169 ("IPS Set eRf nic enable\n"));
3170 rtstatus = stg_rtl_ps_enable_nic(hw);
3171 } while (!rtstatus && (init_count < 10));
3172 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3174 RT_TRACE(COMP_RF, DBG_DMESG,
3175 ("Set ERFON sleeped:%d ms\n",
3176 jiffies_to_msecs(jiffies -
3177 ppsc->last_sleep_jiffies)));
3178 ppsc->last_awake_jiffies = jiffies;
3179 rtl92ee_phy_set_rf_on(hw);
3181 if (mac->link_state == MAC80211_LINKED)
3182 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
3184 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
3187 for (queue_id = 0, i = 0;
3188 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3189 ring = &pcipriv->dev.tx_ring[queue_id];
3190 if (skb_queue_len(&ring->queue) == 0) {
3194 RT_TRACE(COMP_ERR, DBG_WARNING,
3195 ("eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before "
3196 "doze!\n", (i + 1), queue_id,
3197 skb_queue_len(&ring->queue)));
3202 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3203 RT_TRACE(COMP_ERR, DBG_WARNING,
3204 ("\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
3205 MAX_DOZE_WAITING_TIMES_9x,
3207 skb_queue_len(&ring->queue)));
3212 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3213 RT_TRACE(COMP_RF, DBG_DMESG,
3214 ("IPS Set eRf nic disable\n"));
3215 stg_rtl_ps_disable_nic(hw);
3216 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3218 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
3219 rtlpriv->cfg->ops->led_control(hw,
3222 rtlpriv->cfg->ops->led_control(hw,
3228 if (ppsc->rfpwr_state == ERFOFF)
3230 for (queue_id = 0, i = 0;
3231 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3232 ring = &pcipriv->dev.tx_ring[queue_id];
3233 if (skb_queue_len(&ring->queue) == 0) {
3237 RT_TRACE(COMP_ERR, DBG_WARNING,
3238 ("eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3240 skb_queue_len(&ring->queue)));
3244 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3245 RT_TRACE(COMP_ERR, DBG_WARNING,
3246 ("\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
3247 MAX_DOZE_WAITING_TIMES_9x,
3249 skb_queue_len(&ring->queue)));
3253 RT_TRACE(COMP_RF, DBG_DMESG,
3254 ("Set ERFSLEEP awaked:%d ms\n",
3255 jiffies_to_msecs(jiffies -
3256 ppsc->last_awake_jiffies)));
3257 ppsc->last_sleep_jiffies = jiffies;
3258 _rtl92ee_phy_set_rf_sleep(hw);
3261 RT_TRACE(COMP_ERR, DBG_EMERG,
3262 ("switch case not process\n"));
3267 ppsc->rfpwr_state = rfpwr_state;
3271 bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
3272 enum rf_pwrstate rfpwr_state)
3274 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3276 bool bresult = false;
3278 if (rfpwr_state == ppsc->rfpwr_state)
3280 bresult = _rtl92ee_phy_set_rf_power_state(hw, rfpwr_state);