drivers/staging/rtl8192u/r8192U_dm.c

   1 /*++
   2 Copyright-c Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8192U_dm.c
   6
   7 Abstract:
   8         HW dynamic mechanism.
   9
  10 Major Change History:
  11         When            Who                             What
  12         ----------      --------------- -------------------------------
  13         2008-05-14      amy                     create version 0 porting from windows code.
  14
  15 --*/
  16 #include "r8192U.h"
  17 #include "r8192U_dm.h"
  18 #include "r8192U_hw.h"
  19 #include "r819xU_phy.h"
  20 #include "r819xU_phyreg.h"
  21 #include "r8190_rtl8256.h"
  22 #include "r819xU_cmdpkt.h"
  23 /*---------------------------Define Local Constant---------------------------*/
  24 /* Indicate different AP vendor for IOT issue. */
  25 static u32 edca_setting_DL[HT_IOT_PEER_MAX] = {
  26         0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0x00a44f, 0x5ea44f
  27 };
  28 static u32 edca_setting_UL[HT_IOT_PEER_MAX] = {
  29         0x5e4322, 0x00a44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f
  30 };
  31
  32 #define RTK_UL_EDCA 0xa44f
  33 #define RTK_DL_EDCA 0x5e4322
  34 /*---------------------------Define Local Constant---------------------------*/
  35
  36
  37 /*------------------------Define global variable-----------------------------*/
  38 /* Debug variable ? */
  39 dig_t   dm_digtable;
  40 /* Store current software write register content for MAC PHY. */
  41 u8              dm_shadow[16][256] = { {0} };
  42 /* For Dynamic Rx Path Selection by Signal Strength */
  43 DRxPathSel      DM_RxPathSelTable;
  44 /*------------------------Define global variable-----------------------------*/
  45
  46
  47 /*------------------------Define local variable------------------------------*/
  48 /*------------------------Define local variable------------------------------*/
  49
  50
  51 /*--------------------Define export function prototype-----------------------*/
  52 extern  void dm_check_fsync(struct net_device *dev);
  53
  54 /*--------------------Define export function prototype-----------------------*/
  55
  56
  57 /*---------------------Define local function prototype-----------------------*/
  58 /* DM --> Rate Adaptive */
  59 static  void    dm_check_rate_adaptive(struct net_device *dev);
  60
  61 /* DM --> Bandwidth switch */
  62 static  void    dm_init_bandwidth_autoswitch(struct net_device *dev);
  63 static  void    dm_bandwidth_autoswitch(struct net_device *dev);
  64
  65 /* DM --> TX power control */
  66 /*static        void    dm_initialize_txpower_tracking(struct net_device *dev);*/
  67
  68 static  void    dm_check_txpower_tracking(struct net_device *dev);
  69
  70 /*static        void    dm_txpower_reset_recovery(struct net_device *dev);*/
  71
  72 /* DM --> Dynamic Init Gain by RSSI */
  73 static  void    dm_dig_init(struct net_device *dev);
  74 static  void    dm_ctrl_initgain_byrssi(struct net_device *dev);
  75 static  void    dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
  76 static  void    dm_ctrl_initgain_byrssi_by_driverrssi(struct net_device *dev);
  77 static  void    dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
  78 static  void    dm_initial_gain(struct net_device *dev);
  79 static  void    dm_pd_th(struct net_device *dev);
  80 static  void    dm_cs_ratio(struct net_device *dev);
  81
  82 static  void dm_init_ctstoself(struct net_device *dev);
  83 /* DM --> EDCA turbo mode control */
  84 static  void    dm_check_edca_turbo(struct net_device *dev);
  85
  86 /*static        void    dm_gpio_change_rf(struct net_device *dev);*/
  87 /* DM --> Check PBC */
  88 static  void dm_check_pbc_gpio(struct net_device *dev);
  89
  90 /* DM --> Check current RX RF path state */
  91 static  void    dm_check_rx_path_selection(struct net_device *dev);
  92 static  void dm_init_rxpath_selection(struct net_device *dev);
  93 static  void dm_rxpath_sel_byrssi(struct net_device *dev);
  94
  95 /* DM --> Fsync for broadcom ap */
  96 static void dm_init_fsync(struct net_device *dev);
  97 static void dm_deInit_fsync(struct net_device *dev);
  98
  99 /* Added by vivi, 20080522 */
 100 static  void    dm_check_txrateandretrycount(struct net_device *dev);
 101
 102 /*---------------------Define local function prototype-----------------------*/
 103
 104 /*---------------------Define of Tx Power Control For Near/Far Range --------*/   /*Add by Jacken 2008/02/18 */
 105 static  void    dm_init_dynamic_txpower(struct net_device *dev);
 106 static  void    dm_dynamic_txpower(struct net_device *dev);
 107
 108 /* DM --> For rate adaptive and DIG, we must send RSSI to firmware */
 109 static  void dm_send_rssi_tofw(struct net_device *dev);
 110 static  void    dm_ctstoself(struct net_device *dev);
 111 /*---------------------------Define function prototype------------------------*/
 112 /*
 113  * ================================================================================
 114  *      HW Dynamic mechanism interface.
 115  * ================================================================================
 116  *
 117  *
 118  *      Description:
 119  *              Prepare SW resource for HW dynamic mechanism.
 120  *
 121  *      Assumption:
 122  *              This function is only invoked at driver intialization once.
 123  */
 124 void init_hal_dm(struct net_device *dev)
 125 {
 126         struct r8192_priv *priv = ieee80211_priv(dev);
 127
 128         /* Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism. */
 129         priv->undecorated_smoothed_pwdb = -1;
 130
 131         /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */
 132         dm_init_dynamic_txpower(dev);
 133         init_rate_adaptive(dev);
 134         /*dm_initialize_txpower_tracking(dev);*/
 135         dm_dig_init(dev);
 136         dm_init_edca_turbo(dev);
 137         dm_init_bandwidth_autoswitch(dev);
 138         dm_init_fsync(dev);
 139         dm_init_rxpath_selection(dev);
 140         dm_init_ctstoself(dev);
 141
 142 }       /* InitHalDm */
 143
 144 void deinit_hal_dm(struct net_device *dev)
 145 {
 146         dm_deInit_fsync(dev);
 147 }
 148
 149 #ifdef USB_RX_AGGREGATION_SUPPORT
 150 void dm_CheckRxAggregation(struct net_device *dev)
 151 {
 152         struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
 153         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
 154         static unsigned long    lastTxOkCnt;
 155         static unsigned long    lastRxOkCnt;
 156         unsigned long           curTxOkCnt = 0;
 157         unsigned long           curRxOkCnt = 0;
 158
 159 /*
 160         if (pHalData->bForcedUsbRxAggr) {
 161                 if (pHalData->ForcedUsbRxAggrInfo == 0) {
 162                         if (pHalData->bCurrentRxAggrEnable) {
 163                                 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
 164                         }
 165                 } else {
 166                         if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
 167                                 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
 168                         }
 169                 }
 170                 return;
 171         }
 172
 173 */
 174         curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
 175         curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
 176
 177         if ((curTxOkCnt + curRxOkCnt) < 15000000)
 178                 return;
 179
 180         if (curTxOkCnt > 4*curRxOkCnt) {
 181                 if (priv->bCurrentRxAggrEnable) {
 182                         write_nic_dword(dev, 0x1a8, 0);
 183                         priv->bCurrentRxAggrEnable = false;
 184                 }
 185         } else {
 186                 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
 187                         u32 ulValue;
 188
 189                         ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
 190                                 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
 191                         /*
 192                          * If usb rx firmware aggregation is enabled,
 193                          * when anyone of three threshold conditions above is reached,
 194                          * firmware will send aggregated packet to driver.
 195                          */
 196                         write_nic_dword(dev, 0x1a8, ulValue);
 197                         priv->bCurrentRxAggrEnable = true;
 198                 }
 199         }
 200
 201         lastTxOkCnt = priv->stats.txbytesunicast;
 202         lastRxOkCnt = priv->stats.rxbytesunicast;
 203 }       /* dm_CheckEdcaTurbo */
 204 #endif
 205
 206 void hal_dm_watchdog(struct net_device *dev)
 207 {
 208         /*struct r8192_priv *priv = ieee80211_priv(dev);*/
 209
 210         /*static u8     previous_bssid[6] ={0};*/
 211
 212         /*Add by amy 2008/05/15 ,porting from windows code.*/
 213         dm_check_rate_adaptive(dev);
 214         dm_dynamic_txpower(dev);
 215         dm_check_txrateandretrycount(dev);
 216         dm_check_txpower_tracking(dev);
 217         dm_ctrl_initgain_byrssi(dev);
 218         dm_check_edca_turbo(dev);
 219         dm_bandwidth_autoswitch(dev);
 220         dm_check_rx_path_selection(dev);
 221         dm_check_fsync(dev);
 222
 223         /* Add by amy 2008-05-15 porting from windows code. */
 224         dm_check_pbc_gpio(dev);
 225         dm_send_rssi_tofw(dev);
 226         dm_ctstoself(dev);
 227 #ifdef USB_RX_AGGREGATION_SUPPORT
 228         dm_CheckRxAggregation(dev);
 229 #endif
 230 }       /* HalDmWatchDog */
 231
 232 /*
 233  * Decide Rate Adaptive Set according to distance (signal strength)
 234  *      01/11/2008      MHC             Modify input arguments and RATR table level.
 235  *      01/16/2008      MHC             RF_Type is assigned in ReadAdapterInfo(). We must call
 236  *                                              the function after making sure RF_Type.
 237  */
 238 void init_rate_adaptive(struct net_device *dev)
 239 {
 240         struct r8192_priv *priv = ieee80211_priv(dev);
 241         prate_adaptive  pra = (prate_adaptive)&priv->rate_adaptive;
 242
 243         pra->ratr_state = DM_RATR_STA_MAX;
 244         pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High;
 245         pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5;
 246         pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5;
 247
 248         pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5;
 249         pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M;
 250         pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M;
 251
 252         if (priv->CustomerID == RT_CID_819x_Netcore)
 253                 pra->ping_rssi_enable = 1;
 254         else
 255                 pra->ping_rssi_enable = 0;
 256         pra->ping_rssi_thresh_for_ra = 15;
 257
 258         if (priv->rf_type == RF_2T4R) {
 259                 /*
 260                  * 07/10/08 MH Modify for RA smooth scheme.
 261                  * 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.
 262                  */
 263                 pra->upper_rssi_threshold_ratr          =       0x8f0f0000;
 264                 pra->middle_rssi_threshold_ratr         =       0x8f0ff000;
 265                 pra->low_rssi_threshold_ratr            =       0x8f0ff001;
 266                 pra->low_rssi_threshold_ratr_40M        =       0x8f0ff005;
 267                 pra->low_rssi_threshold_ratr_20M        =       0x8f0ff001;
 268                 pra->ping_rssi_ratr     =       0x0000000d;/* cosa add for test */
 269         } else if (priv->rf_type == RF_1T2R) {
 270                 pra->upper_rssi_threshold_ratr          =       0x000f0000;
 271                 pra->middle_rssi_threshold_ratr         =       0x000ff000;
 272                 pra->low_rssi_threshold_ratr            =       0x000ff001;
 273                 pra->low_rssi_threshold_ratr_40M        =       0x000ff005;
 274                 pra->low_rssi_threshold_ratr_20M        =       0x000ff001;
 275                 pra->ping_rssi_ratr     =       0x0000000d;/* cosa add for test */
 276         }
 277
 278 }       /* InitRateAdaptive */
 279
 280 /*-----------------------------------------------------------------------------
 281  * Function:    dm_check_rate_adaptive()
 282  *
 283  * Overview:
 284  *
 285  * Input:               NONE
 286  *
 287  * Output:              NONE
 288  *
 289  * Return:              NONE
 290  *
 291  * Revised History:
 292  *      When            Who             Remark
 293  *      05/26/08        amy     Create version 0 porting from windows code.
 294  *
 295  *---------------------------------------------------------------------------*/
 296 static void dm_check_rate_adaptive(struct net_device *dev)
 297 {
 298         struct r8192_priv *priv = ieee80211_priv(dev);
 299         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
 300         prate_adaptive                  pra = (prate_adaptive)&priv->rate_adaptive;
 301         u32                                             currentRATR, targetRATR = 0;
 302         u32                                             LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
 303         bool                                            bshort_gi_enabled = false;
 304         static u8                                       ping_rssi_state;
 305
 306         if (!priv->up) {
 307                 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
 308                 return;
 309         }
 310
 311         if (pra->rate_adaptive_disabled) /* this variable is set by ioctl. */
 312                 return;
 313
 314         /* TODO: Only 11n mode is implemented currently, */
 315         if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
 316               priv->ieee80211->mode == WIRELESS_MODE_N_5G))
 317                 return;
 318
 319         if (priv->ieee80211->state == IEEE80211_LINKED) {
 320                 /*RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");*/
 321
 322                 /* Check whether Short GI is enabled */
 323                 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
 324                         (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
 325
 326                 pra->upper_rssi_threshold_ratr =
 327                                 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);
 328
 329                 pra->middle_rssi_threshold_ratr =
 330                                 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);
 331
 332                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
 333                         pra->low_rssi_threshold_ratr =
 334                                 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);
 335                 } else {
 336                         pra->low_rssi_threshold_ratr =
 337                         (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);
 338                 }
 339                 /* cosa add for test */
 340                 pra->ping_rssi_ratr =
 341                                 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0);
 342
 343                 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
 344                    time to link with AP. We will not change upper/lower threshold. If
 345                    STA stay in high or low level, we must change two different threshold
 346                    to prevent jumping frequently. */
 347                 if (pra->ratr_state == DM_RATR_STA_HIGH) {
 348                         HighRSSIThreshForRA     = pra->high2low_rssi_thresh_for_ra;
 349                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 350                                         (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
 351                 } else if (pra->ratr_state == DM_RATR_STA_LOW) {
 352                         HighRSSIThreshForRA     = pra->high_rssi_thresh_for_ra;
 353                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 354                                         (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
 355                 } else {
 356                         HighRSSIThreshForRA     = pra->high_rssi_thresh_for_ra;
 357                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 358                                         (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
 359                 }
 360
 361                 /*DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);*/
 362                 if (priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) {
 363                         /*DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);*/
 364                         pra->ratr_state = DM_RATR_STA_HIGH;
 365                         targetRATR = pra->upper_rssi_threshold_ratr;
 366                 } else if (priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) {
 367                         /*DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);*/
 368                         pra->ratr_state = DM_RATR_STA_MIDDLE;
 369                         targetRATR = pra->middle_rssi_threshold_ratr;
 370                 } else {
 371                         /*DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);*/
 372                         pra->ratr_state = DM_RATR_STA_LOW;
 373                         targetRATR = pra->low_rssi_threshold_ratr;
 374                 }
 375
 376                 /* cosa add for test */
 377                 if (pra->ping_rssi_enable) {
 378                         /*pHalData->UndecoratedSmoothedPWDB = 19;*/
 379                         if (priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) {
 380                                 if ((priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
 381                                         ping_rssi_state) {
 382                                         /*DbgPrint("TestRSSI = %d, set RATR to 0x%x\n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);*/
 383                                         pra->ratr_state = DM_RATR_STA_LOW;
 384                                         targetRATR = pra->ping_rssi_ratr;
 385                                         ping_rssi_state = 1;
 386                                 }
 387                                 /*else
 388                                         DbgPrint("TestRSSI is between the range.\n");*/
 389                         } else {
 390                                 /*DbgPrint("TestRSSI Recover to 0x%x\n", targetRATR);*/
 391                                 ping_rssi_state = 0;
 392                         }
 393                 }
 394
 395                 /*
 396                  * 2008.04.01
 397                  * For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
 398                  */
 399                 if (priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
 400                         targetRATR &= 0xf00fffff;
 401
 402                 /* Check whether updating of RATR0 is required */
 403                 read_nic_dword(dev, RATR0, &currentRATR);
 404                 if (targetRATR !=  currentRATR) {
 405                         u32 ratr_value;
 406
 407                         ratr_value = targetRATR;
 408                         RT_TRACE(COMP_RATE, "currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
 409                         if (priv->rf_type == RF_1T2R)
 410                                 ratr_value &= ~(RATE_ALL_OFDM_2SS);
 411                         write_nic_dword(dev, RATR0, ratr_value);
 412                         write_nic_byte(dev, UFWP, 1);
 413
 414                         pra->last_ratr = targetRATR;
 415                 }
 416
 417         } else {
 418                 pra->ratr_state = DM_RATR_STA_MAX;
 419         }
 420
 421 }       /* dm_CheckRateAdaptive */
 422
 423 static void dm_init_bandwidth_autoswitch(struct net_device *dev)
 424 {
 425         struct r8192_priv *priv = ieee80211_priv(dev);
 426
 427         priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
 428         priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
 429         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
 430         priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
 431
 432 }       /* dm_init_bandwidth_autoswitch */
 433
 434 static void dm_bandwidth_autoswitch(struct net_device *dev)
 435 {
 436         struct r8192_priv *priv = ieee80211_priv(dev);
 437
 438         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 || !priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable)
 439                 return;
 440         if (priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false) { /* If send packets in 40 Mhz in 20/40 */
 441                 if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
 442                         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
 443         } else { /* in force send packets in 20 Mhz in 20/40 */
 444                 if (priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
 445                         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
 446         }
 447 }       /* dm_BandwidthAutoSwitch */
 448
 449 /* OFDM default at 0db, index=6. */
 450 static u32 OFDMSwingTable[OFDM_Table_Length] = {
 451         0x7f8001fe,     /* 0, +6db */
 452         0x71c001c7,     /* 1, +5db */
 453         0x65400195,     /* 2, +4db */
 454         0x5a400169,     /* 3, +3db */
 455         0x50800142,     /* 4, +2db */
 456         0x47c0011f,     /* 5, +1db */
 457         0x40000100,     /* 6, +0db ===> default, upper for higher temperature, lower for low temperature */
 458         0x390000e4,     /* 7, -1db */
 459         0x32c000cb,     /* 8, -2db */
 460         0x2d4000b5,     /* 9, -3db */
 461         0x288000a2,     /* 10, -4db */
 462         0x24000090,     /* 11, -5db */
 463         0x20000080,     /* 12, -6db */
 464         0x1c800072,     /* 13, -7db */
 465         0x19800066,     /* 14, -8db */
 466         0x26c0005b,     /* 15, -9db */
 467         0x24400051,     /* 16, -10db */
 468         0x12000048,     /* 17, -11db */
 469         0x10000040      /* 18, -12db */
 470 };
 471
 472 static u8       CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
 473         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},       /* 0, +0db ===> CCK40M default */
 474         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       /* 1, -1db */
 475         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       /* 2, -2db */
 476         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       /* 3, -3db */
 477         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       /* 4, -4db */
 478         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       /* 5, -5db */
 479         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},       /* 6, -6db ===> CCK20M default */
 480         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       /* 7, -7db */
 481         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       /* 8, -8db */
 482         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       /* 9, -9db */
 483         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       /* 10, -10db */
 484         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}        /* 11, -11db */
 485 };
 486
 487 static u8       CCKSwingTable_Ch14[CCK_Table_length][8] = {
 488         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},       /* 0, +0db  ===> CCK40M default */
 489         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       /* 1, -1db */
 490         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       /* 2, -2db */
 491         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       /* 3, -3db */
 492         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       /* 4, -4db */
 493         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       /* 5, -5db */
 494         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       /* 6, -6db  ===> CCK20M default */
 495         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       /* 7, -7db */
 496         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       /* 8, -8db */
 497         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       /* 9, -9db */
 498         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       /* 10, -10db */
 499         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}        /* 11, -11db */
 500 };
 501
 502 static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
 503 {
 504         struct r8192_priv *priv = ieee80211_priv(dev);
 505         bool                                            bHighpowerstate, viviflag = FALSE;
 506         DCMD_TXCMD_T                    tx_cmd;
 507         u8                                              powerlevelOFDM24G;
 508         int                                             i = 0, j = 0, k = 0;
 509         u8                                              RF_Type, tmp_report[5] = {0, 0, 0, 0, 0};
 510         u32                                             Value;
 511         u8                                              Pwr_Flag;
 512         u16                                             Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0;
 513         /*RT_STATUS                             rtStatus = RT_STATUS_SUCCESS;*/
 514         bool rtStatus = true;
 515         u32                                             delta = 0;
 516
 517         write_nic_byte(dev, 0x1ba, 0);
 518
 519         priv->ieee80211->bdynamic_txpower_enable = false;
 520         bHighpowerstate = priv->bDynamicTxHighPower;
 521
 522         powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
 523         RF_Type = priv->rf_type;
 524         Value = (RF_Type<<8) | powerlevelOFDM24G;
 525
 526         RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
 527
 528         for (j = 0; j <= 30; j++) { /* fill tx_cmd */
 529                 tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING;
 530                 tx_cmd.Length = 4;
 531                 tx_cmd.Value = Value;
 532                 rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
 533                 if (rtStatus == RT_STATUS_FAILURE)
 534                         RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
 535                 mdelay(1);
 536                 /*DbgPrint("hi, vivi, strange\n");*/
 537                 for (i = 0; i <= 30; i++) {
 538                         read_nic_byte(dev, 0x1ba, &Pwr_Flag);
 539
 540                         if (Pwr_Flag == 0) {
 541                                 mdelay(1);
 542                                 continue;
 543                         }
 544                         read_nic_word(dev, 0x13c, &Avg_TSSI_Meas);
 545                         if (Avg_TSSI_Meas == 0) {
 546                                 write_nic_byte(dev, 0x1ba, 0);
 547                                 break;
 548                         }
 549
 550                         for (k = 0; k < 5; k++) {
 551                                 if (k != 4)
 552                                         read_nic_byte(dev, 0x134+k, &tmp_report[k]);
 553                                 else
 554                                         read_nic_byte(dev, 0x13e, &tmp_report[k]);
 555                                 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
 556                         }
 557
 558                         /* check if the report value is right */
 559                         for (k = 0; k < 5; k++) {
 560                                 if (tmp_report[k] <= 20) {
 561                                         viviflag = TRUE;
 562                                         break;
 563                                 }
 564                         }
 565                         if (viviflag == TRUE) {
 566                                 write_nic_byte(dev, 0x1ba, 0);
 567                                 viviflag = FALSE;
 568                                 RT_TRACE(COMP_POWER_TRACKING, "we filtered the data\n");
 569                                 for (k = 0; k < 5; k++)
 570                                         tmp_report[k] = 0;
 571                                 break;
 572                         }
 573
 574                         for (k = 0; k < 5; k++)
 575                                 Avg_TSSI_Meas_from_driver += tmp_report[k];
 576
 577                         Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
 578                         RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
 579                         TSSI_13dBm = priv->TSSI_13dBm;
 580                         RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
 581
 582                         /*if (abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)*/
 583                         /* For MacOS-compatible */
 584                         if (Avg_TSSI_Meas_from_driver > TSSI_13dBm)
 585                                 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
 586                         else
 587                                 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
 588
 589                         if (delta <= E_FOR_TX_POWER_TRACK) {
 590                                 priv->ieee80211->bdynamic_txpower_enable = TRUE;
 591                                 write_nic_byte(dev, 0x1ba, 0);
 592                                 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
 593                                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
 594                                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
 595                                 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d\n", priv->cck_present_attentuation_difference);
 596                                 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d\n", priv->cck_present_attentuation);
 597                                 return;
 598                         }
 599                         if (Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) {
 600                                 if (priv->rfa_txpowertrackingindex > 0) {
 601                                         priv->rfa_txpowertrackingindex--;
 602                                         if (priv->rfa_txpowertrackingindex_real > 4) {
 603                                                 priv->rfa_txpowertrackingindex_real--;
 604                                                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
 605                                         }
 606                                 }
 607                         } else {
 608                                 if (priv->rfa_txpowertrackingindex < 36) {
 609                                         priv->rfa_txpowertrackingindex++;
 610                                         priv->rfa_txpowertrackingindex_real++;
 611                                         rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
 612
 613                                 }
 614                         }
 615                         priv->cck_present_attentuation_difference
 616                                 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
 617
 618                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 619                                 priv->cck_present_attentuation
 620                                         = priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference;
 621                         else
 622                                 priv->cck_present_attentuation
 623                                         = priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference;
 624
 625                         if (priv->cck_present_attentuation > -1 && priv->cck_present_attentuation < 23) {
 626                                 if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) {
 627                                         priv->bcck_in_ch14 = TRUE;
 628                                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 629                                 } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) {
 630                                         priv->bcck_in_ch14 = FALSE;
 631                                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 632                                 } else
 633                                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 634                         }
 635                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
 636                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
 637                         RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d\n", priv->cck_present_attentuation_difference);
 638                         RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d\n", priv->cck_present_attentuation);
 639
 640                         if (priv->cck_present_attentuation_difference <= -12 || priv->cck_present_attentuation_difference >= 24) {
 641                                 priv->ieee80211->bdynamic_txpower_enable = TRUE;
 642                                 write_nic_byte(dev, 0x1ba, 0);
 643                                 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
 644                                 return;
 645                         }
 646
 647                         write_nic_byte(dev, 0x1ba, 0);
 648                         Avg_TSSI_Meas_from_driver = 0;
 649                         for (k = 0; k < 5; k++)
 650                                 tmp_report[k] = 0;
 651                         break;
 652                 }
 653         }
 654         priv->ieee80211->bdynamic_txpower_enable = TRUE;
 655         write_nic_byte(dev, 0x1ba, 0);
 656 }
 657
 658 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev)
 659 {
 660 #define ThermalMeterVal 9
 661         struct r8192_priv *priv = ieee80211_priv(dev);
 662         u32 tmpRegA, TempCCk;
 663         u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
 664         int i = 0, CCKSwingNeedUpdate = 0;
 665
 666         if (!priv->btxpower_trackingInit) {
 667                 /* Query OFDM default setting */
 668                 tmpRegA = rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
 669                 for (i = 0; i < OFDM_Table_Length; i++) { /* find the index */
 670                         if (tmpRegA == OFDMSwingTable[i]) {
 671                                 priv->OFDM_index = (u8)i;
 672                                 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
 673                                         rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
 674                         }
 675                 }
 676
 677                 /* Query CCK default setting From 0xa22 */
 678                 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
 679                 for (i = 0; i < CCK_Table_length; i++) {
 680                         if (TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) {
 681                                 priv->CCK_index = (u8) i;
 682                                 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
 683                                         rCCK0_TxFilter1, TempCCk, priv->CCK_index);
 684                                 break;
 685                         }
 686                 }
 687                 priv->btxpower_trackingInit = TRUE;
 688                 /*pHalData->TXPowercount = 0;*/
 689                 return;
 690         }
 691
 692         /*
 693          * ==========================
 694          * this is only for test, should be masked
 695          * ==========================
 696          */
 697
 698         /* read and filter out unreasonable value */
 699         tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078);        /* 0x12: RF Reg[10:7] */
 700         RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d\n", tmpRegA);
 701         if (tmpRegA < 3 || tmpRegA > 13)
 702                 return;
 703         if (tmpRegA >= 12)      /* if over 12, TP will be bad when high temperature */
 704                 tmpRegA = 12;
 705         RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d\n", tmpRegA);
 706         priv->ThermalMeter[0] = ThermalMeterVal;        /* We use fixed value by Bryant's suggestion */
 707         priv->ThermalMeter[1] = ThermalMeterVal;        /* We use fixed value by Bryant's suggestion */
 708
 709         /* Get current RF-A temperature index */
 710         if (priv->ThermalMeter[0] >= (u8)tmpRegA) {     /* lower temperature */
 711                 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
 712                 tmpCCK40Mindex = tmpCCK20Mindex - 6;
 713                 if (tmpOFDMindex >= OFDM_Table_Length)
 714                         tmpOFDMindex = OFDM_Table_Length-1;
 715                 if (tmpCCK20Mindex >= CCK_Table_length)
 716                         tmpCCK20Mindex = CCK_Table_length-1;
 717                 if (tmpCCK40Mindex >= CCK_Table_length)
 718                         tmpCCK40Mindex = CCK_Table_length-1;
 719         } else {
 720                 tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]);
 721
 722                 if (tmpval >= 6) /* higher temperature */
 723                         tmpOFDMindex = tmpCCK20Mindex = 0; /* max to +6dB */
 724                 else
 725                         tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval;
 726                 tmpCCK40Mindex = 0;
 727         }
 728         /*DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
 729                 ((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
 730                 tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);*/
 731         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)      /* 40M */
 732                 tmpCCKindex = tmpCCK40Mindex;
 733         else
 734                 tmpCCKindex = tmpCCK20Mindex;
 735
 736         if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) {
 737                 priv->bcck_in_ch14 = TRUE;
 738                 CCKSwingNeedUpdate = 1;
 739         } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) {
 740                 priv->bcck_in_ch14 = FALSE;
 741                 CCKSwingNeedUpdate = 1;
 742         }
 743
 744         if (priv->CCK_index != tmpCCKindex) {
 745                 priv->CCK_index = tmpCCKindex;
 746                 CCKSwingNeedUpdate = 1;
 747         }
 748
 749         if (CCKSwingNeedUpdate) {
 750                 /*DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);*/
 751                 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 752         }
 753         if (priv->OFDM_index != tmpOFDMindex) {
 754                 priv->OFDM_index = tmpOFDMindex;
 755                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
 756                 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
 757                         priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
 758         }
 759         priv->txpower_count = 0;
 760 }
 761
 762 void dm_txpower_trackingcallback(struct work_struct *work)
 763 {
 764         struct delayed_work *dwork = container_of(work, struct delayed_work, work);
 765         struct r8192_priv *priv = container_of(dwork, struct r8192_priv, txpower_tracking_wq);
 766         struct net_device *dev = priv->ieee80211->dev;
 767
 768         if (priv->bDcut == TRUE)
 769                 dm_TXPowerTrackingCallback_TSSI(dev);
 770         else
 771                 dm_TXPowerTrackingCallback_ThermalMeter(dev);
 772 }
 773
 774 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
 775 {
 776         struct r8192_priv *priv = ieee80211_priv(dev);
 777
 778         /* Initial the Tx BB index and mapping value */
 779         priv->txbbgain_table[0].txbb_iq_amplifygain =                   12;
 780         priv->txbbgain_table[0].txbbgain_value = 0x7f8001fe;
 781         priv->txbbgain_table[1].txbb_iq_amplifygain =                   11;
 782         priv->txbbgain_table[1].txbbgain_value = 0x788001e2;
 783         priv->txbbgain_table[2].txbb_iq_amplifygain =                   10;
 784         priv->txbbgain_table[2].txbbgain_value = 0x71c001c7;
 785         priv->txbbgain_table[3].txbb_iq_amplifygain =                   9;
 786         priv->txbbgain_table[3].txbbgain_value = 0x6b8001ae;
 787         priv->txbbgain_table[4].txbb_iq_amplifygain =                  8;
 788         priv->txbbgain_table[4].txbbgain_value = 0x65400195;
 789         priv->txbbgain_table[5].txbb_iq_amplifygain =                  7;
 790         priv->txbbgain_table[5].txbbgain_value = 0x5fc0017f;
 791         priv->txbbgain_table[6].txbb_iq_amplifygain =                  6;
 792         priv->txbbgain_table[6].txbbgain_value = 0x5a400169;
 793         priv->txbbgain_table[7].txbb_iq_amplifygain =                  5;
 794         priv->txbbgain_table[7].txbbgain_value = 0x55400155;
 795         priv->txbbgain_table[8].txbb_iq_amplifygain =                  4;
 796         priv->txbbgain_table[8].txbbgain_value = 0x50800142;
 797         priv->txbbgain_table[9].txbb_iq_amplifygain =                  3;
 798         priv->txbbgain_table[9].txbbgain_value = 0x4c000130;
 799         priv->txbbgain_table[10].txbb_iq_amplifygain =                 2;
 800         priv->txbbgain_table[10].txbbgain_value = 0x47c0011f;
 801         priv->txbbgain_table[11].txbb_iq_amplifygain =                 1;
 802         priv->txbbgain_table[11].txbbgain_value = 0x43c0010f;
 803         priv->txbbgain_table[12].txbb_iq_amplifygain =                 0;
 804         priv->txbbgain_table[12].txbbgain_value = 0x40000100;
 805         priv->txbbgain_table[13].txbb_iq_amplifygain =                 -1;
 806         priv->txbbgain_table[13].txbbgain_value = 0x3c8000f2;
 807         priv->txbbgain_table[14].txbb_iq_amplifygain =               -2;
 808         priv->txbbgain_table[14].txbbgain_value = 0x390000e4;
 809         priv->txbbgain_table[15].txbb_iq_amplifygain =               -3;
 810         priv->txbbgain_table[15].txbbgain_value = 0x35c000d7;
 811         priv->txbbgain_table[16].txbb_iq_amplifygain =               -4;
 812         priv->txbbgain_table[16].txbbgain_value = 0x32c000cb;
 813         priv->txbbgain_table[17].txbb_iq_amplifygain =               -5;
 814         priv->txbbgain_table[17].txbbgain_value = 0x300000c0;
 815         priv->txbbgain_table[18].txbb_iq_amplifygain =                      -6;
 816         priv->txbbgain_table[18].txbbgain_value = 0x2d4000b5;
 817         priv->txbbgain_table[19].txbb_iq_amplifygain =               -7;
 818         priv->txbbgain_table[19].txbbgain_value = 0x2ac000ab;
 819         priv->txbbgain_table[20].txbb_iq_amplifygain =               -8;
 820         priv->txbbgain_table[20].txbbgain_value = 0x288000a2;
 821         priv->txbbgain_table[21].txbb_iq_amplifygain =               -9;
 822         priv->txbbgain_table[21].txbbgain_value = 0x26000098;
 823         priv->txbbgain_table[22].txbb_iq_amplifygain =               -10;
 824         priv->txbbgain_table[22].txbbgain_value = 0x24000090;
 825         priv->txbbgain_table[23].txbb_iq_amplifygain =               -11;
 826         priv->txbbgain_table[23].txbbgain_value = 0x22000088;
 827         priv->txbbgain_table[24].txbb_iq_amplifygain =               -12;
 828         priv->txbbgain_table[24].txbbgain_value = 0x20000080;
 829         priv->txbbgain_table[25].txbb_iq_amplifygain =               -13;
 830         priv->txbbgain_table[25].txbbgain_value = 0x1a00006c;
 831         priv->txbbgain_table[26].txbb_iq_amplifygain =               -14;
 832         priv->txbbgain_table[26].txbbgain_value = 0x1c800072;
 833         priv->txbbgain_table[27].txbb_iq_amplifygain =               -15;
 834         priv->txbbgain_table[27].txbbgain_value = 0x18000060;
 835         priv->txbbgain_table[28].txbb_iq_amplifygain =               -16;
 836         priv->txbbgain_table[28].txbbgain_value = 0x19800066;
 837         priv->txbbgain_table[29].txbb_iq_amplifygain =               -17;
 838         priv->txbbgain_table[29].txbbgain_value = 0x15800056;
 839         priv->txbbgain_table[30].txbb_iq_amplifygain =               -18;
 840         priv->txbbgain_table[30].txbbgain_value = 0x26c0005b;
 841         priv->txbbgain_table[31].txbb_iq_amplifygain =               -19;
 842         priv->txbbgain_table[31].txbbgain_value = 0x14400051;
 843         priv->txbbgain_table[32].txbb_iq_amplifygain =               -20;
 844         priv->txbbgain_table[32].txbbgain_value = 0x24400051;
 845         priv->txbbgain_table[33].txbb_iq_amplifygain =               -21;
 846         priv->txbbgain_table[33].txbbgain_value = 0x1300004c;
 847         priv->txbbgain_table[34].txbb_iq_amplifygain =               -22;
 848         priv->txbbgain_table[34].txbbgain_value = 0x12000048;
 849         priv->txbbgain_table[35].txbb_iq_amplifygain =               -23;
 850         priv->txbbgain_table[35].txbbgain_value = 0x11000044;
 851         priv->txbbgain_table[36].txbb_iq_amplifygain =               -24;
 852         priv->txbbgain_table[36].txbbgain_value = 0x10000040;
 853
 854         /*
 855          * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
 856          * This Table is for CH1~CH13
 857          */
 858         priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36;
 859         priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35;
 860         priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e;
 861         priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25;
 862         priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c;
 863         priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12;
 864         priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09;
 865         priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04;
 866
 867         priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33;
 868         priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32;
 869         priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b;
 870         priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23;
 871         priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a;
 872         priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11;
 873         priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08;
 874         priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04;
 875
 876         priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30;
 877         priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f;
 878         priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29;
 879         priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21;
 880         priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19;
 881         priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10;
 882         priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08;
 883         priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03;
 884
 885         priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d;
 886         priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d;
 887         priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27;
 888         priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f;
 889         priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18;
 890         priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f;
 891         priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08;
 892         priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03;
 893
 894         priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b;
 895         priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a;
 896         priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25;
 897         priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e;
 898         priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16;
 899         priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e;
 900         priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07;
 901         priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03;
 902
 903         priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28;
 904         priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28;
 905         priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22;
 906         priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c;
 907         priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15;
 908         priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d;
 909         priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07;
 910         priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03;
 911
 912         priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26;
 913         priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25;
 914         priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21;
 915         priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b;
 916         priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14;
 917         priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d;
 918         priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06;
 919         priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03;
 920
 921         priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24;
 922         priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23;
 923         priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f;
 924         priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19;
 925         priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13;
 926         priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c;
 927         priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06;
 928         priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03;
 929
 930         priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22;
 931         priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21;
 932         priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d;
 933         priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18;
 934         priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11;
 935         priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b;
 936         priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06;
 937         priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02;
 938
 939         priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20;
 940         priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20;
 941         priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b;
 942         priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16;
 943         priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11;
 944         priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08;
 945         priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05;
 946         priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02;
 947
 948         priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f;
 949         priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e;
 950         priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a;
 951         priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15;
 952         priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10;
 953         priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a;
 954         priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05;
 955         priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02;
 956
 957         priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d;
 958         priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c;
 959         priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18;
 960         priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14;
 961         priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f;
 962         priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a;
 963         priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05;
 964         priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02;
 965
 966         priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b;
 967         priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a;
 968         priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17;
 969         priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13;
 970         priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e;
 971         priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09;
 972         priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04;
 973         priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02;
 974
 975         priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a;
 976         priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19;
 977         priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16;
 978         priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12;
 979         priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d;
 980         priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09;
 981         priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04;
 982         priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02;
 983
 984         priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18;
 985         priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17;
 986         priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15;
 987         priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11;
 988         priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c;
 989         priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08;
 990         priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04;
 991         priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02;
 992
 993         priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17;
 994         priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16;
 995         priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13;
 996         priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10;
 997         priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c;
 998         priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08;
 999         priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04;
1000         priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02;
1001
1002         priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16;
1003         priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15;
1004         priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12;
1005         priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f;
1006         priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b;
1007         priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07;
1008         priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04;
1009         priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01;
1010
1011         priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14;
1012         priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14;
1013         priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11;
1014         priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e;
1015         priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b;
1016         priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07;
1017         priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03;
1018         priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02;
1019
1020         priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13;
1021         priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13;
1022         priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10;
1023         priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d;
1024         priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a;
1025         priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06;
1026         priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03;
1027         priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01;
1028
1029         priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12;
1030         priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12;
1031         priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f;
1032         priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c;
1033         priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09;
1034         priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06;
1035         priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03;
1036         priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01;
1037
1038         priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11;
1039         priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11;
1040         priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f;
1041         priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c;
1042         priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09;
1043         priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06;
1044         priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03;
1045         priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01;
1046
1047         priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10;
1048         priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10;
1049         priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e;
1050         priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b;
1051         priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08;
1052         priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05;
1053         priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03;
1054         priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01;
1055
1056         priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f;
1057         priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f;
1058         priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d;
1059         priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b;
1060         priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08;
1061         priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05;
1062         priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03;
1063         priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01;
1064
1065         /*
1066          * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1067          * This Table is for CH14
1068          */
1069         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36;
1070         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35;
1071         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e;
1072         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b;
1073         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00;
1074         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00;
1075         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00;
1076         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00;
1077
1078         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33;
1079         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32;
1080         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b;
1081         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19;
1082         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00;
1083         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00;
1084         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00;
1085         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00;
1086
1087         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30;
1088         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f;
1089         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29;
1090         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18;
1091         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00;
1092         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00;
1093         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00;
1094         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00;
1095
1096         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d;
1097         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d;
1098         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27;
1099         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17;
1100         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00;
1101         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00;
1102         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00;
1103         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00;
1104
1105         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b;
1106         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a;
1107         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25;
1108         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15;
1109         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00;
1110         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00;
1111         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00;
1112         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00;
1113
1114         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28;
1115         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28;
1116         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22;
1117         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14;
1118         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00;
1119         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00;
1120         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00;
1121         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00;
1122
1123         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26;
1124         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25;
1125         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21;
1126         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13;
1127         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00;
1128         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00;
1129         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00;
1130         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00;
1131
1132         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24;
1133         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23;
1134         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f;
1135         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12;
1136         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00;
1137         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00;
1138         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00;
1139         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00;
1140
1141         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22;
1142         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21;
1143         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d;
1144         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11;
1145         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00;
1146         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00;
1147         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00;
1148         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00;
1149
1150         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20;
1151         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20;
1152         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b;
1153         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10;
1154         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00;
1155         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00;
1156         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00;
1157         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00;
1158
1159         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f;
1160         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e;
1161         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a;
1162         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f;
1163         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00;
1164         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00;
1165         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00;
1166         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00;
1167
1168         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d;
1169         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c;
1170         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18;
1171         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e;
1172         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00;
1173         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00;
1174         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00;
1175         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00;
1176
1177         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b;
1178         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a;
1179         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17;
1180         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e;
1181         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00;
1182         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00;
1183         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00;
1184         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00;
1185
1186         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a;
1187         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19;
1188         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16;
1189         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d;
1190         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00;
1191         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00;
1192         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00;
1193         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00;
1194
1195         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18;
1196         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17;
1197         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15;
1198         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c;
1199         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00;
1200         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00;
1201         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00;
1202         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00;
1203
1204         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17;
1205         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16;
1206         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13;
1207         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b;
1208         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00;
1209         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00;
1210         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00;
1211         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00;
1212
1213         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16;
1214         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15;
1215         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12;
1216         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b;
1217         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00;
1218         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00;
1219         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00;
1220         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00;
1221
1222         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14;
1223         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14;
1224         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11;
1225         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a;
1226         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00;
1227         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00;
1228         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00;
1229         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00;
1230
1231         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13;
1232         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13;
1233         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10;
1234         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a;
1235         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00;
1236         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00;
1237         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00;
1238         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00;
1239
1240         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12;
1241         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12;
1242         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f;
1243         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09;
1244         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00;
1245         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00;
1246         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00;
1247         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00;
1248
1249         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11;
1250         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11;
1251         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f;
1252         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09;
1253         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00;
1254         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00;
1255         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00;
1256         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00;
1257
1258         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10;
1259         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10;
1260         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e;
1261         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08;
1262         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00;
1263         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00;
1264         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00;
1265         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00;
1266
1267         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f;
1268         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f;
1269         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d;
1270         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08;
1271         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00;
1272         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00;
1273         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00;
1274         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00;
1275
1276         priv->btxpower_tracking = TRUE;
1277         priv->txpower_count       = 0;
1278         priv->btxpower_trackingInit = FALSE;
1279
1280 }
1281
1282 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1283 {
1284         struct r8192_priv *priv = ieee80211_priv(dev);
1285
1286         /*
1287          * Tx Power tracking by Thermal Meter requires Firmware R/W 3-wire. This mechanism
1288          * can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1289          * 3-wire by driver causes RF to go into a wrong state.
1290          */
1291         if (priv->ieee80211->FwRWRF)
1292                 priv->btxpower_tracking = TRUE;
1293         else
1294                 priv->btxpower_tracking = FALSE;
1295         priv->txpower_count       = 0;
1296         priv->btxpower_trackingInit = FALSE;
1297 }
1298
1299 void dm_initialize_txpower_tracking(struct net_device *dev)
1300 {
1301         struct r8192_priv *priv = ieee80211_priv(dev);
1302
1303         if (priv->bDcut == TRUE)
1304                 dm_InitializeTXPowerTracking_TSSI(dev);
1305         else
1306                 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1307 } /* dm_InitializeTXPowerTracking */
1308
1309 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1310 {
1311         struct r8192_priv *priv = ieee80211_priv(dev);
1312         static u32 tx_power_track_counter;
1313
1314         if (!priv->btxpower_tracking)
1315                 return;
1316         if ((tx_power_track_counter % 30 == 0) && (tx_power_track_counter != 0))
1317                 queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0);
1318         tx_power_track_counter++;
1319 }
1320
1321 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1322 {
1323         struct r8192_priv *priv = ieee80211_priv(dev);
1324         static u8       TM_Trigger;
1325         /*DbgPrint("dm_CheckTXPowerTracking()\n");*/
1326         if (!priv->btxpower_tracking)
1327                 return;
1328         if (priv->txpower_count  <= 2) {
1329                 priv->txpower_count++;
1330                 return;
1331         }
1332
1333         if (!TM_Trigger) {
1334                 /*
1335                  * Attention!! You have to write all 12bits of data to RF, or it may cause RF to crash
1336                  * actually write reg0x02 bit1=0, then bit1=1.
1337                  * DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1338                  */
1339                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1340                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1341                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1342                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1343                 TM_Trigger = 1;
1344                 return;
1345         }
1346         /*DbgPrint("Schedule TxPowerTrackingWorkItem\n");*/
1347                 queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0);
1348         TM_Trigger = 0;
1349 }
1350
1351 static void dm_check_txpower_tracking(struct net_device *dev)
1352 {
1353         struct r8192_priv *priv = ieee80211_priv(dev);
1354         /*static u32 tx_power_track_counter = 0;*/
1355
1356 #ifdef RTL8190P
1357         dm_CheckTXPowerTracking_TSSI(dev);
1358 #else
1359         if (priv->bDcut == TRUE)
1360                 dm_CheckTXPowerTracking_TSSI(dev);
1361         else
1362                 dm_CheckTXPowerTracking_ThermalMeter(dev);
1363 #endif
1364
1365 }       /* dm_CheckTXPowerTracking */
1366
1367 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool  bInCH14)
1368 {
1369         u32 TempVal;
1370         struct r8192_priv *priv = ieee80211_priv(dev);
1371
1372         /* Write 0xa22 0xa23 */
1373         TempVal = 0;
1374         if (!bInCH14) {
1375                 /* Write 0xa22 0xa23 */
1376                 TempVal =       priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] +
1377                                         (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8);
1378
1379                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1380                 /* Write 0xa24 ~ 0xa27 */
1381                 TempVal =       priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] +
1382                                         (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) +
1383                                         (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16)+
1384                                         (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24);
1385                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1386                 /* Write 0xa28  0xa29 */
1387                 TempVal =       priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] +
1388                                         (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8);
1389
1390                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1391         } else {
1392                 TempVal =       priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] +
1393                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8);
1394
1395                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1396                 /* Write 0xa24 ~ 0xa27 */
1397                 TempVal =       priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] +
1398                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) +
1399                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16)+
1400                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24);
1401                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1402                 /* Write 0xa28  0xa29 */
1403                 TempVal =       priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] +
1404                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8);
1405
1406                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1407         }
1408 }
1409
1410 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool  bInCH14)
1411 {
1412         u32 TempVal;
1413         struct r8192_priv *priv = ieee80211_priv(dev);
1414
1415         TempVal = 0;
1416         if (!bInCH14) {
1417                 /* Write 0xa22 0xa23 */
1418                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1419                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8);
1420                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1421                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1422                         rCCK0_TxFilter1, TempVal);
1423                 /* Write 0xa24 ~ 0xa27 */
1424                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1425                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1426                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16)+
1427                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1428                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1429                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1430                         rCCK0_TxFilter2, TempVal);
1431                 /* Write 0xa28  0xa29 */
1432                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1433                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8);
1434
1435                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1436                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1437                         rCCK0_DebugPort, TempVal);
1438         } else {
1439                 /*priv->CCKTxPowerAdjustCntNotCh14++;   cosa add for debug.*/
1440                 /* Write 0xa22 0xa23 */
1441                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][0] +
1442                                         (CCKSwingTable_Ch14[priv->CCK_index][1]<<8);
1443
1444                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1445                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1446                         rCCK0_TxFilter1, TempVal);
1447                 /* Write 0xa24 ~ 0xa27 */
1448                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][2] +
1449                                         (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1450                                         (CCKSwingTable_Ch14[priv->CCK_index][4]<<16)+
1451                                         (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1452                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1453                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1454                         rCCK0_TxFilter2, TempVal);
1455                 /* Write 0xa28  0xa29 */
1456                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][6] +
1457                                         (CCKSwingTable_Ch14[priv->CCK_index][7]<<8);
1458
1459                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1460                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1461                         rCCK0_DebugPort, TempVal);
1462         }
1463 }
1464
1465 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1466 {       /*  dm_CCKTxPowerAdjust */
1467         struct r8192_priv *priv = ieee80211_priv(dev);
1468
1469         if (priv->bDcut == TRUE)
1470                 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1471         else
1472                 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1473 }
1474
1475 #ifndef RTL8192U
1476 static void dm_txpower_reset_recovery(
1477         struct net_device *dev
1478 )
1479 {
1480         struct r8192_priv *priv = ieee80211_priv(dev);
1481
1482         RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1483         rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1484         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1485         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n", priv->rfa_txpowertrackingindex);
1486         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1487         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n", priv->cck_present_attentuation);
1488         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1489
1490         rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1491         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1492         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n", priv->rfc_txpowertrackingindex);
1493         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1494
1495 }       /* dm_TXPowerResetRecovery */
1496
1497 void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1498 {
1499         struct r8192_priv *priv = ieee80211_priv(dev);
1500         u32     reg_ratr = priv->rate_adaptive.last_ratr;
1501
1502         if (!priv->up) {
1503                 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1504                 return;
1505         }
1506
1507         /* Restore previous state for rate adaptive */
1508         if (priv->rate_adaptive.rate_adaptive_disabled)
1509                 return;
1510         /* TODO: Only 11n mode is implemented currently, */
1511         if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
1512                 priv->ieee80211->mode == WIRELESS_MODE_N_5G))
1513                 return;
1514
1515         {
1516                         /* 2007/11/15 MH Copy from 8190PCI. */
1517                         u32 ratr_value;
1518
1519                         ratr_value = reg_ratr;
1520                         if (priv->rf_type == RF_1T2R) { /* 1T2R, Spatial Stream 2 should be disabled */
1521                                 ratr_value &= ~(RATE_ALL_OFDM_2SS);
1522                                 /*DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);*/
1523                         }
1524                         /*DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);*/
1525                         /*cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);*/
1526                         write_nic_dword(dev, RATR0, ratr_value);
1527                         write_nic_byte(dev, UFWP, 1);
1528         }
1529         /* Restore TX Power Tracking Index */
1530         if (priv->btxpower_trackingInit && priv->btxpower_tracking)
1531                 dm_txpower_reset_recovery(dev);
1532
1533         /* Restore BB Initial Gain */
1534         dm_bb_initialgain_restore(dev);
1535
1536 }       /* DM_RestoreDynamicMechanismState */
1537
1538 static void dm_bb_initialgain_restore(struct net_device *dev)
1539 {
1540         struct r8192_priv *priv = ieee80211_priv(dev);
1541         u32 bit_mask = 0x7f; /* Bit0~ Bit6 */
1542
1543         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1544                 return;
1545
1546         /* Disable Initial Gain */
1547         /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/
1548         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /* Only clear byte 1 and rewrite. */
1549         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1550         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1551         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1552         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1553         bit_mask  = bMaskByte2;
1554         rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1555
1556         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n", priv->initgain_backup.xaagccore1);
1557         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n", priv->initgain_backup.xbagccore1);
1558         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n", priv->initgain_backup.xcagccore1);
1559         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n", priv->initgain_backup.xdagccore1);
1560         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n", priv->initgain_backup.cca);
1561         /* Enable Initial Gain */
1562         /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);*/
1563         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   /* Only clear byte 1 and rewrite. */
1564
1565 }       /* dm_BBInitialGainRestore */
1566
1567 void dm_backup_dynamic_mechanism_state(struct net_device *dev)
1568 {
1569         struct r8192_priv *priv = ieee80211_priv(dev);
1570
1571         /* Fsync to avoid reset */
1572         priv->bswitch_fsync  = false;
1573         priv->bfsync_processing = false;
1574         /* Backup BB InitialGain */
1575         dm_bb_initialgain_backup(dev);
1576
1577 }       /* DM_BackupDynamicMechanismState */
1578
1579 static void dm_bb_initialgain_backup(struct net_device *dev)
1580 {
1581         struct r8192_priv *priv = ieee80211_priv(dev);
1582         u32 bit_mask = bMaskByte0; /* Bit0~ Bit6 */
1583
1584         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1585                 return;
1586
1587         /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/
1588         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /* Only clear byte 1 and rewrite. */
1589         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1590         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1591         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1592         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1593         bit_mask  = bMaskByte2;
1594         priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1595
1596         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n", priv->initgain_backup.xaagccore1);
1597         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n", priv->initgain_backup.xbagccore1);
1598         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n", priv->initgain_backup.xcagccore1);
1599         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n", priv->initgain_backup.xdagccore1);
1600         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n", priv->initgain_backup.cca);
1601
1602 }   /* dm_BBInitialGainBakcup */
1603
1604 #endif
1605 /*-----------------------------------------------------------------------------
1606  * Function:    dm_change_dynamic_initgain_thresh()
1607  *
1608  * Overview:
1609  *
1610  * Input:               NONE
1611  *
1612  * Output:              NONE
1613  *
1614  * Return:              NONE
1615  *
1616  * Revised History:
1617  *      When            Who             Remark
1618  *      05/29/2008      amy             Create Version 0 porting from windows code.
1619  *
1620  *---------------------------------------------------------------------------*/
1621
1622 void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type,
1623                                        u32 dm_value)
1624 {
1625         if (dm_type == DIG_TYPE_THRESH_HIGH) {
1626                 dm_digtable.rssi_high_thresh = dm_value;
1627         } else if (dm_type == DIG_TYPE_THRESH_LOW) {
1628                 dm_digtable.rssi_low_thresh = dm_value;
1629         } else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH) {
1630                 dm_digtable.rssi_high_power_highthresh = dm_value;
1631         } else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH) {
1632                 dm_digtable.rssi_high_power_highthresh = dm_value;
1633         } else if (dm_type == DIG_TYPE_ENABLE) {
1634                 dm_digtable.dig_state           = DM_STA_DIG_MAX;
1635                 dm_digtable.dig_enable_flag     = true;
1636         } else if (dm_type == DIG_TYPE_DISABLE) {
1637                 dm_digtable.dig_state           = DM_STA_DIG_MAX;
1638                 dm_digtable.dig_enable_flag     = false;
1639         } else if (dm_type == DIG_TYPE_DBG_MODE) {
1640                 if (dm_value >= DM_DBG_MAX)
1641                         dm_value = DM_DBG_OFF;
1642                 dm_digtable.dbg_mode            = (u8)dm_value;
1643         } else if (dm_type == DIG_TYPE_RSSI) {
1644                 if (dm_value > 100)
1645                         dm_value = 30;
1646                 dm_digtable.rssi_val                    = (long)dm_value;
1647         } else if (dm_type == DIG_TYPE_ALGORITHM) {
1648                 if (dm_value >= DIG_ALGO_MAX)
1649                         dm_value = DIG_ALGO_BY_FALSE_ALARM;
1650                 if (dm_digtable.dig_algorithm != (u8)dm_value)
1651                         dm_digtable.dig_algorithm_switch = 1;
1652                 dm_digtable.dig_algorithm       = (u8)dm_value;
1653         } else if (dm_type == DIG_TYPE_BACKOFF) {
1654                 if (dm_value > 30)
1655                         dm_value = 30;
1656                 dm_digtable.backoff_val         = (u8)dm_value;
1657         } else if (dm_type == DIG_TYPE_RX_GAIN_MIN) {
1658                 if (dm_value == 0)
1659                         dm_value = 0x1;
1660                 dm_digtable.rx_gain_range_min = (u8)dm_value;
1661         } else if (dm_type == DIG_TYPE_RX_GAIN_MAX) {
1662                 if (dm_value > 0x50)
1663                         dm_value = 0x50;
1664                 dm_digtable.rx_gain_range_max = (u8)dm_value;
1665         }
1666 }       /* DM_ChangeDynamicInitGainThresh */
1667
1668 /*-----------------------------------------------------------------------------
1669  * Function:    dm_dig_init()
1670  *
1671  * Overview:    Set DIG scheme init value.
1672  *
1673  * Input:               NONE
1674  *
1675  * Output:              NONE
1676  *
1677  * Return:              NONE
1678  *
1679  * Revised History:
1680  *      When            Who             Remark
1681  *      05/15/2008      amy             Create Version 0 porting from windows code.
1682  *
1683  *---------------------------------------------------------------------------*/
1684 static void dm_dig_init(struct net_device *dev)
1685 {
1686         struct r8192_priv *priv = ieee80211_priv(dev);
1687         /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
1688         dm_digtable.dig_enable_flag     = true;
1689         dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
1690         dm_digtable.dbg_mode = DM_DBG_OFF;      /* off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig */
1691         dm_digtable.dig_algorithm_switch = 0;
1692
1693         /* 2007/10/04 MH Define init gain threshold. */
1694         dm_digtable.dig_state           = DM_STA_DIG_MAX;
1695         dm_digtable.dig_highpwr_state   = DM_STA_DIG_MAX;
1696         dm_digtable.initialgain_lowerbound_state = false;
1697
1698         dm_digtable.rssi_low_thresh     = DM_DIG_THRESH_LOW;
1699         dm_digtable.rssi_high_thresh    = DM_DIG_THRESH_HIGH;
1700
1701         dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
1702         dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
1703
1704         dm_digtable.rssi_val = 50;      /* for new dig debug rssi value */
1705         dm_digtable.backoff_val = DM_DIG_BACKOFF;
1706         dm_digtable.rx_gain_range_max = DM_DIG_MAX;
1707         if (priv->CustomerID == RT_CID_819x_Netcore)
1708                 dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore;
1709         else
1710                 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
1711
1712 }       /* dm_dig_init */
1713
1714 /*-----------------------------------------------------------------------------
1715  * Function:    dm_ctrl_initgain_byrssi()
1716  *
1717  * Overview:    Driver must monitor RSSI and notify firmware to change initial
1718  *                              gain according to different threshold. BB team provide the
1719  *                              suggested solution.
1720  *
1721  * Input:                       struct net_device *dev
1722  *
1723  * Output:              NONE
1724  *
1725  * Return:              NONE
1726  *
1727  * Revised History:
1728  *      When            Who             Remark
1729  *      05/27/2008      amy             Create Version 0 porting from windows code.
1730  *---------------------------------------------------------------------------*/
1731 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
1732 {
1733         if (dm_digtable.dig_enable_flag == false)
1734                 return;
1735
1736         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1737                 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
1738         else if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1739                 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
1740         /* ; */
1741         else
1742                 return;
1743 }
1744
1745 static void dm_ctrl_initgain_byrssi_by_driverrssi(
1746         struct net_device *dev)
1747 {
1748         struct r8192_priv *priv = ieee80211_priv(dev);
1749         u8 i;
1750         static u8       fw_dig;
1751
1752         if (dm_digtable.dig_enable_flag == false)
1753                 return;
1754
1755         /*DbgPrint("Dig by Sw Rssi\n");*/
1756         if (dm_digtable.dig_algorithm_switch)   /* if switched algorithm, we have to disable FW Dig. */
1757                 fw_dig = 0;
1758
1759         if (fw_dig <= 3) { /* execute several times to make sure the FW Dig is disabled */
1760                 /* FW DIG Off */
1761                 for (i = 0; i < 3; i++)
1762                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /* Only clear byte 1 and rewrite. */
1763                 fw_dig++;
1764                 dm_digtable.dig_state = DM_STA_DIG_OFF; /* fw dig off. */
1765         }
1766
1767         if (priv->ieee80211->state == IEEE80211_LINKED)
1768                 dm_digtable.cur_connect_state = DIG_CONNECT;
1769         else
1770                 dm_digtable.cur_connect_state = DIG_DISCONNECT;
1771
1772         /*DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d\n",
1773                 DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);*/
1774
1775         if (dm_digtable.dbg_mode == DM_DBG_OFF)
1776                 dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
1777         /*DbgPrint("DM_DigTable.Rssi_val = %d\n", DM_DigTable.Rssi_val);*/
1778         dm_initial_gain(dev);
1779         dm_pd_th(dev);
1780         dm_cs_ratio(dev);
1781         if (dm_digtable.dig_algorithm_switch)
1782                 dm_digtable.dig_algorithm_switch = 0;
1783         dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
1784
1785 }       /* dm_CtrlInitGainByRssi */
1786
1787 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1788         struct net_device *dev)
1789 {
1790         struct r8192_priv *priv = ieee80211_priv(dev);
1791         static u32 reset_cnt;
1792         u8 i;
1793
1794         if (dm_digtable.dig_enable_flag == false)
1795                 return;
1796
1797         if (dm_digtable.dig_algorithm_switch) {
1798                 dm_digtable.dig_state = DM_STA_DIG_MAX;
1799                 /* Fw DIG On. */
1800                 for (i = 0; i < 3; i++)
1801                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   /* Only clear byte 1 and rewrite.*/
1802                 dm_digtable.dig_algorithm_switch = 0;
1803         }
1804
1805         if (priv->ieee80211->state != IEEE80211_LINKED)
1806                 return;
1807
1808         /* For smooth, we can not change DIG state. */
1809         if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
1810                 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
1811                 return;
1812
1813         /*DbgPrint("Dig by Fw False Alarm\n");*/
1814         /*if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)*/
1815         /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
1816         pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
1817         DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
1818         /* 1. When RSSI decrease, We have to judge if it is smaller than a threshold
1819                   and then execute the step below. */
1820         if (priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh) {
1821                 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
1822                    will be reset to init value. We must prevent the condition. */
1823                 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
1824                     (priv->reset_count == reset_cnt)) {
1825                         return;
1826                 }
1827                 reset_cnt = priv->reset_count;
1828
1829                 /* If DIG is off, DIG high power state must reset. */
1830                 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1831                 dm_digtable.dig_state = DM_STA_DIG_OFF;
1832
1833                 /*  1.1 DIG Off. */
1834                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /*  Only clear byte 1 and rewrite. */
1835
1836                 /*  1.2 Set initial gain. */
1837                 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
1838                 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
1839                 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
1840                 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
1841
1842                 /*  1.3 Lower PD_TH for OFDM. */
1843                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1844                         /*
1845                          * 2008/01/11 MH 40MHZ 90/92 register are not the same.
1846                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1847                          */
1848                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
1849                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1850                                 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1851                         else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1852                         else
1853                                 PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1854                         */
1855                 } else
1856                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1857
1858                 /* 1.4 Lower CS ratio for CCK. */
1859                 write_nic_byte(dev, 0xa0a, 0x08);
1860
1861                 /* 1.5 Higher EDCCA. */
1862                 /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);*/
1863                 return;
1864
1865         }
1866
1867         /* 2. When RSSI increase, We have to judge if it is larger than a threshold
1868                   and then execute the step below.  */
1869         if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) {
1870                 u8 reset_flag = 0;
1871
1872                 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
1873                         (priv->reset_count == reset_cnt)) {
1874                         dm_ctrl_initgain_byrssi_highpwr(dev);
1875                         return;
1876                 }
1877                 if (priv->reset_count != reset_cnt)
1878                         reset_flag = 1;
1879
1880                 reset_cnt = priv->reset_count;
1881
1882                 dm_digtable.dig_state = DM_STA_DIG_ON;
1883                 /*DbgPrint("DIG ON\n\r");*/
1884
1885                 /*
1886                  * 2.1 Set initial gain.
1887                  * 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
1888                  */
1889                 if (reset_flag == 1) {
1890                         write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
1891                         write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
1892                         write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
1893                         write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
1894                 } else {
1895                         write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
1896                         write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
1897                         write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
1898                         write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
1899                 }
1900
1901                 /* 2.2 Higher PD_TH for OFDM. */
1902                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1903                         /*
1904                          * 2008/01/11 MH 40MHZ 90/92 register are not the same.
1905                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1906                          */
1907                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1908                         /*
1909                         else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1910                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1911                         else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1912                         else
1913                                 PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
1914                         */
1915                 } else
1916                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1917
1918                 /* 2.3 Higher CS ratio for CCK. */
1919                 write_nic_byte(dev, 0xa0a, 0xcd);
1920
1921                 /*
1922                  * 2.4 Lower EDCCA.
1923                  * 2008/01/11 MH 90/92 series are the same.
1924                  */
1925                 /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);*/
1926
1927                 /* 2.5 DIG On. */
1928                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   /*  Only clear byte 1 and rewrite. */
1929
1930         }
1931
1932         dm_ctrl_initgain_byrssi_highpwr(dev);
1933
1934 }       /* dm_CtrlInitGainByRssi */
1935
1936 /*-----------------------------------------------------------------------------
1937  * Function:    dm_ctrl_initgain_byrssi_highpwr()
1938  *
1939  * Overview:
1940  *
1941  * Input:               NONE
1942  *
1943  * Output:              NONE
1944  *
1945  * Return:              NONE
1946  *
1947  * Revised History:
1948  *      When            Who             Remark
1949  *      05/28/2008      amy             Create Version 0 porting from windows code.
1950  *
1951  *---------------------------------------------------------------------------*/
1952 static void dm_ctrl_initgain_byrssi_highpwr(
1953         struct net_device *dev)
1954 {
1955         struct r8192_priv *priv = ieee80211_priv(dev);
1956         static u32 reset_cnt_highpwr;
1957
1958         /*  For smooth, we can not change high power DIG state in the range. */
1959         if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
1960                 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
1961                 return;
1962
1963         /*
1964          * 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
1965          *    it is larger than a threshold and then execute the step below.
1966          *
1967          * 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
1968          */
1969         if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh) {
1970                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
1971                         (priv->reset_count == reset_cnt_highpwr))
1972                         return;
1973                 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
1974
1975                 /* 3.1 Higher PD_TH for OFDM for high power state. */
1976                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1977                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
1978
1979                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1980                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
1981                         */
1982
1983                 } else
1984                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
1985         } else {
1986                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF &&
1987                         (priv->reset_count == reset_cnt_highpwr))
1988                         return;
1989                 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
1990
1991                 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
1992                          priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) {
1993                         /*  3.2 Recover PD_TH for OFDM for normal power region. */
1994                         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1995                                 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1996                                 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1997                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1998                                 */
1999
2000                         } else
2001                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2002                 }
2003         }
2004
2005         reset_cnt_highpwr = priv->reset_count;
2006
2007 }       /* dm_CtrlInitGainByRssiHighPwr */
2008
2009 static void dm_initial_gain(
2010         struct net_device *dev)
2011 {
2012         struct r8192_priv *priv = ieee80211_priv(dev);
2013         u8                                      initial_gain = 0;
2014         static u8                               initialized, force_write;
2015         static u32                      reset_cnt;
2016         u8                              tmp;
2017
2018         if (dm_digtable.dig_algorithm_switch) {
2019                 initialized = 0;
2020                 reset_cnt = 0;
2021         }
2022
2023         if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
2024                 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
2025                         if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max)
2026                                 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max;
2027                         else if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
2028                                 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
2029                         else
2030                                 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
2031                 } else {        /* current state is disconnected */
2032                         if (dm_digtable.cur_ig_value == 0)
2033                                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2034                         else
2035                                 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
2036                 }
2037         } else { /*  disconnected -> connected or connected -> disconnected */
2038                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2039                 dm_digtable.pre_ig_value = 0;
2040         }
2041         /*DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);*/
2042
2043         /* if silent reset happened, we should rewrite the values back */
2044         if (priv->reset_count != reset_cnt) {
2045                 force_write = 1;
2046                 reset_cnt = priv->reset_count;
2047         }
2048
2049         read_nic_byte(dev, rOFDM0_XAAGCCore1, &tmp);
2050         if (dm_digtable.pre_ig_value != tmp)
2051                 force_write = 1;
2052
2053         {
2054                 if ((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
2055                         || !initialized || force_write) {
2056                         initial_gain = (u8)dm_digtable.cur_ig_value;
2057                         /*DbgPrint("Write initial gain = 0x%x\n", initial_gain);*/
2058                         /*  Set initial gain. */
2059                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
2060                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
2061                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
2062                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
2063                         dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
2064                         initialized = 1;
2065                         force_write = 0;
2066                 }
2067         }
2068 }
2069
2070 static void dm_pd_th(
2071         struct net_device *dev)
2072 {
2073         struct r8192_priv *priv = ieee80211_priv(dev);
2074         static u8                               initialized, force_write;
2075         static u32                      reset_cnt;
2076
2077         if (dm_digtable.dig_algorithm_switch) {
2078                 initialized = 0;
2079                 reset_cnt = 0;
2080         }
2081
2082         if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
2083                 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
2084                         if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
2085                                 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
2086                         else if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)
2087                                 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2088                         else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
2089                                         (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
2090                                 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
2091                         else
2092                                 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
2093                 } else {
2094                         dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2095                 }
2096         } else { /* disconnected -> connected or connected -> disconnected */
2097                 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2098         }
2099
2100         /*  if silent reset happened, we should rewrite the values back */
2101         if (priv->reset_count != reset_cnt) {
2102                 force_write = 1;
2103                 reset_cnt = priv->reset_count;
2104         }
2105
2106         {
2107                 if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
2108                     (initialized <= 3) || force_write) {
2109                         /*DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);*/
2110                         if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) {
2111                                 /*  Lower PD_TH for OFDM. */
2112                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
2113                                         /*
2114                                          * 2008/01/11 MH 40MHZ 90/92 register are not the same.
2115                                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2116                                          */
2117                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2118                                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2119                                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2120                                         */
2121                                 } else
2122                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2123                         } else if (dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) {
2124                                 /* Higher PD_TH for OFDM. */
2125                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
2126                                         /*
2127                                          * 2008/01/11 MH 40MHZ 90/92 register are not the same.
2128                                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2129                                          */
2130                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2131                                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2132                                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2133                                         */
2134                                 } else
2135                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2136                         } else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) {
2137                                 /* Higher PD_TH for OFDM for high power state. */
2138                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
2139                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2140                                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2141                                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2142                                         */
2143                                 } else
2144                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2145                         }
2146                         dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2147                         if (initialized <= 3)
2148                                 initialized++;
2149                         force_write = 0;
2150                 }
2151         }
2152 }
2153
2154 static  void dm_cs_ratio(
2155         struct net_device *dev)
2156 {
2157         struct r8192_priv *priv = ieee80211_priv(dev);
2158         static u8                               initialized, force_write;
2159         static u32                      reset_cnt;
2160
2161         if (dm_digtable.dig_algorithm_switch) {
2162                 initialized = 0;
2163                 reset_cnt = 0;
2164         }
2165
2166         if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
2167                 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
2168                         if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)
2169                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2170                         else if (dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh)
2171                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2172                         else
2173                                 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2174                 } else {
2175                         dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2176                 }
2177         } else  /* disconnected -> connected or connected -> disconnected */
2178                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2179
2180         /* if silent reset happened, we should rewrite the values back */
2181         if (priv->reset_count != reset_cnt) {
2182                 force_write = 1;
2183                 reset_cnt = priv->reset_count;
2184         }
2185
2186         {
2187                 if ((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2188                         !initialized || force_write) {
2189                         /*DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);*/
2190                         if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) {
2191                                 /*  Lower CS ratio for CCK. */
2192                                 write_nic_byte(dev, 0xa0a, 0x08);
2193                         } else if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) {
2194                                 /*  Higher CS ratio for CCK. */
2195                                 write_nic_byte(dev, 0xa0a, 0xcd);
2196                         }
2197                         dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2198                         initialized = 1;
2199                         force_write = 0;
2200                 }
2201         }
2202 }
2203
2204 void dm_init_edca_turbo(struct net_device *dev)
2205 {
2206         struct r8192_priv *priv = ieee80211_priv(dev);
2207
2208         priv->bcurrent_turbo_EDCA = false;
2209         priv->ieee80211->bis_any_nonbepkts = false;
2210         priv->bis_cur_rdlstate = false;
2211 }       /* dm_init_edca_turbo */
2212
2213 static void dm_check_edca_turbo(
2214         struct net_device *dev)
2215 {
2216         struct r8192_priv *priv = ieee80211_priv(dev);
2217         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
2218         /*PSTA_QOS                      pStaQos = pMgntInfo->pStaQos;*/
2219
2220         /* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */
2221         static unsigned long                    lastTxOkCnt;
2222         static unsigned long                    lastRxOkCnt;
2223         unsigned long                           curTxOkCnt = 0;
2224         unsigned long                           curRxOkCnt = 0;
2225
2226         /*
2227          * Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2228          * should follow the settings from QAP. By Bruce, 2007-12-07.
2229          */
2230         if (priv->ieee80211->state != IEEE80211_LINKED)
2231                 goto dm_CheckEdcaTurbo_EXIT;
2232         /* We do not turn on EDCA turbo mode for some AP that has IOT issue */
2233         if (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2234                 goto dm_CheckEdcaTurbo_EXIT;
2235
2236         /*printk("========>%s():bis_any_nonbepkts is %d\n", __func__, priv->bis_any_nonbepkts);*/
2237         /* Check the status for current condition. */
2238         if (!priv->ieee80211->bis_any_nonbepkts) {
2239                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2240                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2241                 /* For RT-AP, we needs to turn it on when Rx>Tx */
2242                 if (curRxOkCnt > 4*curTxOkCnt) {
2243                         /*printk("%s():curRxOkCnt > 4*curTxOkCnt\n");*/
2244                         if (!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
2245                                 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2246                                 priv->bis_cur_rdlstate = true;
2247                         }
2248                 } else {
2249                         /*printk("%s():curRxOkCnt < 4*curTxOkCnt\n");*/
2250                         if (priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
2251                                 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2252                                 priv->bis_cur_rdlstate = false;
2253                         }
2254
2255                 }
2256
2257                 priv->bcurrent_turbo_EDCA = true;
2258         } else {
2259                 /*
2260                  * Turn Off EDCA turbo here.
2261                  * Restore original EDCA according to the declaration of AP.
2262                  */
2263                 if (priv->bcurrent_turbo_EDCA) {
2264                         {
2265                                 u8              u1bAIFS;
2266                                 u32             u4bAcParam;
2267                                 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2268                                 u8 mode = priv->ieee80211->mode;
2269
2270                                 /*  For Each time updating EDCA parameter, reset EDCA turbo mode status. */
2271                                 dm_init_edca_turbo(dev);
2272                                 u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
2273                                 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0])) << AC_PARAM_TXOP_LIMIT_OFFSET)|
2274                                         (((u32)(qos_parameters->cw_max[0])) << AC_PARAM_ECW_MAX_OFFSET)|
2275                                         (((u32)(qos_parameters->cw_min[0])) << AC_PARAM_ECW_MIN_OFFSET)|
2276                                         ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
2277                                 /*write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);*/
2278                                 write_nic_dword(dev, EDCAPARA_BE,  u4bAcParam);
2279
2280                                 /*
2281                                  * Check ACM bit.
2282                                  * If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2283                                  */
2284                                 {
2285                                         /*  TODO:  Modified this part and try to set acm control in only 1 IO processing!! */
2286
2287                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
2288                                         u8              AcmCtrl;
2289
2290                                         read_nic_byte(dev, AcmHwCtrl, &AcmCtrl);
2291
2292                                         if (pAciAifsn->f.ACM) { /*  ACM bit is 1. */
2293                                                 AcmCtrl |= AcmHw_BeqEn;
2294                                         } else {        /* ACM bit is 0. */
2295                                                 AcmCtrl &= (~AcmHw_BeqEn);
2296                                         }
2297
2298                                         RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2299                                         write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
2300                                 }
2301                         }
2302                         priv->bcurrent_turbo_EDCA = false;
2303                 }
2304         }
2305
2306 dm_CheckEdcaTurbo_EXIT:
2307         /* Set variables for next time. */
2308         priv->ieee80211->bis_any_nonbepkts = false;
2309         lastTxOkCnt = priv->stats.txbytesunicast;
2310         lastRxOkCnt = priv->stats.rxbytesunicast;
2311 }       /* dm_CheckEdcaTurbo */
2312
2313 static void dm_init_ctstoself(struct net_device *dev)
2314 {
2315         struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2316
2317         priv->ieee80211->bCTSToSelfEnable = TRUE;
2318         priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal;
2319 }
2320
2321 static void dm_ctstoself(struct net_device *dev)
2322 {
2323         struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2324         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
2325         static unsigned long                            lastTxOkCnt;
2326         static unsigned long                            lastRxOkCnt;
2327         unsigned long                                           curTxOkCnt = 0;
2328         unsigned long                                           curRxOkCnt = 0;
2329
2330         if (priv->ieee80211->bCTSToSelfEnable != TRUE) {
2331                 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2332                 return;
2333         }
2334         /*
2335         1. Uplink
2336         2. Linksys350/Linksys300N
2337         3. <50 disable, >55 enable
2338         */
2339
2340         if (pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) {
2341                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2342                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2343                 if (curRxOkCnt > 4*curTxOkCnt) { /* downlink, disable CTS to self */
2344                         pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2345                         /*DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");*/
2346                 } else { /* uplink */
2347                         pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2348                 }
2349
2350                 lastTxOkCnt = priv->stats.txbytesunicast;
2351                 lastRxOkCnt = priv->stats.rxbytesunicast;
2352         }
2353 }
2354
2355 /*-----------------------------------------------------------------------------
2356  * Function:    dm_check_pbc_gpio()
2357  *
2358  * Overview:    Check if PBC button is pressed.
2359  *
2360  * Input:               NONE
2361  *
2362  * Output:              NONE
2363  *
2364  * Return:              NONE
2365  *
2366  * Revised History:
2367  *      When            Who             Remark
2368  *      05/28/2008      amy     Create Version 0 porting from windows code.
2369  *
2370  *---------------------------------------------------------------------------*/
2371 static  void    dm_check_pbc_gpio(struct net_device *dev)
2372 {
2373         struct r8192_priv *priv = ieee80211_priv(dev);
2374         u8 tmp1byte;
2375
2376         read_nic_byte(dev, GPI, &tmp1byte);
2377         if (tmp1byte == 0xff)
2378                 return;
2379
2380         if (tmp1byte&BIT6 || tmp1byte&BIT0) {
2381                 /*
2382                  * Here we only set bPbcPressed to TRUE
2383                  * After trigger PBC, the variable will be set to FALSE
2384                  */
2385                 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
2386                 priv->bpbc_pressed = true;
2387         }
2388
2389 }
2390
2391 /*-----------------------------------------------------------------------------
2392  * Function:    DM_RFPathCheckWorkItemCallBack()
2393  *
2394  * Overview:    Check if Current RF RX path is enabled
2395  *
2396  * Input:               NONE
2397  *
2398  * Output:              NONE
2399  *
2400  * Return:              NONE
2401  *
2402  * Revised History:
2403  *      When            Who             Remark
2404  *      01/30/2008      MHC             Create Version 0.
2405  *
2406  *---------------------------------------------------------------------------*/
2407 void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
2408 {
2409         struct delayed_work *dwork = container_of(work, struct delayed_work, work);
2410         struct r8192_priv *priv = container_of(dwork, struct r8192_priv, rfpath_check_wq);
2411         struct net_device *dev = priv->ieee80211->dev;
2412         /*bool bactually_set = false;*/
2413         u8 rfpath = 0, i;
2414
2415         /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
2416            always be the same. We only read 0xc04 now. */
2417         read_nic_byte(dev, 0xc04, &rfpath);
2418
2419         /* Check Bit 0-3, it means if RF A-D is enabled. */
2420         for (i = 0; i < RF90_PATH_MAX; i++) {
2421                 if (rfpath & (0x01<<i))
2422                         priv->brfpath_rxenable[i] = 1;
2423                 else
2424                         priv->brfpath_rxenable[i] = 0;
2425         }
2426         if (!DM_RxPathSelTable.Enable)
2427                 return;
2428
2429         dm_rxpath_sel_byrssi(dev);
2430 }       /* DM_RFPathCheckWorkItemCallBack */
2431
2432 static void dm_init_rxpath_selection(struct net_device *dev)
2433 {
2434         u8 i;
2435         struct r8192_priv *priv = ieee80211_priv(dev);
2436
2437         DM_RxPathSelTable.Enable = 1;   /* default enabled */
2438         DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;
2439         DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;
2440         if (priv->CustomerID == RT_CID_819x_Netcore)
2441                 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
2442         else
2443                 DM_RxPathSelTable.cck_method = CCK_Rx_Version_1;
2444         DM_RxPathSelTable.DbgMode = DM_DBG_OFF;
2445         DM_RxPathSelTable.disabledRF = 0;
2446         for (i = 0; i < 4; i++) {
2447                 DM_RxPathSelTable.rf_rssi[i] = 50;
2448                 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
2449                 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2450         }
2451 }
2452
2453 static void dm_rxpath_sel_byrssi(struct net_device *dev)
2454 {
2455         struct r8192_priv *priv = ieee80211_priv(dev);
2456         u8                              i, max_rssi_index = 0, min_rssi_index = 0, sec_rssi_index = 0, rf_num = 0;
2457         u8                              tmp_max_rssi = 0, tmp_min_rssi = 0, tmp_sec_rssi = 0;
2458         u8                              cck_default_Rx = 0x2;  /* RF-C */
2459         u8                              cck_optional_Rx = 0x3; /* RF-D */
2460         long                            tmp_cck_max_pwdb = 0, tmp_cck_min_pwdb = 0, tmp_cck_sec_pwdb = 0;
2461         u8                              cck_rx_ver2_max_index = 0, cck_rx_ver2_min_index = 0, cck_rx_ver2_sec_index = 0;
2462         u8                              cur_rf_rssi;
2463         long                            cur_cck_pwdb;
2464         static u8                       disabled_rf_cnt, cck_Rx_Path_initialized;
2465         u8                              update_cck_rx_path;
2466
2467         if (priv->rf_type != RF_2T4R)
2468                 return;
2469
2470         if (!cck_Rx_Path_initialized) {
2471                 read_nic_byte(dev, 0xa07, &DM_RxPathSelTable.cck_Rx_path);
2472                 DM_RxPathSelTable.cck_Rx_path &= 0xf;
2473                 cck_Rx_Path_initialized = 1;
2474         }
2475
2476         read_nic_byte(dev, 0xc04, &DM_RxPathSelTable.disabledRF);
2477         DM_RxPathSelTable.disabledRF = ~DM_RxPathSelTable.disabledRF & 0xf;
2478
2479         if (priv->ieee80211->mode == WIRELESS_MODE_B) {
2480                 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;        /* pure B mode, fixed cck version2 */
2481                 /*DbgPrint("Pure B mode, use cck rx version2\n");*/
2482         }
2483
2484         /* decide max/sec/min rssi index */
2485         for (i = 0; i < RF90_PATH_MAX; i++) {
2486                 if (!DM_RxPathSelTable.DbgMode)
2487                         DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
2488
2489                 if (priv->brfpath_rxenable[i]) {
2490                         rf_num++;
2491                         cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
2492
2493                         if (rf_num == 1) { /* find first enabled rf path and the rssi values */
2494                                 /* initialize, set all rssi index to the same one */
2495                                 max_rssi_index = min_rssi_index = sec_rssi_index = i;
2496                                 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
2497                         } else if (rf_num == 2) { /* we pick up the max index first, and let sec and min to be the same one */
2498                                 if (cur_rf_rssi >= tmp_max_rssi) {
2499                                         tmp_max_rssi = cur_rf_rssi;
2500                                         max_rssi_index = i;
2501                                 } else {
2502                                         tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
2503                                         sec_rssi_index = min_rssi_index = i;
2504                                 }
2505                         } else {
2506                                 if (cur_rf_rssi > tmp_max_rssi) {
2507                                         tmp_sec_rssi = tmp_max_rssi;
2508                                         sec_rssi_index = max_rssi_index;
2509                                         tmp_max_rssi = cur_rf_rssi;
2510                                         max_rssi_index = i;
2511                                 } else if (cur_rf_rssi == tmp_max_rssi) {       /* let sec and min point to the different index */
2512                                         tmp_sec_rssi = cur_rf_rssi;
2513                                         sec_rssi_index = i;
2514                                 } else if ((cur_rf_rssi < tmp_max_rssi) && (cur_rf_rssi > tmp_sec_rssi)) {
2515                                         tmp_sec_rssi = cur_rf_rssi;
2516                                         sec_rssi_index = i;
2517                                 } else if (cur_rf_rssi == tmp_sec_rssi) {
2518                                         if (tmp_sec_rssi == tmp_min_rssi) {
2519                                                 /* let sec and min point to the different index */
2520                                                 tmp_sec_rssi = cur_rf_rssi;
2521                                                 sec_rssi_index = i;
2522                                         } else {
2523                                                 /* This case we don't need to set any index */
2524                                         }
2525                                 } else if ((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi)) {
2526                                         /* This case we don't need to set any index */
2527                                 } else if (cur_rf_rssi == tmp_min_rssi) {
2528                                         if (tmp_sec_rssi == tmp_min_rssi) {
2529                                                 /* let sec and min point to the different index */
2530                                                 tmp_min_rssi = cur_rf_rssi;
2531                                                 min_rssi_index = i;
2532                                         } else {
2533                                                 /* This case we don't need to set any index */
2534                                         }
2535                                 } else if (cur_rf_rssi < tmp_min_rssi) {
2536                                         tmp_min_rssi = cur_rf_rssi;
2537                                         min_rssi_index = i;
2538                                 }
2539                         }
2540                 }
2541         }
2542
2543         rf_num = 0;
2544         /* decide max/sec/min cck pwdb index */
2545         if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) {
2546                 for (i = 0; i < RF90_PATH_MAX; i++) {
2547                         if (priv->brfpath_rxenable[i]) {
2548                                 rf_num++;
2549                                 cur_cck_pwdb =  DM_RxPathSelTable.cck_pwdb_sta[i];
2550
2551                                 if (rf_num == 1) {      /* find first enabled rf path and the rssi values */
2552                                         /* initialize, set all rssi index to the same one */
2553                                         cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
2554                                         tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
2555                                 } else if (rf_num == 2) {       /* we pick up the max index first, and let sec and min to be the same one */
2556                                         if (cur_cck_pwdb >= tmp_cck_max_pwdb) {
2557                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
2558                                                 cck_rx_ver2_max_index = i;
2559                                         } else {
2560                                                 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
2561                                                 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
2562                                         }
2563                                 } else {
2564                                         if (cur_cck_pwdb > tmp_cck_max_pwdb) {
2565                                                 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
2566                                                 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
2567                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
2568                                                 cck_rx_ver2_max_index = i;
2569                                         } else if (cur_cck_pwdb == tmp_cck_max_pwdb) { /* let sec and min point to the different index */
2570                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
2571                                                 cck_rx_ver2_sec_index = i;
2572                                         } else if ((cur_cck_pwdb < tmp_cck_max_pwdb) && (cur_cck_pwdb > tmp_cck_sec_pwdb)) {
2573                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
2574                                                 cck_rx_ver2_sec_index = i;
2575                                         } else if (cur_cck_pwdb == tmp_cck_sec_pwdb) {
2576                                                 if (tmp_cck_sec_pwdb == tmp_cck_min_pwdb) { /* let sec and min point to the different index */
2577                                                         tmp_cck_sec_pwdb = cur_cck_pwdb;
2578                                                         cck_rx_ver2_sec_index = i;
2579                                                 } else {
2580                                                         /*  This case we don't need to set any index */
2581                                                 }
2582                                         } else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb)) {
2583                                                 /*  This case we don't need to set any index */
2584                                         } else if (cur_cck_pwdb == tmp_cck_min_pwdb) {
2585                                                 if (tmp_cck_sec_pwdb == tmp_cck_min_pwdb) { /*  let sec and min point to the different index */
2586                                                         tmp_cck_min_pwdb = cur_cck_pwdb;
2587                                                         cck_rx_ver2_min_index = i;
2588                                                 } else {
2589                                                         /*  This case we don't need to set any index */
2590                                                 }
2591                                         } else if (cur_cck_pwdb < tmp_cck_min_pwdb) {
2592                                                 tmp_cck_min_pwdb = cur_cck_pwdb;
2593                                                 cck_rx_ver2_min_index = i;
2594                                         }
2595                                 }
2596
2597                         }
2598                 }
2599         }
2600
2601         /*
2602          * Set CCK Rx path
2603          * reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
2604          */
2605         update_cck_rx_path = 0;
2606         if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) {
2607                 cck_default_Rx = cck_rx_ver2_max_index;
2608                 cck_optional_Rx = cck_rx_ver2_sec_index;
2609                 if (tmp_cck_max_pwdb != -64)
2610                         update_cck_rx_path = 1;
2611         }
2612
2613         if (tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2) {
2614                 if ((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH) {
2615                         /* record the enabled rssi threshold */
2616                         DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
2617                         /* disable the BB Rx path, OFDM */
2618                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0);  /* 0xc04[3:0] */
2619                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0);  /* 0xd04[3:0] */
2620                         disabled_rf_cnt++;
2621                 }
2622                 if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_1) {
2623                         cck_default_Rx = max_rssi_index;
2624                         cck_optional_Rx = sec_rssi_index;
2625                         if (tmp_max_rssi)
2626                                 update_cck_rx_path = 1;
2627                 }
2628         }
2629
2630         if (update_cck_rx_path) {
2631                 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
2632                 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);
2633         }
2634
2635         if (DM_RxPathSelTable.disabledRF) {
2636                 for (i = 0; i < 4; i++) {
2637                         if ((DM_RxPathSelTable.disabledRF>>i) & 0x1) {  /* disabled rf */
2638                                 if (tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) {
2639                                         /* enable the BB Rx path */
2640                                         /*DbgPrint("RF-%d is enabled.\n", 0x1<<i);*/
2641                                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1);       /* 0xc04[3:0] */
2642                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1);       /* 0xd04[3:0] */
2643                                         DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2644                                         disabled_rf_cnt--;
2645                                 }
2646                         }
2647                 }
2648         }
2649 }
2650
2651 /*-----------------------------------------------------------------------------
2652  * Function:    dm_check_rx_path_selection()
2653  *
2654  * Overview:    Call a workitem to check current RXRF path and Rx Path selection by RSSI.
2655  *
2656  * Input:               NONE
2657  *
2658  * Output:              NONE
2659  *
2660  * Return:              NONE
2661  *
2662  * Revised History:
2663  *      When            Who             Remark
2664  *      05/28/2008      amy             Create Version 0 porting from windows code.
2665  *
2666  *---------------------------------------------------------------------------*/
2667 static void dm_check_rx_path_selection(struct net_device *dev)
2668 {
2669         struct r8192_priv *priv = ieee80211_priv(dev);
2670
2671         queue_delayed_work(priv->priv_wq, &priv->rfpath_check_wq, 0);
2672 }       /* dm_CheckRxRFPath */
2673
2674 static void dm_init_fsync(struct net_device *dev)
2675 {
2676         struct r8192_priv *priv = ieee80211_priv(dev);
2677
2678         priv->ieee80211->fsync_time_interval = 500;
2679         priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
2680         priv->ieee80211->fsync_rssi_threshold = 30;
2681         priv->ieee80211->bfsync_enable = false;
2682         priv->ieee80211->fsync_multiple_timeinterval = 3;
2683         priv->ieee80211->fsync_firstdiff_ratethreshold = 100;
2684         priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2685         priv->ieee80211->fsync_state = Default_Fsync;
2686         priv->framesyncMonitor = 1;     /* current default 0xc38 monitor on */
2687
2688         init_timer(&priv->fsync_timer);
2689         priv->fsync_timer.data = (unsigned long)dev;
2690         priv->fsync_timer.function = dm_fsync_timer_callback;
2691 }
2692
2693 static void dm_deInit_fsync(struct net_device *dev)
2694 {
2695         struct r8192_priv *priv = ieee80211_priv(dev);
2696
2697         del_timer_sync(&priv->fsync_timer);
2698 }
2699
2700 void dm_fsync_timer_callback(unsigned long data)
2701 {
2702         struct net_device *dev = (struct net_device *)data;
2703         struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
2704         u32 rate_index, rate_count = 0, rate_count_diff = 0;
2705         bool            bSwitchFromCountDiff = false;
2706         bool            bDoubleTimeInterval = false;
2707
2708         if (priv->ieee80211->state == IEEE80211_LINKED &&
2709                 priv->ieee80211->bfsync_enable &&
2710                 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) {
2711                 /* Count rate 54, MCS [7], [12, 13, 14, 15] */
2712                 u32 rate_bitmap;
2713
2714                 for (rate_index = 0; rate_index <= 27; rate_index++) {
2715                         rate_bitmap  = 1 << rate_index;
2716                         if (priv->ieee80211->fsync_rate_bitmap &  rate_bitmap)
2717                                 rate_count += priv->stats.received_rate_histogram[1][rate_index];
2718                 }
2719
2720                 if (rate_count < priv->rate_record)
2721                         rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
2722                 else
2723                         rate_count_diff = rate_count - priv->rate_record;
2724                 if (rate_count_diff < priv->rateCountDiffRecord) {
2725                         u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
2726                         /* Continue count */
2727                         if (DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
2728                                 priv->ContinueDiffCount++;
2729                         else
2730                                 priv->ContinueDiffCount = 0;
2731
2732                         /* Continue count over */
2733                         if (priv->ContinueDiffCount >= 2) {
2734                                 bSwitchFromCountDiff = true;
2735                                 priv->ContinueDiffCount = 0;
2736                         }
2737                 } else {
2738                         /* Stop the continued count */
2739                         priv->ContinueDiffCount = 0;
2740                 }
2741
2742                 /* If Count diff <= FsyncRateCountThreshold */
2743                 if (rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold) {
2744                         bSwitchFromCountDiff = true;
2745                         priv->ContinueDiffCount = 0;
2746                 }
2747                 priv->rate_record = rate_count;
2748                 priv->rateCountDiffRecord = rate_count_diff;
2749                 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync);
2750                 /* if we never receive those mcs rate and rssi > 30 % then switch fsyn */
2751                 if (priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff) {
2752                         bDoubleTimeInterval = true;
2753                         priv->bswitch_fsync = !priv->bswitch_fsync;
2754                         if (priv->bswitch_fsync) {
2755                                 write_nic_byte(dev, 0xC36, 0x1c);
2756                                 write_nic_byte(dev, 0xC3e, 0x90);
2757                         } else {
2758                                 write_nic_byte(dev, 0xC36, 0x5c);
2759                                 write_nic_byte(dev, 0xC3e, 0x96);
2760                         }
2761                 } else if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold) {
2762                         if (priv->bswitch_fsync) {
2763                                 priv->bswitch_fsync  = false;
2764                                 write_nic_byte(dev, 0xC36, 0x5c);
2765                                 write_nic_byte(dev, 0xC3e, 0x96);
2766                         }
2767                 }
2768                 if (bDoubleTimeInterval) {
2769                         if (timer_pending(&priv->fsync_timer))
2770                                 del_timer_sync(&priv->fsync_timer);
2771                         priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
2772                         add_timer(&priv->fsync_timer);
2773                 } else {
2774                         if (timer_pending(&priv->fsync_timer))
2775                                 del_timer_sync(&priv->fsync_timer);
2776                         priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
2777                         add_timer(&priv->fsync_timer);
2778                 }
2779         } else {
2780                 /* Let Register return to default value; */
2781                 if (priv->bswitch_fsync) {
2782                         priv->bswitch_fsync  = false;
2783                         write_nic_byte(dev, 0xC36, 0x5c);
2784                         write_nic_byte(dev, 0xC3e, 0x96);
2785                 }
2786                 priv->ContinueDiffCount = 0;
2787                 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2788         }
2789         RT_TRACE(COMP_HALDM, "ContinueDiffCount %d\n", priv->ContinueDiffCount);
2790         RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync);
2791 }
2792
2793 static void dm_StartHWFsync(struct net_device *dev)
2794 {
2795         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2796         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
2797         write_nic_byte(dev, 0xc3b, 0x41);
2798 }
2799
2800 static void dm_EndSWFsync(struct net_device *dev)
2801 {
2802         struct r8192_priv *priv = ieee80211_priv(dev);
2803
2804         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2805         del_timer_sync(&(priv->fsync_timer));
2806
2807         /* Let Register return to default value; */
2808         if (priv->bswitch_fsync) {
2809                 priv->bswitch_fsync  = false;
2810
2811                 write_nic_byte(dev, 0xC36, 0x5c);
2812
2813                 write_nic_byte(dev, 0xC3e, 0x96);
2814         }
2815
2816         priv->ContinueDiffCount = 0;
2817         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2818
2819 }
2820
2821 static void dm_StartSWFsync(struct net_device *dev)
2822 {
2823         struct r8192_priv *priv = ieee80211_priv(dev);
2824         u32                     rateIndex;
2825         u32                     rateBitmap;
2826
2827         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2828         /* Initial rate record to zero, start to record. */
2829         priv->rate_record = 0;
2830         /* Initialize continue diff count to zero, start to record. */
2831         priv->ContinueDiffCount = 0;
2832         priv->rateCountDiffRecord = 0;
2833         priv->bswitch_fsync  = false;
2834
2835         if (priv->ieee80211->mode == WIRELESS_MODE_N_24G) {
2836                 priv->ieee80211->fsync_firstdiff_ratethreshold = 600;
2837                 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
2838         } else {
2839                 priv->ieee80211->fsync_firstdiff_ratethreshold = 200;
2840                 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2841         }
2842         for (rateIndex = 0; rateIndex <= 27; rateIndex++) {
2843                 rateBitmap = 1 << rateIndex;
2844                 if (priv->ieee80211->fsync_rate_bitmap &  rateBitmap)
2845                         priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
2846         }
2847         if (timer_pending(&priv->fsync_timer))
2848                 del_timer_sync(&priv->fsync_timer);
2849         priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
2850         add_timer(&priv->fsync_timer);
2851
2852         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
2853
2854 }
2855
2856 static void dm_EndHWFsync(struct net_device *dev)
2857 {
2858         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2859         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2860         write_nic_byte(dev, 0xc3b, 0x49);
2861
2862 }
2863
2864 void dm_check_fsync(struct net_device *dev)
2865 {
2866 #define RegC38_Default                          0
2867 #define RegC38_NonFsync_Other_AP                1
2868 #define RegC38_Fsync_AP_BCM                     2
2869         struct r8192_priv *priv = ieee80211_priv(dev);
2870         /*u32                   framesyncC34;*/
2871         static u8               reg_c38_State = RegC38_Default;
2872         static u32      reset_cnt;
2873
2874         RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
2875         RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
2876
2877         if (priv->ieee80211->state == IEEE80211_LINKED &&
2878                 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) {
2879                 if (priv->ieee80211->bfsync_enable == 0) {
2880                         switch (priv->ieee80211->fsync_state) {
2881                         case Default_Fsync:
2882                                 dm_StartHWFsync(dev);
2883                                 priv->ieee80211->fsync_state = HW_Fsync;
2884                                 break;
2885                         case SW_Fsync:
2886                                 dm_EndSWFsync(dev);
2887                                 dm_StartHWFsync(dev);
2888                                 priv->ieee80211->fsync_state = HW_Fsync;
2889                                 break;
2890                         case HW_Fsync:
2891                         default:
2892                                 break;
2893                         }
2894                 } else {
2895                         switch (priv->ieee80211->fsync_state) {
2896                         case Default_Fsync:
2897                                 dm_StartSWFsync(dev);
2898                                 priv->ieee80211->fsync_state = SW_Fsync;
2899                                 break;
2900                         case HW_Fsync:
2901                                 dm_EndHWFsync(dev);
2902                                 dm_StartSWFsync(dev);
2903                                 priv->ieee80211->fsync_state = SW_Fsync;
2904                                 break;
2905                         case SW_Fsync:
2906                         default:
2907                                 break;
2908                         }
2909                 }
2910                 if (priv->framesyncMonitor) {
2911                         if (reg_c38_State != RegC38_Fsync_AP_BCM) {
2912                                 /* For broadcom AP we write different default value */
2913                                 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
2914
2915                                 reg_c38_State = RegC38_Fsync_AP_BCM;
2916                         }
2917                 }
2918         } else {
2919                 switch (priv->ieee80211->fsync_state) {
2920                 case HW_Fsync:
2921                         dm_EndHWFsync(dev);
2922                         priv->ieee80211->fsync_state = Default_Fsync;
2923                         break;
2924                 case SW_Fsync:
2925                         dm_EndSWFsync(dev);
2926                         priv->ieee80211->fsync_state = Default_Fsync;
2927                         break;
2928                 case Default_Fsync:
2929                 default:
2930                         break;
2931                 }
2932
2933                 if (priv->framesyncMonitor) {
2934                         if (priv->ieee80211->state == IEEE80211_LINKED) {
2935                                 if (priv->undecorated_smoothed_pwdb <= RegC38_TH) {
2936                                         if (reg_c38_State != RegC38_NonFsync_Other_AP) {
2937                                                 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
2938
2939                                                 reg_c38_State = RegC38_NonFsync_Other_AP;
2940                                         }
2941                                 } else if (priv->undecorated_smoothed_pwdb >= (RegC38_TH+5)) {
2942                                         if (reg_c38_State) {
2943                                                 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2944                                                 reg_c38_State = RegC38_Default;
2945                                                 /*DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x\n", pHalData->framesync);*/
2946                                         }
2947                                 }
2948                         } else {
2949                                 if (reg_c38_State) {
2950                                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2951                                         reg_c38_State = RegC38_Default;
2952                                         /*DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x\n", pHalData->framesync);*/
2953                                 }
2954                         }
2955                 }
2956         }
2957         if (priv->framesyncMonitor) {
2958                 if (priv->reset_count != reset_cnt) { /* After silent reset, the reg_c38_State will be returned to default value */
2959                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2960                         reg_c38_State = RegC38_Default;
2961                         reset_cnt = priv->reset_count;
2962                         /*DbgPrint("reg_c38_State = 0 for silent reset.\n");*/
2963                 }
2964         } else {
2965                 if (reg_c38_State) {
2966                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2967                         reg_c38_State = RegC38_Default;
2968                         /*DbgPrint("framesync no monitor, write 0xc38 = 0x%x\n", pHalData->framesync);*/
2969                 }
2970         }
2971 }
2972
2973 /*-----------------------------------------------------------------------------
2974  * Function:    dm_shadow_init()
2975  *
2976  * Overview:    Store all NIC MAC/BB register content.
2977  *
2978  * Input:               NONE
2979  *
2980  * Output:              NONE
2981  *
2982  * Return:              NONE
2983  *
2984  * Revised History:
2985  *      When            Who             Remark
2986  *      05/29/2008      amy             Create Version 0 porting from windows code.
2987  *
2988  *---------------------------------------------------------------------------*/
2989 void dm_shadow_init(struct net_device *dev)
2990 {
2991         u8      page;
2992         u16     offset;
2993
2994         for (page = 0; page < 5; page++)
2995                 for (offset = 0; offset < 256; offset++) {
2996                         read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
2997                         /*DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);*/
2998                 }
2999
3000         for (page = 8; page < 11; page++)
3001                 for (offset = 0; offset < 256; offset++)
3002                         read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
3003
3004         for (page = 12; page < 15; page++)
3005                 for (offset = 0; offset < 256; offset++)
3006                         read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
3007
3008 }   /* dm_shadow_init */
3009
3010 /*---------------------------Define function prototype------------------------*/
3011 /*-----------------------------------------------------------------------------
3012  * Function:    DM_DynamicTxPower()
3013  *
3014  * Overview:    Detect Signal strength to control TX Registry
3015                         Tx Power Control For Near/Far Range
3016  *
3017  * Input:               NONE
3018  *
3019  * Output:              NONE
3020  *
3021  * Return:              NONE
3022  *
3023  * Revised History:
3024  *      When            Who             Remark
3025  *      03/06/2008      Jacken  Create Version 0.
3026  *
3027  *---------------------------------------------------------------------------*/
3028 static void dm_init_dynamic_txpower(struct net_device *dev)
3029 {
3030         struct r8192_priv *priv = ieee80211_priv(dev);
3031
3032         /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */
3033         priv->ieee80211->bdynamic_txpower_enable = true;    /* Default to enable Tx Power Control */
3034         priv->bLastDTPFlag_High = false;
3035         priv->bLastDTPFlag_Low = false;
3036         priv->bDynamicTxHighPower = false;
3037         priv->bDynamicTxLowPower = false;
3038 }
3039
3040 static void dm_dynamic_txpower(struct net_device *dev)
3041 {
3042         struct r8192_priv *priv = ieee80211_priv(dev);
3043         unsigned int txhipower_threshhold = 0;
3044         unsigned int txlowpower_threshold = 0;
3045
3046         if (priv->ieee80211->bdynamic_txpower_enable != true) {
3047                 priv->bDynamicTxHighPower = false;
3048                 priv->bDynamicTxLowPower = false;
3049                 return;
3050         }
3051         /*printk("priv->ieee80211->current_network.unknown_cap_exist is %d , priv->ieee80211->current_network.broadcom_cap_exist is %d\n", priv->ieee80211->current_network.unknown_cap_exist, priv->ieee80211->current_network.broadcom_cap_exist);*/
3052         if ((priv->ieee80211->current_network.atheros_cap_exist) && (priv->ieee80211->mode == IEEE_G)) {
3053                 txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;
3054                 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
3055         } else {
3056                 txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
3057                 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
3058         }
3059
3060         /*printk("=======>%s(): txhipower_threshhold is %d, txlowpower_threshold is %d\n", __func__, txhipower_threshhold, txlowpower_threshold);*/
3061         RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld\n", priv->undecorated_smoothed_pwdb);
3062
3063         if (priv->ieee80211->state == IEEE80211_LINKED) {
3064                 if (priv->undecorated_smoothed_pwdb >= txhipower_threshhold) {
3065                         priv->bDynamicTxHighPower = true;
3066                         priv->bDynamicTxLowPower = false;
3067                 } else {
3068                         /* high power state check */
3069                         if (priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true)
3070                                 priv->bDynamicTxHighPower = false;
3071
3072                         /* low power state check */
3073                         if (priv->undecorated_smoothed_pwdb < 35)
3074                                 priv->bDynamicTxLowPower = true;
3075                         else if (priv->undecorated_smoothed_pwdb >= 40)
3076                                 priv->bDynamicTxLowPower = false;
3077                 }
3078         } else {
3079                 /*pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;*/
3080                 priv->bDynamicTxHighPower = false;
3081                 priv->bDynamicTxLowPower = false;
3082         }
3083
3084         if ((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) ||
3085                 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low)) {
3086                 RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190()  channel = %d\n", priv->ieee80211->current_network.channel);
3087
3088 #if  defined(RTL8190P) || defined(RTL8192E)
3089                 SetTxPowerLevel8190(Adapter, pHalData->CurrentChannel);
3090 #endif
3091
3092                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
3093                 /*pHalData->bStartTxCtrlByTPCNFR = FALSE;    Clear th flag of Set TX Power from Sitesurvey*/
3094         }
3095         priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
3096         priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
3097
3098 }       /* dm_dynamic_txpower */
3099
3100 /* added by vivi, for read tx rate and retrycount */
3101 static void dm_check_txrateandretrycount(struct net_device *dev)
3102 {
3103         struct r8192_priv *priv = ieee80211_priv(dev);
3104         struct ieee80211_device *ieee = priv->ieee80211;
3105         /* for 11n tx rate */
3106         /*priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);*/
3107         read_nic_byte(dev, Current_Tx_Rate_Reg, &ieee->softmac_stats.CurrentShowTxate);
3108         /*printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);*/
3109         /* for initial tx rate */
3110         /*priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);*/
3111         read_nic_byte(dev, Initial_Tx_Rate_Reg, &ieee->softmac_stats.last_packet_rate);
3112         /* for tx tx retry count */
3113         /*priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);*/
3114         read_nic_dword(dev, Tx_Retry_Count_Reg, &ieee->softmac_stats.txretrycount);
3115 }
3116
3117 static void dm_send_rssi_tofw(struct net_device *dev)
3118 {
3119         struct r8192_priv *priv = ieee80211_priv(dev);
3120
3121         /*
3122          * If we test chariot, we should stop the TX command ?
3123          * Because 92E will always silent reset when we send tx command. We use register
3124          * 0x1e0(byte) to notify driver.
3125          */
3126         write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
3127 }
3128
3129 /*---------------------------Define function prototype------------------------*/