drivers/staging/rtl8192u/r819xU_phy.c

   1 #include "r8192U.h"
   2 #include "r8192U_hw.h"
   3 #include "r819xU_phy.h"
   4 #include "r819xU_phyreg.h"
   5 #include "r8190_rtl8256.h"
   6 #include "r8192U_dm.h"
   7 #include "r819xU_firmware_img.h"
   8
   9 #include "dot11d.h"
  10 #include <linux/bitops.h>
  11
  12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  13         0,
  14         0x085c, /* 2412 1  */
  15         0x08dc, /* 2417 2  */
  16         0x095c, /* 2422 3  */
  17         0x09dc, /* 2427 4  */
  18         0x0a5c, /* 2432 5  */
  19         0x0adc, /* 2437 6  */
  20         0x0b5c, /* 2442 7  */
  21         0x0bdc, /* 2447 8  */
  22         0x0c5c, /* 2452 9  */
  23         0x0cdc, /* 2457 10 */
  24         0x0d5c, /* 2462 11 */
  25         0x0ddc, /* 2467 12 */
  26         0x0e5c, /* 2472 13 */
  27         0x0f72, /* 2484    */
  28 };
  29
  30
  31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
  32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
  33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  34 #define rtl819XRadioA_Array  Rtl8192UsbRadioA_Array
  35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
  36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
  37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
  38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
  39
  40 /******************************************************************************
  41  * function: This function reads BB parameters from header file we generate,
  42  *           and does register read/write
  43  * input:    u32        bitmask  //taget bit pos in the addr to be modified
  44  * output:   none
  45  * return:   u32        return the shift bit position of the mask
  46  ******************************************************************************/
  47 u32 rtl8192_CalculateBitShift(u32 bitmask)
  48 {
  49         u32 i;
  50         i = ffs(bitmask) - 1;
  51         return i;
  52 }
  53 /******************************************************************************
  54  * function:  This function checks different RF type to execute legal judgement.
  55  *            If RF Path is illegal, we will return false.
  56  * input:     net_device         *dev
  57  *            u32                eRFPath
  58  * output:    none
  59  * return:    0(illegal, false), 1(legal, true)
  60  *****************************************************************************/
  61 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
  62 {
  63         u8 ret = 1;
  64         struct r8192_priv *priv = ieee80211_priv(dev);
  65         if (priv->rf_type == RF_2T4R) {
  66                 ret = 0;
  67         } else if (priv->rf_type == RF_1T2R) {
  68                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  69                         ret = 1;
  70                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  71                         ret = 0;
  72         }
  73         return ret;
  74 }
  75 /******************************************************************************
  76  * function:  This function sets specific bits to BB register
  77  * input:     net_device *dev
  78  *            u32        reg_addr   //target addr to be modified
  79  *            u32        bitmask    //taget bit pos to be modified
  80  *            u32        data       //value to be write
  81  * output:    none
  82  * return:    none
  83  * notice:
  84  ******************************************************************************/
  85 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
  86                       u32 data)
  87 {
  88
  89         u32 reg, bitshift;
  90
  91         if (bitmask != bMaskDWord) {
  92                 read_nic_dword(dev, reg_addr, &reg);
  93                 bitshift = rtl8192_CalculateBitShift(bitmask);
  94                 reg &= ~bitmask;
  95                 reg |= data << bitshift;
  96                 write_nic_dword(dev, reg_addr, reg);
  97         } else {
  98                 write_nic_dword(dev, reg_addr, data);
  99         }
 100         return;
 101 }
 102 /******************************************************************************
 103  * function:  This function reads specific bits from BB register
 104  * input:     net_device        *dev
 105  *            u32               reg_addr   //target addr to be readback
 106  *            u32               bitmask    //taget bit pos to be readback
 107  * output:    none
 108  * return:    u32               data       //the readback register value
 109  * notice:
 110  ******************************************************************************/
 111 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
 112 {
 113         u32 reg, bitshift;
 114
 115         read_nic_dword(dev, reg_addr, &reg);
 116         bitshift = rtl8192_CalculateBitShift(bitmask);
 117
 118         return (reg & bitmask) >> bitshift;
 119 }
 120 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 121                               u32 offset);
 122
 123 static void phy_FwRFSerialWrite(struct net_device *dev,
 124                                 RF90_RADIO_PATH_E eRFPath, u32  offset,
 125                                 u32  data);
 126
 127 /******************************************************************************
 128  * function:  This function reads register from RF chip
 129  * input:     net_device        *dev
 130  *            RF90_RADIO_PATH_E eRFPath    //radio path of A/B/C/D
 131  *            u32               offset     //target address to be read
 132  * output:    none
 133  * return:    u32               readback value
 134  * notice:    There are three types of serial operations:
 135  *            (1) Software serial write.
 136  *            (2)Hardware LSSI-Low Speed Serial Interface.
 137  *            (3)Hardware HSSI-High speed serial write.
 138  *            Driver here need to implement (1) and (2)
 139  *            ---need more spec for this information.
 140  ******************************************************************************/
 141 u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 142                              u32 offset)
 143 {
 144         struct r8192_priv *priv = ieee80211_priv(dev);
 145         u32 ret = 0;
 146         u32 new_offset = 0;
 147         BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
 148         rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 149         /* Make sure RF register offset is correct */
 150         offset &= 0x3f;
 151
 152         /* Switch page for 8256 RF IC */
 153         if (priv->rf_chip == RF_8256) {
 154                 if (offset >= 31) {
 155                         priv->RfReg0Value[eRFPath] |= 0x140;
 156                         /* Switch to Reg_Mode2 for Reg 31-45 */
 157                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 158                                          bMaskDWord,
 159                                          priv->RfReg0Value[eRFPath]<<16);
 160                         /* Modify offset */
 161                         new_offset = offset - 30;
 162                 } else if (offset >= 16) {
 163                         priv->RfReg0Value[eRFPath] |= 0x100;
 164                         priv->RfReg0Value[eRFPath] &= (~0x40);
 165                         /* Switch to Reg_Mode1 for Reg16-30 */
 166                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 167                                          bMaskDWord,
 168                                          priv->RfReg0Value[eRFPath]<<16);
 169
 170                         new_offset = offset - 15;
 171                 } else {
 172                         new_offset = offset;
 173                 }
 174         } else {
 175                 RT_TRACE((COMP_PHY|COMP_ERR),
 176                          "check RF type here, need to be 8256\n");
 177                 new_offset = offset;
 178         }
 179         /* Put desired read addr to LSSI control Register */
 180         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
 181                          new_offset);
 182         /* Issue a posedge trigger */
 183         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 184         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 185
 186
 187         /* TODO: we should not delay such a long time. Ask for help from SD3 */
 188         msleep(1);
 189
 190         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
 191                                  bLSSIReadBackData);
 192
 193
 194         /* Switch back to Reg_Mode0 */
 195         if (priv->rf_chip == RF_8256) {
 196                 priv->RfReg0Value[eRFPath] &= 0xebf;
 197
 198                 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
 199                                  priv->RfReg0Value[eRFPath] << 16);
 200         }
 201
 202         return ret;
 203
 204 }
 205
 206 /******************************************************************************
 207  * function:  This function writes data to RF register
 208  * input:     net_device        *dev
 209  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 210  *            u32               offset   //target address to be written
 211  *            u32               data     //the new register data to be written
 212  * output:    none
 213  * return:    none
 214  * notice:    For RF8256 only.
 215  * ===========================================================================
 216  * Reg Mode     RegCTL[1]       RegCTL[0]               Note
 217  *              (Reg00[12])     (Reg00[10])
 218  * ===========================================================================
 219  * Reg_Mode0    0               x                       Reg 0 ~ 15(0x0 ~ 0xf)
 220  * ---------------------------------------------------------------------------
 221  * Reg_Mode1    1               0                       Reg 16 ~ 30(0x1 ~ 0xf)
 222  * ---------------------------------------------------------------------------
 223  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 224  * ---------------------------------------------------------------------------
 225  *****************************************************************************/
 226 void rtl8192_phy_RFSerialWrite(struct net_device *dev,
 227                                RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
 228 {
 229         struct r8192_priv *priv = ieee80211_priv(dev);
 230         u32 DataAndAddr = 0, new_offset = 0;
 231         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 232
 233         offset &= 0x3f;
 234         if (priv->rf_chip == RF_8256) {
 235
 236                 if (offset >= 31) {
 237                         priv->RfReg0Value[eRFPath] |= 0x140;
 238                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 239                                          bMaskDWord,
 240                                          priv->RfReg0Value[eRFPath] << 16);
 241                         new_offset = offset - 30;
 242                 } else if (offset >= 16) {
 243                         priv->RfReg0Value[eRFPath] |= 0x100;
 244                         priv->RfReg0Value[eRFPath] &= (~0x40);
 245                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 246                                          bMaskDWord,
 247                                          priv->RfReg0Value[eRFPath]<<16);
 248                         new_offset = offset - 15;
 249                 } else {
 250                         new_offset = offset;
 251                 }
 252         } else {
 253                 RT_TRACE((COMP_PHY|COMP_ERR),
 254                          "check RF type here, need to be 8256\n");
 255                 new_offset = offset;
 256         }
 257
 258         /* Put write addr in [5:0] and write data in [31:16] */
 259         DataAndAddr = (data<<16) | (new_offset&0x3f);
 260
 261         /* Write operation */
 262         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 263
 264
 265         if (offset == 0x0)
 266                 priv->RfReg0Value[eRFPath] = data;
 267
 268         /* Switch back to Reg_Mode0 */
 269         if (priv->rf_chip == RF_8256) {
 270                 if (offset != 0) {
 271                         priv->RfReg0Value[eRFPath] &= 0xebf;
 272                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 273                                          bMaskDWord,
 274                                          priv->RfReg0Value[eRFPath] << 16);
 275                 }
 276         }
 277         return;
 278 }
 279
 280 /******************************************************************************
 281  * function:  This function set specific bits to RF register
 282  * input:     net_device        dev
 283  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 284  *            u32               reg_addr //target addr to be modified
 285  *            u32               bitmask  //taget bit pos to be modified
 286  *            u32               data     //value to be written
 287  * output:    none
 288  * return:    none
 289  * notice:
 290  *****************************************************************************/
 291 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 292                           u32 reg_addr, u32 bitmask, u32 data)
 293 {
 294         struct r8192_priv *priv = ieee80211_priv(dev);
 295         u32 reg, bitshift;
 296
 297         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 298                 return;
 299
 300         if (priv->Rf_Mode == RF_OP_By_FW) {
 301                 if (bitmask != bMask12Bits) {
 302                         /* RF data is 12 bits only */
 303                         reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 304                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 305                         reg &= ~bitmask;
 306                         reg |= data << bitshift;
 307
 308                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
 309                 } else {
 310                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
 311                 }
 312
 313                 udelay(200);
 314
 315         } else {
 316                 if (bitmask != bMask12Bits) {
 317                         /* RF data is 12 bits only */
 318                         reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 319                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 320                         reg &= ~bitmask;
 321                         reg |= data << bitshift;
 322
 323                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
 324                 } else {
 325                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
 326                 }
 327         }
 328         return;
 329 }
 330
 331 /******************************************************************************
 332  * function:  This function reads specific bits from RF register
 333  * input:     net_device        *dev
 334  *            u32               reg_addr //target addr to be readback
 335  *            u32               bitmask  //taget bit pos to be readback
 336  * output:    none
 337  * return:    u32               data     //the readback register value
 338  * notice:
 339  *****************************************************************************/
 340 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 341                            u32 reg_addr, u32 bitmask)
 342 {
 343         u32 reg, bitshift;
 344         struct r8192_priv *priv = ieee80211_priv(dev);
 345
 346
 347         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 348                 return 0;
 349         if (priv->Rf_Mode == RF_OP_By_FW) {
 350                 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 351                 bitshift =  rtl8192_CalculateBitShift(bitmask);
 352                 reg = (reg & bitmask) >> bitshift;
 353                 udelay(200);
 354                 return reg;
 355         } else {
 356                 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 357                 bitshift =  rtl8192_CalculateBitShift(bitmask);
 358                 reg = (reg & bitmask) >> bitshift;
 359                 return reg;
 360         }
 361 }
 362 /******************************************************************************
 363  * function:  We support firmware to execute RF-R/W.
 364  * input:     net_device        *dev
 365  *            RF90_RADIO_PATH_E eRFPath
 366  *            u32               offset
 367  * output:    none
 368  * return:    u32
 369  * notice:
 370  ****************************************************************************/
 371 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 372                               u32 offset)
 373 {
 374         u32             reg = 0;
 375         u32             data = 0;
 376         u8              time = 0;
 377         u32             tmp;
 378         /* Firmware RF Write control.
 379          * We can not execute the scheme in the initial step.
 380          * Otherwise, RF-R/W will waste much time.
 381          * This is only for site survey. */
 382         /* 1. Read operation need not insert data. bit 0-11 */
 383         /* 2. Write RF register address. bit 12-19 */
 384         data |= ((offset&0xFF)<<12);
 385         /* 3. Write RF path.  bit 20-21 */
 386         data |= ((eRFPath&0x3)<<20);
 387         /* 4. Set RF read indicator. bit 22=0 */
 388         /* 5. Trigger Fw to operate the command. bit 31 */
 389         data |= 0x80000000;
 390         /* 6. We can not execute read operation if bit 31 is 1. */
 391         read_nic_dword(dev, QPNR, &tmp);
 392         while (tmp & 0x80000000) {
 393                 /* If FW can not finish RF-R/W for more than ?? times.
 394                    We must reset FW. */
 395                 if (time++ < 100) {
 396                         udelay(10);
 397                         read_nic_dword(dev, QPNR, &tmp);
 398                 } else {
 399                         break;
 400                 }
 401         }
 402         /* 7. Execute read operation. */
 403         write_nic_dword(dev, QPNR, data);
 404         /* 8. Check if firmware send back RF content. */
 405         read_nic_dword(dev, QPNR, &tmp);
 406         while (tmp & 0x80000000) {
 407                 /* If FW can not finish RF-R/W for more than ?? times.
 408                    We must reset FW. */
 409                 if (time++ < 100) {
 410                         udelay(10);
 411                         read_nic_dword(dev, QPNR, &tmp);
 412                 } else {
 413                         return 0;
 414                 }
 415         }
 416         read_nic_dword(dev, RF_DATA, &reg);
 417
 418         return reg;
 419
 420 }
 421
 422 /******************************************************************************
 423  * function:  We support firmware to execute RF-R/W.
 424  * input:     net_device        *dev
 425  *            RF90_RADIO_PATH_E eRFPath
 426  *            u32               offset
 427  *            u32               data
 428  * output:    none
 429  * return:    none
 430  * notice:
 431  ****************************************************************************/
 432 static void phy_FwRFSerialWrite(struct net_device *dev,
 433                                 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
 434 {
 435         u8      time = 0;
 436         u32     tmp;
 437
 438         /* Firmware RF Write control.
 439          * We can not execute the scheme in the initial step.
 440          * Otherwise, RF-R/W will waste much time.
 441          * This is only for site survey. */
 442
 443         /* 1. Set driver write bit and 12 bit data. bit 0-11 */
 444         /* 2. Write RF register address. bit 12-19 */
 445         data |= ((offset&0xFF)<<12);
 446         /* 3. Write RF path.  bit 20-21 */
 447         data |= ((eRFPath&0x3)<<20);
 448         /* 4. Set RF write indicator. bit 22=1 */
 449         data |= 0x400000;
 450         /* 5. Trigger Fw to operate the command. bit 31=1 */
 451         data |= 0x80000000;
 452
 453         /* 6. Write operation. We can not write if bit 31 is 1. */
 454         read_nic_dword(dev, QPNR, &tmp);
 455         while (tmp & 0x80000000) {
 456                 /* If FW can not finish RF-R/W for more than ?? times.
 457                    We must reset FW. */
 458                 if (time++ < 100) {
 459                         udelay(10);
 460                         read_nic_dword(dev, QPNR, &tmp);
 461                 } else {
 462                         break;
 463                 }
 464         }
 465         /* 7. No matter check bit. We always force the write.
 466            Because FW will not accept the command. */
 467         write_nic_dword(dev, QPNR, data);
 468         /* According to test, we must delay 20us to wait firmware
 469            to finish RF write operation. */
 470         /* We support delay in firmware side now. */
 471
 472 }
 473
 474
 475 /******************************************************************************
 476  * function:  This function reads BB parameters from header file we generate,
 477  *            and do register read/write
 478  * input:     net_device        *dev
 479  * output:    none
 480  * return:    none
 481  * notice:    BB parameters may change all the time, so please make
 482  *            sure it has been synced with the newest.
 483  *****************************************************************************/
 484 void rtl8192_phy_configmac(struct net_device *dev)
 485 {
 486         u32 dwArrayLen = 0, i;
 487         u32 *pdwArray = NULL;
 488         struct r8192_priv *priv = ieee80211_priv(dev);
 489
 490         if (priv->btxpowerdata_readfromEEPORM) {
 491                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 492                 dwArrayLen = MACPHY_Array_PGLength;
 493                 pdwArray = rtl819XMACPHY_Array_PG;
 494
 495         } else {
 496                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
 497                 dwArrayLen = MACPHY_ArrayLength;
 498                 pdwArray = rtl819XMACPHY_Array;
 499         }
 500         for (i = 0; i < dwArrayLen; i = i+3) {
 501                 if (pdwArray[i] == 0x318) {
 502                         pdwArray[i+2] = 0x00000800;
 503                 }
 504
 505                 RT_TRACE(COMP_DBG,
 506                          "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
 507                          pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 508                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
 509                                  pdwArray[i+2]);
 510         }
 511         return;
 512
 513 }
 514
 515 /******************************************************************************
 516  * function:  This function does dirty work
 517  * input:     net_device        *dev
 518  *            u8                ConfigType
 519  * output:    none
 520  * return:    none
 521  * notice:    BB parameters may change all the time, so please make
 522  *            sure it has been synced with the newest.
 523  *****************************************************************************/
 524
 525 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 526 {
 527         u32 i;
 528
 529 #ifdef TO_DO_LIST
 530         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
 531         if (Adapter->bInHctTest) {
 532                 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
 533                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
 534                 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
 535                 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
 536         }
 537 #endif
 538         if (ConfigType == BaseBand_Config_PHY_REG) {
 539                 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
 540                         rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i],
 541                                          bMaskDWord,
 542                                          rtl819XPHY_REG_1T2RArray[i+1]);
 543                         RT_TRACE(COMP_DBG,
 544                                  "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
 545                                  i, rtl819XPHY_REG_1T2RArray[i],
 546                                  rtl819XPHY_REG_1T2RArray[i+1]);
 547                 }
 548         } else if (ConfigType == BaseBand_Config_AGC_TAB) {
 549                 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
 550                         rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i],
 551                                          bMaskDWord, rtl819XAGCTAB_Array[i+1]);
 552                         RT_TRACE(COMP_DBG,
 553                                  "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
 554                                  i, rtl819XAGCTAB_Array[i],
 555                                  rtl819XAGCTAB_Array[i+1]);
 556                 }
 557         }
 558         return;
 559
 560
 561 }
 562 /******************************************************************************
 563  * function:  This function initializes Register definition offset for
 564  *            Radio Path A/B/C/D
 565  * input:     net_device        *dev
 566  * output:    none
 567  * return:    none
 568  * notice:    Initialization value here is constant and it should never
 569  *            be changed
 570  *****************************************************************************/
 571 void rtl8192_InitBBRFRegDef(struct net_device *dev)
 572 {
 573         struct r8192_priv *priv = ieee80211_priv(dev);
 574         /* RF Interface Software Control */
 575         /* 16 LSBs if read 32-bit from 0x870 */
 576         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 577         /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 578         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 579         /* 16 LSBs if read 32-bit from 0x874 */
 580         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 581         /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 582         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 583
 584         /* RF Interface Readback Value */
 585         /* 16 LSBs if read 32-bit from 0x8E0 */
 586         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 587         /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 588         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 589         /* 16 LSBs if read 32-bit from 0x8E4 */
 590         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 591         /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 592         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 593
 594         /* RF Interface Output (and Enable) */
 595         /* 16 LSBs if read 32-bit from 0x860 */
 596         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
 597         /* 16 LSBs if read 32-bit from 0x864 */
 598         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
 599         /* 16 LSBs if read 32-bit from 0x868 */
 600         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
 601         /* 16 LSBs if read 32-bit from 0x86C */
 602         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
 603
 604         /* RF Interface (Output and) Enable */
 605         /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 606         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
 607         /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 608         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
 609         /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
 610         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
 611         /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
 612         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
 613
 614         /* Addr of LSSI. Write RF register by driver */
 615         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
 616         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 617         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 618         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 619
 620         /* RF parameter */
 621         /* BB Band Select */
 622         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 623         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 624         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 625         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 626
 627         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 628         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
 629         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
 630         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
 631         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
 632
 633         /* Tranceiver A~D HSSI Parameter-1 */
 634         /* wire control parameter1 */
 635         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 636         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 637         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
 638         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
 639
 640         /* Tranceiver A~D HSSI Parameter-2 */
 641         /* wire control parameter2 */
 642         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 643         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 644         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
 645         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 646
 647         /* RF Switch Control */
 648         /* TR/Ant switch control */
 649         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 650         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 651         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 652         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 653
 654         /* AGC control 1 */
 655         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 656         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 657         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 658         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 659
 660         /* AGC control 2 */
 661         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 662         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 663         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 664         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 665
 666         /* RX AFE control 1 */
 667         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 668         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 669         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 670         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 671
 672         /* RX AFE control 1 */
 673         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 674         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 675         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 676         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 677
 678         /* Tx AFE control 1 */
 679         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 680         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 681         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 682         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 683
 684         /* Tx AFE control 2 */
 685         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 686         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 687         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 688         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 689
 690         /* Tranceiver LSSI Readback */
 691         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 692         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 693         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 694         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 695
 696 }
 697 /******************************************************************************
 698  * function:  This function is to write register and then readback to make
 699  *            sure whether BB and RF is OK
 700  * input:     net_device        *dev
 701  *            HW90_BLOCK_E      CheckBlock
 702  *            RF90_RADIO_PATH_E eRFPath  //only used when checkblock is
 703  *                                       //HW90_BLOCK_RF
 704  * output:    none
 705  * return:    return whether BB and RF is ok (0:OK, 1:Fail)
 706  * notice:    This function may be removed in the ASIC
 707  ******************************************************************************/
 708 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
 709                             RF90_RADIO_PATH_E eRFPath)
 710 {
 711         u8 ret = 0;
 712         u32 i, CheckTimes = 4, dwRegRead = 0;
 713         u32 WriteAddr[4];
 714         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 715         /* Initialize register address offset to be checked */
 716         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 717         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 718         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 719         WriteAddr[HW90_BLOCK_RF] = 0x3;
 720         RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __FUNCTION__, CheckBlock);
 721         for (i = 0; i < CheckTimes; i++) {
 722
 723                 /* Write data to register and readback */
 724                 switch (CheckBlock) {
 725                 case HW90_BLOCK_MAC:
 726                         RT_TRACE(COMP_ERR,
 727                                  "PHY_CheckBBRFOK(): Never Write 0x100 here!");
 728                         break;
 729
 730                 case HW90_BLOCK_PHY0:
 731                 case HW90_BLOCK_PHY1:
 732                         write_nic_dword(dev, WriteAddr[CheckBlock],
 733                                         WriteData[i]);
 734                         read_nic_dword(dev, WriteAddr[CheckBlock], &dwRegRead);
 735                         break;
 736
 737                 case HW90_BLOCK_RF:
 738                         WriteData[i] &= 0xfff;
 739                         rtl8192_phy_SetRFReg(dev, eRFPath,
 740                                              WriteAddr[HW90_BLOCK_RF],
 741                                              bMask12Bits, WriteData[i]);
 742                         /* TODO: we should not delay for such a long time.
 743                            Ask SD3 */
 744                         msleep(1);
 745                         dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath,
 746                                                            WriteAddr[HW90_BLOCK_RF],
 747                                                            bMask12Bits);
 748                         msleep(1);
 749                         break;
 750
 751                 default:
 752                         ret = 1;
 753                         break;
 754                 }
 755
 756
 757                 /* Check whether readback data is correct */
 758                 if (dwRegRead != WriteData[i]) {
 759                         RT_TRACE((COMP_PHY|COMP_ERR),
 760                                  "error dwRegRead: %x, WriteData: %x\n",
 761                                  dwRegRead, WriteData[i]);
 762                         ret = 1;
 763                         break;
 764                 }
 765         }
 766
 767         return ret;
 768 }
 769
 770
 771 /******************************************************************************
 772  * function:  This function initializes BB&RF
 773  * input:     net_device        *dev
 774  * output:    none
 775  * return:    none
 776  * notice:    Initialization value may change all the time, so please make
 777  *            sure it has been synced with the newest.
 778  ******************************************************************************/
 779 void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 780 {
 781         struct r8192_priv *priv = ieee80211_priv(dev);
 782         u8 reg_u8 = 0, eCheckItem = 0, rtStatus = 0;
 783         u32 reg_u32 = 0;
 784         /**************************************
 785          * <1> Initialize BaseBand
 786          *************************************/
 787
 788         /* --set BB Global Reset-- */
 789         read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
 790         write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
 791         mdelay(50);
 792         /* ---set BB reset Active--- */
 793         read_nic_dword(dev, CPU_GEN, &reg_u32);
 794         write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
 795
 796         /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
 797         /* TODO: this function should be removed on ASIC */
 798         for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0;
 799              eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
 800                 /* don't care RF path */
 801                 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem,
 802                                                     (RF90_RADIO_PATH_E)0);
 803                 if (rtStatus != 0) {
 804                         RT_TRACE((COMP_ERR | COMP_PHY),
 805                                  "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
 806                                  eCheckItem-1);
 807                         return;
 808                 }
 809         }
 810         /* ---- Set CCK and OFDM Block "OFF"---- */
 811         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 812         /* ----BB Register Initilazation---- */
 813         /* ==m==>Set PHY REG From Header<==m== */
 814         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 815
 816         /* ----Set BB reset de-Active---- */
 817         read_nic_dword(dev, CPU_GEN, &reg_u32);
 818         write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
 819
 820         /* ----BB AGC table Initialization---- */
 821         /* ==m==>Set PHY REG From Header<==m== */
 822         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 823
 824         /* ----Enable XSTAL ---- */
 825         write_nic_byte_E(dev, 0x5e, 0x00);
 826         if (priv->card_8192_version == (u8)VERSION_819xU_A) {
 827                 /* Antenna gain offset from B/C/D to A */
 828                 reg_u32 = (priv->AntennaTxPwDiff[1]<<4 |
 829                            priv->AntennaTxPwDiff[0]);
 830                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
 831                                  reg_u32);
 832
 833                 /* XSTALLCap */
 834                 reg_u32 = priv->CrystalCap & 0xf;
 835                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
 836                                  reg_u32);
 837         }
 838
 839         /* Check if the CCK HighPower is turned ON.
 840            This is used to calculate PWDB. */
 841         priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
 842                                                      rFPGA0_XA_HSSIParameter2,
 843                                                      0x200);
 844         return;
 845 }
 846 /******************************************************************************
 847  * function:  This function initializes BB&RF
 848  * input:     net_device        *dev
 849  * output:    none
 850  * return:    none
 851  * notice:    Initialization value may change all the time, so please make
 852  *            sure it has been synced with the newest.
 853  *****************************************************************************/
 854 void rtl8192_BBConfig(struct net_device *dev)
 855 {
 856         rtl8192_InitBBRFRegDef(dev);
 857         /* config BB&RF. As hardCode based initialization has not been well
 858          * implemented, so use file first.
 859          * FIXME: should implement it for hardcode? */
 860         rtl8192_BB_Config_ParaFile(dev);
 861         return;
 862 }
 863
 864 /******************************************************************************
 865  * function:  This function obtains the initialization value of Tx power Level
 866  *            offset
 867  * input:     net_device        *dev
 868  * output:    none
 869  * return:    none
 870  *****************************************************************************/
 871 void rtl8192_phy_getTxPower(struct net_device *dev)
 872 {
 873         struct r8192_priv *priv = ieee80211_priv(dev);
 874         u8 tmp;
 875         read_nic_dword(dev, rTxAGC_Rate18_06,
 876                        &priv->MCSTxPowerLevelOriginalOffset[0]);
 877         read_nic_dword(dev, rTxAGC_Rate54_24,
 878                        &priv->MCSTxPowerLevelOriginalOffset[1]);
 879         read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
 880                        &priv->MCSTxPowerLevelOriginalOffset[2]);
 881         read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
 882                        &priv->MCSTxPowerLevelOriginalOffset[3]);
 883         read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
 884                        &priv->MCSTxPowerLevelOriginalOffset[4]);
 885         read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
 886                        &priv->MCSTxPowerLevelOriginalOffset[5]);
 887
 888         /* Read rx initial gain */
 889         read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
 890         read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
 891         read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
 892         read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
 893         RT_TRACE(COMP_INIT,
 894                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
 895                  priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 896                  priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 897
 898         /* Read framesync */
 899         read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
 900         read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
 901         priv->framesyncC34 = tmp;
 902         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
 903                 rOFDM0_RxDetector3, priv->framesync);
 904
 905         /* Read SIFS (save the value read fome MACPHY_REG.txt) */
 906         read_nic_word(dev, SIFS, &priv->SifsTime);
 907
 908         return;
 909 }
 910
 911 /******************************************************************************
 912  * function:  This function sets the initialization value of Tx power Level
 913  *            offset
 914  * input:     net_device        *dev
 915  *            u8                channel
 916  * output:    none
 917  * return:    none
 918  ******************************************************************************/
 919 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 920 {
 921         struct r8192_priv *priv = ieee80211_priv(dev);
 922         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 923         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 924
 925         switch (priv->rf_chip) {
 926         case RF_8256:
 927                 /* need further implement */
 928                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 929                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 930                 break;
 931         default:
 932                 RT_TRACE((COMP_PHY|COMP_ERR),
 933                          "error RF chipID(8225 or 8258) in function %s()\n",
 934                          __FUNCTION__);
 935                 break;
 936         }
 937         return;
 938 }
 939
 940 /******************************************************************************
 941  * function:  This function checks Rf chip to do RF config
 942  * input:     net_device        *dev
 943  * output:    none
 944  * return:    only 8256 is supported
 945  ******************************************************************************/
 946 void rtl8192_phy_RFConfig(struct net_device *dev)
 947 {
 948         struct r8192_priv *priv = ieee80211_priv(dev);
 949
 950         switch (priv->rf_chip) {
 951                 case RF_8256:
 952                         PHY_RF8256_Config(dev);
 953                         break;
 954                 default:
 955                         RT_TRACE(COMP_ERR, "error chip id\n");
 956                         break;
 957         }
 958         return;
 959 }
 960
 961 /******************************************************************************
 962  * function:  This function updates Initial gain
 963  * input:     net_device        *dev
 964  * output:    none
 965  * return:    As Windows has not implemented this, wait for complement
 966  ******************************************************************************/
 967 void rtl8192_phy_updateInitGain(struct net_device *dev)
 968 {
 969         return;
 970 }
 971
 972 /******************************************************************************
 973  * function:  This function read RF parameters from general head file,
 974  *            and do RF 3-wire
 975  * input:     net_device        *dev
 976  *            RF90_RADIO_PATH_E eRFPath
 977  * output:    none
 978  * return:    return code show if RF configuration is successful(0:pass, 1:fail)
 979  * notice:    Delay may be required for RF configuration
 980  *****************************************************************************/
 981 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
 982                                       RF90_RADIO_PATH_E eRFPath)
 983 {
 984
 985         int i;
 986         u8 ret = 0;
 987
 988         switch (eRFPath) {
 989         case RF90_PATH_A:
 990                 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
 991
 992                         if (rtl819XRadioA_Array[i] == 0xfe) {
 993                                 mdelay(100);
 994                                 continue;
 995                         }
 996                         rtl8192_phy_SetRFReg(dev, eRFPath,
 997                                              rtl819XRadioA_Array[i],
 998                                              bMask12Bits,
 999                                              rtl819XRadioA_Array[i+1]);
1000                         mdelay(1);
1001
1002                 }
1003                 break;
1004         case RF90_PATH_B:
1005                 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
1006
1007                         if (rtl819XRadioB_Array[i] == 0xfe) {
1008                                 mdelay(100);
1009                                 continue;
1010                         }
1011                         rtl8192_phy_SetRFReg(dev, eRFPath,
1012                                              rtl819XRadioB_Array[i],
1013                                              bMask12Bits,
1014                                              rtl819XRadioB_Array[i+1]);
1015                         mdelay(1);
1016
1017                 }
1018                 break;
1019         case RF90_PATH_C:
1020                 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1021
1022                         if (rtl819XRadioC_Array[i] == 0xfe) {
1023                                 mdelay(100);
1024                                 continue;
1025                         }
1026                         rtl8192_phy_SetRFReg(dev, eRFPath,
1027                                              rtl819XRadioC_Array[i],
1028                                              bMask12Bits,
1029                                              rtl819XRadioC_Array[i+1]);
1030                         mdelay(1);
1031
1032                 }
1033                 break;
1034         case RF90_PATH_D:
1035                 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1036
1037                         if (rtl819XRadioD_Array[i] == 0xfe) {
1038                                 mdelay(100);
1039                                 continue;
1040                         }
1041                         rtl8192_phy_SetRFReg(dev, eRFPath,
1042                                              rtl819XRadioD_Array[i],
1043                                              bMask12Bits,
1044                                              rtl819XRadioD_Array[i+1]);
1045                         mdelay(1);
1046
1047                 }
1048                 break;
1049         default:
1050                 break;
1051         }
1052
1053         return ret;
1054
1055 }
1056 /******************************************************************************
1057  * function:  This function sets Tx Power of the channel
1058  * input:     net_device        *dev
1059  *            u8                channel
1060  * output:    none
1061  * return:    none
1062  * notice:
1063  ******************************************************************************/
1064 void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1065 {
1066         struct r8192_priv *priv = ieee80211_priv(dev);
1067         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
1068         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1069
1070         switch (priv->rf_chip) {
1071         case RF_8225:
1072 #ifdef TO_DO_LIST
1073                 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1074                 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1075 #endif
1076                 break;
1077
1078         case RF_8256:
1079                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1080                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1081                 break;
1082
1083         case RF_8258:
1084                 break;
1085         default:
1086                 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1087                 break;
1088         }
1089         return;
1090 }
1091
1092 /******************************************************************************
1093  * function:  This function sets RF state on or off
1094  * input:     net_device         *dev
1095  *            RT_RF_POWER_STATE  eRFPowerState  //Power State to set
1096  * output:    none
1097  * return:    none
1098  * notice:
1099  *****************************************************************************/
1100 bool rtl8192_SetRFPowerState(struct net_device *dev,
1101                              RT_RF_POWER_STATE eRFPowerState)
1102 {
1103         bool                            bResult = true;
1104         struct r8192_priv *priv = ieee80211_priv(dev);
1105
1106         if (eRFPowerState == priv->ieee80211->eRFPowerState)
1107                 return false;
1108
1109         if (priv->SetRFPowerStateInProgress == true)
1110                 return false;
1111
1112         priv->SetRFPowerStateInProgress = true;
1113
1114         switch (priv->rf_chip) {
1115         case RF_8256:
1116                 switch (eRFPowerState) {
1117                 case eRfOn:
1118                         /* RF-A, RF-B */
1119                         /* enable RF-Chip A/B - 0x860[4] */
1120                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1121                                          0x1);
1122                         /* analog to digital on - 0x88c[9:8] */
1123                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1124                                          0x3);
1125                         /* digital to analog on - 0x880[4:3] */
1126                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1127                                          0x3);
1128                         /* rx antenna on - 0xc04[1:0] */
1129                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1130                         /* rx antenna on - 0xd04[1:0] */
1131                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1132                         /* analog to digital part2 on - 0x880[6:5] */
1133                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1134                                          0x3);
1135
1136                         break;
1137
1138                 case eRfSleep:
1139
1140                         break;
1141
1142                 case eRfOff:
1143                         /* RF-A, RF-B */
1144                         /* disable RF-Chip A/B - 0x860[4] */
1145                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1146                                          0x0);
1147                         /* analog to digital off, for power save */
1148                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1149                                          0x0); /* 0x88c[11:8] */
1150                         /* digital to analog off, for power save - 0x880[4:3] */
1151                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1152                                          0x0);
1153                         /* rx antenna off - 0xc04[3:0] */
1154                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1155                         /* rx antenna off - 0xd04[3:0] */
1156                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1157                         /* analog to digital part2 off, for power save */
1158                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1159                                          0x0); /* 0x880[6:5] */
1160
1161                         break;
1162
1163                 default:
1164                         bResult = false;
1165                         RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1166                                  __func__, eRFPowerState);
1167                         break;
1168                 }
1169                 break;
1170         default:
1171                 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1172                 break;
1173         }
1174 #ifdef TO_DO_LIST
1175         if (bResult) {
1176                 /* Update current RF state variable. */
1177                 pHalData->eRFPowerState = eRFPowerState;
1178                 switch (pHalData->RFChipID) {
1179                 case RF_8256:
1180                         switch (pHalData->eRFPowerState) {
1181                         case eRfOff:
1182                                 /* If Rf off reason is from IPS,
1183                                    LED should blink with no link */
1184                                 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1185                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1186                                 else
1187                                         /* Turn off LED if RF is not ON. */
1188                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1189                                 break;
1190
1191                         case eRfOn:
1192                                 /* Turn on RF we are still linked, which might
1193                                    happen when we quickly turn off and on HW RF.
1194                                  */
1195                                 if (pMgntInfo->bMediaConnect == TRUE)
1196                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1197                                 else
1198                                         /* Turn off LED if RF is not ON. */
1199                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1200                                 break;
1201
1202                         default:
1203                                 break;
1204                         }
1205                         break;
1206
1207                 default:
1208                         RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1209                                  __func__);
1210                         break;
1211                 }
1212
1213         }
1214 #endif
1215         priv->SetRFPowerStateInProgress = false;
1216
1217         return bResult;
1218 }
1219
1220 /******************************************************************************
1221  * function:  This function sets command table variable (struct SwChnlCmd).
1222  * input:     SwChnlCmd      *CmdTable    //table to be set
1223  *            u32            CmdTableIdx  //variable index in table to be set
1224  *            u32            CmdTableSz   //table size
1225  *            SwChnlCmdID    CmdID        //command ID to set
1226  *            u32            Para1
1227  *            u32            Para2
1228  *            u32            msDelay
1229  * output:
1230  * return:    true if finished, false otherwise
1231  * notice:
1232  ******************************************************************************/
1233 u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
1234                                  u32 CmdTableSz, SwChnlCmdID CmdID, u32 Para1,
1235                                  u32 Para2, u32 msDelay)
1236 {
1237         SwChnlCmd *pCmd;
1238
1239         if (CmdTable == NULL) {
1240                 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1241                 return false;
1242         }
1243         if (CmdTableIdx >= CmdTableSz) {
1244                 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1245                          __func__, CmdTableIdx, CmdTableSz);
1246                 return false;
1247         }
1248
1249         pCmd = CmdTable + CmdTableIdx;
1250         pCmd->CmdID = CmdID;
1251         pCmd->Para1 = Para1;
1252         pCmd->Para2 = Para2;
1253         pCmd->msDelay = msDelay;
1254
1255         return true;
1256 }
1257 /******************************************************************************
1258  * function:  This function sets channel step by step
1259  * input:     net_device        *dev
1260  *            u8                channel
1261  *            u8                *stage   //3 stages
1262  *            u8                *step
1263  *            u32               *delay   //whether need to delay
1264  * output:    store new stage, step and delay for next step
1265  *            (combine with function above)
1266  * return:    true if finished, false otherwise
1267  * notice:    Wait for simpler function to replace it
1268  *****************************************************************************/
1269 u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage,
1270                                 u8 *step, u32 *delay)
1271 {
1272         struct r8192_priv *priv = ieee80211_priv(dev);
1273         SwChnlCmd       PreCommonCmd[MAX_PRECMD_CNT];
1274         u32             PreCommonCmdCnt;
1275         SwChnlCmd       PostCommonCmd[MAX_POSTCMD_CNT];
1276         u32             PostCommonCmdCnt;
1277         SwChnlCmd       RfDependCmd[MAX_RFDEPENDCMD_CNT];
1278         u32             RfDependCmdCnt;
1279         SwChnlCmd       *CurrentCmd = NULL;
1280         u8              eRFPath;
1281
1282         RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1283                  __FUNCTION__, *stage, *step, channel);
1284         if (!IsLegalChannel(priv->ieee80211, channel)) {
1285                 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1286                 /* return true to tell upper caller function this channel
1287                    setting is finished! Or it will in while loop. */
1288                 return true;
1289         }
1290         /* FIXME: need to check whether channel is legal or not here */
1291
1292
1293         /* <1> Fill up pre common command. */
1294         PreCommonCmdCnt = 0;
1295         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1296                                       MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
1297                                       0, 0, 0);
1298         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1299                                       MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
1300
1301         /* <2> Fill up post common command. */
1302         PostCommonCmdCnt = 0;
1303
1304         rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1305                                       MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
1306
1307         /* <3> Fill up RF dependent command. */
1308         RfDependCmdCnt = 0;
1309         switch (priv->rf_chip) {
1310         case RF_8225:
1311                 if (!(channel >= 1 && channel <= 14)) {
1312                         RT_TRACE(COMP_ERR,
1313                                  "illegal channel for Zebra 8225: %d\n",
1314                                  channel);
1315                         return true;
1316                 }
1317                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1318                                               MAX_RFDEPENDCMD_CNT,
1319                                               CmdID_RF_WriteReg,
1320                                               rZebra1_Channel,
1321                                               RF_CHANNEL_TABLE_ZEBRA[channel],
1322                                               10);
1323                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1324                                               MAX_RFDEPENDCMD_CNT,
1325                                               CmdID_End, 0, 0, 0);
1326                 break;
1327
1328         case RF_8256:
1329                 /* TEST!! This is not the table for 8256!! */
1330                 if (!(channel >= 1 && channel <= 14)) {
1331                         RT_TRACE(COMP_ERR,
1332                                  "illegal channel for Zebra 8256: %d\n",
1333                                  channel);
1334                         return true;
1335                 }
1336                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1337                                               MAX_RFDEPENDCMD_CNT,
1338                                               CmdID_RF_WriteReg,
1339                                               rZebra1_Channel, channel, 10);
1340                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1341                                               MAX_RFDEPENDCMD_CNT,
1342                                               CmdID_End, 0, 0, 0);
1343                 break;
1344
1345         case RF_8258:
1346                 break;
1347
1348         default:
1349                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1350                 return true;
1351                 break;
1352         }
1353
1354
1355         do {
1356                 switch (*stage) {
1357                 case 0:
1358                         CurrentCmd = &PreCommonCmd[*step];
1359                         break;
1360                 case 1:
1361                         CurrentCmd = &RfDependCmd[*step];
1362                         break;
1363                 case 2:
1364                         CurrentCmd = &PostCommonCmd[*step];
1365                         break;
1366                 }
1367
1368                 if (CurrentCmd->CmdID == CmdID_End) {
1369                         if ((*stage) == 2) {
1370                                 (*delay) = CurrentCmd->msDelay;
1371                                 return true;
1372                         } else {
1373                                 (*stage)++;
1374                                 (*step) = 0;
1375                                 continue;
1376                         }
1377                 }
1378
1379                 switch (CurrentCmd->CmdID) {
1380                 case CmdID_SetTxPowerLevel:
1381                         if (priv->card_8192_version == (u8)VERSION_819xU_A)
1382                                 /* consider it later! */
1383                                 rtl8192_SetTxPowerLevel(dev, channel);
1384                         break;
1385                 case CmdID_WritePortUlong:
1386                         write_nic_dword(dev, CurrentCmd->Para1,
1387                                         CurrentCmd->Para2);
1388                         break;
1389                 case CmdID_WritePortUshort:
1390                         write_nic_word(dev, CurrentCmd->Para1,
1391                                        (u16)CurrentCmd->Para2);
1392                         break;
1393                 case CmdID_WritePortUchar:
1394                         write_nic_byte(dev, CurrentCmd->Para1,
1395                                        (u8)CurrentCmd->Para2);
1396                         break;
1397                 case CmdID_RF_WriteReg:
1398                         for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1399                                 rtl8192_phy_SetRFReg(dev,
1400                                                      (RF90_RADIO_PATH_E)eRFPath,
1401                                                      CurrentCmd->Para1,
1402                                                      bZebra1_ChannelNum,
1403                                                      CurrentCmd->Para2);
1404                         }
1405                         break;
1406                 default:
1407                         break;
1408                 }
1409
1410                 break;
1411         } while (true);
1412
1413         (*delay) = CurrentCmd->msDelay;
1414         (*step)++;
1415         return false;
1416 }
1417
1418 /******************************************************************************
1419  * function:  This function does actually set channel work
1420  * input:     net_device        *dev
1421  *            u8                channel
1422  * output:    none
1423  * return:    none
1424  * notice:    We should not call this function directly
1425  *****************************************************************************/
1426 void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1427 {
1428         struct r8192_priv *priv = ieee80211_priv(dev);
1429         u32     delay = 0;
1430
1431         while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1432                                              &priv->SwChnlStep, &delay)) {
1433                 if (!priv->up)
1434                         break;
1435         }
1436 }
1437 /******************************************************************************
1438  * function:  Callback routine of the work item for switch channel.
1439  * input:     net_device        *dev
1440  *
1441  * output:    none
1442  * return:    none
1443  *****************************************************************************/
1444 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1445 {
1446
1447         struct r8192_priv *priv = ieee80211_priv(dev);
1448
1449         RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1450                  priv->chan);
1451
1452
1453         rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1454
1455         RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1456 }
1457
1458 /******************************************************************************
1459  * function:  This function scheduled actual work item to set channel
1460  * input:     net_device        *dev
1461  *            u8                channel   //channel to set
1462  * output:    none
1463  * return:    return code show if workitem is scheduled (1:pass, 0:fail)
1464  * notice:    Delay may be required for RF configuration
1465  ******************************************************************************/
1466 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1467 {
1468         struct r8192_priv *priv = ieee80211_priv(dev);
1469         RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __FUNCTION__,
1470                  priv->SwChnlInProgress);
1471         if (!priv->up)
1472                 return false;
1473         if (priv->SwChnlInProgress)
1474                 return false;
1475
1476         /* -------------------------------------------- */
1477         switch (priv->ieee80211->mode) {
1478         case WIRELESS_MODE_A:
1479         case WIRELESS_MODE_N_5G:
1480                 if (channel <= 14) {
1481                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1482                         return false;
1483                 }
1484                 break;
1485         case WIRELESS_MODE_B:
1486                 if (channel > 14) {
1487                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1488                         return false;
1489                 }
1490                 break;
1491         case WIRELESS_MODE_G:
1492         case WIRELESS_MODE_N_24G:
1493                 if (channel > 14) {
1494                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1495                         return false;
1496                 }
1497                 break;
1498         }
1499         /* -------------------------------------------- */
1500
1501         priv->SwChnlInProgress = true;
1502         if (channel == 0)
1503                 channel = 1;
1504
1505         priv->chan = channel;
1506
1507         priv->SwChnlStage = 0;
1508         priv->SwChnlStep = 0;
1509         if (priv->up)
1510                 rtl8192_SwChnl_WorkItem(dev);
1511
1512         priv->SwChnlInProgress = false;
1513         return true;
1514 }
1515
1516
1517 /******************************************************************************
1518  * function:  Callback routine of the work item for set bandwidth mode.
1519  * input:     net_device         *dev
1520  * output:    none
1521  * return:    none
1522  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1523  *            test whether current work in the queue or not.//do I?
1524  *****************************************************************************/
1525 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1526 {
1527
1528         struct r8192_priv *priv = ieee80211_priv(dev);
1529         u8 regBwOpMode;
1530
1531         RT_TRACE(COMP_SWBW, "%s()  Switch to %s bandwidth\n", __func__,
1532                  priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1533
1534
1535         if (priv->rf_chip == RF_PSEUDO_11N) {
1536                 priv->SetBWModeInProgress = false;
1537                 return;
1538         }
1539
1540         /* <1> Set MAC register */
1541         read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1542
1543         switch (priv->CurrentChannelBW) {
1544         case HT_CHANNEL_WIDTH_20:
1545                 regBwOpMode |= BW_OPMODE_20MHZ;
1546                 /* We have not verify whether this register works */
1547                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1548                 break;
1549
1550         case HT_CHANNEL_WIDTH_20_40:
1551                 regBwOpMode &= ~BW_OPMODE_20MHZ;
1552                 /* We have not verify whether this register works */
1553                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1554                 break;
1555
1556         default:
1557                 RT_TRACE(COMP_ERR,
1558                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1559                          priv->CurrentChannelBW);
1560                 break;
1561         }
1562
1563         /* <2> Set PHY related register */
1564         switch (priv->CurrentChannelBW) {
1565         case HT_CHANNEL_WIDTH_20:
1566                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1567                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1568                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1569                                  0x00100000, 1);
1570
1571                 /* Correct the tx power for CCK rate in 20M. */
1572                 priv->cck_present_attentuation =
1573                         priv->cck_present_attentuation_20Mdefault +
1574                         priv->cck_present_attentuation_difference;
1575
1576                 if (priv->cck_present_attentuation > 22)
1577                         priv->cck_present_attentuation = 22;
1578                 if (priv->cck_present_attentuation < 0)
1579                         priv->cck_present_attentuation = 0;
1580                 RT_TRACE(COMP_INIT,
1581                          "20M, pHalData->CCKPresentAttentuation = %d\n",
1582                          priv->cck_present_attentuation);
1583
1584                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1585                         priv->bcck_in_ch14 = TRUE;
1586                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1587                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1588                         priv->bcck_in_ch14 = FALSE;
1589                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1590                 } else {
1591                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1592                 }
1593
1594                 break;
1595         case HT_CHANNEL_WIDTH_20_40:
1596                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1597                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1598                 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1599                                  priv->nCur40MhzPrimeSC>>1);
1600                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1601                 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1602                                  priv->nCur40MhzPrimeSC);
1603                 priv->cck_present_attentuation =
1604                         priv->cck_present_attentuation_40Mdefault +
1605                         priv->cck_present_attentuation_difference;
1606
1607                 if (priv->cck_present_attentuation > 22)
1608                         priv->cck_present_attentuation = 22;
1609                 if (priv->cck_present_attentuation < 0)
1610                         priv->cck_present_attentuation = 0;
1611
1612                 RT_TRACE(COMP_INIT,
1613                          "40M, pHalData->CCKPresentAttentuation = %d\n",
1614                          priv->cck_present_attentuation);
1615                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1616                         priv->bcck_in_ch14 = true;
1617                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1618                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1619                         priv->bcck_in_ch14 = false;
1620                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1621                 } else {
1622                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1623                 }
1624
1625                 break;
1626         default:
1627                 RT_TRACE(COMP_ERR,
1628                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1629                          priv->CurrentChannelBW);
1630                 break;
1631
1632         }
1633         /* Skip over setting of J-mode in BB register here.
1634            Default value is "None J mode". */
1635
1636         /* <3> Set RF related register */
1637         switch (priv->rf_chip) {
1638         case RF_8225:
1639 #ifdef TO_DO_LIST
1640                 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1641 #endif
1642                 break;
1643
1644         case RF_8256:
1645                 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1646                 break;
1647
1648         case RF_8258:
1649                 break;
1650
1651         case RF_PSEUDO_11N:
1652                 break;
1653
1654         default:
1655                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1656                 break;
1657         }
1658         priv->SetBWModeInProgress = false;
1659
1660         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d",
1661                  atomic_read(&priv->ieee80211->atm_swbw));
1662 }
1663
1664 /******************************************************************************
1665  * function:  This function schedules bandwidth switch work.
1666  * input:     struct net_deviceq   *dev
1667  *            HT_CHANNEL_WIDTH     bandwidth  //20M or 40M
1668  *            HT_EXTCHNL_OFFSET    offset     //Upper, Lower, or Don't care
1669  * output:    none
1670  * return:    none
1671  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1672  *            test whether current work in the queue or not.//do I?
1673  *****************************************************************************/
1674 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
1675                        HT_EXTCHNL_OFFSET offset)
1676 {
1677         struct r8192_priv *priv = ieee80211_priv(dev);
1678
1679         if (priv->SetBWModeInProgress)
1680                 return;
1681         priv->SetBWModeInProgress = true;
1682
1683         priv->CurrentChannelBW = bandwidth;
1684
1685         if (offset == HT_EXTCHNL_OFFSET_LOWER)
1686                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1687         else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1688                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1689         else
1690                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1691
1692         rtl8192_SetBWModeWorkItem(dev);
1693
1694 }
1695
1696 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1697 {
1698         struct r8192_priv *priv = ieee80211_priv(dev);
1699
1700         priv->InitialGainOperateType = Operation;
1701
1702         if (priv->up)
1703                 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1704 }
1705
1706 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1707 {
1708         struct delayed_work *dwork = container_of(work, struct delayed_work,
1709                                                   work);
1710         struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1711                                                initialgain_operate_wq);
1712         struct net_device *dev = priv->ieee80211->dev;
1713 #define SCAN_RX_INITIAL_GAIN    0x17
1714 #define POWER_DETECTION_TH      0x08
1715         u32     bitmask;
1716         u8      initial_gain;
1717         u8      Operation;
1718
1719         Operation = priv->InitialGainOperateType;
1720
1721         switch (Operation) {
1722         case IG_Backup:
1723                 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1724                 initial_gain = SCAN_RX_INITIAL_GAIN;
1725                 bitmask = bMaskByte0;
1726                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1727                         /* FW DIG OFF */
1728                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1729                 priv->initgain_backup.xaagccore1 =
1730                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1731                 priv->initgain_backup.xbagccore1 =
1732                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1733                 priv->initgain_backup.xcagccore1 =
1734                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1735                 priv->initgain_backup.xdagccore1 =
1736                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1737                 bitmask = bMaskByte2;
1738                 priv->initgain_backup.cca =
1739                         (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1740
1741                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1742                          priv->initgain_backup.xaagccore1);
1743                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1744                          priv->initgain_backup.xbagccore1);
1745                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1746                          priv->initgain_backup.xcagccore1);
1747                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1748                          priv->initgain_backup.xdagccore1);
1749                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1750                          priv->initgain_backup.cca);
1751
1752                 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n",
1753                          initial_gain);
1754                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1755                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1756                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1757                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1758                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n",
1759                          POWER_DETECTION_TH);
1760                 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1761                 break;
1762         case IG_Restore:
1763                 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1764                 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1765                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1766                         /* FW DIG OFF */
1767                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1768
1769                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1770                                  (u32)priv->initgain_backup.xaagccore1);
1771                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1772                                  (u32)priv->initgain_backup.xbagccore1);
1773                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1774                                  (u32)priv->initgain_backup.xcagccore1);
1775                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1776                                  (u32)priv->initgain_backup.xdagccore1);
1777                 bitmask  = bMaskByte2;
1778                 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1779                                  (u32)priv->initgain_backup.cca);
1780
1781                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1782                          priv->initgain_backup.xaagccore1);
1783                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1784                          priv->initgain_backup.xbagccore1);
1785                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1786                          priv->initgain_backup.xcagccore1);
1787                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1788                          priv->initgain_backup.xdagccore1);
1789                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1790                          priv->initgain_backup.cca);
1791
1792 #ifdef RTL8190P
1793                 SetTxPowerLevel8190(Adapter, priv->CurrentChannel);
1794 #endif
1795 #ifdef RTL8192E
1796                 SetTxPowerLevel8190(Adapter, priv->CurrentChannel);
1797 #endif
1798                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1799
1800                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1801                         /* FW DIG ON */
1802                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1803                 break;
1804         default:
1805                 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1806                 break;
1807         }
1808 }