drivers/staging/rtl8192u/r819xU_phy.c

   1 #include "r8192U.h"
   2 #include "r8192U_hw.h"
   3 #include "r819xU_phy.h"
   4 #include "r819xU_phyreg.h"
   5 #include "r8190_rtl8256.h"
   6 #include "r8192U_dm.h"
   7 #include "r819xU_firmware_img.h"
   8
   9 #include "dot11d.h"
  10 #include <linux/bitops.h>
  11
  12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  13         0,
  14         0x085c, /* 2412 1  */
  15         0x08dc, /* 2417 2  */
  16         0x095c, /* 2422 3  */
  17         0x09dc, /* 2427 4  */
  18         0x0a5c, /* 2432 5  */
  19         0x0adc, /* 2437 6  */
  20         0x0b5c, /* 2442 7  */
  21         0x0bdc, /* 2447 8  */
  22         0x0c5c, /* 2452 9  */
  23         0x0cdc, /* 2457 10 */
  24         0x0d5c, /* 2462 11 */
  25         0x0ddc, /* 2467 12 */
  26         0x0e5c, /* 2472 13 */
  27         0x0f72, /* 2484    */
  28 };
  29
  30
  31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
  32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
  33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  34 #define rtl819XRadioA_Array  Rtl8192UsbRadioA_Array
  35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
  36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
  37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
  38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
  39
  40 /******************************************************************************
  41  * function: This function reads BB parameters from header file we generate,
  42  *           and does register read/write
  43  * input:    u32        bitmask  //taget bit pos in the addr to be modified
  44  * output:   none
  45  * return:   u32        return the shift bit position of the mask
  46  ******************************************************************************/
  47 static u32 rtl8192_CalculateBitShift(u32 bitmask)
  48 {
  49         u32 i;
  50
  51         i = ffs(bitmask) - 1;
  52         return i;
  53 }
  54
  55 /******************************************************************************
  56  * function:  This function checks different RF type to execute legal judgement.
  57  *            If RF Path is illegal, we will return false.
  58  * input:     net_device         *dev
  59  *            u32                eRFPath
  60  * output:    none
  61  * return:    0(illegal, false), 1(legal, true)
  62  *****************************************************************************/
  63 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
  64 {
  65         u8 ret = 1;
  66         struct r8192_priv *priv = ieee80211_priv(dev);
  67
  68         if (priv->rf_type == RF_2T4R) {
  69                 ret = 0;
  70         } else if (priv->rf_type == RF_1T2R) {
  71                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  72                         ret = 1;
  73                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  74                         ret = 0;
  75         }
  76         return ret;
  77 }
  78
  79 /******************************************************************************
  80  * function:  This function sets specific bits to BB register
  81  * input:     net_device *dev
  82  *            u32        reg_addr   //target addr to be modified
  83  *            u32        bitmask    //taget bit pos to be modified
  84  *            u32        data       //value to be write
  85  * output:    none
  86  * return:    none
  87  * notice:
  88  ******************************************************************************/
  89 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
  90                       u32 data)
  91 {
  92
  93         u32 reg, bitshift;
  94
  95         if (bitmask != bMaskDWord) {
  96                 read_nic_dword(dev, reg_addr, &reg);
  97                 bitshift = rtl8192_CalculateBitShift(bitmask);
  98                 reg &= ~bitmask;
  99                 reg |= data << bitshift;
 100                 write_nic_dword(dev, reg_addr, reg);
 101         } else {
 102                 write_nic_dword(dev, reg_addr, data);
 103         }
 104         return;
 105 }
 106
 107 /******************************************************************************
 108  * function:  This function reads specific bits from BB register
 109  * input:     net_device        *dev
 110  *            u32               reg_addr   //target addr to be readback
 111  *            u32               bitmask    //taget bit pos to be readback
 112  * output:    none
 113  * return:    u32               data       //the readback register value
 114  * notice:
 115  ******************************************************************************/
 116 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
 117 {
 118         u32 reg, bitshift;
 119
 120         read_nic_dword(dev, reg_addr, &reg);
 121         bitshift = rtl8192_CalculateBitShift(bitmask);
 122
 123         return (reg & bitmask) >> bitshift;
 124 }
 125
 126 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 127                               u32 offset);
 128
 129 static void phy_FwRFSerialWrite(struct net_device *dev,
 130                                 RF90_RADIO_PATH_E eRFPath, u32  offset,
 131                                 u32  data);
 132
 133 /******************************************************************************
 134  * function:  This function reads register from RF chip
 135  * input:     net_device        *dev
 136  *            RF90_RADIO_PATH_E eRFPath    //radio path of A/B/C/D
 137  *            u32               offset     //target address to be read
 138  * output:    none
 139  * return:    u32               readback value
 140  * notice:    There are three types of serial operations:
 141  *            (1) Software serial write.
 142  *            (2)Hardware LSSI-Low Speed Serial Interface.
 143  *            (3)Hardware HSSI-High speed serial write.
 144  *            Driver here need to implement (1) and (2)
 145  *            ---need more spec for this information.
 146  ******************************************************************************/
 147 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
 148                                     RF90_RADIO_PATH_E eRFPath, u32 offset)
 149 {
 150         struct r8192_priv *priv = ieee80211_priv(dev);
 151         u32 ret = 0;
 152         u32 new_offset = 0;
 153         BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
 154
 155         rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 156         /* Make sure RF register offset is correct */
 157         offset &= 0x3f;
 158
 159         /* Switch page for 8256 RF IC */
 160         if (priv->rf_chip == RF_8256) {
 161                 if (offset >= 31) {
 162                         priv->RfReg0Value[eRFPath] |= 0x140;
 163                         /* Switch to Reg_Mode2 for Reg 31-45 */
 164                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 165                                          bMaskDWord,
 166                                          priv->RfReg0Value[eRFPath]<<16);
 167                         /* Modify offset */
 168                         new_offset = offset - 30;
 169                 } else if (offset >= 16) {
 170                         priv->RfReg0Value[eRFPath] |= 0x100;
 171                         priv->RfReg0Value[eRFPath] &= (~0x40);
 172                         /* Switch to Reg_Mode1 for Reg16-30 */
 173                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 174                                          bMaskDWord,
 175                                          priv->RfReg0Value[eRFPath]<<16);
 176
 177                         new_offset = offset - 15;
 178                 } else {
 179                         new_offset = offset;
 180                 }
 181         } else {
 182                 RT_TRACE((COMP_PHY|COMP_ERR),
 183                          "check RF type here, need to be 8256\n");
 184                 new_offset = offset;
 185         }
 186         /* Put desired read addr to LSSI control Register */
 187         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
 188                          new_offset);
 189         /* Issue a posedge trigger */
 190         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 191         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 192
 193
 194         /* TODO: we should not delay such a long time. Ask for help from SD3 */
 195         usleep_range(1000, 1000);
 196
 197         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
 198                                  bLSSIReadBackData);
 199
 200
 201         /* Switch back to Reg_Mode0 */
 202         if (priv->rf_chip == RF_8256) {
 203                 priv->RfReg0Value[eRFPath] &= 0xebf;
 204
 205                 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
 206                                  priv->RfReg0Value[eRFPath] << 16);
 207         }
 208
 209         return ret;
 210 }
 211
 212 /******************************************************************************
 213  * function:  This function writes data to RF register
 214  * input:     net_device        *dev
 215  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 216  *            u32               offset   //target address to be written
 217  *            u32               data     //the new register data to be written
 218  * output:    none
 219  * return:    none
 220  * notice:    For RF8256 only.
 221  * ===========================================================================
 222  * Reg Mode     RegCTL[1]       RegCTL[0]               Note
 223  *              (Reg00[12])     (Reg00[10])
 224  * ===========================================================================
 225  * Reg_Mode0    0               x                       Reg 0 ~ 15(0x0 ~ 0xf)
 226  * ---------------------------------------------------------------------------
 227  * Reg_Mode1    1               0                       Reg 16 ~ 30(0x1 ~ 0xf)
 228  * ---------------------------------------------------------------------------
 229  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 230  * ---------------------------------------------------------------------------
 231  *****************************************************************************/
 232 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
 233                                       RF90_RADIO_PATH_E eRFPath, u32 offset,
 234                                       u32 data)
 235 {
 236         struct r8192_priv *priv = ieee80211_priv(dev);
 237         u32 DataAndAddr = 0, new_offset = 0;
 238         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 239
 240         offset &= 0x3f;
 241         if (priv->rf_chip == RF_8256) {
 242
 243                 if (offset >= 31) {
 244                         priv->RfReg0Value[eRFPath] |= 0x140;
 245                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 246                                          bMaskDWord,
 247                                          priv->RfReg0Value[eRFPath] << 16);
 248                         new_offset = offset - 30;
 249                 } else if (offset >= 16) {
 250                         priv->RfReg0Value[eRFPath] |= 0x100;
 251                         priv->RfReg0Value[eRFPath] &= (~0x40);
 252                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 253                                          bMaskDWord,
 254                                          priv->RfReg0Value[eRFPath]<<16);
 255                         new_offset = offset - 15;
 256                 } else {
 257                         new_offset = offset;
 258                 }
 259         } else {
 260                 RT_TRACE((COMP_PHY|COMP_ERR),
 261                          "check RF type here, need to be 8256\n");
 262                 new_offset = offset;
 263         }
 264
 265         /* Put write addr in [5:0] and write data in [31:16] */
 266         DataAndAddr = (data<<16) | (new_offset&0x3f);
 267
 268         /* Write operation */
 269         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 270
 271
 272         if (offset == 0x0)
 273                 priv->RfReg0Value[eRFPath] = data;
 274
 275         /* Switch back to Reg_Mode0 */
 276         if (priv->rf_chip == RF_8256) {
 277                 if (offset != 0) {
 278                         priv->RfReg0Value[eRFPath] &= 0xebf;
 279                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 280                                          bMaskDWord,
 281                                          priv->RfReg0Value[eRFPath] << 16);
 282                 }
 283         }
 284         return;
 285 }
 286
 287 /******************************************************************************
 288  * function:  This function set specific bits to RF register
 289  * input:     net_device        dev
 290  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 291  *            u32               reg_addr //target addr to be modified
 292  *            u32               bitmask  //taget bit pos to be modified
 293  *            u32               data     //value to be written
 294  * output:    none
 295  * return:    none
 296  * notice:
 297  *****************************************************************************/
 298 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 299                           u32 reg_addr, u32 bitmask, u32 data)
 300 {
 301         struct r8192_priv *priv = ieee80211_priv(dev);
 302         u32 reg, bitshift;
 303
 304         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 305                 return;
 306
 307         if (priv->Rf_Mode == RF_OP_By_FW) {
 308                 if (bitmask != bMask12Bits) {
 309                         /* RF data is 12 bits only */
 310                         reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 311                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 312                         reg &= ~bitmask;
 313                         reg |= data << bitshift;
 314
 315                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
 316                 } else {
 317                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
 318                 }
 319
 320                 udelay(200);
 321
 322         } else {
 323                 if (bitmask != bMask12Bits) {
 324                         /* RF data is 12 bits only */
 325                         reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 326                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 327                         reg &= ~bitmask;
 328                         reg |= data << bitshift;
 329
 330                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
 331                 } else {
 332                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
 333                 }
 334         }
 335         return;
 336 }
 337
 338 /******************************************************************************
 339  * function:  This function reads specific bits from RF register
 340  * input:     net_device        *dev
 341  *            u32               reg_addr //target addr to be readback
 342  *            u32               bitmask  //taget bit pos to be readback
 343  * output:    none
 344  * return:    u32               data     //the readback register value
 345  * notice:
 346  *****************************************************************************/
 347 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 348                            u32 reg_addr, u32 bitmask)
 349 {
 350         u32 reg, bitshift;
 351         struct r8192_priv *priv = ieee80211_priv(dev);
 352
 353
 354         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 355                 return 0;
 356         if (priv->Rf_Mode == RF_OP_By_FW) {
 357                 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 358                 bitshift =  rtl8192_CalculateBitShift(bitmask);
 359                 reg = (reg & bitmask) >> bitshift;
 360                 udelay(200);
 361                 return reg;
 362         } else {
 363                 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 364                 bitshift =  rtl8192_CalculateBitShift(bitmask);
 365                 reg = (reg & bitmask) >> bitshift;
 366                 return reg;
 367         }
 368 }
 369
 370 /******************************************************************************
 371  * function:  We support firmware to execute RF-R/W.
 372  * input:     net_device        *dev
 373  *            RF90_RADIO_PATH_E eRFPath
 374  *            u32               offset
 375  * output:    none
 376  * return:    u32
 377  * notice:
 378  ****************************************************************************/
 379 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 380                               u32 offset)
 381 {
 382         u32             reg = 0;
 383         u32             data = 0;
 384         u8              time = 0;
 385         u32             tmp;
 386
 387         /* Firmware RF Write control.
 388          * We can not execute the scheme in the initial step.
 389          * Otherwise, RF-R/W will waste much time.
 390          * This is only for site survey. */
 391         /* 1. Read operation need not insert data. bit 0-11 */
 392         /* 2. Write RF register address. bit 12-19 */
 393         data |= ((offset&0xFF)<<12);
 394         /* 3. Write RF path.  bit 20-21 */
 395         data |= ((eRFPath&0x3)<<20);
 396         /* 4. Set RF read indicator. bit 22=0 */
 397         /* 5. Trigger Fw to operate the command. bit 31 */
 398         data |= 0x80000000;
 399         /* 6. We can not execute read operation if bit 31 is 1. */
 400         read_nic_dword(dev, QPNR, &tmp);
 401         while (tmp & 0x80000000) {
 402                 /* If FW can not finish RF-R/W for more than ?? times.
 403                    We must reset FW. */
 404                 if (time++ < 100) {
 405                         udelay(10);
 406                         read_nic_dword(dev, QPNR, &tmp);
 407                 } else {
 408                         break;
 409                 }
 410         }
 411         /* 7. Execute read operation. */
 412         write_nic_dword(dev, QPNR, data);
 413         /* 8. Check if firmware send back RF content. */
 414         read_nic_dword(dev, QPNR, &tmp);
 415         while (tmp & 0x80000000) {
 416                 /* If FW can not finish RF-R/W for more than ?? times.
 417                    We must reset FW. */
 418                 if (time++ < 100) {
 419                         udelay(10);
 420                         read_nic_dword(dev, QPNR, &tmp);
 421                 } else {
 422                         return 0;
 423                 }
 424         }
 425         read_nic_dword(dev, RF_DATA, &reg);
 426
 427         return reg;
 428 }
 429
 430 /******************************************************************************
 431  * function:  We support firmware to execute RF-R/W.
 432  * input:     net_device        *dev
 433  *            RF90_RADIO_PATH_E eRFPath
 434  *            u32               offset
 435  *            u32               data
 436  * output:    none
 437  * return:    none
 438  * notice:
 439  ****************************************************************************/
 440 static void phy_FwRFSerialWrite(struct net_device *dev,
 441                                 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
 442 {
 443         u8      time = 0;
 444         u32     tmp;
 445
 446         /* Firmware RF Write control.
 447          * We can not execute the scheme in the initial step.
 448          * Otherwise, RF-R/W will waste much time.
 449          * This is only for site survey. */
 450
 451         /* 1. Set driver write bit and 12 bit data. bit 0-11 */
 452         /* 2. Write RF register address. bit 12-19 */
 453         data |= ((offset&0xFF)<<12);
 454         /* 3. Write RF path.  bit 20-21 */
 455         data |= ((eRFPath&0x3)<<20);
 456         /* 4. Set RF write indicator. bit 22=1 */
 457         data |= 0x400000;
 458         /* 5. Trigger Fw to operate the command. bit 31=1 */
 459         data |= 0x80000000;
 460
 461         /* 6. Write operation. We can not write if bit 31 is 1. */
 462         read_nic_dword(dev, QPNR, &tmp);
 463         while (tmp & 0x80000000) {
 464                 /* If FW can not finish RF-R/W for more than ?? times.
 465                    We must reset FW. */
 466                 if (time++ < 100) {
 467                         udelay(10);
 468                         read_nic_dword(dev, QPNR, &tmp);
 469                 } else {
 470                         break;
 471                 }
 472         }
 473         /* 7. No matter check bit. We always force the write.
 474            Because FW will not accept the command. */
 475         write_nic_dword(dev, QPNR, data);
 476         /* According to test, we must delay 20us to wait firmware
 477            to finish RF write operation. */
 478         /* We support delay in firmware side now. */
 479 }
 480
 481 /******************************************************************************
 482  * function:  This function reads BB parameters from header file we generate,
 483  *            and do register read/write
 484  * input:     net_device        *dev
 485  * output:    none
 486  * return:    none
 487  * notice:    BB parameters may change all the time, so please make
 488  *            sure it has been synced with the newest.
 489  *****************************************************************************/
 490 void rtl8192_phy_configmac(struct net_device *dev)
 491 {
 492         u32 dwArrayLen = 0, i;
 493         u32 *pdwArray = NULL;
 494         struct r8192_priv *priv = ieee80211_priv(dev);
 495
 496         if (priv->btxpowerdata_readfromEEPORM) {
 497                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 498                 dwArrayLen = MACPHY_Array_PGLength;
 499                 pdwArray = rtl819XMACPHY_Array_PG;
 500
 501         } else {
 502                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
 503                 dwArrayLen = MACPHY_ArrayLength;
 504                 pdwArray = rtl819XMACPHY_Array;
 505         }
 506         for (i = 0; i < dwArrayLen; i = i+3) {
 507                 if (pdwArray[i] == 0x318) {
 508                         pdwArray[i+2] = 0x00000800;
 509                 }
 510
 511                 RT_TRACE(COMP_DBG,
 512                          "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
 513                          pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 514                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
 515                                  pdwArray[i+2]);
 516         }
 517         return;
 518 }
 519
 520 /******************************************************************************
 521  * function:  This function does dirty work
 522  * input:     net_device        *dev
 523  *            u8                ConfigType
 524  * output:    none
 525  * return:    none
 526  * notice:    BB parameters may change all the time, so please make
 527  *            sure it has been synced with the newest.
 528  *****************************************************************************/
 529 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 530 {
 531         u32 i;
 532
 533 #ifdef TO_DO_LIST
 534         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
 535
 536         if (Adapter->bInHctTest) {
 537                 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
 538                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
 539                 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
 540                 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
 541         }
 542 #endif
 543         if (ConfigType == BaseBand_Config_PHY_REG) {
 544                 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
 545                         rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i],
 546                                          bMaskDWord,
 547                                          rtl819XPHY_REG_1T2RArray[i+1]);
 548                         RT_TRACE(COMP_DBG,
 549                                  "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
 550                                  i, rtl819XPHY_REG_1T2RArray[i],
 551                                  rtl819XPHY_REG_1T2RArray[i+1]);
 552                 }
 553         } else if (ConfigType == BaseBand_Config_AGC_TAB) {
 554                 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
 555                         rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i],
 556                                          bMaskDWord, rtl819XAGCTAB_Array[i+1]);
 557                         RT_TRACE(COMP_DBG,
 558                                  "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
 559                                  i, rtl819XAGCTAB_Array[i],
 560                                  rtl819XAGCTAB_Array[i+1]);
 561                 }
 562         }
 563         return;
 564 }
 565
 566 /******************************************************************************
 567  * function:  This function initializes Register definition offset for
 568  *            Radio Path A/B/C/D
 569  * input:     net_device        *dev
 570  * output:    none
 571  * return:    none
 572  * notice:    Initialization value here is constant and it should never
 573  *            be changed
 574  *****************************************************************************/
 575 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
 576 {
 577         struct r8192_priv *priv = ieee80211_priv(dev);
 578
 579         /* RF Interface Software Control */
 580         /* 16 LSBs if read 32-bit from 0x870 */
 581         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 582         /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 583         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 584         /* 16 LSBs if read 32-bit from 0x874 */
 585         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 586         /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 587         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 588
 589         /* RF Interface Readback Value */
 590         /* 16 LSBs if read 32-bit from 0x8E0 */
 591         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 592         /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 593         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 594         /* 16 LSBs if read 32-bit from 0x8E4 */
 595         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 596         /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 597         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 598
 599         /* RF Interface Output (and Enable) */
 600         /* 16 LSBs if read 32-bit from 0x860 */
 601         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
 602         /* 16 LSBs if read 32-bit from 0x864 */
 603         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
 604         /* 16 LSBs if read 32-bit from 0x868 */
 605         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
 606         /* 16 LSBs if read 32-bit from 0x86C */
 607         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
 608
 609         /* RF Interface (Output and) Enable */
 610         /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 611         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
 612         /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 613         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
 614         /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
 615         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
 616         /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
 617         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
 618
 619         /* Addr of LSSI. Write RF register by driver */
 620         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
 621         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 622         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 623         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 624
 625         /* RF parameter */
 626         /* BB Band Select */
 627         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 628         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 629         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 630         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 631
 632         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 633         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
 634         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
 635         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
 636         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
 637
 638         /* Tranceiver A~D HSSI Parameter-1 */
 639         /* wire control parameter1 */
 640         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 641         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 642         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
 643         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
 644
 645         /* Tranceiver A~D HSSI Parameter-2 */
 646         /* wire control parameter2 */
 647         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 648         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 649         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
 650         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 651
 652         /* RF Switch Control */
 653         /* TR/Ant switch control */
 654         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 655         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 656         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 657         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 658
 659         /* AGC control 1 */
 660         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 661         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 662         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 663         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 664
 665         /* AGC control 2 */
 666         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 667         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 668         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 669         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 670
 671         /* RX AFE control 1 */
 672         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 673         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 674         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 675         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 676
 677         /* RX AFE control 1 */
 678         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 679         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 680         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 681         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 682
 683         /* Tx AFE control 1 */
 684         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 685         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 686         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 687         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 688
 689         /* Tx AFE control 2 */
 690         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 691         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 692         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 693         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 694
 695         /* Tranceiver LSSI Readback */
 696         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 697         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 698         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 699         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 700 }
 701
 702 /******************************************************************************
 703  * function:  This function is to write register and then readback to make
 704  *            sure whether BB and RF is OK
 705  * input:     net_device        *dev
 706  *            HW90_BLOCK_E      CheckBlock
 707  *            RF90_RADIO_PATH_E eRFPath  //only used when checkblock is
 708  *                                       //HW90_BLOCK_RF
 709  * output:    none
 710  * return:    return whether BB and RF is ok (0:OK, 1:Fail)
 711  * notice:    This function may be removed in the ASIC
 712  ******************************************************************************/
 713 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
 714                             RF90_RADIO_PATH_E eRFPath)
 715 {
 716         u8 ret = 0;
 717         u32 i, CheckTimes = 4, reg = 0;
 718         u32 WriteAddr[4];
 719         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 720
 721         /* Initialize register address offset to be checked */
 722         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 723         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 724         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 725         WriteAddr[HW90_BLOCK_RF] = 0x3;
 726         RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
 727         for (i = 0; i < CheckTimes; i++) {
 728
 729                 /* Write data to register and readback */
 730                 switch (CheckBlock) {
 731                 case HW90_BLOCK_MAC:
 732                         RT_TRACE(COMP_ERR,
 733                                  "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
 734                         break;
 735
 736                 case HW90_BLOCK_PHY0:
 737                 case HW90_BLOCK_PHY1:
 738                         write_nic_dword(dev, WriteAddr[CheckBlock],
 739                                         WriteData[i]);
 740                         read_nic_dword(dev, WriteAddr[CheckBlock], &reg);
 741                         break;
 742
 743                 case HW90_BLOCK_RF:
 744                         WriteData[i] &= 0xfff;
 745                         rtl8192_phy_SetRFReg(dev, eRFPath,
 746                                              WriteAddr[HW90_BLOCK_RF],
 747                                              bMask12Bits, WriteData[i]);
 748                         /* TODO: we should not delay for such a long time.
 749                            Ask SD3 */
 750                         usleep_range(1000, 1000);
 751                         reg = rtl8192_phy_QueryRFReg(dev, eRFPath,
 752                                                      WriteAddr[HW90_BLOCK_RF],
 753                                                      bMask12Bits);
 754                         usleep_range(1000, 1000);
 755                         break;
 756
 757                 default:
 758                         ret = 1;
 759                         break;
 760                 }
 761
 762
 763                 /* Check whether readback data is correct */
 764                 if (reg != WriteData[i]) {
 765                         RT_TRACE((COMP_PHY|COMP_ERR),
 766                                  "error reg: %x, WriteData: %x\n",
 767                                  reg, WriteData[i]);
 768                         ret = 1;
 769                         break;
 770                 }
 771         }
 772
 773         return ret;
 774 }
 775
 776 /******************************************************************************
 777  * function:  This function initializes BB&RF
 778  * input:     net_device        *dev
 779  * output:    none
 780  * return:    none
 781  * notice:    Initialization value may change all the time, so please make
 782  *            sure it has been synced with the newest.
 783  ******************************************************************************/
 784 static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 785 {
 786         struct r8192_priv *priv = ieee80211_priv(dev);
 787         u8 reg_u8 = 0, eCheckItem = 0, status = 0;
 788         u32 reg_u32 = 0;
 789
 790         /**************************************
 791          * <1> Initialize BaseBand
 792          *************************************/
 793
 794         /* --set BB Global Reset-- */
 795         read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
 796         write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
 797         mdelay(50);
 798         /* ---set BB reset Active--- */
 799         read_nic_dword(dev, CPU_GEN, &reg_u32);
 800         write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
 801
 802         /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
 803         /* TODO: this function should be removed on ASIC */
 804         for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0;
 805              eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
 806                 /* don't care RF path */
 807                 status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem,
 808                                                   (RF90_RADIO_PATH_E)0);
 809                 if (status != 0) {
 810                         RT_TRACE((COMP_ERR | COMP_PHY),
 811                                  "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
 812                                  eCheckItem-1);
 813                         return;
 814                 }
 815         }
 816         /* ---- Set CCK and OFDM Block "OFF"---- */
 817         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 818         /* ----BB Register Initilazation---- */
 819         /* ==m==>Set PHY REG From Header<==m== */
 820         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 821
 822         /* ----Set BB reset de-Active---- */
 823         read_nic_dword(dev, CPU_GEN, &reg_u32);
 824         write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
 825
 826         /* ----BB AGC table Initialization---- */
 827         /* ==m==>Set PHY REG From Header<==m== */
 828         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 829
 830         /* ----Enable XSTAL ---- */
 831         write_nic_byte_E(dev, 0x5e, 0x00);
 832         if (priv->card_8192_version == (u8)VERSION_819xU_A) {
 833                 /* Antenna gain offset from B/C/D to A */
 834                 reg_u32 = (priv->AntennaTxPwDiff[1]<<4 |
 835                            priv->AntennaTxPwDiff[0]);
 836                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
 837                                  reg_u32);
 838
 839                 /* XSTALLCap */
 840                 reg_u32 = priv->CrystalCap & 0xf;
 841                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
 842                                  reg_u32);
 843         }
 844
 845         /* Check if the CCK HighPower is turned ON.
 846            This is used to calculate PWDB. */
 847         priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
 848                                                      rFPGA0_XA_HSSIParameter2,
 849                                                      0x200);
 850         return;
 851 }
 852
 853 /******************************************************************************
 854  * function:  This function initializes BB&RF
 855  * input:     net_device        *dev
 856  * output:    none
 857  * return:    none
 858  * notice:    Initialization value may change all the time, so please make
 859  *            sure it has been synced with the newest.
 860  *****************************************************************************/
 861 void rtl8192_BBConfig(struct net_device *dev)
 862 {
 863         rtl8192_InitBBRFRegDef(dev);
 864         /* config BB&RF. As hardCode based initialization has not been well
 865          * implemented, so use file first.
 866          * FIXME: should implement it for hardcode? */
 867         rtl8192_BB_Config_ParaFile(dev);
 868         return;
 869 }
 870
 871
 872 /******************************************************************************
 873  * function:  This function obtains the initialization value of Tx power Level
 874  *            offset
 875  * input:     net_device        *dev
 876  * output:    none
 877  * return:    none
 878  *****************************************************************************/
 879 void rtl8192_phy_getTxPower(struct net_device *dev)
 880 {
 881         struct r8192_priv *priv = ieee80211_priv(dev);
 882         u8 tmp;
 883
 884         read_nic_dword(dev, rTxAGC_Rate18_06,
 885                        &priv->MCSTxPowerLevelOriginalOffset[0]);
 886         read_nic_dword(dev, rTxAGC_Rate54_24,
 887                        &priv->MCSTxPowerLevelOriginalOffset[1]);
 888         read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
 889                        &priv->MCSTxPowerLevelOriginalOffset[2]);
 890         read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
 891                        &priv->MCSTxPowerLevelOriginalOffset[3]);
 892         read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
 893                        &priv->MCSTxPowerLevelOriginalOffset[4]);
 894         read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
 895                        &priv->MCSTxPowerLevelOriginalOffset[5]);
 896
 897         /* Read rx initial gain */
 898         read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
 899         read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
 900         read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
 901         read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
 902         RT_TRACE(COMP_INIT,
 903                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
 904                  priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 905                  priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 906
 907         /* Read framesync */
 908         read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
 909         read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
 910         priv->framesyncC34 = tmp;
 911         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
 912                 rOFDM0_RxDetector3, priv->framesync);
 913
 914         /* Read SIFS (save the value read fome MACPHY_REG.txt) */
 915         read_nic_word(dev, SIFS, &priv->SifsTime);
 916
 917         return;
 918 }
 919
 920 /******************************************************************************
 921  * function:  This function sets the initialization value of Tx power Level
 922  *            offset
 923  * input:     net_device        *dev
 924  *            u8                channel
 925  * output:    none
 926  * return:    none
 927  ******************************************************************************/
 928 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 929 {
 930         struct r8192_priv *priv = ieee80211_priv(dev);
 931         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 932         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 933
 934         switch (priv->rf_chip) {
 935         case RF_8256:
 936                 /* need further implement */
 937                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 938                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 939                 break;
 940         default:
 941                 RT_TRACE((COMP_PHY|COMP_ERR),
 942                          "error RF chipID(8225 or 8258) in function %s()\n",
 943                          __func__);
 944                 break;
 945         }
 946         return;
 947 }
 948
 949 /******************************************************************************
 950  * function:  This function checks Rf chip to do RF config
 951  * input:     net_device        *dev
 952  * output:    none
 953  * return:    only 8256 is supported
 954  ******************************************************************************/
 955 void rtl8192_phy_RFConfig(struct net_device *dev)
 956 {
 957         struct r8192_priv *priv = ieee80211_priv(dev);
 958
 959         switch (priv->rf_chip) {
 960                 case RF_8256:
 961                         PHY_RF8256_Config(dev);
 962                         break;
 963                 default:
 964                         RT_TRACE(COMP_ERR, "error chip id\n");
 965                         break;
 966         }
 967         return;
 968 }
 969
 970 /******************************************************************************
 971  * function:  This function updates Initial gain
 972  * input:     net_device        *dev
 973  * output:    none
 974  * return:    As Windows has not implemented this, wait for complement
 975  ******************************************************************************/
 976 void rtl8192_phy_updateInitGain(struct net_device *dev)
 977 {
 978         return;
 979 }
 980
 981 /******************************************************************************
 982  * function:  This function read RF parameters from general head file,
 983  *            and do RF 3-wire
 984  * input:     net_device        *dev
 985  *            RF90_RADIO_PATH_E eRFPath
 986  * output:    none
 987  * return:    return code show if RF configuration is successful(0:pass, 1:fail)
 988  * notice:    Delay may be required for RF configuration
 989  *****************************************************************************/
 990 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
 991                                       RF90_RADIO_PATH_E eRFPath)
 992 {
 993
 994         int i;
 995         u8 ret = 0;
 996
 997         switch (eRFPath) {
 998         case RF90_PATH_A:
 999                 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
1000
1001                         if (rtl819XRadioA_Array[i] == 0xfe) {
1002                                 mdelay(100);
1003                                 continue;
1004                         }
1005                         rtl8192_phy_SetRFReg(dev, eRFPath,
1006                                              rtl819XRadioA_Array[i],
1007                                              bMask12Bits,
1008                                              rtl819XRadioA_Array[i+1]);
1009                         mdelay(1);
1010
1011                 }
1012                 break;
1013         case RF90_PATH_B:
1014                 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
1015
1016                         if (rtl819XRadioB_Array[i] == 0xfe) {
1017                                 mdelay(100);
1018                                 continue;
1019                         }
1020                         rtl8192_phy_SetRFReg(dev, eRFPath,
1021                                              rtl819XRadioB_Array[i],
1022                                              bMask12Bits,
1023                                              rtl819XRadioB_Array[i+1]);
1024                         mdelay(1);
1025
1026                 }
1027                 break;
1028         case RF90_PATH_C:
1029                 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1030
1031                         if (rtl819XRadioC_Array[i] == 0xfe) {
1032                                 mdelay(100);
1033                                 continue;
1034                         }
1035                         rtl8192_phy_SetRFReg(dev, eRFPath,
1036                                              rtl819XRadioC_Array[i],
1037                                              bMask12Bits,
1038                                              rtl819XRadioC_Array[i+1]);
1039                         mdelay(1);
1040
1041                 }
1042                 break;
1043         case RF90_PATH_D:
1044                 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1045
1046                         if (rtl819XRadioD_Array[i] == 0xfe) {
1047                                 mdelay(100);
1048                                 continue;
1049                         }
1050                         rtl8192_phy_SetRFReg(dev, eRFPath,
1051                                              rtl819XRadioD_Array[i],
1052                                              bMask12Bits,
1053                                              rtl819XRadioD_Array[i+1]);
1054                         mdelay(1);
1055
1056                 }
1057                 break;
1058         default:
1059                 break;
1060         }
1061
1062         return ret;
1063
1064 }
1065
1066 /******************************************************************************
1067  * function:  This function sets Tx Power of the channel
1068  * input:     net_device        *dev
1069  *            u8                channel
1070  * output:    none
1071  * return:    none
1072  * notice:
1073  ******************************************************************************/
1074 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1075 {
1076         struct r8192_priv *priv = ieee80211_priv(dev);
1077         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
1078         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1079
1080         switch (priv->rf_chip) {
1081         case RF_8225:
1082 #ifdef TO_DO_LIST
1083                 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1084                 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1085 #endif
1086                 break;
1087
1088         case RF_8256:
1089                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1090                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1091                 break;
1092
1093         case RF_8258:
1094                 break;
1095         default:
1096                 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1097                 break;
1098         }
1099         return;
1100 }
1101
1102 /******************************************************************************
1103  * function:  This function sets RF state on or off
1104  * input:     net_device         *dev
1105  *            RT_RF_POWER_STATE  eRFPowerState  //Power State to set
1106  * output:    none
1107  * return:    none
1108  * notice:
1109  *****************************************************************************/
1110 bool rtl8192_SetRFPowerState(struct net_device *dev,
1111                              RT_RF_POWER_STATE eRFPowerState)
1112 {
1113         bool                            bResult = true;
1114         struct r8192_priv *priv = ieee80211_priv(dev);
1115
1116         if (eRFPowerState == priv->ieee80211->eRFPowerState)
1117                 return false;
1118
1119         if (priv->SetRFPowerStateInProgress == true)
1120                 return false;
1121
1122         priv->SetRFPowerStateInProgress = true;
1123
1124         switch (priv->rf_chip) {
1125         case RF_8256:
1126                 switch (eRFPowerState) {
1127                 case eRfOn:
1128                         /* RF-A, RF-B */
1129                         /* enable RF-Chip A/B - 0x860[4] */
1130                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1131                                          0x1);
1132                         /* analog to digital on - 0x88c[9:8] */
1133                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1134                                          0x3);
1135                         /* digital to analog on - 0x880[4:3] */
1136                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1137                                          0x3);
1138                         /* rx antenna on - 0xc04[1:0] */
1139                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1140                         /* rx antenna on - 0xd04[1:0] */
1141                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1142                         /* analog to digital part2 on - 0x880[6:5] */
1143                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1144                                          0x3);
1145
1146                         break;
1147
1148                 case eRfSleep:
1149
1150                         break;
1151
1152                 case eRfOff:
1153                         /* RF-A, RF-B */
1154                         /* disable RF-Chip A/B - 0x860[4] */
1155                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1156                                          0x0);
1157                         /* analog to digital off, for power save */
1158                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1159                                          0x0); /* 0x88c[11:8] */
1160                         /* digital to analog off, for power save - 0x880[4:3] */
1161                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1162                                          0x0);
1163                         /* rx antenna off - 0xc04[3:0] */
1164                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1165                         /* rx antenna off - 0xd04[3:0] */
1166                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1167                         /* analog to digital part2 off, for power save */
1168                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1169                                          0x0); /* 0x880[6:5] */
1170
1171                         break;
1172
1173                 default:
1174                         bResult = false;
1175                         RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1176                                  __func__, eRFPowerState);
1177                         break;
1178                 }
1179                 break;
1180         default:
1181                 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1182                 break;
1183         }
1184 #ifdef TO_DO_LIST
1185         if (bResult) {
1186                 /* Update current RF state variable. */
1187                 pHalData->eRFPowerState = eRFPowerState;
1188                 switch (pHalData->RFChipID) {
1189                 case RF_8256:
1190                         switch (pHalData->eRFPowerState) {
1191                         case eRfOff:
1192                                 /* If Rf off reason is from IPS,
1193                                    LED should blink with no link */
1194                                 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1195                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1196                                 else
1197                                         /* Turn off LED if RF is not ON. */
1198                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1199                                 break;
1200
1201                         case eRfOn:
1202                                 /* Turn on RF we are still linked, which might
1203                                    happen when we quickly turn off and on HW RF.
1204                                  */
1205                                 if (pMgntInfo->bMediaConnect == TRUE)
1206                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1207                                 else
1208                                         /* Turn off LED if RF is not ON. */
1209                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1210                                 break;
1211
1212                         default:
1213                                 break;
1214                         }
1215                         break;
1216
1217                 default:
1218                         RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1219                                  __func__);
1220                         break;
1221                 }
1222
1223         }
1224 #endif
1225         priv->SetRFPowerStateInProgress = false;
1226
1227         return bResult;
1228 }
1229
1230 /******************************************************************************
1231  * function:  This function sets command table variable (struct SwChnlCmd).
1232  * input:     SwChnlCmd      *CmdTable    //table to be set
1233  *            u32            CmdTableIdx  //variable index in table to be set
1234  *            u32            CmdTableSz   //table size
1235  *            SwChnlCmdID    CmdID        //command ID to set
1236  *            u32            Para1
1237  *            u32            Para2
1238  *            u32            msDelay
1239  * output:
1240  * return:    true if finished, false otherwise
1241  * notice:
1242  ******************************************************************************/
1243 static u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
1244                                         u32 CmdTableSz, SwChnlCmdID CmdID,
1245                                         u32 Para1, u32 Para2, u32 msDelay)
1246 {
1247         SwChnlCmd *pCmd;
1248
1249         if (CmdTable == NULL) {
1250                 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1251                 return false;
1252         }
1253         if (CmdTableIdx >= CmdTableSz) {
1254                 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1255                          __func__, CmdTableIdx, CmdTableSz);
1256                 return false;
1257         }
1258
1259         pCmd = CmdTable + CmdTableIdx;
1260         pCmd->CmdID = CmdID;
1261         pCmd->Para1 = Para1;
1262         pCmd->Para2 = Para2;
1263         pCmd->msDelay = msDelay;
1264
1265         return true;
1266 }
1267
1268 /******************************************************************************
1269  * function:  This function sets channel step by step
1270  * input:     net_device        *dev
1271  *            u8                channel
1272  *            u8                *stage   //3 stages
1273  *            u8                *step
1274  *            u32               *delay   //whether need to delay
1275  * output:    store new stage, step and delay for next step
1276  *            (combine with function above)
1277  * return:    true if finished, false otherwise
1278  * notice:    Wait for simpler function to replace it
1279  *****************************************************************************/
1280 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1281                                        u8 *stage, u8 *step, u32 *delay)
1282 {
1283         struct r8192_priv *priv = ieee80211_priv(dev);
1284         SwChnlCmd       PreCommonCmd[MAX_PRECMD_CNT];
1285         u32             PreCommonCmdCnt;
1286         SwChnlCmd       PostCommonCmd[MAX_POSTCMD_CNT];
1287         u32             PostCommonCmdCnt;
1288         SwChnlCmd       RfDependCmd[MAX_RFDEPENDCMD_CNT];
1289         u32             RfDependCmdCnt;
1290         SwChnlCmd       *CurrentCmd = NULL;
1291         u8              eRFPath;
1292
1293         RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1294                  __func__, *stage, *step, channel);
1295         if (!IsLegalChannel(priv->ieee80211, channel)) {
1296                 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1297                 /* return true to tell upper caller function this channel
1298                    setting is finished! Or it will in while loop. */
1299                 return true;
1300         }
1301         /* FIXME: need to check whether channel is legal or not here */
1302
1303
1304         /* <1> Fill up pre common command. */
1305         PreCommonCmdCnt = 0;
1306         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1307                                       MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
1308                                       0, 0, 0);
1309         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1310                                       MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
1311
1312         /* <2> Fill up post common command. */
1313         PostCommonCmdCnt = 0;
1314
1315         rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1316                                       MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
1317
1318         /* <3> Fill up RF dependent command. */
1319         RfDependCmdCnt = 0;
1320         switch (priv->rf_chip) {
1321         case RF_8225:
1322                 if (!(channel >= 1 && channel <= 14)) {
1323                         RT_TRACE(COMP_ERR,
1324                                  "illegal channel for Zebra 8225: %d\n",
1325                                  channel);
1326                         return true;
1327                 }
1328                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1329                                               MAX_RFDEPENDCMD_CNT,
1330                                               CmdID_RF_WriteReg,
1331                                               rZebra1_Channel,
1332                                               RF_CHANNEL_TABLE_ZEBRA[channel],
1333                                               10);
1334                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1335                                               MAX_RFDEPENDCMD_CNT,
1336                                               CmdID_End, 0, 0, 0);
1337                 break;
1338
1339         case RF_8256:
1340                 /* TEST!! This is not the table for 8256!! */
1341                 if (!(channel >= 1 && channel <= 14)) {
1342                         RT_TRACE(COMP_ERR,
1343                                  "illegal channel for Zebra 8256: %d\n",
1344                                  channel);
1345                         return true;
1346                 }
1347                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1348                                               MAX_RFDEPENDCMD_CNT,
1349                                               CmdID_RF_WriteReg,
1350                                               rZebra1_Channel, channel, 10);
1351                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1352                                               MAX_RFDEPENDCMD_CNT,
1353                                               CmdID_End, 0, 0, 0);
1354                 break;
1355
1356         case RF_8258:
1357                 break;
1358
1359         default:
1360                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1361                 return true;
1362                 break;
1363         }
1364
1365
1366         do {
1367                 switch (*stage) {
1368                 case 0:
1369                         CurrentCmd = &PreCommonCmd[*step];
1370                         break;
1371                 case 1:
1372                         CurrentCmd = &RfDependCmd[*step];
1373                         break;
1374                 case 2:
1375                         CurrentCmd = &PostCommonCmd[*step];
1376                         break;
1377                 }
1378
1379                 if (CurrentCmd->CmdID == CmdID_End) {
1380                         if ((*stage) == 2) {
1381                                 (*delay) = CurrentCmd->msDelay;
1382                                 return true;
1383                         } else {
1384                                 (*stage)++;
1385                                 (*step) = 0;
1386                                 continue;
1387                         }
1388                 }
1389
1390                 switch (CurrentCmd->CmdID) {
1391                 case CmdID_SetTxPowerLevel:
1392                         if (priv->card_8192_version == (u8)VERSION_819xU_A)
1393                                 /* consider it later! */
1394                                 rtl8192_SetTxPowerLevel(dev, channel);
1395                         break;
1396                 case CmdID_WritePortUlong:
1397                         write_nic_dword(dev, CurrentCmd->Para1,
1398                                         CurrentCmd->Para2);
1399                         break;
1400                 case CmdID_WritePortUshort:
1401                         write_nic_word(dev, CurrentCmd->Para1,
1402                                        (u16)CurrentCmd->Para2);
1403                         break;
1404                 case CmdID_WritePortUchar:
1405                         write_nic_byte(dev, CurrentCmd->Para1,
1406                                        (u8)CurrentCmd->Para2);
1407                         break;
1408                 case CmdID_RF_WriteReg:
1409                         for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1410                                 rtl8192_phy_SetRFReg(dev,
1411                                                      (RF90_RADIO_PATH_E)eRFPath,
1412                                                      CurrentCmd->Para1,
1413                                                      bZebra1_ChannelNum,
1414                                                      CurrentCmd->Para2);
1415                         }
1416                         break;
1417                 default:
1418                         break;
1419                 }
1420
1421                 break;
1422         } while (true);
1423
1424         (*delay) = CurrentCmd->msDelay;
1425         (*step)++;
1426         return false;
1427 }
1428
1429 /******************************************************************************
1430  * function:  This function does actually set channel work
1431  * input:     net_device        *dev
1432  *            u8                channel
1433  * output:    none
1434  * return:    none
1435  * notice:    We should not call this function directly
1436  *****************************************************************************/
1437 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1438 {
1439         struct r8192_priv *priv = ieee80211_priv(dev);
1440         u32     delay = 0;
1441
1442         while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1443                                              &priv->SwChnlStep, &delay)) {
1444                 if (!priv->up)
1445                         break;
1446         }
1447 }
1448
1449 /******************************************************************************
1450  * function:  Callback routine of the work item for switch channel.
1451  * input:     net_device        *dev
1452  *
1453  * output:    none
1454  * return:    none
1455  *****************************************************************************/
1456 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1457 {
1458
1459         struct r8192_priv *priv = ieee80211_priv(dev);
1460
1461         RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1462                  priv->chan);
1463
1464
1465         rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1466
1467         RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1468 }
1469
1470 /******************************************************************************
1471  * function:  This function scheduled actual work item to set channel
1472  * input:     net_device        *dev
1473  *            u8                channel   //channel to set
1474  * output:    none
1475  * return:    return code show if workitem is scheduled (1:pass, 0:fail)
1476  * notice:    Delay may be required for RF configuration
1477  ******************************************************************************/
1478 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1479 {
1480         struct r8192_priv *priv = ieee80211_priv(dev);
1481         RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1482                  priv->SwChnlInProgress);
1483         if (!priv->up)
1484                 return false;
1485         if (priv->SwChnlInProgress)
1486                 return false;
1487
1488         /* -------------------------------------------- */
1489         switch (priv->ieee80211->mode) {
1490         case WIRELESS_MODE_A:
1491         case WIRELESS_MODE_N_5G:
1492                 if (channel <= 14) {
1493                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1494                         return false;
1495                 }
1496                 break;
1497         case WIRELESS_MODE_B:
1498                 if (channel > 14) {
1499                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1500                         return false;
1501                 }
1502                 break;
1503         case WIRELESS_MODE_G:
1504         case WIRELESS_MODE_N_24G:
1505                 if (channel > 14) {
1506                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1507                         return false;
1508                 }
1509                 break;
1510         }
1511         /* -------------------------------------------- */
1512
1513         priv->SwChnlInProgress = true;
1514         if (channel == 0)
1515                 channel = 1;
1516
1517         priv->chan = channel;
1518
1519         priv->SwChnlStage = 0;
1520         priv->SwChnlStep = 0;
1521         if (priv->up)
1522                 rtl8192_SwChnl_WorkItem(dev);
1523
1524         priv->SwChnlInProgress = false;
1525         return true;
1526 }
1527
1528 /******************************************************************************
1529  * function:  Callback routine of the work item for set bandwidth mode.
1530  * input:     net_device         *dev
1531  * output:    none
1532  * return:    none
1533  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1534  *            test whether current work in the queue or not.//do I?
1535  *****************************************************************************/
1536 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1537 {
1538
1539         struct r8192_priv *priv = ieee80211_priv(dev);
1540         u8 regBwOpMode;
1541
1542         RT_TRACE(COMP_SWBW, "%s()  Switch to %s bandwidth\n", __func__,
1543                  priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1544
1545
1546         if (priv->rf_chip == RF_PSEUDO_11N) {
1547                 priv->SetBWModeInProgress = false;
1548                 return;
1549         }
1550
1551         /* <1> Set MAC register */
1552         read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1553
1554         switch (priv->CurrentChannelBW) {
1555         case HT_CHANNEL_WIDTH_20:
1556                 regBwOpMode |= BW_OPMODE_20MHZ;
1557                 /* We have not verify whether this register works */
1558                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1559                 break;
1560
1561         case HT_CHANNEL_WIDTH_20_40:
1562                 regBwOpMode &= ~BW_OPMODE_20MHZ;
1563                 /* We have not verify whether this register works */
1564                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1565                 break;
1566
1567         default:
1568                 RT_TRACE(COMP_ERR,
1569                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1570                          priv->CurrentChannelBW);
1571                 break;
1572         }
1573
1574         /* <2> Set PHY related register */
1575         switch (priv->CurrentChannelBW) {
1576         case HT_CHANNEL_WIDTH_20:
1577                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1578                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1579                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1580                                  0x00100000, 1);
1581
1582                 /* Correct the tx power for CCK rate in 20M. */
1583                 priv->cck_present_attentuation =
1584                         priv->cck_present_attentuation_20Mdefault +
1585                         priv->cck_present_attentuation_difference;
1586
1587                 if (priv->cck_present_attentuation > 22)
1588                         priv->cck_present_attentuation = 22;
1589                 if (priv->cck_present_attentuation < 0)
1590                         priv->cck_present_attentuation = 0;
1591                 RT_TRACE(COMP_INIT,
1592                          "20M, pHalData->CCKPresentAttentuation = %d\n",
1593                          priv->cck_present_attentuation);
1594
1595                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1596                         priv->bcck_in_ch14 = TRUE;
1597                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1598                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1599                         priv->bcck_in_ch14 = FALSE;
1600                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1601                 } else {
1602                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1603                 }
1604
1605                 break;
1606         case HT_CHANNEL_WIDTH_20_40:
1607                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1608                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1609                 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1610                                  priv->nCur40MhzPrimeSC>>1);
1611                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1612                 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1613                                  priv->nCur40MhzPrimeSC);
1614                 priv->cck_present_attentuation =
1615                         priv->cck_present_attentuation_40Mdefault +
1616                         priv->cck_present_attentuation_difference;
1617
1618                 if (priv->cck_present_attentuation > 22)
1619                         priv->cck_present_attentuation = 22;
1620                 if (priv->cck_present_attentuation < 0)
1621                         priv->cck_present_attentuation = 0;
1622
1623                 RT_TRACE(COMP_INIT,
1624                          "40M, pHalData->CCKPresentAttentuation = %d\n",
1625                          priv->cck_present_attentuation);
1626                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1627                         priv->bcck_in_ch14 = true;
1628                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1629                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1630                         priv->bcck_in_ch14 = false;
1631                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1632                 } else {
1633                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1634                 }
1635
1636                 break;
1637         default:
1638                 RT_TRACE(COMP_ERR,
1639                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1640                          priv->CurrentChannelBW);
1641                 break;
1642
1643         }
1644         /* Skip over setting of J-mode in BB register here.
1645            Default value is "None J mode". */
1646
1647         /* <3> Set RF related register */
1648         switch (priv->rf_chip) {
1649         case RF_8225:
1650 #ifdef TO_DO_LIST
1651                 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1652 #endif
1653                 break;
1654
1655         case RF_8256:
1656                 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1657                 break;
1658
1659         case RF_8258:
1660                 break;
1661
1662         case RF_PSEUDO_11N:
1663                 break;
1664
1665         default:
1666                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1667                 break;
1668         }
1669         priv->SetBWModeInProgress = false;
1670
1671         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1672                  atomic_read(&priv->ieee80211->atm_swbw));
1673 }
1674
1675 /******************************************************************************
1676  * function:  This function schedules bandwidth switch work.
1677  * input:     struct net_deviceq   *dev
1678  *            HT_CHANNEL_WIDTH     bandwidth  //20M or 40M
1679  *            HT_EXTCHNL_OFFSET    offset     //Upper, Lower, or Don't care
1680  * output:    none
1681  * return:    none
1682  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1683  *            test whether current work in the queue or not.//do I?
1684  *****************************************************************************/
1685 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
1686                        HT_EXTCHNL_OFFSET offset)
1687 {
1688         struct r8192_priv *priv = ieee80211_priv(dev);
1689
1690         if (priv->SetBWModeInProgress)
1691                 return;
1692         priv->SetBWModeInProgress = true;
1693
1694         priv->CurrentChannelBW = bandwidth;
1695
1696         if (offset == HT_EXTCHNL_OFFSET_LOWER)
1697                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1698         else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1699                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1700         else
1701                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1702
1703         rtl8192_SetBWModeWorkItem(dev);
1704
1705 }
1706
1707 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1708 {
1709         struct r8192_priv *priv = ieee80211_priv(dev);
1710
1711         priv->InitialGainOperateType = Operation;
1712
1713         if (priv->up)
1714                 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1715 }
1716
1717 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1718 {
1719         struct delayed_work *dwork = container_of(work, struct delayed_work,
1720                                                   work);
1721         struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1722                                                initialgain_operate_wq);
1723         struct net_device *dev = priv->ieee80211->dev;
1724 #define SCAN_RX_INITIAL_GAIN    0x17
1725 #define POWER_DETECTION_TH      0x08
1726         u32     bitmask;
1727         u8      initial_gain;
1728         u8      Operation;
1729
1730         Operation = priv->InitialGainOperateType;
1731
1732         switch (Operation) {
1733         case IG_Backup:
1734                 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1735                 initial_gain = SCAN_RX_INITIAL_GAIN;
1736                 bitmask = bMaskByte0;
1737                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1738                         /* FW DIG OFF */
1739                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1740                 priv->initgain_backup.xaagccore1 =
1741                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1742                 priv->initgain_backup.xbagccore1 =
1743                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1744                 priv->initgain_backup.xcagccore1 =
1745                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1746                 priv->initgain_backup.xdagccore1 =
1747                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1748                 bitmask = bMaskByte2;
1749                 priv->initgain_backup.cca =
1750                         (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1751
1752                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1753                          priv->initgain_backup.xaagccore1);
1754                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1755                          priv->initgain_backup.xbagccore1);
1756                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1757                          priv->initgain_backup.xcagccore1);
1758                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1759                          priv->initgain_backup.xdagccore1);
1760                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1761                          priv->initgain_backup.cca);
1762
1763                 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n",
1764                          initial_gain);
1765                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1766                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1767                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1768                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1769                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n",
1770                          POWER_DETECTION_TH);
1771                 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1772                 break;
1773         case IG_Restore:
1774                 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1775                 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1776                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1777                         /* FW DIG OFF */
1778                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1779
1780                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1781                                  (u32)priv->initgain_backup.xaagccore1);
1782                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1783                                  (u32)priv->initgain_backup.xbagccore1);
1784                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1785                                  (u32)priv->initgain_backup.xcagccore1);
1786                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1787                                  (u32)priv->initgain_backup.xdagccore1);
1788                 bitmask  = bMaskByte2;
1789                 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1790                                  (u32)priv->initgain_backup.cca);
1791
1792                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1793                          priv->initgain_backup.xaagccore1);
1794                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1795                          priv->initgain_backup.xbagccore1);
1796                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1797                          priv->initgain_backup.xcagccore1);
1798                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1799                          priv->initgain_backup.xdagccore1);
1800                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1801                          priv->initgain_backup.cca);
1802
1803                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1804
1805                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1806                         /* FW DIG ON */
1807                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1808                 break;
1809         default:
1810                 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1811                 break;
1812         }
1813 }