drivers/staging/rtl8192u/r819xU_phy.c

   1 #include "r8192U.h"
   2 #include "r8192U_hw.h"
   3 #include "r819xU_phy.h"
   4 #include "r819xU_phyreg.h"
   5 #include "r8190_rtl8256.h"
   6 #include "r8192U_dm.h"
   7 #include "r819xU_firmware_img.h"
   8
   9 #include "dot11d.h"
  10 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  11         0,
  12         0x085c, //2412 1
  13         0x08dc, //2417 2
  14         0x095c, //2422 3
  15         0x09dc, //2427 4
  16         0x0a5c, //2432 5
  17         0x0adc, //2437 6
  18         0x0b5c, //2442 7
  19         0x0bdc, //2447 8
  20         0x0c5c, //2452 9
  21         0x0cdc, //2457 10
  22         0x0d5c, //2462 11
  23         0x0ddc, //2467 12
  24         0x0e5c, //2472 13
  25         0x0f72, //2484
  26 };
  27
  28
  29 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
  30 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
  31 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  32 #define rtl819XRadioA_Array  Rtl8192UsbRadioA_Array
  33 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
  34 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
  35 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
  36 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
  37
  38 /******************************************************************************
  39  *function:  This function read BB parameters from Header file we gen,
  40  *           and do register read/write
  41  *   input:  u32        dwBitMask  //taget bit pos in the addr to be modified
  42  *  output:  none
  43  *  return:  u32        return the shift bit position of the mask
  44  * ****************************************************************************/
  45 u32 rtl8192_CalculateBitShift(u32 dwBitMask)
  46 {
  47         u32 i;
  48         for (i=0; i<=31; i++)
  49         {
  50                 if (((dwBitMask>>i)&0x1) == 1)
  51                         break;
  52         }
  53         return i;
  54 }
  55 /******************************************************************************
  56  *function:  This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
  57  *   input:  none
  58  *  output:  none
  59  *  return:  0(illegal, false), 1(legal,true)
  60  * ***************************************************************************/
  61 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
  62 {
  63         u8 ret = 1;
  64         struct r8192_priv *priv = ieee80211_priv(dev);
  65         if (priv->rf_type == RF_2T4R)
  66                 ret = 0;
  67         else if (priv->rf_type == RF_1T2R)
  68         {
  69                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  70                         ret = 1;
  71                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  72                         ret = 0;
  73         }
  74         return ret;
  75 }
  76 /******************************************************************************
  77  *function:  This function set specific bits to BB register
  78  *   input:  net_device dev
  79  *           u32        dwRegAddr  //target addr to be modified
  80  *           u32        dwBitMask  //taget bit pos in the addr to be modified
  81  *           u32        dwData     //value to be write
  82  *  output:  none
  83  *  return:  none
  84  *  notice:
  85  * ****************************************************************************/
  86 void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
  87 {
  88
  89         u32 OriginalValue, BitShift, NewValue;
  90
  91         if(dwBitMask!= bMaskDWord)
  92         {//if not "double word" write
  93                 read_nic_dword(dev, dwRegAddr, &OriginalValue);
  94                 BitShift = rtl8192_CalculateBitShift(dwBitMask);
  95                 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
  96                 write_nic_dword(dev, dwRegAddr, NewValue);
  97         }else
  98                 write_nic_dword(dev, dwRegAddr, dwData);
  99         return;
 100 }
 101 /******************************************************************************
 102  *function:  This function reads specific bits from BB register
 103  *   input:  net_device dev
 104  *           u32        dwRegAddr  //target addr to be readback
 105  *           u32        dwBitMask  //taget bit pos in the addr to be readback
 106  *  output:  none
 107  *  return:  u32        Data    //the readback register value
 108  *  notice:
 109  * ****************************************************************************/
 110 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
 111 {
 112         u32 Ret = 0, OriginalValue, BitShift;
 113
 114         read_nic_dword(dev, dwRegAddr, &OriginalValue);
 115         BitShift = rtl8192_CalculateBitShift(dwBitMask);
 116         Ret =(OriginalValue & dwBitMask) >> BitShift;
 117
 118         return (Ret);
 119 }
 120 static  u32 phy_FwRFSerialRead( struct net_device *dev, RF90_RADIO_PATH_E       eRFPath, u32 Offset  );
 121
 122 static void phy_FwRFSerialWrite( struct net_device *dev, RF90_RADIO_PATH_E       eRFPath, u32  Offset, u32  Data);
 123
 124 /******************************************************************************
 125  *function:  This function read register from RF chip
 126  *   input:  net_device dev
 127  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
 128  *           u32        Offset     //target address to be read
 129  *  output:  none
 130  *  return:  u32        readback value
 131  *  notice:  There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
 132  * ****************************************************************************/
 133 u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
 134 {
 135         struct r8192_priv *priv = ieee80211_priv(dev);
 136         u32 ret = 0;
 137         u32 NewOffset = 0;
 138         BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
 139         rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 140         //make sure RF register offset is correct
 141         Offset &= 0x3f;
 142
 143         //switch page for 8256 RF IC
 144         if (priv->rf_chip == RF_8256)
 145         {
 146                 if (Offset >= 31)
 147                 {
 148                         priv->RfReg0Value[eRFPath] |= 0x140;
 149                         //Switch to Reg_Mode2 for Reg 31-45
 150                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
 151                         //modify offset
 152                         NewOffset = Offset -30;
 153                 }
 154                 else if (Offset >= 16)
 155                 {
 156                         priv->RfReg0Value[eRFPath] |= 0x100;
 157                         priv->RfReg0Value[eRFPath] &= (~0x40);
 158                         //Switch to Reg_Mode 1 for Reg16-30
 159                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
 160
 161                         NewOffset = Offset - 15;
 162                 }
 163                 else
 164                         NewOffset = Offset;
 165         }
 166         else
 167         {
 168                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
 169                 NewOffset = Offset;
 170         }
 171         //put desired read addr to LSSI control Register
 172         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
 173         //Issue a posedge trigger
 174         //
 175         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 176         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 177
 178
 179         // TODO: we should not delay such a long time. Ask for help from SD3
 180         msleep(1);
 181
 182         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 183
 184
 185         // Switch back to Reg_Mode0;
 186         if(priv->rf_chip == RF_8256)
 187         {
 188                 priv->RfReg0Value[eRFPath] &= 0xebf;
 189
 190                 rtl8192_setBBreg(
 191                         dev,
 192                         pPhyReg->rf3wireOffset,
 193                         bMaskDWord,
 194                         (priv->RfReg0Value[eRFPath] << 16));
 195         }
 196
 197         return ret;
 198
 199 }
 200
 201 /******************************************************************************
 202  *function:  This function write data to RF register
 203  *   input:  net_device dev
 204  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
 205  *           u32        Offset     //target address to be written
 206  *           u32        Data    //The new register data to be written
 207  *  output:  none
 208  *  return:  none
 209  *  notice:  For RF8256 only.
 210   ===========================================================
 211  *Reg Mode      RegCTL[1]       RegCTL[0]               Note
 212  *              (Reg00[12])     (Reg00[10])
 213  *===========================================================
 214  *Reg_Mode0     0               x                       Reg 0 ~15(0x0 ~ 0xf)
 215  *------------------------------------------------------------------
 216  *Reg_Mode1     1               0                       Reg 16 ~30(0x1 ~ 0xf)
 217  *------------------------------------------------------------------
 218  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 219  *------------------------------------------------------------------
 220  * ****************************************************************************/
 221 void rtl8192_phy_RFSerialWrite(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
 222 {
 223         struct r8192_priv *priv = ieee80211_priv(dev);
 224         u32 DataAndAddr = 0, NewOffset = 0;
 225         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 226
 227         Offset &= 0x3f;
 228         //spin_lock_irqsave(&priv->rf_lock, flags);
 229 //      down(&priv->rf_sem);
 230         if (priv->rf_chip == RF_8256)
 231         {
 232
 233                 if (Offset >= 31)
 234                 {
 235                         priv->RfReg0Value[eRFPath] |= 0x140;
 236                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
 237                         NewOffset = Offset - 30;
 238                 }
 239                 else if (Offset >= 16)
 240                 {
 241                         priv->RfReg0Value[eRFPath] |= 0x100;
 242                         priv->RfReg0Value[eRFPath] &= (~0x40);
 243                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
 244                         NewOffset = Offset - 15;
 245                 }
 246                 else
 247                         NewOffset = Offset;
 248         }
 249         else
 250         {
 251                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
 252                 NewOffset = Offset;
 253         }
 254
 255         // Put write addr in [5:0] and write data in [31:16]
 256         DataAndAddr = (Data<<16) | (NewOffset&0x3f);
 257
 258         // Write Operation
 259         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 260
 261
 262         if(Offset==0x0)
 263                 priv->RfReg0Value[eRFPath] = Data;
 264
 265         // Switch back to Reg_Mode0;
 266         if(priv->rf_chip == RF_8256)
 267         {
 268                 if(Offset != 0)
 269                 {
 270                         priv->RfReg0Value[eRFPath] &= 0xebf;
 271                         rtl8192_setBBreg(
 272                                 dev,
 273                                 pPhyReg->rf3wireOffset,
 274                                 bMaskDWord,
 275                                 (priv->RfReg0Value[eRFPath] << 16));
 276                 }
 277         }
 278         //spin_unlock_irqrestore(&priv->rf_lock, flags);
 279 //      up(&priv->rf_sem);
 280         return;
 281 }
 282
 283 /******************************************************************************
 284  *function:  This function set specific bits to RF register
 285  *   input:  net_device dev
 286  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
 287  *           u32        RegAddr  //target addr to be modified
 288  *           u32        BitMask  //taget bit pos in the addr to be modified
 289  *           u32        Data     //value to be write
 290  *  output:  none
 291  *  return:  none
 292  *  notice:
 293  * ****************************************************************************/
 294 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
 295 {
 296         struct r8192_priv *priv = ieee80211_priv(dev);
 297         u32 Original_Value, BitShift, New_Value;
 298 //      u8      time = 0;
 299
 300         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 301                 return;
 302
 303         if (priv->Rf_Mode == RF_OP_By_FW)
 304         {
 305                 if (BitMask != bMask12Bits) // RF data is 12 bits only
 306                 {
 307                         Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 308                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 309                         New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift);
 310
 311                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 312                 }else
 313                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
 314
 315                 udelay(200);
 316
 317         }
 318         else
 319         {
 320                 if (BitMask != bMask12Bits) // RF data is 12 bits only
 321                 {
 322                         Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
 323                         BitShift =  rtl8192_CalculateBitShift(BitMask);
 324                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 325
 326                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 327                 }else
 328                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
 329         }
 330         return;
 331 }
 332
 333 /******************************************************************************
 334  *function:  This function reads specific bits from RF register
 335  *   input:  net_device dev
 336  *           u32        RegAddr  //target addr to be readback
 337  *           u32        BitMask  //taget bit pos in the addr to be readback
 338  *  output:  none
 339  *  return:  u32        Data    //the readback register value
 340  *  notice:
 341  * ****************************************************************************/
 342 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 343 {
 344         u32 Original_Value, Readback_Value, BitShift;
 345         struct r8192_priv *priv = ieee80211_priv(dev);
 346
 347
 348         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 349                 return 0;
 350         if (priv->Rf_Mode == RF_OP_By_FW)
 351         {
 352                 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 353                 BitShift =  rtl8192_CalculateBitShift(BitMask);
 354                 Readback_Value = (Original_Value & BitMask) >> BitShift;
 355                 udelay(200);
 356                 return (Readback_Value);
 357         }
 358         else
 359         {
 360                 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
 361                 BitShift =  rtl8192_CalculateBitShift(BitMask);
 362                 Readback_Value = (Original_Value & BitMask) >> BitShift;
 363                 return (Readback_Value);
 364         }
 365 }
 366 /******************************************************************************
 367  *function:  We support firmware to execute RF-R/W.
 368  *   input:  dev
 369  *  output:  none
 370  *  return:  none
 371  *  notice:
 372  * ***************************************************************************/
 373 static  u32
 374 phy_FwRFSerialRead(
 375         struct net_device *dev,
 376         RF90_RADIO_PATH_E       eRFPath,
 377         u32                             Offset  )
 378 {
 379         u32             retValue = 0;
 380         u32             Data = 0;
 381         u8              time = 0;
 382         u32             tmp;
 383         //DbgPrint("FW RF CTRL\n\r");
 384         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 385            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 386            much time. This is only for site survey. */
 387         // 1. Read operation need not insert data. bit 0-11
 388         //Data &= bMask12Bits;
 389         // 2. Write RF register address. Bit 12-19
 390         Data |= ((Offset&0xFF)<<12);
 391         // 3. Write RF path.  bit 20-21
 392         Data |= ((eRFPath&0x3)<<20);
 393         // 4. Set RF read indicator. bit 22=0
 394         //Data |= 0x00000;
 395         // 5. Trigger Fw to operate the command. bit 31
 396         Data |= 0x80000000;
 397         // 6. We can not execute read operation if bit 31 is 1.
 398         read_nic_dword(dev, QPNR, &tmp);
 399         while (tmp & 0x80000000)
 400         {
 401                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 402                 if (time++ < 100)
 403                 {
 404                         //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
 405                         udelay(10);
 406                         read_nic_dword(dev, QPNR, &tmp);
 407                 }
 408                 else
 409                         break;
 410         }
 411         // 7. Execute read operation.
 412         write_nic_dword(dev, QPNR, Data);
 413         // 8. Check if firmawre send back RF content.
 414         read_nic_dword(dev, QPNR, &tmp);
 415         while (tmp & 0x80000000)
 416         {
 417                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 418                 if (time++ < 100)
 419                 {
 420                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 421                         udelay(10);
 422                         read_nic_dword(dev, QPNR, &tmp);
 423                 }
 424                 else
 425                         return  (0);
 426         }
 427         read_nic_dword(dev, RF_DATA, &retValue);
 428
 429         return  (retValue);
 430
 431 }       /* phy_FwRFSerialRead */
 432
 433 /******************************************************************************
 434  *function:  We support firmware to execute RF-R/W.
 435  *   input:  dev
 436  *  output:  none
 437  *  return:  none
 438  *  notice:
 439  * ***************************************************************************/
 440 static void
 441 phy_FwRFSerialWrite(
 442                 struct net_device *dev,
 443                 RF90_RADIO_PATH_E       eRFPath,
 444                 u32                             Offset,
 445                 u32                             Data    )
 446 {
 447         u8      time = 0;
 448         u32     tmp;
 449
 450         //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
 451         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 452            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 453            much time. This is only for site survey. */
 454
 455         // 1. Set driver write bit and 12 bit data. bit 0-11
 456         //Data &= bMask12Bits;  // Done by uper layer.
 457         // 2. Write RF register address. bit 12-19
 458         Data |= ((Offset&0xFF)<<12);
 459         // 3. Write RF path.  bit 20-21
 460         Data |= ((eRFPath&0x3)<<20);
 461         // 4. Set RF write indicator. bit 22=1
 462         Data |= 0x400000;
 463         // 5. Trigger Fw to operate the command. bit 31=1
 464         Data |= 0x80000000;
 465
 466         // 6. Write operation. We can not write if bit 31 is 1.
 467         read_nic_dword(dev, QPNR, &tmp);
 468         while (tmp & 0x80000000)
 469         {
 470                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 471                 if (time++ < 100)
 472                 {
 473                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 474                         udelay(10);
 475                         read_nic_dword(dev, QPNR, &tmp);
 476                 }
 477                 else
 478                         break;
 479         }
 480         // 7. No matter check bit. We always force the write. Because FW will
 481         //    not accept the command.
 482         write_nic_dword(dev, QPNR, Data);
 483         /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
 484            to finish RF write operation. */
 485         /* 2008/01/17 MH We support delay in firmware side now. */
 486         //delay_us(20);
 487
 488 }       /* phy_FwRFSerialWrite */
 489
 490
 491 /******************************************************************************
 492  *function:  This function read BB parameters from Header file we gen,
 493  *           and do register read/write
 494  *   input:  dev
 495  *  output:  none
 496  *  return:  none
 497  *  notice:  BB parameters may change all the time, so please make
 498  *           sure it has been synced with the newest.
 499  * ***************************************************************************/
 500 void rtl8192_phy_configmac(struct net_device *dev)
 501 {
 502         u32 dwArrayLen = 0, i;
 503         u32 *pdwArray = NULL;
 504         struct r8192_priv *priv = ieee80211_priv(dev);
 505
 506         if(priv->btxpowerdata_readfromEEPORM)
 507         {
 508                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 509                 dwArrayLen = MACPHY_Array_PGLength;
 510                 pdwArray = rtl819XMACPHY_Array_PG;
 511
 512         }
 513         else
 514         {
 515                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
 516                 dwArrayLen = MACPHY_ArrayLength;
 517                 pdwArray = rtl819XMACPHY_Array;
 518         }
 519         for(i = 0; i<dwArrayLen; i=i+3){
 520                 if(pdwArray[i] == 0x318)
 521                 {
 522                         pdwArray[i+2] = 0x00000800;
 523                         //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
 524                         //      ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
 525                 }
 526
 527                 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
 528                                 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 529                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 530         }
 531         return;
 532
 533 }
 534
 535 /******************************************************************************
 536  *function:  This function does dirty work
 537  *   input:  dev
 538  *  output:  none
 539  *  return:  none
 540  *  notice:  BB parameters may change all the time, so please make
 541  *           sure it has been synced with the newest.
 542  * ***************************************************************************/
 543
 544 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 545 {
 546         u32 i;
 547
 548 #ifdef TO_DO_LIST
 549         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
 550         if(Adapter->bInHctTest)
 551         {
 552                 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
 553                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
 554                 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
 555                 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
 556         }
 557 #endif
 558         if (ConfigType == BaseBand_Config_PHY_REG)
 559         {
 560                 for (i=0; i<PHY_REG_1T2RArrayLength; i+=2)
 561                 {
 562                         rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]);
 563                         RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]);
 564                 }
 565         }
 566         else if (ConfigType == BaseBand_Config_AGC_TAB)
 567         {
 568                 for (i=0; i<AGCTAB_ArrayLength; i+=2)
 569                 {
 570                         rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]);
 571                         RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]);
 572                 }
 573         }
 574         return;
 575
 576
 577 }
 578 /******************************************************************************
 579  *function:  This function initialize Register definition offset for Radio Path
 580  *           A/B/C/D
 581  *   input:  net_device dev
 582  *  output:  none
 583  *  return:  none
 584  *  notice:  Initialization value here is constant and it should never be changed
 585  * ***************************************************************************/
 586 void rtl8192_InitBBRFRegDef(struct net_device *dev)
 587 {
 588         struct r8192_priv *priv = ieee80211_priv(dev);
 589 // RF Interface Software Control
 590         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
 591         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
 592         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
 593         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
 594
 595         // RF Interface Readback Value
 596         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
 597         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
 598         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
 599         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
 600
 601         // RF Interface Output (and Enable)
 602         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
 603         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
 604         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
 605         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
 606
 607         // RF Interface (Output and)  Enable
 608         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
 609         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
 610         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
 611         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
 612
 613         //Addr of LSSI. Write RF register by driver
 614         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
 615         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 616         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 617         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 618
 619         // RF parameter
 620         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
 621         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 622         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 623         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 624
 625         // Tx AGC Gain Stage (same for all path. Should we remove this?)
 626         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 627         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 628         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 629         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 630
 631         // Tranceiver A~D HSSI Parameter-1
 632         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
 633         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
 634         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
 635         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
 636
 637         // Tranceiver A~D HSSI Parameter-2
 638         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
 639         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
 640         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
 641         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
 642
 643         // RF switch Control
 644         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
 645         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 646         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 647         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 648
 649         // AGC control 1
 650         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 651         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 652         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 653         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 654
 655         // AGC control 2
 656         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 657         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 658         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 659         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 660
 661         // RX AFE control 1
 662         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 663         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 664         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 665         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 666
 667         // RX AFE control 1
 668         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 669         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 670         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 671         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 672
 673         // Tx AFE control 1
 674         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 675         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 676         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 677         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 678
 679         // Tx AFE control 2
 680         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 681         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 682         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 683         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 684
 685         // Tranceiver LSSI Readback
 686         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 687         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 688         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 689         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 690
 691 }
 692 /******************************************************************************
 693  *function:  This function is to write register and then readback to make sure whether BB and RF is OK
 694  *   input:  net_device dev
 695  *           HW90_BLOCK_E CheckBlock
 696  *           RF90_RADIO_PATH_E eRFPath  //only used when checkblock is HW90_BLOCK_RF
 697  *  output:  none
 698  *  return:  return whether BB and RF is ok(0:OK; 1:Fail)
 699  *  notice:  This function may be removed in the ASIC
 700  * ***************************************************************************/
 701 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
 702 {
 703 //      struct r8192_priv *priv = ieee80211_priv(dev);
 704 //      BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
 705         u8 ret = 0;
 706         u32 i, CheckTimes = 4, dwRegRead = 0;
 707         u32 WriteAddr[4];
 708         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 709         // Initialize register address offset to be checked
 710         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 711         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 712         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 713         WriteAddr[HW90_BLOCK_RF] = 0x3;
 714         RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
 715         for(i=0 ; i < CheckTimes ; i++)
 716         {
 717
 718                 //
 719                 // Write Data to register and readback
 720                 //
 721                 switch (CheckBlock)
 722                 {
 723                 case HW90_BLOCK_MAC:
 724                         RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
 725                         break;
 726
 727                 case HW90_BLOCK_PHY0:
 728                 case HW90_BLOCK_PHY1:
 729                         write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
 730                         read_nic_dword(dev, WriteAddr[CheckBlock], &dwRegRead);
 731                         break;
 732
 733                 case HW90_BLOCK_RF:
 734                         WriteData[i] &= 0xfff;
 735                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
 736                         // TODO: we should not delay for such a long time. Ask SD3
 737                         msleep(1);
 738                         dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits);
 739                         msleep(1);
 740                         break;
 741
 742                 default:
 743                         ret = 1;
 744                         break;
 745                 }
 746
 747
 748                 //
 749                 // Check whether readback data is correct
 750                 //
 751                 if(dwRegRead != WriteData[i])
 752                 {
 753                         RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
 754                         ret = 1;
 755                         break;
 756                 }
 757         }
 758
 759         return ret;
 760 }
 761
 762
 763 /******************************************************************************
 764  *function:  This function initialize BB&RF
 765  *   input:  net_device dev
 766  *  output:  none
 767  *  return:  none
 768  *  notice:  Initialization value may change all the time, so please make
 769  *           sure it has been synced with the newest.
 770  * ***************************************************************************/
 771 void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 772 {
 773         struct r8192_priv *priv = ieee80211_priv(dev);
 774         u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0;
 775         u32 dwRegValue = 0;
 776         /**************************************
 777         //<1>Initialize BaseBand
 778         **************************************/
 779
 780         /*--set BB Global Reset--*/
 781         read_nic_byte(dev, BB_GLOBAL_RESET, &bRegValue);
 782         write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
 783         mdelay(50);
 784         /*---set BB reset Active---*/
 785         read_nic_dword(dev, CPU_GEN, &dwRegValue);
 786         write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
 787
 788         /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
 789         // TODO: this function should be removed on ASIC , Emily 2007.2.2
 790         for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
 791         {
 792                 rtStatus  = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
 793                 if(rtStatus != 0)
 794                 {
 795                         RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
 796                         return ;
 797                 }
 798         }
 799         /*---- Set CCK and OFDM Block "OFF"----*/
 800         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 801         /*----BB Register Initilazation----*/
 802         //==m==>Set PHY REG From Header<==m==
 803         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 804
 805         /*----Set BB reset de-Active----*/
 806         read_nic_dword(dev, CPU_GEN, &dwRegValue);
 807         write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
 808
 809         /*----BB AGC table Initialization----*/
 810         //==m==>Set PHY REG From Header<==m==
 811         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 812
 813         /*----Enable XSTAL ----*/
 814         write_nic_byte_E(dev, 0x5e, 0x00);
 815         if (priv->card_8192_version == (u8)VERSION_819xU_A)
 816         {
 817                 //Antenna gain offset from B/C/D to A
 818                 dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]);
 819                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue);
 820
 821                 //XSTALLCap
 822                 dwRegValue = priv->CrystalCap & 0xf;
 823                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue);
 824         }
 825
 826         // Check if the CCK HighPower is turned ON.
 827         // This is used to calculate PWDB.
 828         priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
 829         return;
 830 }
 831 /******************************************************************************
 832  *function:  This function initialize BB&RF
 833  *   input:  net_device dev
 834  *  output:  none
 835  *  return:  none
 836  *  notice:  Initialization value may change all the time, so please make
 837  *           sure it has been synced with the newest.
 838  * ***************************************************************************/
 839 void rtl8192_BBConfig(struct net_device *dev)
 840 {
 841         rtl8192_InitBBRFRegDef(dev);
 842         //config BB&RF. As hardCode based initialization has not been well
 843         //implemented, so use file first.FIXME:should implement it for hardcode?
 844         rtl8192_BB_Config_ParaFile(dev);
 845         return;
 846 }
 847
 848 /******************************************************************************
 849  *function:  This function obtains the initialization value of Tx power Level offset
 850  *   input:  net_device dev
 851  *  output:  none
 852  *  return:  none
 853  * ***************************************************************************/
 854 void rtl8192_phy_getTxPower(struct net_device *dev)
 855 {
 856         struct r8192_priv *priv = ieee80211_priv(dev);
 857         u8 tmp;
 858         read_nic_dword(dev, rTxAGC_Rate18_06, &priv->MCSTxPowerLevelOriginalOffset[0]);
 859         read_nic_dword(dev, rTxAGC_Rate54_24, &priv->MCSTxPowerLevelOriginalOffset[1]);
 860         read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, &priv->MCSTxPowerLevelOriginalOffset[2]);
 861         read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, &priv->MCSTxPowerLevelOriginalOffset[3]);
 862         read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, &priv->MCSTxPowerLevelOriginalOffset[4]);
 863         read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, &priv->MCSTxPowerLevelOriginalOffset[5]);
 864
 865         // read rx initial gain
 866         read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
 867         read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
 868         read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
 869         read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
 870         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
 871                 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 872                 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 873
 874         // read framesync
 875         read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
 876         read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
 877         priv->framesyncC34 = tmp;
 878         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
 879                 rOFDM0_RxDetector3, priv->framesync);
 880
 881         // read SIFS (save the value read fome MACPHY_REG.txt)
 882         read_nic_word(dev, SIFS, &priv->SifsTime);
 883
 884         return;
 885 }
 886
 887 /******************************************************************************
 888  *function:  This function obtains the initialization value of Tx power Level offset
 889  *   input:  net_device dev
 890  *  output:  none
 891  *  return:  none
 892  * ***************************************************************************/
 893 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 894 {
 895         struct r8192_priv *priv = ieee80211_priv(dev);
 896         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 897         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 898
 899         switch (priv->rf_chip)
 900         {
 901         case RF_8256:
 902                 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
 903                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 904                 break;
 905         default:
 906 //      case RF_8225:
 907 //      case RF_8258:
 908                 RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__);
 909                 break;
 910         }
 911         return;
 912 }
 913
 914 /******************************************************************************
 915  *function:  This function check Rf chip to do RF config
 916  *   input:  net_device dev
 917  *  output:  none
 918  *  return:  only 8256 is supported
 919  * ***************************************************************************/
 920 void rtl8192_phy_RFConfig(struct net_device *dev)
 921 {
 922         struct r8192_priv *priv = ieee80211_priv(dev);
 923
 924         switch (priv->rf_chip)
 925         {
 926                 case RF_8256:
 927                         PHY_RF8256_Config(dev);
 928                         break;
 929         //      case RF_8225:
 930         //      case RF_8258:
 931                 default:
 932                         RT_TRACE(COMP_ERR, "error chip id\n");
 933                         break;
 934         }
 935         return;
 936 }
 937
 938 /******************************************************************************
 939  *function:  This function update Initial gain
 940  *   input:  net_device dev
 941  *  output:  none
 942  *  return:  As Windows has not implemented this, wait for complement
 943  * ***************************************************************************/
 944 void rtl8192_phy_updateInitGain(struct net_device *dev)
 945 {
 946         return;
 947 }
 948
 949 /******************************************************************************
 950  *function:  This function read RF parameters from general head file, and do RF 3-wire
 951  *   input:  net_device dev
 952  *  output:  none
 953  *  return:  return code show if RF configuration is successful(0:pass, 1:fail)
 954  *    Note:  Delay may be required for RF configuration
 955  * ***************************************************************************/
 956 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, RF90_RADIO_PATH_E eRFPath)
 957 {
 958
 959         int i;
 960         //u32* pRFArray;
 961         u8 ret = 0;
 962
 963         switch (eRFPath){
 964         case RF90_PATH_A:
 965                 for(i = 0;i<RadioA_ArrayLength; i=i+2){
 966
 967                         if(rtl819XRadioA_Array[i] == 0xfe){
 968                                         mdelay(100);
 969                                         continue;
 970                         }
 971                         rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]);
 972                         mdelay(1);
 973
 974                 }
 975                 break;
 976         case RF90_PATH_B:
 977                 for(i = 0;i<RadioB_ArrayLength; i=i+2){
 978
 979                         if(rtl819XRadioB_Array[i] == 0xfe){
 980                                         mdelay(100);
 981                                         continue;
 982                         }
 983                         rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]);
 984                         mdelay(1);
 985
 986                 }
 987                 break;
 988         case RF90_PATH_C:
 989                 for(i = 0;i<RadioC_ArrayLength; i=i+2){
 990
 991                         if(rtl819XRadioC_Array[i] == 0xfe){
 992                                         mdelay(100);
 993                                         continue;
 994                         }
 995                         rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]);
 996                         mdelay(1);
 997
 998                 }
 999                 break;
1000         case RF90_PATH_D:
1001                 for(i = 0;i<RadioD_ArrayLength; i=i+2){
1002
1003                         if(rtl819XRadioD_Array[i] == 0xfe){
1004                                         mdelay(100);
1005                                         continue;
1006                         }
1007                         rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]);
1008                         mdelay(1);
1009
1010                 }
1011                 break;
1012         default:
1013                 break;
1014         }
1015
1016         return ret;
1017
1018 }
1019 /******************************************************************************
1020  *function:  This function set Tx Power of the channel
1021  *   input:  struct net_device *dev
1022  *           u8                 channel
1023  *  output:  none
1024  *  return:  none
1025  *    Note:
1026  * ***************************************************************************/
1027 void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1028 {
1029         struct r8192_priv *priv = ieee80211_priv(dev);
1030         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
1031         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1032
1033         switch (priv->rf_chip)
1034         {
1035         case RF_8225:
1036 #ifdef TO_DO_LIST
1037                 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1038                 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1039 #endif
1040                 break;
1041
1042         case RF_8256:
1043                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1044                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1045                 break;
1046
1047         case RF_8258:
1048                 break;
1049         default:
1050                 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
1051                 break;
1052         }
1053         return;
1054 }
1055
1056 /******************************************************************************
1057  *function:  This function set RF state on or off
1058  *   input:  struct net_device *dev
1059  *           RT_RF_POWER_STATE eRFPowerState  //Power State to set
1060  *  output:  none
1061  *  return:  none
1062  *    Note:
1063  * ***************************************************************************/
1064 bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
1065 {
1066         bool                            bResult = true;
1067 //      u8                                      eRFPath;
1068         struct r8192_priv *priv = ieee80211_priv(dev);
1069
1070         if(eRFPowerState == priv->ieee80211->eRFPowerState)
1071                 return false;
1072
1073         if(priv->SetRFPowerStateInProgress == true)
1074                 return false;
1075
1076         priv->SetRFPowerStateInProgress = true;
1077
1078         switch (priv->rf_chip)
1079         {
1080                 case RF_8256:
1081                 switch ( eRFPowerState )
1082                 {
1083                         case eRfOn:
1084         //RF-A, RF-B
1085                                         //enable RF-Chip A/B
1086                                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1);      // 0x860[4]
1087                                         //analog to digital on
1088                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1089                                         //digital to analog on
1090                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
1091                                         //rx antenna on
1092                                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
1093                                         //rx antenna on
1094                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
1095                                         //analog to digital part2 on
1096                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
1097
1098                                 break;
1099
1100                         case eRfSleep:
1101
1102                                 break;
1103
1104                         case eRfOff:
1105                                         //RF-A, RF-B
1106                                         //disable RF-Chip A/B
1107                                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);      // 0x860[4]
1108                                         //analog to digital off, for power save
1109                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1110                                         //digital to analog off, for power save
1111                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3]
1112                                         //rx antenna off
1113                                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0]
1114                                         //rx antenna off
1115                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0]
1116                                         //analog to digital part2 off, for power save
1117                                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5]
1118
1119                                 break;
1120
1121                         default:
1122                                 bResult = false;
1123                                 RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1124                                 break;
1125                 }
1126                         break;
1127                 default:
1128                         RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1129                         break;
1130         }
1131 #ifdef TO_DO_LIST
1132         if(bResult)
1133         {
1134                 // Update current RF state variable.
1135                 pHalData->eRFPowerState = eRFPowerState;
1136                 switch (pHalData->RFChipID )
1137                 {
1138                         case RF_8256:
1139                 switch (pHalData->eRFPowerState)
1140                                 {
1141                                 case eRfOff:
1142                                         //
1143                                         //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1144                                         //
1145                                         if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
1146                                         {
1147                                                 Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK);
1148                                         }
1149                                         else
1150                                         {
1151                                                 // Turn off LED if RF is not ON.
1152                                                 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1153                                         }
1154                                         break;
1155
1156                                 case eRfOn:
1157                                         // Turn on RF we are still linked, which might happen when
1158                                         // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1159                                         if( pMgntInfo->bMediaConnect == TRUE )
1160                                         {
1161                                                 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1162                                         }
1163                                         else
1164                                         {
1165                                                 // Turn off LED if RF is not ON.
1166                                                 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1167                                         }
1168                                         break;
1169
1170                                 default:
1171                                         // do nothing.
1172                                         break;
1173                                 }// Switch RF state
1174                                 break;
1175
1176                                 default:
1177                                         RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n"));
1178                                         break;
1179                         }
1180
1181         }
1182 #endif
1183         priv->SetRFPowerStateInProgress = false;
1184
1185         return bResult;
1186 }
1187
1188 /****************************************************************************************
1189  *function:  This function set command table variable(struct SwChnlCmd).
1190  *   input:  SwChnlCmd*         CmdTable        //table to be set.
1191  *           u32                CmdTableIdx     //variable index in table to be set
1192  *           u32                CmdTableSz      //table size.
1193  *           SwChnlCmdID        CmdID           //command ID to set.
1194  *           u32                Para1
1195  *           u32                Para2
1196  *           u32                msDelay
1197  *  output:
1198  *  return:  true if finished, false otherwise
1199  *    Note:
1200  * ************************************************************************************/
1201 u8 rtl8192_phy_SetSwChnlCmdArray(
1202         SwChnlCmd               *CmdTable,
1203         u32                     CmdTableIdx,
1204         u32                     CmdTableSz,
1205         SwChnlCmdID             CmdID,
1206         u32                     Para1,
1207         u32                     Para2,
1208         u32                     msDelay
1209         )
1210 {
1211         SwChnlCmd *pCmd;
1212
1213         if(CmdTable == NULL)
1214         {
1215                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
1216                 return false;
1217         }
1218         if(CmdTableIdx >= CmdTableSz)
1219         {
1220                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1221                                 CmdTableIdx, CmdTableSz);
1222                 return false;
1223         }
1224
1225         pCmd = CmdTable + CmdTableIdx;
1226         pCmd->CmdID = CmdID;
1227         pCmd->Para1 = Para1;
1228         pCmd->Para2 = Para2;
1229         pCmd->msDelay = msDelay;
1230
1231         return true;
1232 }
1233 /******************************************************************************
1234  *function:  This function set channel step by step
1235  *   input:  struct net_device *dev
1236  *           u8                 channel
1237  *           u8*                stage //3 stages
1238  *           u8*                step  //
1239  *           u32*               delay //whether need to delay
1240  *  output:  store new stage, step and delay for next step(combine with function above)
1241  *  return:  true if finished, false otherwise
1242  *    Note:  Wait for simpler function to replace it //wb
1243  * ***************************************************************************/
1244 u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, u8 *step, u32 *delay)
1245 {
1246         struct r8192_priv *priv = ieee80211_priv(dev);
1247 //      PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
1248         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
1249         u32                                     PreCommonCmdCnt;
1250         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
1251         u32                                     PostCommonCmdCnt;
1252         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
1253         u32                                     RfDependCmdCnt;
1254         SwChnlCmd                               *CurrentCmd = NULL;
1255         //RF90_RADIO_PATH_E             eRFPath;
1256         u8              eRFPath;
1257 //      u32             RfRetVal;
1258 //      u8              RetryCnt;
1259
1260         RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
1261 //      RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
1262         if (!IsLegalChannel(priv->ieee80211, channel))
1263         {
1264                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
1265                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
1266         }
1267 //FIXME:need to check whether channel is legal or not here.WB
1268
1269
1270         //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1271 //      for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
1272 //      {
1273 //              if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1274 //                      continue;
1275                 // <1> Fill up pre common command.
1276                 PreCommonCmdCnt = 0;
1277                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1278                                         CmdID_SetTxPowerLevel, 0, 0, 0);
1279                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1280                                         CmdID_End, 0, 0, 0);
1281
1282                 // <2> Fill up post common command.
1283                 PostCommonCmdCnt = 0;
1284
1285                 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
1286                                         CmdID_End, 0, 0, 0);
1287
1288                 // <3> Fill up RF dependent command.
1289                 RfDependCmdCnt = 0;
1290                 switch ( priv->rf_chip )
1291                 {
1292                 case RF_8225:
1293                         if (!(channel >= 1 && channel <= 14))
1294                         {
1295                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
1296                                 return true;
1297                         }
1298                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1299                                 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
1300                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1301                                 CmdID_End, 0, 0, 0);
1302                         break;
1303
1304                 case RF_8256:
1305                         // TEST!! This is not the table for 8256!!
1306                         if (!(channel >= 1 && channel <= 14))
1307                         {
1308                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
1309                                 return true;
1310                         }
1311                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1312                                 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
1313                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1314                         CmdID_End, 0, 0, 0);
1315                         break;
1316
1317                 case RF_8258:
1318                         break;
1319
1320                 default:
1321                         RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1322                         return true;
1323                         break;
1324                 }
1325
1326
1327                 do{
1328                         switch (*stage)
1329                         {
1330                         case 0:
1331                                 CurrentCmd=&PreCommonCmd[*step];
1332                                 break;
1333                         case 1:
1334                                 CurrentCmd=&RfDependCmd[*step];
1335                                 break;
1336                         case 2:
1337                                 CurrentCmd=&PostCommonCmd[*step];
1338                                 break;
1339                         }
1340
1341                         if(CurrentCmd->CmdID==CmdID_End)
1342                         {
1343                                 if((*stage)==2)
1344                                 {
1345                                         (*delay)=CurrentCmd->msDelay;
1346                                         return true;
1347                                 }
1348                                 else
1349                                 {
1350                                         (*stage)++;
1351                                         (*step)=0;
1352                                         continue;
1353                                 }
1354                         }
1355
1356                         switch (CurrentCmd->CmdID)
1357                         {
1358                         case CmdID_SetTxPowerLevel:
1359                                 if(priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later!
1360                                         rtl8192_SetTxPowerLevel(dev,channel);
1361                                 break;
1362                         case CmdID_WritePortUlong:
1363                                 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
1364                                 break;
1365                         case CmdID_WritePortUshort:
1366                                 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
1367                                 break;
1368                         case CmdID_WritePortUchar:
1369                                 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
1370                                 break;
1371                         case CmdID_RF_WriteReg:
1372                                 for(eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++)
1373                                 {
1374                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2);
1375                                 }
1376                                 break;
1377                         default:
1378                                 break;
1379                         }
1380
1381                         break;
1382                 }while(true);
1383 //      }/*for(Number of RF paths)*/
1384
1385         (*delay)=CurrentCmd->msDelay;
1386         (*step)++;
1387         return false;
1388 }
1389
1390 /******************************************************************************
1391  *function:  This function does actually set channel work
1392  *   input:  struct net_device *dev
1393  *           u8                 channel
1394  *  output:  none
1395  *  return:  noin
1396  *    Note:  We should not call this function directly
1397  * ***************************************************************************/
1398 void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1399 {
1400         struct r8192_priv *priv = ieee80211_priv(dev);
1401         u32     delay = 0;
1402
1403         while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
1404         {
1405         //      if(delay>0)
1406         //              msleep(delay);//or mdelay? need further consideration
1407                 if(!priv->up)
1408                         break;
1409         }
1410 }
1411 /******************************************************************************
1412  *function:  Callback routine of the work item for switch channel.
1413  *   input:
1414  *
1415  *  output:  none
1416  *  return:  noin
1417  * ***************************************************************************/
1418 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1419 {
1420
1421         struct r8192_priv *priv = ieee80211_priv(dev);
1422
1423         RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan);
1424
1425
1426         rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1427
1428         RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1429 }
1430
1431 /******************************************************************************
1432  *function:  This function scheduled actual work item to set channel
1433  *   input:  net_device dev
1434  *           u8         channel //channel to set
1435  *  output:  none
1436  *  return:  return code show if workitem is scheduled(1:pass, 0:fail)
1437  *    Note:  Delay may be required for RF configuration
1438  * ***************************************************************************/
1439 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1440 {
1441         struct r8192_priv *priv = ieee80211_priv(dev);
1442         RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress);
1443         if(!priv->up)
1444                 return false;
1445         if(priv->SwChnlInProgress)
1446                 return false;
1447
1448 //      if(pHalData->SetBWModeInProgress)
1449 //              return;
1450 if (0) //to test current channel from RF reg 0x7.
1451 {
1452         u8              eRFPath;
1453         for(eRFPath = 0; eRFPath < 2; eRFPath++){
1454         printk("====>set channel:%x\n",rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x7, bZebra1_ChannelNum));
1455         udelay(10);
1456         }
1457 }
1458         //--------------------------------------------
1459         switch (priv->ieee80211->mode)
1460         {
1461         case WIRELESS_MODE_A:
1462         case WIRELESS_MODE_N_5G:
1463                 if (channel<=14){
1464                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1465                         return false;
1466                 }
1467                 break;
1468         case WIRELESS_MODE_B:
1469                 if (channel>14){
1470                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1471                         return false;
1472                 }
1473                 break;
1474         case WIRELESS_MODE_G:
1475         case WIRELESS_MODE_N_24G:
1476                 if (channel>14){
1477                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1478                         return false;
1479                 }
1480                 break;
1481         }
1482         //--------------------------------------------
1483
1484         priv->SwChnlInProgress = true;
1485         if(channel == 0)
1486                 channel = 1;
1487
1488         priv->chan=channel;
1489
1490         priv->SwChnlStage=0;
1491         priv->SwChnlStep=0;
1492 //      schedule_work(&(priv->SwChnlWorkItem));
1493 //      rtl8192_SwChnl_WorkItem(dev);
1494         if(priv->up) {
1495 //              queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
1496         rtl8192_SwChnl_WorkItem(dev);
1497         }
1498
1499         priv->SwChnlInProgress = false;
1500         return true;
1501 }
1502
1503
1504 //
1505 /******************************************************************************
1506  *function:  Callback routine of the work item for set bandwidth mode.
1507  *   input:  struct net_device *dev
1508  *           HT_CHANNEL_WIDTH   Bandwidth  //20M or 40M
1509  *           HT_EXTCHNL_OFFSET Offset      //Upper, Lower, or Don't care
1510  *  output:  none
1511  *  return:  none
1512  *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
1513  *           test whether current work in the queue or not.//do I?
1514  * ***************************************************************************/
1515 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1516 {
1517
1518         struct r8192_priv *priv = ieee80211_priv(dev);
1519         u8 regBwOpMode;
1520
1521         RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem()  Switch to %s bandwidth\n", \
1522                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
1523
1524
1525         if(priv->rf_chip == RF_PSEUDO_11N)
1526         {
1527                 priv->SetBWModeInProgress= false;
1528                 return;
1529         }
1530
1531         //<1>Set MAC register
1532         read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1533
1534         switch (priv->CurrentChannelBW)
1535         {
1536                 case HT_CHANNEL_WIDTH_20:
1537                         regBwOpMode |= BW_OPMODE_20MHZ;
1538                        // 2007/02/07 Mark by Emily because we have not verify whether this register works
1539                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1540                         break;
1541
1542                 case HT_CHANNEL_WIDTH_20_40:
1543                         regBwOpMode &= ~BW_OPMODE_20MHZ;
1544                         // 2007/02/07 Mark by Emily because we have not verify whether this register works
1545                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1546                         break;
1547
1548                 default:
1549                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
1550                         break;
1551         }
1552
1553         //<2>Set PHY related register
1554         switch (priv->CurrentChannelBW)
1555         {
1556                 case HT_CHANNEL_WIDTH_20:
1557                         // Add by Vivi 20071119
1558                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1559                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1560                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1561
1562                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
1563                         priv->cck_present_attentuation =
1564                                 priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference;
1565
1566                         if(priv->cck_present_attentuation > 22)
1567                                 priv->cck_present_attentuation= 22;
1568                         if(priv->cck_present_attentuation< 0)
1569                                 priv->cck_present_attentuation = 0;
1570                         RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
1571
1572                         if(priv->chan == 14 && !priv->bcck_in_ch14)
1573                         {
1574                                 priv->bcck_in_ch14 = TRUE;
1575                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1576                         }
1577                         else if(priv->chan != 14 && priv->bcck_in_ch14)
1578                         {
1579                                 priv->bcck_in_ch14 = FALSE;
1580                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1581                         }
1582                         else
1583                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1584
1585                         break;
1586                 case HT_CHANNEL_WIDTH_20_40:
1587                         // Add by Vivi 20071119
1588                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1589                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1590                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
1591                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1592                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
1593                         priv->cck_present_attentuation =
1594                                 priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference;
1595
1596                         if(priv->cck_present_attentuation > 22)
1597                                 priv->cck_present_attentuation = 22;
1598                         if(priv->cck_present_attentuation < 0)
1599                                 priv->cck_present_attentuation = 0;
1600
1601                         RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
1602                         if(priv->chan == 14 && !priv->bcck_in_ch14)
1603                         {
1604                                 priv->bcck_in_ch14 = true;
1605                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1606                         }
1607                         else if(priv->chan!= 14 && priv->bcck_in_ch14)
1608                         {
1609                                 priv->bcck_in_ch14 = false;
1610                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1611                         }
1612                         else
1613                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1614
1615                         break;
1616                 default:
1617                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
1618                         break;
1619
1620         }
1621         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
1622
1623         //<3>Set RF related register
1624         switch ( priv->rf_chip )
1625         {
1626                 case RF_8225:
1627 #ifdef TO_DO_LIST
1628                         PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1629 #endif
1630                         break;
1631
1632                 case RF_8256:
1633                         PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1634                         break;
1635
1636                 case RF_8258:
1637                         // PHY_SetRF8258Bandwidth();
1638                         break;
1639
1640                 case RF_PSEUDO_11N:
1641                         // Do Nothing
1642                         break;
1643
1644                 default:
1645                         RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1646                         break;
1647         }
1648         priv->SetBWModeInProgress= false;
1649
1650         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw)) );
1651 }
1652
1653 /******************************************************************************
1654  *function:  This function schedules bandwidth switch work.
1655  *   input:  struct net_device *dev
1656  *           HT_CHANNEL_WIDTH   Bandwidth  //20M or 40M
1657  *           HT_EXTCHNL_OFFSET Offset      //Upper, Lower, or Don't care
1658  *  output:  none
1659  *  return:  none
1660  *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
1661  *           test whether current work in the queue or not.//do I?
1662  * ***************************************************************************/
1663 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
1664 {
1665         struct r8192_priv *priv = ieee80211_priv(dev);
1666
1667         if(priv->SetBWModeInProgress)
1668                 return;
1669         priv->SetBWModeInProgress= true;
1670
1671         priv->CurrentChannelBW = Bandwidth;
1672
1673         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
1674                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1675         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
1676                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1677         else
1678                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1679
1680         //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
1681         //      schedule_work(&(priv->SetBWModeWorkItem));
1682         rtl8192_SetBWModeWorkItem(dev);
1683
1684 }
1685
1686 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1687 {
1688         struct r8192_priv *priv = ieee80211_priv(dev);
1689
1690         priv->InitialGainOperateType = Operation;
1691
1692         if(priv->up)
1693         {
1694                 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
1695         }
1696 }
1697
1698 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1699 {
1700         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
1701        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
1702        struct net_device *dev = priv->ieee80211->dev;
1703 #define SCAN_RX_INITIAL_GAIN    0x17
1704 #define POWER_DETECTION_TH      0x08
1705         u32     BitMask;
1706         u8      initial_gain;
1707         u8      Operation;
1708
1709         Operation = priv->InitialGainOperateType;
1710
1711         switch (Operation)
1712         {
1713                 case IG_Backup:
1714                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1715                         initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
1716                         BitMask = bMaskByte0;
1717                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1718                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
1719                         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
1720                         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
1721                         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
1722                         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
1723                         BitMask  = bMaskByte2;
1724                         priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
1725
1726                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1727                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1728                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1729                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1730                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1731
1732                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
1733                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1734                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1735                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1736                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1737                         RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
1738                         write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1739                         break;
1740                 case IG_Restore:
1741                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1742                         BitMask = 0x7f; //Bit0~ Bit6
1743                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1744                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
1745
1746                         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
1747                         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
1748                         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
1749                         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
1750                         BitMask  = bMaskByte2;
1751                         rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
1752
1753                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1754                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1755                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1756                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1757                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1758
1759 #ifdef RTL8190P
1760                         SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
1761 #endif
1762 #ifdef RTL8192E
1763                         SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
1764 #endif
1765 //#ifdef RTL8192U
1766                         rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
1767 //#endif
1768
1769                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1770                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
1771                         break;
1772                 default:
1773                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1774                         break;
1775         }
1776 }