drivers/staging/rtl8723au/hal/odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #include "odm_precomp.h"
  17 #include "usb_ops_linux.h"
  18
  19 static const u16 dB_Invert_Table[8][12] = {
  20         {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
  21         {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
  22         {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
  23         {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
  24         {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
  25         {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
  26         {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
  27         {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
  28 };
  29
  30 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {          /*  UL                    DL */
  31         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
  32         {0xa44f, 0x5ea44f, 0x5e431c}, /*  1:realtek AP */
  33         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  2:unknown AP => realtek_92SE */
  34         {0x5ea32b, 0x5ea42b, 0x5e4322}, /*  3:broadcom AP */
  35         {0x5ea422, 0x00a44f, 0x00a44f}, /*  4:ralink AP */
  36         {0x5ea322, 0x00a630, 0x00a44f}, /*  5:atheros AP */
  37         {0x5e4322, 0x5e4322, 0x5e4322},/*  6:cisco AP */
  38         {0x5ea44f, 0x00a44f, 0x5ea42b}, /*  8:marvell AP */
  39         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  10:unknown AP => 92U AP */
  40         {0x5ea42b, 0xa630, 0x5e431c}, /*  11:airgocap AP */
  41 };
  42
  43 /*  EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22 */
  44
  45 /*  Global var */
  46 u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D] = {
  47         0x7f8001fe, /*  0, +6.0dB */
  48         0x788001e2, /*  1, +5.5dB */
  49         0x71c001c7, /*  2, +5.0dB */
  50         0x6b8001ae, /*  3, +4.5dB */
  51         0x65400195, /*  4, +4.0dB */
  52         0x5fc0017f, /*  5, +3.5dB */
  53         0x5a400169, /*  6, +3.0dB */
  54         0x55400155, /*  7, +2.5dB */
  55         0x50800142, /*  8, +2.0dB */
  56         0x4c000130, /*  9, +1.5dB */
  57         0x47c0011f, /*  10, +1.0dB */
  58         0x43c0010f, /*  11, +0.5dB */
  59         0x40000100, /*  12, +0dB */
  60         0x3c8000f2, /*  13, -0.5dB */
  61         0x390000e4, /*  14, -1.0dB */
  62         0x35c000d7, /*  15, -1.5dB */
  63         0x32c000cb, /*  16, -2.0dB */
  64         0x300000c0, /*  17, -2.5dB */
  65         0x2d4000b5, /*  18, -3.0dB */
  66         0x2ac000ab, /*  19, -3.5dB */
  67         0x288000a2, /*  20, -4.0dB */
  68         0x26000098, /*  21, -4.5dB */
  69         0x24000090, /*  22, -5.0dB */
  70         0x22000088, /*  23, -5.5dB */
  71         0x20000080, /*  24, -6.0dB */
  72         0x1e400079, /*  25, -6.5dB */
  73         0x1c800072, /*  26, -7.0dB */
  74         0x1b00006c, /*  27. -7.5dB */
  75         0x19800066, /*  28, -8.0dB */
  76         0x18000060, /*  29, -8.5dB */
  77         0x16c0005b, /*  30, -9.0dB */
  78         0x15800056, /*  31, -9.5dB */
  79         0x14400051, /*  32, -10.0dB */
  80         0x1300004c, /*  33, -10.5dB */
  81         0x12000048, /*  34, -11.0dB */
  82         0x11000044, /*  35, -11.5dB */
  83         0x10000040, /*  36, -12.0dB */
  84         0x0f00003c,/*  37, -12.5dB */
  85         0x0e400039,/*  38, -13.0dB */
  86         0x0d800036,/*  39, -13.5dB */
  87         0x0cc00033,/*  40, -14.0dB */
  88         0x0c000030,/*  41, -14.5dB */
  89         0x0b40002d,/*  42, -15.0dB */
  90 };
  91
  92 u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8] = {
  93         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /*  0, +0dB */
  94         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  1, -0.5dB */
  95         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  2, -1.0dB */
  96         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  3, -1.5dB */
  97         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  4, -2.0dB */
  98         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  5, -2.5dB */
  99         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  6, -3.0dB */
 100         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  7, -3.5dB */
 101         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  8, -4.0dB */
 102         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  9, -4.5dB */
 103         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  10, -5.0dB */
 104         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  11, -5.5dB */
 105         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  12, -6.0dB */
 106         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  13, -6.5dB */
 107         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  14, -7.0dB */
 108         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  15, -7.5dB */
 109         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
 110         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  17, -8.5dB */
 111         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  18, -9.0dB */
 112         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  19, -9.5dB */
 113         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  20, -10.0dB */
 114         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  21, -10.5dB */
 115         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  22, -11.0dB */
 116         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*  23, -11.5dB */
 117         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*  24, -12.0dB */
 118         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*  25, -12.5dB */
 119         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*  26, -13.0dB */
 120         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  27, -13.5dB */
 121         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  28, -14.0dB */
 122         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  29, -14.5dB */
 123         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  30, -15.0dB */
 124         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*  31, -15.5dB */
 125         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        /*  32, -16.0dB */
 126 };
 127
 128 u8 CCKSwingTable_Ch1423A[CCK_TABLE_SIZE][8] = {
 129         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /*  0, +0dB */
 130         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /*  1, -0.5dB */
 131         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /*  2, -1.0dB */
 132         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*  3, -1.5dB */
 133         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /*  4, -2.0dB */
 134         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*  5, -2.5dB */
 135         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /*  6, -3.0dB */
 136         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /*  7, -3.5dB */
 137         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /*  8, -4.0dB */
 138         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*  9, -4.5dB */
 139         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /*  10, -5.0dB */
 140         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  11, -5.5dB */
 141         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  12, -6.0dB */
 142         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /*  13, -6.5dB */
 143         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /*  14, -7.0dB */
 144         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  15, -7.5dB */
 145         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  16, -8.0dB */
 146         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  17, -8.5dB */
 147         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  18, -9.0dB */
 148         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  19, -9.5dB */
 149         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  20, -10.0dB */
 150         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  21, -10.5dB */
 151         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  22, -11.0dB */
 152         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  23, -11.5dB */
 153         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  24, -12.0dB */
 154         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  25, -12.5dB */
 155         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  26, -13.0dB */
 156         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  27, -13.5dB */
 157         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  28, -14.0dB */
 158         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  29, -14.5dB */
 159         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  30, -15.0dB */
 160         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  31, -15.5dB */
 161         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        /*  32, -16.0dB */
 162 };
 163
 164 /*  Local Function predefine. */
 165
 166 /* START------------COMMON INFO RELATED--------------- */
 167 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm);
 168
 169 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData);
 170
 171 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm);
 172
 173 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm);
 174
 175 /* START---------------DIG--------------------------- */
 176 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm);
 177
 178 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm);
 179
 180 void odm_DIG23a(struct rtw_adapter *adapter);
 181
 182 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm);
 183 /* END---------------DIG--------------------------- */
 184
 185 /* START-------BB POWER SAVE----------------------- */
 186 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm);
 187
 188 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm);
 189
 190 /* END---------BB POWER SAVE----------------------- */
 191
 192 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm);
 193
 194 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm);
 195
 196 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm);
 197 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm);
 198 void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm);
 199
 200 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm);
 201
 202 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
 203
 204 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm);
 205
 206 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm);
 207
 208 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm);
 209
 210 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm);
 211
 212 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm);
 213 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm);
 214
 215 #define         RxDefaultAnt1           0x65a9
 216 #define RxDefaultAnt2           0x569a
 217
 218 bool odm_StaDefAntSel(struct dm_odm_t *pDM_Odm,
 219  u32 OFDM_Ant1_Cnt,
 220  u32 OFDM_Ant2_Cnt,
 221  u32 CCK_Ant1_Cnt,
 222  u32 CCK_Ant2_Cnt,
 223  u8 *pDefAnt
 224         );
 225
 226 void odm_SetRxIdleAnt(struct dm_odm_t *pDM_Odm,
 227         u8 Ant,
 228    bool   bDualPath
 229 );
 230
 231 /* 3 Export Interface */
 232
 233 /*  2011/09/21 MH Add to describe different team necessary resource allocate?? */
 234 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm)
 235 {
 236         /* For all IC series */
 237         odm_CommonInfoSelfInit23a(pDM_Odm);
 238         odm_CmnInfoInit_Debug23a(pDM_Odm);
 239         odm_DIG23aInit(pDM_Odm);
 240         odm_RateAdaptiveMaskInit23a(pDM_Odm);
 241
 242         odm23a_DynBBPSInit(pDM_Odm);
 243         odm_DynamicTxPower23aInit(pDM_Odm);
 244         odm_TXPowerTrackingInit23a(pDM_Odm);
 245         ODM_EdcaTurboInit23a(pDM_Odm);
 246 }
 247
 248 /*  2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
 249 /*  You can not add any dummy function here, be care, you can only use DM structure */
 250 /*  to perform any new ODM_DM. */
 251 void ODM_DMWatchdog23a(struct rtw_adapter *adapter)
 252 {
 253         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 254         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 255         struct pwrctrl_priv *pwrctrlpriv = &adapter->pwrctrlpriv;
 256
 257         /* 2012.05.03 Luke: For all IC series */
 258         odm_CmnInfoUpdate_Debug23a(pDM_Odm);
 259         odm_CommonInfoSelfUpdate(pHalData);
 260         odm_FalseAlarmCounterStatistics23a(pDM_Odm);
 261         odm_RSSIMonitorCheck23a(pDM_Odm);
 262
 263         /* 8723A or 8189ES platform */
 264         /* NeilChen--2012--08--24-- */
 265         /* Fix Leave LPS issue */
 266         if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/*  in LPS mode */
 267             (pDM_Odm->SupportICType & ODM_RTL8723A)) {
 268                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG23a is in LPS mode\n"));
 269                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
 270                         odm_DIG23abyRSSI_LPS(pDM_Odm);
 271         } else {
 272                 odm_DIG23a(adapter);
 273         }
 274
 275         odm_CCKPacketDetectionThresh23a(pDM_Odm);
 276
 277         if (pwrctrlpriv->bpower_saving)
 278                 return;
 279
 280         odm_RefreshRateAdaptiveMask23a(pDM_Odm);
 281
 282         odm_DynamicBBPowerSaving23a(pDM_Odm);
 283
 284         ODM_TXPowerTrackingCheck23a(pDM_Odm);
 285         odm_EdcaTurboCheck23a(pDM_Odm);
 286
 287         odm_dtc(pDM_Odm);
 288 }
 289
 290 /*  */
 291 /*  Init /.. Fixed HW value. Only init time. */
 292 /*  */
 293 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm,
 294                 enum odm_cmninfo CmnInfo,
 295                 u32 Value
 296         )
 297 {
 298         /* ODM_RT_TRACE(pDM_Odm,); */
 299
 300         /*  */
 301         /*  This section is used for init value */
 302         /*  */
 303         switch  (CmnInfo) {
 304         /*  Fixed ODM value. */
 305         case    ODM_CMNINFO_PLATFORM:
 306                 break;
 307         case    ODM_CMNINFO_INTERFACE:
 308                 pDM_Odm->SupportInterface = (u8)Value;
 309                 break;
 310         case    ODM_CMNINFO_MP_TEST_CHIP:
 311                 pDM_Odm->bIsMPChip = (u8)Value;
 312                 break;
 313         case    ODM_CMNINFO_IC_TYPE:
 314                 pDM_Odm->SupportICType = Value;
 315                 break;
 316         case    ODM_CMNINFO_CUT_VER:
 317                 pDM_Odm->CutVersion = (u8)Value;
 318                 break;
 319         case    ODM_CMNINFO_FAB_VER:
 320                 pDM_Odm->FabVersion = (u8)Value;
 321                 break;
 322         case    ODM_CMNINFO_RF_TYPE:
 323                 pDM_Odm->RFType = (u8)Value;
 324                 break;
 325         case    ODM_CMNINFO_BOARD_TYPE:
 326                 pDM_Odm->BoardType = (u8)Value;
 327                 break;
 328         case    ODM_CMNINFO_EXT_LNA:
 329                 pDM_Odm->ExtLNA = (u8)Value;
 330                 break;
 331         case    ODM_CMNINFO_EXT_PA:
 332                 pDM_Odm->ExtPA = (u8)Value;
 333                 break;
 334         case    ODM_CMNINFO_EXT_TRSW:
 335                 pDM_Odm->ExtTRSW = (u8)Value;
 336                 break;
 337         case    ODM_CMNINFO_PATCH_ID:
 338                 pDM_Odm->PatchID = (u8)Value;
 339                 break;
 340         case    ODM_CMNINFO_BINHCT_TEST:
 341                 pDM_Odm->bInHctTest = (bool)Value;
 342                 break;
 343         case    ODM_CMNINFO_BWIFI_TEST:
 344                 pDM_Odm->bWIFITest = (bool)Value;
 345                 break;
 346         case    ODM_CMNINFO_SMART_CONCURRENT:
 347                 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
 348                 break;
 349         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 350         default:
 351                 /* do nothing */
 352                 break;
 353         }
 354
 355         /*  */
 356         /*  Tx power tracking BB swing table. */
 357         /*  The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
 358         /*  */
 359         pDM_Odm->BbSwingIdxOfdm                 = 12; /*  Set defalut value as index 12. */
 360         pDM_Odm->BbSwingIdxOfdmCurrent  = 12;
 361         pDM_Odm->BbSwingFlagOfdm                = false;
 362
 363 }
 364
 365 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo,
 366                                 u16 Index, void *pValue)
 367 {
 368         /*  Hook call by reference pointer. */
 369         switch  (CmnInfo) {
 370         /*  Dynamic call by reference pointer. */
 371         case    ODM_CMNINFO_STA_STATUS:
 372                 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
 373                 break;
 374         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 375         default:
 376                 /* do nothing */
 377                 break;
 378         }
 379 }
 380
 381 /*  Update Band/CHannel/.. The values are dynamic but non-per-packet. */
 382 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value)
 383 {
 384         /*  This init variable may be changed in run time. */
 385         switch  (CmnInfo) {
 386         case    ODM_CMNINFO_RF_TYPE:
 387                 pDM_Odm->RFType = (u8)Value;
 388                 break;
 389         case    ODM_CMNINFO_WIFI_DIRECT:
 390                 pDM_Odm->bWIFI_Direct = (bool)Value;
 391                 break;
 392         case    ODM_CMNINFO_WIFI_DISPLAY:
 393                 pDM_Odm->bWIFI_Display = (bool)Value;
 394                 break;
 395         case    ODM_CMNINFO_LINK:
 396                 pDM_Odm->bLinked = (bool)Value;
 397                 break;
 398         case    ODM_CMNINFO_RSSI_MIN:
 399                 pDM_Odm->RSSI_Min = (u8)Value;
 400                 break;
 401         case    ODM_CMNINFO_DBG_COMP:
 402                 pDM_Odm->DebugComponents = Value;
 403                 break;
 404         case    ODM_CMNINFO_DBG_LEVEL:
 405                 pDM_Odm->DebugLevel = (u32)Value;
 406                 break;
 407         case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
 408                 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
 409                 break;
 410         case    ODM_CMNINFO_RA_THRESHOLD_LOW:
 411                 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
 412                 break;
 413         }
 414
 415 }
 416
 417 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm
 418         )
 419 {
 420         pDM_Odm->bCckHighPower =
 421                 (bool) ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter2, BIT(9));
 422         pDM_Odm->RFPathRxEnable =
 423                 (u8) ODM_GetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, 0x0F);
 424
 425         ODM_InitDebugSetting23a(pDM_Odm);
 426 }
 427
 428 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData)
 429 {
 430         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 431         struct sta_info *pEntry;
 432         u8 EntryCnt = 0;
 433         u8 i;
 434
 435         if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) {
 436                 if (pHalData->nCur40MhzPrimeSC == 1)
 437                         pDM_Odm->ControlChannel = pHalData->CurrentChannel - 2;
 438                 else if (pHalData->nCur40MhzPrimeSC == 2)
 439                         pDM_Odm->ControlChannel = pHalData->CurrentChannel + 2;
 440         } else {
 441                 pDM_Odm->ControlChannel = pHalData->CurrentChannel;
 442         }
 443
 444         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 445                 pEntry = pDM_Odm->pODM_StaInfo[i];
 446                 if (pEntry)
 447                         EntryCnt++;
 448         }
 449         if (EntryCnt == 1)
 450                 pDM_Odm->bOneEntryOnly = true;
 451         else
 452                 pDM_Odm->bOneEntryOnly = false;
 453 }
 454
 455 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm)
 456 {
 457         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug23a ==>\n"));
 458         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility = 0x%x\n", pDM_Odm->SupportAbility));
 459         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface =%d\n", pDM_Odm->SupportInterface));
 460         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType = 0x%x\n", pDM_Odm->SupportICType));
 461         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion =%d\n", pDM_Odm->CutVersion));
 462         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion =%d\n", pDM_Odm->FabVersion));
 463         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType =%d\n", pDM_Odm->RFType));
 464         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType =%d\n", pDM_Odm->BoardType));
 465         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA =%d\n", pDM_Odm->ExtLNA));
 466         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA =%d\n", pDM_Odm->ExtPA));
 467         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW =%d\n", pDM_Odm->ExtTRSW));
 468         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID =%d\n", pDM_Odm->PatchID));
 469         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest =%d\n", pDM_Odm->bInHctTest));
 470         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest =%d\n", pDM_Odm->bWIFITest));
 471         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent =%d\n", pDM_Odm->bDualMacSmartConcurrent));
 472
 473 }
 474
 475 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm)
 476 {
 477         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug23a ==>\n"));
 478         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct =%d\n", pDM_Odm->bWIFI_Direct));
 479         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display =%d\n", pDM_Odm->bWIFI_Display));
 480         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked =%d\n", pDM_Odm->bLinked));
 481         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min =%d\n", pDM_Odm->RSSI_Min));
 482 }
 483
 484 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm,
 485         u8 CurrentIGI
 486         )
 487 {
 488         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 489
 490         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n",
 491                 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
 492
 493         if (pDM_DigTable->CurIGValue != CurrentIGI) {
 494                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 495                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n", CurrentIGI));
 496                 pDM_DigTable->CurIGValue = CurrentIGI;
 497         }
 498         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 499                      ("ODM_Write_DIG23a():CurrentIGI = 0x%x \n", CurrentIGI));
 500 }
 501
 502 /* Need LPS mode for CE platform --2012--08--24--- */
 503 /* 8723AS/8189ES */
 504 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm)
 505 {
 506         struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
 507         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 508         u8 RSSI_Lower = DM_DIG_MIN_NIC;   /* 0x1E or 0x1C */
 509         u8 bFwCurrentInPSMode = false;
 510         u8 CurrentIGI = pDM_Odm->RSSI_Min;
 511
 512         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
 513                 return;
 514
 515         CurrentIGI = CurrentIGI+RSSI_OFFSET_DIG;
 516         bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
 517
 518         /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n")); */
 519
 520         /*  Using FW PS mode to make IGI */
 521         if (bFwCurrentInPSMode) {
 522                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG23a is in LPS mode\n"));
 523                 /* Adjust by  FA in LPS MODE */
 524                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
 525                         CurrentIGI = CurrentIGI+2;
 526                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
 527                         CurrentIGI = CurrentIGI+1;
 528                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
 529                         CurrentIGI = CurrentIGI-1;
 530         } else {
 531                 CurrentIGI = RSSI_Lower;
 532         }
 533
 534         /* Lower bound checking */
 535
 536         /* RSSI Lower bound check */
 537         if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
 538                 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
 539         else
 540                 RSSI_Lower = DM_DIG_MIN_NIC;
 541
 542         /* Upper and Lower Bound checking */
 543          if (CurrentIGI > DM_DIG_MAX_NIC)
 544                 CurrentIGI = DM_DIG_MAX_NIC;
 545          else if (CurrentIGI < RSSI_Lower)
 546                 CurrentIGI = RSSI_Lower;
 547
 548         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 549
 550 }
 551
 552 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm)
 553 {
 554         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 555
 556         pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
 557         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
 558         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
 559         pDM_DigTable->FALowThresh       = DM_FALSEALARM_THRESH_LOW;
 560         pDM_DigTable->FAHighThresh      = DM_FALSEALARM_THRESH_HIGH;
 561         if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
 562                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 563                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 564         } else {
 565                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 566                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 567         }
 568         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
 569         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
 570         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
 571         pDM_DigTable->PreCCK_CCAThres = 0xFF;
 572         pDM_DigTable->CurCCK_CCAThres = 0x83;
 573         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
 574         pDM_DigTable->LargeFAHit = 0;
 575         pDM_DigTable->Recover_cnt = 0;
 576         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
 577         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
 578         pDM_DigTable->bMediaConnect_0 = false;
 579         pDM_DigTable->bMediaConnect_1 = false;
 580 }
 581
 582 void odm_DIG23a(struct rtw_adapter *adapter)
 583 {
 584         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 585         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 586         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 587         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 588         u8 DIG_Dynamic_MIN;
 589         u8 DIG_MaxOfMin;
 590         bool FirstConnect, FirstDisConnect;
 591         u8 dm_dig_max, dm_dig_min;
 592         u8 CurrentIGI = pDM_DigTable->CurIGValue;
 593
 594         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n"));
 595         /* if (!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) */
 596         if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
 597                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 598                              ("odm_DIG23a() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
 599                 return;
 600         }
 601
 602         if (adapter->mlmepriv.bScanInProcess) {
 603                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: In Scan Progress \n"));
 604                 return;
 605         }
 606
 607         DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 608         FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 609         FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 610
 611         /* 1 Boundary Decision */
 612         if ((pDM_Odm->SupportICType & ODM_RTL8723A) &&
 613             ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
 614                 dm_dig_max = DM_DIG_MAX_NIC_HP;
 615                 dm_dig_min = DM_DIG_MIN_NIC_HP;
 616                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
 617         } else {
 618                 dm_dig_max = DM_DIG_MAX_NIC;
 619                 dm_dig_min = DM_DIG_MIN_NIC;
 620                 DIG_MaxOfMin = DM_DIG_MAX_AP;
 621         }
 622
 623         if (pDM_Odm->bLinked) {
 624               /* 2 8723A Series, offset need to be 10 */
 625                 if (pDM_Odm->SupportICType == ODM_RTL8723A) {
 626                         /* 2 Upper Bound */
 627                         if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
 628                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 629                         else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
 630                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
 631                         else
 632                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
 633
 634                         /* 2 If BT is Concurrent, need to set Lower Bound */
 635                         DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
 636                 } else {
 637                         /* 2 Modify DIG upper bound */
 638                         if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
 639                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 640                         else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
 641                                 pDM_DigTable->rx_gain_range_max = dm_dig_min;
 642                         else
 643                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
 644
 645                         /* 2 Modify DIG lower bound */
 646                         if (pDM_Odm->bOneEntryOnly) {
 647                                 if (pDM_Odm->RSSI_Min < dm_dig_min)
 648                                         DIG_Dynamic_MIN = dm_dig_min;
 649                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
 650                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
 651                                 else
 652                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
 653                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 654                                              ("odm_DIG23a() : bOneEntryOnly = true,  DIG_Dynamic_MIN = 0x%x\n",
 655                                              DIG_Dynamic_MIN));
 656                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 657                                              ("odm_DIG23a() : pDM_Odm->RSSI_Min =%d\n",
 658                                              pDM_Odm->RSSI_Min));
 659                         } else {
 660                                 DIG_Dynamic_MIN = dm_dig_min;
 661                         }
 662                 }
 663         } else {
 664                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 665                 DIG_Dynamic_MIN = dm_dig_min;
 666                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() : No Link\n"));
 667         }
 668
 669         /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
 670         if (pFalseAlmCnt->Cnt_all > 10000) {
 671                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 672                              ("dm_DIG(): Abnornally false alarm case. \n"));
 673
 674                 if (pDM_DigTable->LargeFAHit != 3)
 675                         pDM_DigTable->LargeFAHit++;
 676                 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
 677                         pDM_DigTable->ForbiddenIGI = CurrentIGI;
 678                         pDM_DigTable->LargeFAHit = 1;
 679                 }
 680
 681                 if (pDM_DigTable->LargeFAHit >= 3) {
 682                         if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
 683                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
 684                         else
 685                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 686                         pDM_DigTable->Recover_cnt = 3600; /* 3600 = 2hr */
 687                 }
 688         } else {
 689                 /* Recovery mechanism for IGI lower bound */
 690                 if (pDM_DigTable->Recover_cnt != 0) {
 691                         pDM_DigTable->Recover_cnt--;
 692                 } else {
 693                         if (pDM_DigTable->LargeFAHit < 3) {
 694                                 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) {
 695                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 696                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 697                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 698                                                      ("odm_DIG23a(): Normal Case: At Lower Bound\n"));
 699                                 } else {
 700                                         pDM_DigTable->ForbiddenIGI--;
 701                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 702                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 703                                                      ("odm_DIG23a(): Normal Case: Approach Lower Bound\n"));
 704                                 }
 705                         } else {
 706                                 pDM_DigTable->LargeFAHit = 0;
 707                         }
 708                 }
 709         }
 710         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): pDM_DigTable->LargeFAHit =%d\n", pDM_DigTable->LargeFAHit));
 711
 712         /* 1 Adjust initial gain by false alarm */
 713         if (pDM_Odm->bLinked) {
 714                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG AfterLink\n"));
 715                 if (FirstConnect) {
 716                         CurrentIGI = pDM_Odm->RSSI_Min;
 717                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
 718                 } else {
 719                         if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
 720                                 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 721                         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
 722                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 723                         else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
 724                                 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 725                 }
 726         } else {
 727                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG BeforeLink\n"));
 728                 if (FirstDisConnect) {
 729                         CurrentIGI = pDM_DigTable->rx_gain_range_min;
 730                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): First DisConnect \n"));
 731                 } else {
 732                         /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
 733                         if (pFalseAlmCnt->Cnt_all > 10000)
 734                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 735                         else if (pFalseAlmCnt->Cnt_all > 8000)
 736                                 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 737                         else if (pFalseAlmCnt->Cnt_all < 500)
 738                                 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 739                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): England DIG \n"));
 740                 }
 741         }
 742         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG End Adjust IGI\n"));
 743         /* 1 Check initial gain by upper/lower bound */
 744         if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
 745                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
 746         if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
 747                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
 748
 749         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): rx_gain_range_max = 0x%x, rx_gain_range_min = 0x%x\n",
 750                 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
 751         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): TotalFA =%d\n", pFalseAlmCnt->Cnt_all));
 752         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): CurIGValue = 0x%x\n", CurrentIGI));
 753
 754         /* 2 High power RSSI threshold */
 755
 756         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 757         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
 758         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
 759 }
 760
 761 /* 3 ============================================================ */
 762 /* 3 FASLE ALARM CHECK */
 763 /* 3 ============================================================ */
 764
 765 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm)
 766 {
 767         u32 ret_value;
 768         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 769
 770         if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
 771                 return;
 772
 773         /* hold ofdm counter */
 774          /* hold page C counter */
 775         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
 776         /* hold page D counter */
 777         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
 778         ret_value =
 779                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
 780         FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
 781         FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
 782         ret_value =
 783                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
 784         FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
 785         FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
 786         ret_value =
 787                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
 788         FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
 789         FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
 790         ret_value =
 791                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
 792         FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
 793
 794         FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail +
 795                 FalseAlmCnt->Cnt_Rate_Illegal +
 796                 FalseAlmCnt->Cnt_Crc8_fail +
 797                 FalseAlmCnt->Cnt_Mcs_fail +
 798                 FalseAlmCnt->Cnt_Fast_Fsync +
 799                 FalseAlmCnt->Cnt_SB_Search_fail;
 800         /* hold cck counter */
 801         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
 802         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
 803
 804         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
 805         FalseAlmCnt->Cnt_Cck_fail = ret_value;
 806         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
 807         FalseAlmCnt->Cnt_Cck_fail +=  (ret_value & 0xff) << 8;
 808
 809         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
 810         FalseAlmCnt->Cnt_CCK_CCA =
 811                 ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
 812
 813         FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
 814                                 FalseAlmCnt->Cnt_SB_Search_fail +
 815                                 FalseAlmCnt->Cnt_Parity_Fail +
 816                                 FalseAlmCnt->Cnt_Rate_Illegal +
 817                                 FalseAlmCnt->Cnt_Crc8_fail +
 818                                 FalseAlmCnt->Cnt_Mcs_fail +
 819                                 FalseAlmCnt->Cnt_Cck_fail);
 820
 821         FalseAlmCnt->Cnt_CCA_all =
 822                 FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
 823
 824         if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
 825                 /* reset false alarm counter registers */
 826                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
 827                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
 828                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
 829                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
 830                 /* update ofdm counter */
 831                  /* update page C counter */
 832                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
 833                  /* update page D counter */
 834                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
 835
 836                 /* reset CCK CCA counter */
 837                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 838                              BIT(13) | BIT(12), 0);
 839                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 840                              BIT(13) | BIT(12), 2);
 841                 /* reset CCK FA counter */
 842                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 843                              BIT(15) | BIT(14), 0);
 844                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 845                              BIT(15) | BIT(14), 2);
 846         }
 847
 848         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 849                      ("Enter odm_FalseAlarmCounterStatistics23a\n"));
 850         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 851                      ("Cnt_Fast_Fsync =%d, Cnt_SB_Search_fail =%d\n",
 852                       FalseAlmCnt->Cnt_Fast_Fsync,
 853                       FalseAlmCnt->Cnt_SB_Search_fail));
 854         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 855                      ("Cnt_Parity_Fail =%d, Cnt_Rate_Illegal =%d\n",
 856                       FalseAlmCnt->Cnt_Parity_Fail,
 857                       FalseAlmCnt->Cnt_Rate_Illegal));
 858         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 859                      ("Cnt_Crc8_fail =%d, Cnt_Mcs_fail =%d\n",
 860                       FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
 861
 862         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail =%d\n", FalseAlmCnt->Cnt_Cck_fail));
 863         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail =%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
 864         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm =%d\n", FalseAlmCnt->Cnt_all));
 865 }
 866
 867 /* 3 ============================================================ */
 868 /* 3 CCK Packet Detect Threshold */
 869 /* 3 ============================================================ */
 870
 871 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm)
 872 {
 873         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 874         u8 CurCCK_CCAThres;
 875
 876         if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
 877                 return;
 878
 879         if (pDM_Odm->ExtLNA)
 880                 return;
 881
 882         if (pDM_Odm->bLinked) {
 883                 if (pDM_Odm->RSSI_Min > 25) {
 884                         CurCCK_CCAThres = 0xcd;
 885                 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
 886                         CurCCK_CCAThres = 0x83;
 887                 } else {
 888                         if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 889                                 CurCCK_CCAThres = 0x83;
 890                         else
 891                                 CurCCK_CCAThres = 0x40;
 892                 }
 893         } else {
 894                 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 895                         CurCCK_CCAThres = 0x83;
 896                 else
 897                         CurCCK_CCAThres = 0x40;
 898         }
 899
 900         ODM_Write_CCK_CCA_Thres23a(pDM_Odm, CurCCK_CCAThres);
 901 }
 902
 903 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres)
 904 {
 905         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 906
 907         if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)
 908                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
 909         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
 910         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
 911
 912 }
 913
 914 /* 3 ============================================================ */
 915 /* 3 BB Power Save */
 916 /* 3 ============================================================ */
 917 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm)
 918 {
 919         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 920
 921         pDM_PSTable->PreCCAState = CCA_MAX;
 922         pDM_PSTable->CurCCAState = CCA_MAX;
 923         pDM_PSTable->PreRFState = RF_MAX;
 924         pDM_PSTable->CurRFState = RF_MAX;
 925         pDM_PSTable->Rssi_val_min = 0;
 926         pDM_PSTable->initialize = 0;
 927 }
 928
 929 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm)
 930 {
 931         return;
 932 }
 933
 934 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal)
 935 {
 936         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 937         u8 Rssi_Up_bound = 30;
 938         u8 Rssi_Low_bound = 25;
 939         if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
 940                 Rssi_Up_bound = 50;
 941                 Rssi_Low_bound = 45;
 942         }
 943         if (pDM_PSTable->initialize == 0) {
 944
 945                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
 946                 pDM_PSTable->RegC70 =
 947                         (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord) & BIT(3)) >>3;
 948                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
 949                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
 950                 /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */
 951                 pDM_PSTable->initialize = 1;
 952         }
 953
 954         if (!bForceInNormal) {
 955                 if (pDM_Odm->RSSI_Min != 0xFF) {
 956                         if (pDM_PSTable->PreRFState == RF_Normal) {
 957                                 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
 958                                         pDM_PSTable->CurRFState = RF_Save;
 959                                 else
 960                                         pDM_PSTable->CurRFState = RF_Normal;
 961                         } else {
 962                                 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
 963                                         pDM_PSTable->CurRFState = RF_Normal;
 964                                 else
 965                                         pDM_PSTable->CurRFState = RF_Save;
 966                         }
 967                 } else {
 968                         pDM_PSTable->CurRFState = RF_MAX;
 969                 }
 970         } else {
 971                 pDM_PSTable->CurRFState = RF_Normal;
 972         }
 973
 974         if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
 975                 if (pDM_PSTable->CurRFState == RF_Save) {
 976                         /*  <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]= 1 when enter BB power saving mode. */
 977                         /*  Suggested by SD3 Yu-Nan. 2011.01.20. */
 978                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
 979                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]= 1b'1 */
 980                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]= 3'b010 */
 981                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]= 1'b0 */
 982                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
 983                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]= 2'b10 */
 984                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
 985                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]= 1'b0 */
 986                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]= 1'b1 */
 987                 } else {
 988                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
 989                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->RegC70);
 990                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
 991                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
 992                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
 993
 994                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
 995                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]= 1b'0 */
 996                 }
 997                 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
 998         }
 999 }
1000
1001 /* 3 ============================================================ */
1002 /* 3 RATR MASK */
1003 /* 3 ============================================================ */
1004 /* 3 ============================================================ */
1005 /* 3 Rate Adaptive */
1006 /* 3 ============================================================ */
1007
1008 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm)
1009 {
1010         struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1011
1012         pOdmRA->Type = DM_Type_ByDriver;
1013         if (pOdmRA->Type == DM_Type_ByDriver)
1014                 pDM_Odm->bUseRAMask = true;
1015         else
1016                 pDM_Odm->bUseRAMask = false;
1017
1018         pOdmRA->RATRState = DM_RATR_STA_INIT;
1019         pOdmRA->HighRSSIThresh = 50;
1020         pOdmRA->LowRSSIThresh = 20;
1021 }
1022
1023 u32 ODM_Get_Rate_Bitmap23a(struct hal_data_8723a *pHalData, u32 macid,
1024                            u32 ra_mask, u8 rssi_level)
1025 {
1026         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1027         struct sta_info *pEntry;
1028         u32 rate_bitmap = 0x0fffffff;
1029         u8 WirelessMode;
1030
1031         pEntry = pDM_Odm->pODM_StaInfo[macid];
1032         if (!pEntry)
1033                 return ra_mask;
1034
1035         WirelessMode = pEntry->wireless_mode;
1036
1037         switch (WirelessMode) {
1038         case ODM_WM_B:
1039                 if (ra_mask & 0x0000000c)               /* 11M or 5.5M enable */
1040                         rate_bitmap = 0x0000000d;
1041                 else
1042                         rate_bitmap = 0x0000000f;
1043                 break;
1044         case (ODM_WM_A|ODM_WM_G):
1045                 if (rssi_level == DM_RATR_STA_HIGH)
1046                         rate_bitmap = 0x00000f00;
1047                 else
1048                         rate_bitmap = 0x00000ff0;
1049                 break;
1050         case (ODM_WM_B|ODM_WM_G):
1051                 if (rssi_level == DM_RATR_STA_HIGH)
1052                         rate_bitmap = 0x00000f00;
1053                 else if (rssi_level == DM_RATR_STA_MIDDLE)
1054                         rate_bitmap = 0x00000ff0;
1055                 else
1056                         rate_bitmap = 0x00000ff5;
1057                 break;
1058         case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1059         case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1060                 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
1061                         if (rssi_level == DM_RATR_STA_HIGH) {
1062                                 rate_bitmap = 0x000f0000;
1063                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1064                                 rate_bitmap = 0x000ff000;
1065                         } else {
1066                                 if (pHalData->CurrentChannelBW ==
1067                                     HT_CHANNEL_WIDTH_40)
1068                                         rate_bitmap = 0x000ff015;
1069                                 else
1070                                         rate_bitmap = 0x000ff005;
1071                         }
1072                 } else {
1073                         if (rssi_level == DM_RATR_STA_HIGH) {
1074                                 rate_bitmap = 0x0f8f0000;
1075                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1076                                 rate_bitmap = 0x0f8ff000;
1077                         } else {
1078                                 if (pHalData->CurrentChannelBW ==
1079                                     HT_CHANNEL_WIDTH_40)
1080                                         rate_bitmap = 0x0f8ff015;
1081                                 else
1082                                         rate_bitmap = 0x0f8ff005;
1083                         }
1084                 }
1085                 break;
1086         default:
1087                 /* case WIRELESS_11_24N: */
1088                 /* case WIRELESS_11_5N: */
1089                 if (pDM_Odm->RFType == RF_1T2R)
1090                         rate_bitmap = 0x000fffff;
1091                 else
1092                         rate_bitmap = 0x0fffffff;
1093                 break;
1094         }
1095
1096         /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", __func__, rssi_level, WirelessMode, rate_bitmap); */
1097         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", rssi_level, WirelessMode, rate_bitmap));
1098
1099         return rate_bitmap;
1100
1101 }
1102
1103 /*-----------------------------------------------------------------------------
1104  * Function:    odm_RefreshRateAdaptiveMask23a()
1105  *
1106  * Overview:    Update rate table mask according to rssi
1107  *
1108  * Input:               NONE
1109  *
1110  * Output:              NONE
1111  *
1112  * Return:              NONE
1113  *
1114  * Revised History:
1115  *When          Who             Remark
1116  *05/27/2009    hpfan   Create Version 0.
1117  *
1118  *---------------------------------------------------------------------------*/
1119 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm)
1120 {
1121         if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1122                 return;
1123         /*  */
1124         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1125         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1126         /*  HW dynamic mechanism. */
1127         /*  */
1128         odm_RefreshRateAdaptiveMask23aCE23a(pDM_Odm);
1129 }
1130
1131 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm)
1132 {
1133         u8 i;
1134         struct rtw_adapter *pAdapter     =  pDM_Odm->Adapter;
1135
1136         if (pAdapter->bDriverStopped) {
1137                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE,
1138                              ("<---- odm_RefreshRateAdaptiveMask23a(): driver is going to unload\n"));
1139                 return;
1140         }
1141
1142         if (!pDM_Odm->bUseRAMask) {
1143                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1144                              ("<---- odm_RefreshRateAdaptiveMask23a(): driver does not control rate adaptive mask\n"));
1145                 return;
1146         }
1147
1148         /* printk("==> %s \n", __func__); */
1149
1150         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1151                 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1152                 if (pstat) {
1153                         if (ODM_RAStateCheck23a(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
1154                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1155                                              ("RSSI:%d, RSSI_LEVEL:%d\n",
1156                                              pstat->rssi_stat.UndecoratedSmoothedPWDB,
1157                                              pstat->rssi_level));
1158                                 rtw_hal_update_ra_mask23a(pstat, pstat->rssi_level);
1159                         }
1160
1161                 }
1162         }
1163
1164 }
1165
1166 /*  Return Value: bool */
1167 /*  - true: RATRState is changed. */
1168 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1169                          u8 *pRATRState)
1170 {
1171         struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1172         const u8 GoUpGap = 5;
1173         u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1174         u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1175         u8 RATRState;
1176
1177         /*  Threshold Adjustment: */
1178         /*  when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1179         /*  Here GoUpGap is added to solve the boundary's level alternation issue. */
1180         switch (*pRATRState) {
1181         case DM_RATR_STA_INIT:
1182         case DM_RATR_STA_HIGH:
1183                 break;
1184         case DM_RATR_STA_MIDDLE:
1185                 HighRSSIThreshForRA += GoUpGap;
1186                 break;
1187         case DM_RATR_STA_LOW:
1188                 HighRSSIThreshForRA += GoUpGap;
1189                 LowRSSIThreshForRA += GoUpGap;
1190                 break;
1191         default:
1192                 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1193                 break;
1194         }
1195
1196         /*  Decide RATRState by RSSI. */
1197         if (RSSI > HighRSSIThreshForRA)
1198                 RATRState = DM_RATR_STA_HIGH;
1199         else if (RSSI > LowRSSIThreshForRA)
1200                 RATRState = DM_RATR_STA_MIDDLE;
1201         else
1202                 RATRState = DM_RATR_STA_LOW;
1203
1204         if (*pRATRState != RATRState || bForceUpdate) {
1205                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1206                              ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1207                 *pRATRState = RATRState;
1208                 return true;
1209         }
1210         return false;
1211 }
1212
1213 /* 3 ============================================================ */
1214 /* 3 Dynamic Tx Power */
1215 /* 3 ============================================================ */
1216
1217 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm)
1218 {
1219         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1220         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1221         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1222
1223         /*
1224          * This is never changed, so we should be able to clean up the
1225          * code checking for different values in rtl8723a_rf6052.c
1226          */
1227         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1228 }
1229
1230 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm)
1231 {
1232         /*  For AP/ADSL use struct rtl8723a_priv * */
1233         /*  For CE/NIC use struct rtw_adapter * */
1234
1235         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1236                 return;
1237
1238         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1239         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1240         /*  HW dynamic mechanism. */
1241         odm_RSSIMonitorCheck23aCE(pDM_Odm);
1242 }       /*  odm_RSSIMonitorCheck23a */
1243
1244 static void
1245 FindMinimumRSSI(
1246         struct rtw_adapter *pAdapter
1247         )
1248 {
1249         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1250         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1251         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1252
1253         /* 1 1.Determine the minimum RSSI */
1254
1255         if ((!pDM_Odm->bLinked) &&
1256             (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1257                 pdmpriv->MinUndecoratedPWDBForDM = 0;
1258         else
1259                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1260 }
1261
1262 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm)
1263 {
1264         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1265         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1266         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1267         int     i;
1268         int     tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1269         u8 sta_cnt = 0;
1270         u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1271         struct sta_info *psta;
1272
1273         if (!pDM_Odm->bLinked)
1274                 return;
1275
1276         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1277                 psta = pDM_Odm->pODM_StaInfo[i];
1278                 if (psta) {
1279                         if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1280                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1281
1282                         if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1283                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1284
1285                         if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1286                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1287                 }
1288         }
1289
1290         for (i = 0; i < sta_cnt; i++) {
1291                 if (PWDB_rssi[i] != (0)) {
1292                         if (pHalData->fw_ractrl) /*  Report every sta's RSSI to FW */
1293                                 rtl8723a_set_rssi_cmd(Adapter, (u8 *)&PWDB_rssi[i]);
1294                 }
1295         }
1296
1297         if (tmpEntryMaxPWDB != 0)       /*  If associated entry is found */
1298                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1299         else
1300                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1301
1302         if (tmpEntryMinPWDB != 0xff) /*  If associated entry is found */
1303                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1304         else
1305                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1306
1307         FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */
1308
1309         ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1310 }
1311
1312 /* endif */
1313 /* 3 ============================================================ */
1314 /* 3 Tx Power Tracking */
1315 /* 3 ============================================================ */
1316
1317 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm)
1318 {
1319         odm_TXPowerTrackingThermalMeterInit23a(pDM_Odm);
1320 }
1321
1322 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm)
1323 {
1324         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1325         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1326         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1327
1328         pdmpriv->bTXPowerTracking = true;
1329         pdmpriv->TXPowercount = 0;
1330         pdmpriv->bTXPowerTrackingInit = false;
1331         pdmpriv->TxPowerTrackControl = true;
1332         MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
1333
1334         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1335 }
1336
1337 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm)
1338 {
1339         /*  For AP/ADSL use struct rtl8723a_priv * */
1340         /*  For CE/NIC use struct rtw_adapter * */
1341
1342         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1343         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1344         /*  HW dynamic mechanism. */
1345         odm_TXPowerTrackingCheckCE23a(pDM_Odm);
1346 }
1347
1348 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm)
1349 {
1350 }
1351
1352 /* EDCA Turbo */
1353 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm)
1354 {
1355
1356         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1357
1358         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1359         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1360         Adapter->recvpriv.bIsAnyNonBEPkts = false;
1361
1362         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1363         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1364         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1365         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1366
1367 }       /*  ODM_InitEdcaTurbo */
1368
1369 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm)
1370 {
1371         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1372         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1373         struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1374         struct recv_priv *precvpriv = &Adapter->recvpriv;
1375         struct registry_priv *pregpriv = &Adapter->registrypriv;
1376         struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1377         struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1378         u32 trafficIndex;
1379         u32 edca_param;
1380         u64 cur_tx_bytes = 0;
1381         u64 cur_rx_bytes = 0;
1382         u8 bbtchange = false;
1383
1384         /*  For AP/ADSL use struct rtl8723a_priv * */
1385         /*  For CE/NIC use struct rtw_adapter * */
1386
1387         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1388         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1389         /*  HW dynamic mechanism. */
1390
1391         if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1392                 return;
1393
1394         if ((pregpriv->wifi_spec == 1))/*  (pmlmeinfo->HT_enable == 0)) */
1395                 goto dm_CheckEdcaTurbo_EXIT;
1396
1397         if (pmlmeinfo->assoc_AP_vendor >=  HT_IOT_PEER_MAX)
1398                 goto dm_CheckEdcaTurbo_EXIT;
1399
1400         if (rtl8723a_BT_disable_EDCA_turbo(Adapter))
1401                 goto dm_CheckEdcaTurbo_EXIT;
1402
1403         /*  Check if the status needs to be changed. */
1404         if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1405                 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1406                 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1407
1408                 /* traffic, TX or RX */
1409                 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1410                     (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1411                         if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1412                                 /*  Uplink TP is present. */
1413                                 trafficIndex = UP_LINK;
1414                         } else { /*  Balance TP is present. */
1415                                 trafficIndex = DOWN_LINK;
1416                         }
1417                 } else {
1418                         if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1419                                 /*  Downlink TP is present. */
1420                                 trafficIndex = DOWN_LINK;
1421                         } else { /*  Balance TP is present. */
1422                                 trafficIndex = UP_LINK;
1423                         }
1424                 }
1425
1426                 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) ||
1427                     (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1428                         if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) &&
1429                             (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1430                                 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1431                         else
1432                                 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1433                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1434                                           edca_param);
1435
1436                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1437                 }
1438
1439                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1440         } else {
1441                 /*  Turn Off EDCA turbo here. */
1442                 /*  Restore original EDCA according to the declaration of AP. */
1443                 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1444                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1445                                           pHalData->AcParam_BE);
1446                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1447                 }
1448         }
1449
1450 dm_CheckEdcaTurbo_EXIT:
1451         /*  Set variables for next time. */
1452         precvpriv->bIsAnyNonBEPkts = false;
1453         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1454         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1455 }
1456
1457 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1458 {
1459         u32 psd_report;
1460
1461         /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */
1462         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1463
1464         /* Start PSD calculation, Reg808[22]= 0->1 */
1465         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);
1466         /* Need to wait for HW PSD report */
1467         udelay(30);
1468         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);
1469         /* Read PSD report, Reg8B4[15:0] */
1470         psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1471
1472         psd_report = (u32)(ConvertTo_dB23a(psd_report))+(u32)(initial_gain_psd-0x1c);
1473
1474         return psd_report;
1475 }
1476
1477 u32
1478 ConvertTo_dB23a(
1479         u32 Value)
1480 {
1481         u8 i;
1482         u8 j;
1483         u32 dB;
1484
1485         Value = Value & 0xFFFF;
1486
1487         for (i = 0; i < 8; i++) {
1488                 if (Value <= dB_Invert_Table[i][11])
1489                         break;
1490         }
1491
1492         if (i >= 8)
1493                 return 96;      /*  maximum 96 dB */
1494
1495         for (j = 0; j < 12; j++) {
1496                 if (Value <= dB_Invert_Table[i][j])
1497                         break;
1498         }
1499
1500         dB = i*12 + j + 1;
1501
1502         return dB;
1503 }
1504
1505 /*  */
1506 /*  Description: */
1507 /*Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1508 /*  */
1509 /*  Added by Joseph, 2012.03.22 */
1510 /*  */
1511 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm)
1512 {
1513         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1514
1515         pDM_SWAT_Table->ANTA_ON = true;
1516         pDM_SWAT_Table->ANTB_ON = true;
1517 }
1518
1519 /* 2 8723A ANT DETECT */
1520
1521 static void odm_PHY_SaveAFERegisters(
1522         struct dm_odm_t *pDM_Odm,
1523         u32 *AFEReg,
1524         u32 *AFEBackup,
1525         u32 RegisterNum
1526         )
1527 {
1528         u32 i;
1529
1530         /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1531         for (i = 0 ; i < RegisterNum ; i++)
1532                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1533 }
1534
1535 static void odm_PHY_ReloadAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1536                                        u32 *AFEBackup, u32 RegiesterNum)
1537 {
1538         u32 i;
1539
1540         for (i = 0 ; i < RegiesterNum; i++)
1541                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1542 }
1543
1544 /* 2 8723A ANT DETECT */
1545 /*  Description: */
1546 /* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1547 /* This function is cooperated with BB team Neil. */
1548 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode)
1549 {
1550         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1551         u32 CurrentChannel, RfLoopReg;
1552         u8 n;
1553         u32 Reg88c, Regc08, Reg874, Regc50;
1554         u8 initial_gain = 0x5a;
1555         u32 PSD_report_tmp;
1556         u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1557         bool bResult = true;
1558         u32 AFE_Backup[16];
1559         u32 AFE_REG_8723A[16] = {
1560                 rRx_Wait_CCA, rTx_CCK_RFON,
1561                 rTx_CCK_BBON, rTx_OFDM_RFON,
1562                 rTx_OFDM_BBON, rTx_To_Rx,
1563                 rTx_To_Tx, rRx_CCK,
1564                 rRx_OFDM, rRx_Wait_RIFS,
1565                 rRx_TO_Rx, rStandby,
1566                 rSleep, rPMPD_ANAEN,
1567                 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1568
1569         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
1570                 return bResult;
1571
1572         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1573                 return bResult;
1574         /* 1 Backup Current RF/BB Settings */
1575
1576         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1577         RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1578         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  /*  change to Antenna A */
1579         /*  Step 1: USE IQK to transmitter single tone */
1580
1581         udelay(10);
1582
1583         /* Store A Path Register 88c, c08, 874, c50 */
1584         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1585         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1586         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1587         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1588
1589         /*  Store AFE Registers */
1590         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1591
1592         /* Set PSD 128 pts */
1593         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0);
1594
1595         /*  To SET CH1 to do */
1596         ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */
1597
1598         /*  AFE all on step */
1599         ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1600         ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1601         ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1602         ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1603         ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1604         ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1605         ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1606         ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1607         ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1608         ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1609         ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1610         ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1611         ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1612         ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1613         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1614         ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1615
1616         /*  3 wire Disable */
1617         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1618
1619         /* BB IQK Setting */
1620         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1621         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1622
1623         /* IQK setting tone@ 4.34Mhz */
1624         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1625         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1626
1627         /* Page B init */
1628         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1629         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1630         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1631         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1632         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1633         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1634         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1635
1636         /* RF loop Setting */
1637         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1638
1639         /* IQK Single tone start */
1640         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1641         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1642         udelay(1000);
1643         PSD_report_tmp = 0x0;
1644
1645         for (n = 0; n < 2; n++) {
1646                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1647                 if (PSD_report_tmp > AntA_report)
1648                         AntA_report = PSD_report_tmp;
1649         }
1650
1651         PSD_report_tmp = 0x0;
1652
1653         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);  /*  change to Antenna B */
1654         udelay(10);
1655
1656         for (n = 0; n < 2; n++) {
1657                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1658                 if (PSD_report_tmp > AntB_report)
1659                         AntB_report = PSD_report_tmp;
1660         }
1661
1662         /*  change to open case */
1663         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0);  /*  change to Ant A and B all open case */
1664         udelay(10);
1665
1666         for (n = 0; n < 2; n++) {
1667                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1668                 if (PSD_report_tmp > AntO_report)
1669                         AntO_report = PSD_report_tmp;
1670         }
1671
1672         /* Close IQK Single Tone function */
1673         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1674         PSD_report_tmp = 0x0;
1675
1676         /* 1 Return to antanna A */
1677         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1678         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1679         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1680         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1681         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1682         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1683         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1684         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1685
1686         /* Reload AFE Registers */
1687         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1688
1689         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
1690         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
1691         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
1692
1693         /* 2 Test Ant B based on Ant A is ON */
1694         if (mode == ANTTESTB) {
1695                 if (AntA_report >= 100) {
1696                         if (AntB_report > (AntA_report+1)) {
1697                                 pDM_SWAT_Table->ANTB_ON = false;
1698                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
1699                         } else {
1700                                 pDM_SWAT_Table->ANTB_ON = true;
1701                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
1702                         }
1703                 } else {
1704                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1705                         pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1706                         bResult = false;
1707                 }
1708         } else if (mode == ANTTESTALL) {
1709                 /* 2 Test Ant A and B based on DPDT Open */
1710                 if ((AntO_report >= 100) & (AntO_report < 118)) {
1711                         if (AntA_report > (AntO_report+1)) {
1712                                 pDM_SWAT_Table->ANTA_ON = false;
1713                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
1714                         } else {
1715                                 pDM_SWAT_Table->ANTA_ON = true;
1716                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
1717                         }
1718
1719                         if (AntB_report > (AntO_report+2)) {
1720                                 pDM_SWAT_Table->ANTB_ON = false;
1721                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
1722                         } else {
1723                                 pDM_SWAT_Table->ANTB_ON = true;
1724                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
1725                         }
1726                 }
1727         } else {
1728                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1729                 pDM_SWAT_Table->ANTA_ON = true; /*  Set Antenna A on as default */
1730                 pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1731                 bResult = false;
1732         }
1733         return bResult;
1734 }
1735
1736 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
1737 void odm_dtc(struct dm_odm_t *pDM_Odm)
1738 {
1739 }