drivers/staging/sm750fb/ddk750_display.c

   1 #include "ddk750_reg.h"
   2 #include "ddk750_help.h"
   3 #include "ddk750_display.h"
   4 #include "ddk750_power.h"
   5 #include "ddk750_dvi.h"
   6
   7 #define primaryWaitVerticalSync(delay) waitNextVerticalSync(0, delay)
   8
   9 static void setDisplayControl(int ctrl, int disp_state)
  10 {
  11         /* state != 0 means turn on both timing & plane en_bit */
  12         unsigned long reg, val, reserved;
  13         int cnt = 0;
  14
  15         if (!ctrl) {
  16                 reg = PANEL_DISPLAY_CTRL;
  17                 reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK;
  18         } else {
  19                 reg = CRT_DISPLAY_CTRL;
  20                 reserved = CRT_DISPLAY_CTRL_RESERVED_MASK;
  21         }
  22
  23         val = PEEK32(reg);
  24         if (disp_state) {
  25                 /*
  26                  * Timing should be enabled first before enabling the
  27                  * plane because changing at the same time does not
  28                  * guarantee that the plane will also enabled or
  29                  * disabled.
  30                  */
  31                 val |= DISPLAY_CTRL_TIMING;
  32                 POKE32(reg, val);
  33
  34                 val |= DISPLAY_CTRL_PLANE;
  35
  36                 /*
  37                  * Somehow the register value on the plane is not set
  38                  * until a few delay. Need to write and read it a
  39                  * couple times
  40                  */
  41                 do {
  42                         cnt++;
  43                         POKE32(reg, val);
  44                 } while ((PEEK32(reg) & ~reserved) != (val & ~reserved));
  45                 pr_debug("Set Plane enbit:after tried %d times\n", cnt);
  46         } else {
  47                 /*
  48                  * When turning off, there is no rule on the
  49                  * programming sequence since whenever the clock is
  50                  * off, then it does not matter whether the plane is
  51                  * enabled or disabled.  Note: Modifying the plane bit
  52                  * will take effect on the next vertical sync. Need to
  53                  * find out if it is necessary to wait for 1 vsync
  54                  * before modifying the timing enable bit.
  55                  */
  56                 val &= ~DISPLAY_CTRL_PLANE;
  57                 POKE32(reg, val);
  58
  59                 val &= ~DISPLAY_CTRL_TIMING;
  60                 POKE32(reg, val);
  61         }
  62 }
  63
  64 static void waitNextVerticalSync(int ctrl, int delay)
  65 {
  66         unsigned int status;
  67
  68         if (!ctrl) {
  69                 /* primary controller */
  70
  71                 /* Do not wait when the Primary PLL is off or display control is already off.
  72                    This will prevent the software to wait forever. */
  73                 if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
  74                     !(PEEK32(PANEL_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) {
  75                         return;
  76                 }
  77
  78                 while (delay-- > 0) {
  79                         /* Wait for end of vsync. */
  80                         do {
  81                                 status = PEEK32(SYSTEM_CTRL);
  82                         } while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
  83
  84                         /* Wait for start of vsync. */
  85                         do {
  86                                 status = PEEK32(SYSTEM_CTRL);
  87                         } while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
  88                 }
  89
  90         } else {
  91
  92                 /* Do not wait when the Primary PLL is off or display control is already off.
  93                            This will prevent the software to wait forever. */
  94                 if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) ||
  95                     !(PEEK32(CRT_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) {
  96                         return;
  97                 }
  98
  99                 while (delay-- > 0) {
 100                         /* Wait for end of vsync. */
 101                         do {
 102                                 status = PEEK32(SYSTEM_CTRL);
 103                         } while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
 104
 105                         /* Wait for start of vsync. */
 106                         do {
 107                                 status = PEEK32(SYSTEM_CTRL);
 108                         } while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
 109                 }
 110         }
 111 }
 112
 113 static void swPanelPowerSequence(int disp, int delay)
 114 {
 115         unsigned int reg;
 116
 117         /* disp should be 1 to open sequence */
 118         reg = PEEK32(PANEL_DISPLAY_CTRL);
 119         reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
 120         POKE32(PANEL_DISPLAY_CTRL, reg);
 121         primaryWaitVerticalSync(delay);
 122
 123         reg = PEEK32(PANEL_DISPLAY_CTRL);
 124         reg |= (disp ? PANEL_DISPLAY_CTRL_DATA : 0);
 125         POKE32(PANEL_DISPLAY_CTRL, reg);
 126         primaryWaitVerticalSync(delay);
 127
 128         reg = PEEK32(PANEL_DISPLAY_CTRL);
 129         reg |= (disp ? PANEL_DISPLAY_CTRL_VBIASEN : 0);
 130         POKE32(PANEL_DISPLAY_CTRL, reg);
 131         primaryWaitVerticalSync(delay);
 132
 133         reg = PEEK32(PANEL_DISPLAY_CTRL);
 134         reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
 135         POKE32(PANEL_DISPLAY_CTRL, reg);
 136         primaryWaitVerticalSync(delay);
 137
 138 }
 139
 140 void ddk750_setLogicalDispOut(disp_output_t output)
 141 {
 142         unsigned int reg;
 143
 144         if (output & PNL_2_USAGE) {
 145                 /* set panel path controller select */
 146                 reg = PEEK32(PANEL_DISPLAY_CTRL);
 147                 reg &= ~PANEL_DISPLAY_CTRL_SELECT_MASK;
 148                 reg |= (((output & PNL_2_MASK) >> PNL_2_OFFSET) <<
 149                         PANEL_DISPLAY_CTRL_SELECT_SHIFT);
 150                 POKE32(PANEL_DISPLAY_CTRL, reg);
 151         }
 152
 153         if (output & CRT_2_USAGE) {
 154                 /* set crt path controller select */
 155                 reg = PEEK32(CRT_DISPLAY_CTRL);
 156                 reg &= ~CRT_DISPLAY_CTRL_SELECT_MASK;
 157                 reg |= (((output & CRT_2_MASK) >> CRT_2_OFFSET) <<
 158                         CRT_DISPLAY_CTRL_SELECT_SHIFT);
 159                 /*se blank off */
 160                 reg &= ~CRT_DISPLAY_CTRL_BLANK;
 161                 POKE32(CRT_DISPLAY_CTRL, reg);
 162
 163         }
 164
 165         if (output & PRI_TP_USAGE) {
 166                 /* set primary timing and plane en_bit */
 167                 setDisplayControl(0, (output & PRI_TP_MASK) >> PRI_TP_OFFSET);
 168         }
 169
 170         if (output & SEC_TP_USAGE) {
 171                 /* set secondary timing and plane en_bit*/
 172                 setDisplayControl(1, (output & SEC_TP_MASK) >> SEC_TP_OFFSET);
 173         }
 174
 175         if (output & PNL_SEQ_USAGE) {
 176                 /* set  panel sequence */
 177                 swPanelPowerSequence((output & PNL_SEQ_MASK) >> PNL_SEQ_OFFSET, 4);
 178         }
 179
 180         if (output & DAC_USAGE)
 181                 setDAC((output & DAC_MASK) >> DAC_OFFSET);
 182
 183         if (output & DPMS_USAGE)
 184                 ddk750_setDPMS((output & DPMS_MASK) >> DPMS_OFFSET);
 185 }