drivers/staging/sm750fb/ddk750_mode.c

   1
   2 #include "ddk750_help.h"
   3 #include "ddk750_reg.h"
   4 #include "ddk750_mode.h"
   5 #include "ddk750_chip.h"
   6
   7 /*
   8         SM750LE only:
   9     This function takes care extra registers and bit fields required to set
  10     up a mode in SM750LE
  11
  12         Explanation about Display Control register:
  13     HW only supports 7 predefined pixel clocks, and clock select is
  14     in bit 29:27 of     Display Control register.
  15 */
  16 static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, unsigned long dispControl)
  17 {
  18         unsigned long x, y;
  19
  20         x = pModeParam->horizontal_display_end;
  21         y = pModeParam->vertical_display_end;
  22
  23         /* SM750LE has to set up the top-left and bottom-right
  24            registers as well.
  25            Note that normal SM750/SM718 only use those two register for
  26            auto-centering mode.
  27          */
  28         POKE32(CRT_AUTO_CENTERING_TL, 0);
  29
  30         POKE32(CRT_AUTO_CENTERING_BR,
  31                 (((y - 1) << CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT) &
  32                         CRT_AUTO_CENTERING_BR_BOTTOM_MASK) |
  33                 ((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK));
  34
  35         /* Assume common fields in dispControl have been properly set before
  36            calling this function.
  37            This function only sets the extra fields in dispControl.
  38          */
  39
  40         /* Clear bit 29:27 of display control register */
  41         dispControl &= ~CRT_DISPLAY_CTRL_CLK_MASK;
  42
  43         /* Set bit 29:27 of display control register for the right clock */
  44         /* Note that SM750LE only need to supported 7 resolutions. */
  45         if (x == 800 && y == 600)
  46                 dispControl |= CRT_DISPLAY_CTRL_CLK_PLL41;
  47         else if (x == 1024 && y == 768)
  48                 dispControl |= CRT_DISPLAY_CTRL_CLK_PLL65;
  49         else if (x == 1152 && y == 864)
  50                 dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80;
  51         else if (x == 1280 && y == 768)
  52                 dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80;
  53         else if (x == 1280 && y == 720)
  54                 dispControl |= CRT_DISPLAY_CTRL_CLK_PLL74;
  55         else if (x == 1280 && y == 960)
  56                 dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108;
  57         else if (x == 1280 && y == 1024)
  58                 dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108;
  59         else /* default to VGA clock */
  60                 dispControl |= CRT_DISPLAY_CTRL_CLK_PLL25;
  61
  62         /* Set bit 25:24 of display controller */
  63         dispControl |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT);
  64
  65         /* Set bit 14 of display controller */
  66         dispControl = DISPLAY_CTRL_CLOCK_PHASE;
  67
  68         POKE32(CRT_DISPLAY_CTRL, dispControl);
  69
  70         return dispControl;
  71 }
  72
  73
  74
  75 /* only timing related registers will be  programed */
  76 static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll)
  77 {
  78         int ret = 0;
  79         int cnt = 0;
  80         unsigned int tmp, reg;
  81
  82         if (pll->clockType == SECONDARY_PLL) {
  83                 /* programe secondary pixel clock */
  84                 POKE32(CRT_PLL_CTRL, formatPllReg(pll));
  85                 POKE32(CRT_HORIZONTAL_TOTAL,
  86                         (((pModeParam->horizontal_total - 1) <<
  87                                 CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
  88                                 CRT_HORIZONTAL_TOTAL_TOTAL_MASK) |
  89                         ((pModeParam->horizontal_display_end - 1) &
  90                                 CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK));
  91
  92                 POKE32(CRT_HORIZONTAL_SYNC,
  93                         ((pModeParam->horizontal_sync_width <<
  94                                 CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) &
  95                                 CRT_HORIZONTAL_SYNC_WIDTH_MASK) |
  96                         ((pModeParam->horizontal_sync_start - 1) &
  97                                 CRT_HORIZONTAL_SYNC_START_MASK));
  98
  99                 POKE32(CRT_VERTICAL_TOTAL,
 100                         (((pModeParam->vertical_total - 1) <<
 101                                 CRT_VERTICAL_TOTAL_TOTAL_SHIFT) &
 102                                 CRT_VERTICAL_TOTAL_TOTAL_MASK) |
 103                         ((pModeParam->vertical_display_end - 1) &
 104                                 CRT_VERTICAL_TOTAL_DISPLAY_END_MASK));
 105
 106                 POKE32(CRT_VERTICAL_SYNC,
 107                 FIELD_VALUE(0, CRT_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height)
 108                 | FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
 109
 110
 111                 tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
 112                 if (pModeParam->vertical_sync_polarity)
 113                         tmp |= DISPLAY_CTRL_VSYNC_PHASE;
 114                 if (pModeParam->horizontal_sync_polarity)
 115                         tmp |= DISPLAY_CTRL_HSYNC_PHASE;
 116
 117                 if (getChipType() == SM750LE) {
 118                         displayControlAdjust_SM750LE(pModeParam, tmp);
 119                 } else {
 120                         reg = PEEK32(CRT_DISPLAY_CTRL) &
 121                                 ~(DISPLAY_CTRL_VSYNC_PHASE |
 122                                   DISPLAY_CTRL_HSYNC_PHASE |
 123                                   DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE);
 124
 125                          POKE32(CRT_DISPLAY_CTRL, tmp | reg);
 126                 }
 127
 128         } else if (pll->clockType == PRIMARY_PLL) {
 129                 unsigned int reserved;
 130
 131                 POKE32(PANEL_PLL_CTRL, formatPllReg(pll));
 132
 133                 reg = ((pModeParam->horizontal_total - 1) <<
 134                         PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
 135                         PANEL_HORIZONTAL_TOTAL_TOTAL_MASK;
 136                 reg |= ((pModeParam->horizontal_display_end - 1) &
 137                         PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK);
 138                 POKE32(PANEL_HORIZONTAL_TOTAL, reg);
 139
 140                 POKE32(PANEL_HORIZONTAL_SYNC,
 141                 FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, WIDTH, pModeParam->horizontal_sync_width)
 142                 | FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, START, pModeParam->horizontal_sync_start - 1));
 143
 144                 POKE32(PANEL_VERTICAL_TOTAL,
 145                 FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, TOTAL, pModeParam->vertical_total - 1)
 146                         | FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, DISPLAY_END, pModeParam->vertical_display_end - 1));
 147
 148                 POKE32(PANEL_VERTICAL_SYNC,
 149                 FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height)
 150                 | FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
 151
 152                 tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
 153                 if (pModeParam->vertical_sync_polarity)
 154                         tmp |= DISPLAY_CTRL_VSYNC_PHASE;
 155                 if (pModeParam->horizontal_sync_polarity)
 156                         tmp |= DISPLAY_CTRL_HSYNC_PHASE;
 157                 if (pModeParam->clock_phase_polarity)
 158                         tmp |= DISPLAY_CTRL_CLOCK_PHASE;
 159
 160                 reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK |
 161                         PANEL_DISPLAY_CTRL_VSYNC;
 162
 163                 reg = (PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) &
 164                         ~(DISPLAY_CTRL_CLOCK_PHASE | DISPLAY_CTRL_VSYNC_PHASE |
 165                           DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING |
 166                           DISPLAY_CTRL_PLANE);
 167
 168                 /* May a hardware bug or just my test chip (not confirmed).
 169                 * PANEL_DISPLAY_CTRL register seems requiring few writes
 170                 * before a value can be successfully written in.
 171                 * Added some masks to mask out the reserved bits.
 172                 * Note: This problem happens by design. The hardware will wait for the
 173                 *       next vertical sync to turn on/off the plane.
 174                 */
 175
 176                 POKE32(PANEL_DISPLAY_CTRL, tmp | reg);
 177
 178                 while ((PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) !=
 179                         (tmp | reg)) {
 180                         cnt++;
 181                         if (cnt > 1000)
 182                                 break;
 183                         POKE32(PANEL_DISPLAY_CTRL, tmp | reg);
 184                 }
 185         } else {
 186                 ret = -1;
 187         }
 188         return ret;
 189 }
 190
 191 int ddk750_setModeTiming(mode_parameter_t *parm, clock_type_t clock)
 192 {
 193         pll_value_t pll;
 194         unsigned int uiActualPixelClk;
 195
 196         pll.inputFreq = DEFAULT_INPUT_CLOCK;
 197         pll.clockType = clock;
 198
 199         uiActualPixelClk = calcPllValue(parm->pixel_clock, &pll);
 200         if (getChipType() == SM750LE) {
 201                 /* set graphic mode via IO method */
 202                 outb_p(0x88, 0x3d4);
 203                 outb_p(0x06, 0x3d5);
 204         }
 205         programModeRegisters(parm, &pll);
 206         return 0;
 207 }
 208
 209