2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: Implement functions to access baseband
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
31 * BBbReadEmbedded - Embedded read baseband register via MAC
32 * BBbWriteEmbedded - Embedded write baseband register via MAC
33 * BBbIsRegBitsOn - Test if baseband register bits on
34 * BBbIsRegBitsOff - Test if baseband register bits off
35 * BBbVT3253Init - VIA VT3253 baseband chip init code
36 * BBvReadAllRegs - Read All Baseband Registers
37 * BBvLoopbackOn - Turn on BaseBand Loopback mode
38 * BBvLoopbackOff - Turn off BaseBand Loopback mode
41 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
42 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
43 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter().
44 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
46 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
47 * Modified BBvLoopbackOn & BBvLoopbackOff().
59 /*--------------------- Static Definitions -------------------------*/
60 //static int msglevel =MSG_LEVEL_DEBUG;
61 static int msglevel = MSG_LEVEL_INFO;
63 /*--------------------- Static Classes ----------------------------*/
65 /*--------------------- Static Variables --------------------------*/
67 /*--------------------- Static Functions --------------------------*/
69 /*--------------------- Export Variables --------------------------*/
71 /*--------------------- Static Definitions -------------------------*/
73 /*--------------------- Static Classes ----------------------------*/
75 /*--------------------- Static Variables --------------------------*/
77 #define CB_VT3253_INIT_FOR_RFMD 446
78 unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
527 #define CB_VT3253B0_INIT_FOR_RFMD 256
528 unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
787 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
789 unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
987 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
989 unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1098 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1248 #define CB_VT3253B0_INIT_FOR_UW2451 256
1250 unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1359 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1509 #define CB_VT3253B0_AGC 193
1511 unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1707 const unsigned short awcFrameTime[MAX_RATE] =
1708 {10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216};
1710 /*--------------------- Static Functions --------------------------*/
1714 s_ulGetRatio(PSDevice pDevice);
1728 if (pDevice->dwRxAntennaSel == 0) {
1729 pDevice->dwRxAntennaSel = 1;
1730 if (pDevice->bTxRxAntInv == true)
1731 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1733 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1735 pDevice->dwRxAntennaSel = 0;
1736 if (pDevice->bTxRxAntInv == true)
1737 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1739 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1741 if (pDevice->dwTxAntennaSel == 0) {
1742 pDevice->dwTxAntennaSel = 1;
1743 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_B);
1745 pDevice->dwTxAntennaSel = 0;
1746 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_A);
1750 /*--------------------- Export Variables --------------------------*/
1752 * Description: Calculate data frame transmitting time
1756 * byPreambleType - Preamble Type
1757 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1758 * cbFrameLength - Baseband Type
1762 * Return Value: FrameTime
1767 unsigned char byPreambleType,
1768 unsigned char byPktType,
1769 unsigned int cbFrameLength,
1770 unsigned short wRate
1773 unsigned int uFrameTime;
1774 unsigned int uPreamble;
1776 unsigned int uRateIdx = (unsigned int) wRate;
1777 unsigned int uRate = 0;
1779 if (uRateIdx > RATE_54M) {
1784 uRate = (unsigned int)awcFrameTime[uRateIdx];
1786 if (uRateIdx <= 3) { //CCK mode
1787 if (byPreambleType == 1) //Short
1792 uFrameTime = (cbFrameLength * 80) / uRate; //?????
1793 uTmp = (uFrameTime * uRate) / 80;
1794 if (cbFrameLength != uTmp)
1797 return uPreamble + uFrameTime;
1799 uFrameTime = (cbFrameLength * 8 + 22) / uRate; //????????
1800 uTmp = ((uFrameTime * uRate) - 22) / 8;
1801 if (cbFrameLength != uTmp)
1804 uFrameTime = uFrameTime * 4; //???????
1805 if (byPktType != PK_TYPE_11A)
1806 uFrameTime += 6; //??????
1808 return 20 + uFrameTime; //??????
1813 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1817 * pDevice - Device Structure
1818 * cbFrameLength - Tx Frame Length
1821 * pwPhyLen - pointer to Phy Length field
1822 * pbyPhySrv - pointer to Phy Service field
1823 * pbyPhySgn - pointer to Phy Signal field
1825 * Return Value: none
1829 BBvCalculateParameter(
1831 unsigned int cbFrameLength,
1832 unsigned short wRate,
1833 unsigned char byPacketType,
1834 unsigned short *pwPhyLen,
1835 unsigned char *pbyPhySrv,
1836 unsigned char *pbyPhySgn
1839 unsigned int cbBitCount;
1840 unsigned int cbUsCount = 0;
1843 unsigned char byPreambleType = pDevice->byPreambleType;
1844 bool bCCK = pDevice->bCCK;
1846 cbBitCount = cbFrameLength * 8;
1851 cbUsCount = cbBitCount;
1856 cbUsCount = cbBitCount / 2;
1857 if (byPreambleType == 1)
1859 else // long preamble
1866 cbUsCount = (cbBitCount * 10) / 55;
1867 cbTmp = (cbUsCount * 55) / 10;
1868 if (cbTmp != cbBitCount)
1870 if (byPreambleType == 1)
1872 else // long preamble
1880 cbUsCount = cbBitCount / 11;
1881 cbTmp = cbUsCount * 11;
1882 if (cbTmp != cbBitCount) {
1884 if ((cbBitCount - cbTmp) <= 3)
1887 if (byPreambleType == 1)
1889 else // long preamble
1894 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1895 *pbyPhySgn = 0x9B; //1001 1011
1896 } else {//11g, 2.4GHZ
1897 *pbyPhySgn = 0x8B; //1000 1011
1902 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1903 *pbyPhySgn = 0x9F; //1001 1111
1904 } else {//11g, 2.4GHZ
1905 *pbyPhySgn = 0x8F; //1000 1111
1910 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1911 *pbyPhySgn = 0x9A; //1001 1010
1912 } else {//11g, 2.4GHZ
1913 *pbyPhySgn = 0x8A; //1000 1010
1918 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1919 *pbyPhySgn = 0x9E; //1001 1110
1920 } else {//11g, 2.4GHZ
1921 *pbyPhySgn = 0x8E; //1000 1110
1926 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1927 *pbyPhySgn = 0x99; //1001 1001
1928 } else {//11g, 2.4GHZ
1929 *pbyPhySgn = 0x89; //1000 1001
1934 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1935 *pbyPhySgn = 0x9D; //1001 1101
1936 } else {//11g, 2.4GHZ
1937 *pbyPhySgn = 0x8D; //1000 1101
1942 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1943 *pbyPhySgn = 0x98; //1001 1000
1944 } else {//11g, 2.4GHZ
1945 *pbyPhySgn = 0x88; //1000 1000
1950 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1951 *pbyPhySgn = 0x9C; //1001 1100
1952 } else {//11g, 2.4GHZ
1953 *pbyPhySgn = 0x8C; //1000 1100
1958 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1959 *pbyPhySgn = 0x9C; //1001 1100
1960 } else {//11g, 2.4GHZ
1961 *pbyPhySgn = 0x8C; //1000 1100
1966 if (byPacketType == PK_TYPE_11B) {
1969 *pbyPhySrv = *pbyPhySrv | 0x80;
1970 *pwPhyLen = (unsigned short)cbUsCount;
1973 *pwPhyLen = (unsigned short)cbFrameLength;
1978 * Description: Read a byte from BASEBAND, by embedded programming
1982 * dwIoBase - I/O base address
1983 * byBBAddr - address of register in Baseband
1985 * pbyData - data read
1987 * Return Value: true if succeeded; false if failed.
1990 bool BBbReadEmbedded(unsigned long dwIoBase, unsigned char byBBAddr, unsigned char *pbyData)
1993 unsigned char byValue;
1996 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
1999 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
2000 // W_MAX_TIMEOUT is the timeout period
2001 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2002 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2003 if (byValue & BBREGCTL_DONE)
2008 VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);
2010 if (ww == W_MAX_TIMEOUT) {
2012 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO " DBG_PORT80(0x30)\n");
2019 * Description: Write a Byte to BASEBAND, by embedded programming
2023 * dwIoBase - I/O base address
2024 * byBBAddr - address of register in Baseband
2025 * byData - data to write
2029 * Return Value: true if succeeded; false if failed.
2032 bool BBbWriteEmbedded(unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byData)
2035 unsigned char byValue;
2038 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2040 VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);
2042 // turn on BBREGCTL_REGW
2043 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
2044 // W_MAX_TIMEOUT is the timeout period
2045 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2046 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2047 if (byValue & BBREGCTL_DONE)
2051 if (ww == W_MAX_TIMEOUT) {
2053 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO " DBG_PORT80(0x31)\n");
2060 * Description: Test if all bits are set for the Baseband register
2064 * dwIoBase - I/O base address
2065 * byBBAddr - address of register in Baseband
2066 * byTestBits - TestBits
2070 * Return Value: true if all TestBits are set; false otherwise.
2073 bool BBbIsRegBitsOn(unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2075 unsigned char byOrgData;
2077 BBbReadEmbedded(dwIoBase, byBBAddr, &byOrgData);
2078 return (byOrgData & byTestBits) == byTestBits;
2082 * Description: Test if all bits are clear for the Baseband register
2086 * dwIoBase - I/O base address
2087 * byBBAddr - address of register in Baseband
2088 * byTestBits - TestBits
2092 * Return Value: true if all TestBits are clear; false otherwise.
2095 bool BBbIsRegBitsOff(unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2097 unsigned char byOrgData;
2099 BBbReadEmbedded(dwIoBase, byBBAddr, &byOrgData);
2100 return (byOrgData & byTestBits) == 0;
2104 * Description: VIA VT3253 Baseband chip init function
2108 * dwIoBase - I/O base address
2109 * byRevId - Revision ID
2110 * byRFType - RF type
2114 * Return Value: true if succeeded; false if failed.
2118 bool BBbVT3253Init(PSDevice pDevice)
2120 bool bResult = true;
2122 unsigned long dwIoBase = pDevice->PortOffset;
2123 unsigned char byRFType = pDevice->byRFType;
2124 unsigned char byLocalID = pDevice->byLocalID;
2126 if (byRFType == RF_RFMD2959) {
2127 if (byLocalID <= REV_ID_VT3253_A1) {
2128 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++)
2129 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253InitTab_RFMD[ii][0], byVT3253InitTab_RFMD[ii][1]);
2132 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++)
2133 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_RFMD[ii][0], byVT3253B0_RFMD[ii][1]);
2135 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++)
2136 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC4_RFMD2959[ii][0], byVT3253B0_AGC4_RFMD2959[ii][1]);
2138 VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2139 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2141 pDevice->abyBBVGA[0] = 0x18;
2142 pDevice->abyBBVGA[1] = 0x0A;
2143 pDevice->abyBBVGA[2] = 0x0;
2144 pDevice->abyBBVGA[3] = 0x0;
2145 pDevice->ldBmThreshold[0] = -70;
2146 pDevice->ldBmThreshold[1] = -50;
2147 pDevice->ldBmThreshold[2] = 0;
2148 pDevice->ldBmThreshold[3] = 0;
2149 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S)) {
2150 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2151 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2153 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2154 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2156 pDevice->abyBBVGA[0] = 0x1C;
2157 pDevice->abyBBVGA[1] = 0x10;
2158 pDevice->abyBBVGA[2] = 0x0;
2159 pDevice->abyBBVGA[3] = 0x0;
2160 pDevice->ldBmThreshold[0] = -70;
2161 pDevice->ldBmThreshold[1] = -48;
2162 pDevice->ldBmThreshold[2] = 0;
2163 pDevice->ldBmThreshold[3] = 0;
2164 } else if (byRFType == RF_UW2451) {
2165 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2166 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]);
2168 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2169 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2171 VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2172 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2174 pDevice->abyBBVGA[0] = 0x14;
2175 pDevice->abyBBVGA[1] = 0x0A;
2176 pDevice->abyBBVGA[2] = 0x0;
2177 pDevice->abyBBVGA[3] = 0x0;
2178 pDevice->ldBmThreshold[0] = -60;
2179 pDevice->ldBmThreshold[1] = -50;
2180 pDevice->ldBmThreshold[2] = 0;
2181 pDevice->ldBmThreshold[3] = 0;
2182 } else if (byRFType == RF_UW2452) {
2183 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2184 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]);
2186 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2187 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2188 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2189 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2190 // Select VC1/VC2, CR215 = 0x02->0x06
2191 bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
2193 //{{RobertYu:20050125, request by Jack
2194 bResult &= BBbWriteEmbedded(dwIoBase, 0x90, 0x20);
2195 bResult &= BBbWriteEmbedded(dwIoBase, 0x97, 0xeb);
2198 //{{RobertYu:20050221, request by Jack
2199 bResult &= BBbWriteEmbedded(dwIoBase, 0xa6, 0x00);
2200 bResult &= BBbWriteEmbedded(dwIoBase, 0xa8, 0x30);
2202 bResult &= BBbWriteEmbedded(dwIoBase, 0xb0, 0x58);
2204 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2205 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2207 pDevice->abyBBVGA[0] = 0x14;
2208 pDevice->abyBBVGA[1] = 0x0A;
2209 pDevice->abyBBVGA[2] = 0x0;
2210 pDevice->abyBBVGA[3] = 0x0;
2211 pDevice->ldBmThreshold[0] = -60;
2212 pDevice->ldBmThreshold[1] = -50;
2213 pDevice->ldBmThreshold[2] = 0;
2214 pDevice->ldBmThreshold[3] = 0;
2217 } else if (byRFType == RF_VT3226) {
2218 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2219 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2221 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2222 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2224 pDevice->abyBBVGA[0] = 0x1C;
2225 pDevice->abyBBVGA[1] = 0x10;
2226 pDevice->abyBBVGA[2] = 0x0;
2227 pDevice->abyBBVGA[3] = 0x0;
2228 pDevice->ldBmThreshold[0] = -70;
2229 pDevice->ldBmThreshold[1] = -48;
2230 pDevice->ldBmThreshold[2] = 0;
2231 pDevice->ldBmThreshold[3] = 0;
2232 // Fix VT3226 DFC system timing issue
2233 MACvSetRFLE_LatchBase(dwIoBase);
2234 //{{ RobertYu: 20050104
2235 } else if (byRFType == RF_AIROHA7230) {
2236 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2237 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2240 //{{ RobertYu:20050223, request by JerryChung
2241 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2242 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2243 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2244 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2245 // Select VC1/VC2, CR215 = 0x02->0x06
2246 bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
2249 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2250 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2252 pDevice->abyBBVGA[0] = 0x1C;
2253 pDevice->abyBBVGA[1] = 0x10;
2254 pDevice->abyBBVGA[2] = 0x0;
2255 pDevice->abyBBVGA[3] = 0x0;
2256 pDevice->ldBmThreshold[0] = -70;
2257 pDevice->ldBmThreshold[1] = -48;
2258 pDevice->ldBmThreshold[2] = 0;
2259 pDevice->ldBmThreshold[3] = 0;
2263 pDevice->bUpdateBBVGA = false;
2264 pDevice->abyBBVGA[0] = 0x1C;
2267 if (byLocalID > REV_ID_VT3253_A1) {
2268 BBbWriteEmbedded(dwIoBase, 0x04, 0x7F);
2269 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01);
2276 * Description: Read All Baseband Registers
2280 * dwIoBase - I/O base address
2281 * pbyBBRegs - Point to struct that stores Baseband Registers
2285 * Return Value: none
2288 void BBvReadAllRegs(unsigned long dwIoBase, unsigned char *pbyBBRegs)
2291 unsigned char byBase = 1;
2292 for (ii = 0; ii < BB_MAX_CONTEXT_SIZE; ii++) {
2293 BBbReadEmbedded(dwIoBase, (unsigned char)(ii*byBase), pbyBBRegs);
2294 pbyBBRegs += byBase;
2299 * Description: Turn on BaseBand Loopback mode
2303 * dwIoBase - I/O base address
2304 * bCCK - If CCK is set
2308 * Return Value: none
2312 void BBvLoopbackOn(PSDevice pDevice)
2314 unsigned char byData;
2315 unsigned long dwIoBase = pDevice->PortOffset;
2318 BBbReadEmbedded(dwIoBase, 0xC9, &pDevice->byBBCRc9);//CR201
2319 BBbWriteEmbedded(dwIoBase, 0xC9, 0);
2320 BBbReadEmbedded(dwIoBase, 0x4D, &pDevice->byBBCR4d);//CR77
2321 BBbWriteEmbedded(dwIoBase, 0x4D, 0x90);
2323 //CR 88 = 0x02(CCK), 0x03(OFDM)
2324 BBbReadEmbedded(dwIoBase, 0x88, &pDevice->byBBCR88);//CR136
2326 if (pDevice->uConnectionRate <= RATE_11M) { //CCK
2327 // Enable internal digital loopback: CR33 |= 0000 0001
2328 BBbReadEmbedded(dwIoBase, 0x21, &byData);//CR33
2329 BBbWriteEmbedded(dwIoBase, 0x21, (unsigned char)(byData | 0x01));//CR33
2331 BBbWriteEmbedded(dwIoBase, 0x9A, 0); //CR154
2333 BBbWriteEmbedded(dwIoBase, 0x88, 0x02);//CR239
2335 // Enable internal digital loopback:CR154 |= 0000 0001
2336 BBbReadEmbedded(dwIoBase, 0x9A, &byData);//CR154
2337 BBbWriteEmbedded(dwIoBase, 0x9A, (unsigned char)(byData | 0x01));//CR154
2339 BBbWriteEmbedded(dwIoBase, 0x21, 0); //CR33
2341 BBbWriteEmbedded(dwIoBase, 0x88, 0x03);//CR239
2345 BBbWriteEmbedded(dwIoBase, 0x0E, 0);//CR14
2348 BBbReadEmbedded(pDevice->PortOffset, 0x09, &pDevice->byBBCR09);
2349 BBbWriteEmbedded(pDevice->PortOffset, 0x09, (unsigned char)(pDevice->byBBCR09 & 0xDE));
2353 * Description: Turn off BaseBand Loopback mode
2357 * pDevice - Device Structure
2362 * Return Value: none
2365 void BBvLoopbackOff(PSDevice pDevice)
2367 unsigned char byData;
2368 unsigned long dwIoBase = pDevice->PortOffset;
2370 BBbWriteEmbedded(dwIoBase, 0xC9, pDevice->byBBCRc9);//CR201
2371 BBbWriteEmbedded(dwIoBase, 0x88, pDevice->byBBCR88);//CR136
2372 BBbWriteEmbedded(dwIoBase, 0x09, pDevice->byBBCR09);//CR136
2373 BBbWriteEmbedded(dwIoBase, 0x4D, pDevice->byBBCR4d);//CR77
2375 if (pDevice->uConnectionRate <= RATE_11M) { // CCK
2376 // Set the CR33 Bit2 to disable internal Loopback.
2377 BBbReadEmbedded(dwIoBase, 0x21, &byData);//CR33
2378 BBbWriteEmbedded(dwIoBase, 0x21, (unsigned char)(byData & 0xFE));//CR33
2380 BBbReadEmbedded(dwIoBase, 0x9A, &byData);//CR154
2381 BBbWriteEmbedded(dwIoBase, 0x9A, (unsigned char)(byData & 0xFE));//CR154
2383 BBbReadEmbedded(dwIoBase, 0x0E, &byData);//CR14
2384 BBbWriteEmbedded(dwIoBase, 0x0E, (unsigned char)(byData | 0x80));//CR14
2388 * Description: Set ShortSlotTime mode
2392 * pDevice - Device Structure
2396 * Return Value: none
2400 BBvSetShortSlotTime(PSDevice pDevice)
2402 unsigned char byBBRxConf = 0;
2403 unsigned char byBBVGA = 0;
2405 BBbReadEmbedded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2407 if (pDevice->bShortSlotTime)
2408 byBBRxConf &= 0xDF;//1101 1111
2410 byBBRxConf |= 0x20;//0010 0000
2412 // patch for 3253B0 Baseband with Cardbus module
2413 BBbReadEmbedded(pDevice->PortOffset, 0xE7, &byBBVGA);
2414 if (byBBVGA == pDevice->abyBBVGA[0])
2415 byBBRxConf |= 0x20;//0010 0000
2417 BBbWriteEmbedded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2420 void BBvSetVGAGainOffset(PSDevice pDevice, unsigned char byData)
2422 unsigned char byBBRxConf = 0;
2424 BBbWriteEmbedded(pDevice->PortOffset, 0xE7, byData);
2426 BBbReadEmbedded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2427 // patch for 3253B0 Baseband with Cardbus module
2428 if (byData == pDevice->abyBBVGA[0])
2429 byBBRxConf |= 0x20;//0010 0000
2430 else if (pDevice->bShortSlotTime)
2431 byBBRxConf &= 0xDF;//1101 1111
2433 byBBRxConf |= 0x20;//0010 0000
2434 pDevice->byBBVGACurrent = byData;
2435 BBbWriteEmbedded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2439 * Description: Baseband SoftwareReset
2443 * dwIoBase - I/O base address
2447 * Return Value: none
2451 BBvSoftwareReset(unsigned long dwIoBase)
2453 BBbWriteEmbedded(dwIoBase, 0x50, 0x40);
2454 BBbWriteEmbedded(dwIoBase, 0x50, 0);
2455 BBbWriteEmbedded(dwIoBase, 0x9C, 0x01);
2456 BBbWriteEmbedded(dwIoBase, 0x9C, 0);
2460 * Description: Baseband Power Save Mode ON
2464 * dwIoBase - I/O base address
2468 * Return Value: none
2472 BBvPowerSaveModeON(unsigned long dwIoBase)
2474 unsigned char byOrgData;
2476 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2478 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2482 * Description: Baseband Power Save Mode OFF
2486 * dwIoBase - I/O base address
2490 * Return Value: none
2494 BBvPowerSaveModeOFF(unsigned long dwIoBase)
2496 unsigned char byOrgData;
2498 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2499 byOrgData &= ~(BIT0);
2500 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2504 * Description: Set Tx Antenna mode
2508 * pDevice - Device Structure
2509 * byAntennaMode - Antenna Mode
2513 * Return Value: none
2518 BBvSetTxAntennaMode(unsigned long dwIoBase, unsigned char byAntennaMode)
2520 unsigned char byBBTxConf;
2522 BBbReadEmbedded(dwIoBase, 0x09, &byBBTxConf);//CR09
2523 if (byAntennaMode == ANT_DIVERSITY) {
2524 // bit 1 is diversity
2526 } else if (byAntennaMode == ANT_A) {
2528 byBBTxConf &= 0xF9; // 1111 1001
2529 } else if (byAntennaMode == ANT_B) {
2530 byBBTxConf &= 0xFD; // 1111 1101
2533 BBbWriteEmbedded(dwIoBase, 0x09, byBBTxConf);//CR09
2537 * Description: Set Rx Antenna mode
2541 * pDevice - Device Structure
2542 * byAntennaMode - Antenna Mode
2546 * Return Value: none
2551 BBvSetRxAntennaMode(unsigned long dwIoBase, unsigned char byAntennaMode)
2553 unsigned char byBBRxConf;
2555 BBbReadEmbedded(dwIoBase, 0x0A, &byBBRxConf);//CR10
2556 if (byAntennaMode == ANT_DIVERSITY) {
2559 } else if (byAntennaMode == ANT_A) {
2560 byBBRxConf &= 0xFC; // 1111 1100
2561 } else if (byAntennaMode == ANT_B) {
2562 byBBRxConf &= 0xFE; // 1111 1110
2565 BBbWriteEmbedded(dwIoBase, 0x0A, byBBRxConf);//CR10
2569 * Description: BBvSetDeepSleep
2573 * pDevice - Device Structure
2577 * Return Value: none
2581 BBvSetDeepSleep(unsigned long dwIoBase, unsigned char byLocalID)
2583 BBbWriteEmbedded(dwIoBase, 0x0C, 0x17);//CR12
2584 BBbWriteEmbedded(dwIoBase, 0x0D, 0xB9);//CR13
2588 BBvExitDeepSleep(unsigned long dwIoBase, unsigned char byLocalID)
2590 BBbWriteEmbedded(dwIoBase, 0x0C, 0x00);//CR12
2591 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01);//CR13
2596 s_ulGetRatio(PSDevice pDevice)
2598 unsigned long ulRatio = 0;
2599 unsigned long ulMaxPacket;
2600 unsigned long ulPacketNum;
2602 //This is a thousand-ratio
2603 ulMaxPacket = pDevice->uNumSQ3[RATE_54M];
2604 if (pDevice->uNumSQ3[RATE_54M] != 0) {
2605 ulPacketNum = pDevice->uNumSQ3[RATE_54M];
2606 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2607 ulRatio += TOP_RATE_54M;
2609 if (pDevice->uNumSQ3[RATE_48M] > ulMaxPacket) {
2610 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M];
2611 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2612 ulRatio += TOP_RATE_48M;
2613 ulMaxPacket = pDevice->uNumSQ3[RATE_48M];
2615 if (pDevice->uNumSQ3[RATE_36M] > ulMaxPacket) {
2616 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2617 pDevice->uNumSQ3[RATE_36M];
2618 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2619 ulRatio += TOP_RATE_36M;
2620 ulMaxPacket = pDevice->uNumSQ3[RATE_36M];
2622 if (pDevice->uNumSQ3[RATE_24M] > ulMaxPacket) {
2623 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2624 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M];
2625 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2626 ulRatio += TOP_RATE_24M;
2627 ulMaxPacket = pDevice->uNumSQ3[RATE_24M];
2629 if (pDevice->uNumSQ3[RATE_18M] > ulMaxPacket) {
2630 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2631 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2632 pDevice->uNumSQ3[RATE_18M];
2633 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2634 ulRatio += TOP_RATE_18M;
2635 ulMaxPacket = pDevice->uNumSQ3[RATE_18M];
2637 if (pDevice->uNumSQ3[RATE_12M] > ulMaxPacket) {
2638 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2639 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2640 pDevice->uNumSQ3[RATE_18M] + pDevice->uNumSQ3[RATE_12M];
2641 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2642 ulRatio += TOP_RATE_12M;
2643 ulMaxPacket = pDevice->uNumSQ3[RATE_12M];
2645 if (pDevice->uNumSQ3[RATE_11M] > ulMaxPacket) {
2646 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2647 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2648 pDevice->uNumSQ3[RATE_6M] - pDevice->uNumSQ3[RATE_9M];
2649 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2650 ulRatio += TOP_RATE_11M;
2651 ulMaxPacket = pDevice->uNumSQ3[RATE_11M];
2653 if (pDevice->uNumSQ3[RATE_9M] > ulMaxPacket) {
2654 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2655 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2656 pDevice->uNumSQ3[RATE_6M];
2657 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2658 ulRatio += TOP_RATE_9M;
2659 ulMaxPacket = pDevice->uNumSQ3[RATE_9M];
2661 if (pDevice->uNumSQ3[RATE_6M] > ulMaxPacket) {
2662 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2663 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M];
2664 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2665 ulRatio += TOP_RATE_6M;
2666 ulMaxPacket = pDevice->uNumSQ3[RATE_6M];
2668 if (pDevice->uNumSQ3[RATE_5M] > ulMaxPacket) {
2669 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2670 pDevice->uNumSQ3[RATE_2M];
2671 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2672 ulRatio += TOP_RATE_55M;
2673 ulMaxPacket = pDevice->uNumSQ3[RATE_5M];
2675 if (pDevice->uNumSQ3[RATE_2M] > ulMaxPacket) {
2676 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M];
2677 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2678 ulRatio += TOP_RATE_2M;
2679 ulMaxPacket = pDevice->uNumSQ3[RATE_2M];
2681 if (pDevice->uNumSQ3[RATE_1M] > ulMaxPacket) {
2682 ulPacketNum = pDevice->uDiversityCnt;
2683 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2684 ulRatio += TOP_RATE_1M;
2691 BBvClearAntDivSQ3Value(PSDevice pDevice)
2695 pDevice->uDiversityCnt = 0;
2696 for (ii = 0; ii < MAX_RATE; ii++)
2697 pDevice->uNumSQ3[ii] = 0;
2701 * Description: Antenna Diversity
2705 * pDevice - Device Structure
2706 * byRSR - RSR from received packet
2707 * bySQ3 - SQ3 value from received packet
2711 * Return Value: none
2716 BBvAntennaDiversity(PSDevice pDevice, unsigned char byRxRate, unsigned char bySQ3)
2718 if ((byRxRate >= MAX_RATE) || (pDevice->wAntDiversityMaxRate >= MAX_RATE))
2721 pDevice->uDiversityCnt++;
2723 pDevice->uNumSQ3[byRxRate]++;
2725 if (pDevice->byAntennaState == 0) {
2726 if (pDevice->uDiversityCnt > pDevice->ulDiversityNValue) {
2727 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "ulDiversityNValue=[%d],54M-[%d]\n",
2728 (int)pDevice->ulDiversityNValue, (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate]);
2730 if (pDevice->uNumSQ3[pDevice->wAntDiversityMaxRate] < pDevice->uDiversityCnt/2) {
2731 pDevice->ulRatio_State0 = s_ulGetRatio(pDevice);
2732 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "SQ3_State0, rate = [%08x]\n", (int)pDevice->ulRatio_State0);
2734 if (pDevice->byTMax == 0)
2736 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "1.[%08x], uNumSQ3[%d]=%d, %d\n",
2737 (int)pDevice->ulRatio_State0, (int)pDevice->wAntDiversityMaxRate,
2738 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2740 s_vChangeAntenna(pDevice);
2741 pDevice->byAntennaState = 1;
2742 del_timer(&pDevice->TimerSQ3Tmax3);
2743 del_timer(&pDevice->TimerSQ3Tmax2);
2744 pDevice->TimerSQ3Tmax1.expires = RUN_AT(pDevice->byTMax * HZ);
2745 add_timer(&pDevice->TimerSQ3Tmax1);
2748 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2749 add_timer(&pDevice->TimerSQ3Tmax3);
2751 BBvClearAntDivSQ3Value(pDevice);
2754 } else { //byAntennaState == 1
2756 if (pDevice->uDiversityCnt > pDevice->ulDiversityMValue) {
2757 del_timer(&pDevice->TimerSQ3Tmax1);
2759 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2760 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "RX:SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2761 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1);
2763 if (pDevice->ulRatio_State1 < pDevice->ulRatio_State0) {
2764 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2765 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2766 (int)pDevice->wAntDiversityMaxRate,
2767 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2769 s_vChangeAntenna(pDevice);
2770 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2771 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2772 add_timer(&pDevice->TimerSQ3Tmax3);
2773 add_timer(&pDevice->TimerSQ3Tmax2);
2775 pDevice->byAntennaState = 0;
2776 BBvClearAntDivSQ3Value(pDevice);
2784 * Timer for SQ3 antenna diversity
2791 * Return Value: none
2797 void *hDeviceContext
2800 PSDevice pDevice = (PSDevice)hDeviceContext;
2802 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "TimerSQ3CallBack...");
2803 spin_lock_irq(&pDevice->lock);
2805 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "3.[%08x][%08x], %d\n", (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1, (int)pDevice->uDiversityCnt);
2807 s_vChangeAntenna(pDevice);
2808 pDevice->byAntennaState = 0;
2809 BBvClearAntDivSQ3Value(pDevice);
2811 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2812 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2813 add_timer(&pDevice->TimerSQ3Tmax3);
2814 add_timer(&pDevice->TimerSQ3Tmax2);
2816 spin_unlock_irq(&pDevice->lock);
2823 * Timer for SQ3 antenna diversity
2828 * hDeviceContext - Pointer to the adapter
2834 * Return Value: none
2839 TimerState1CallBack(
2840 void *hDeviceContext
2843 PSDevice pDevice = (PSDevice)hDeviceContext;
2845 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "TimerState1CallBack...");
2847 spin_lock_irq(&pDevice->lock);
2848 if (pDevice->uDiversityCnt < pDevice->ulDiversityMValue/100) {
2849 s_vChangeAntenna(pDevice);
2850 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2851 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2852 add_timer(&pDevice->TimerSQ3Tmax3);
2853 add_timer(&pDevice->TimerSQ3Tmax2);
2855 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2856 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2857 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1);
2859 if (pDevice->ulRatio_State1 < pDevice->ulRatio_State0) {
2860 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2861 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2862 (int)pDevice->wAntDiversityMaxRate,
2863 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2865 s_vChangeAntenna(pDevice);
2867 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2868 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2869 add_timer(&pDevice->TimerSQ3Tmax3);
2870 add_timer(&pDevice->TimerSQ3Tmax2);
2873 pDevice->byAntennaState = 0;
2874 BBvClearAntDivSQ3Value(pDevice);
2875 spin_unlock_irq(&pDevice->lock);