drivers/staging/wilc1000/wilc_spi.c

   1 /* ////////////////////////////////////////////////////////////////////////// */
   2 /*  */
   3 /* Copyright (c) Atmel Corporation.  All rights reserved. */
   4 /*  */
   5 /* Module Name:  wilc_spi.c */
   6 /*  */
   7 /*  */
   8 /* //////////////////////////////////////////////////////////////////////////// */
   9 #include <linux/module.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/fs.h>
  13 #include <linux/slab.h>
  14 #include <linux/types.h>
  15 #include <linux/cdev.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/device.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/of_gpio.h>
  20
  21 #include <linux/string.h>
  22 #include "wilc_wlan_if.h"
  23 #include "wilc_wlan.h"
  24 #include "wilc_wfi_netdevice.h"
  25
  26 struct wilc_spi {
  27         int crc_off;
  28         int nint;
  29         int has_thrpt_enh;
  30 };
  31
  32 static struct wilc_spi g_spi;
  33
  34 static int wilc_spi_read(struct wilc *wilc, u32, u8 *, u32);
  35 static int wilc_spi_write(struct wilc *wilc, u32, u8 *, u32);
  36
  37 /********************************************
  38  *
  39  *      Crc7
  40  *
  41  ********************************************/
  42
  43 static const u8 crc7_syndrome_table[256] = {
  44         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  45         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  46         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  47         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  48         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  49         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  50         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  51         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  52         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  53         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  54         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  55         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  56         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  57         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  58         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  59         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  60         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  61         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  62         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  63         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  64         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  65         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  66         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  67         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  68         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  69         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  70         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  71         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  72         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  73         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  74         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  75         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  76 };
  77
  78 static u8 crc7_byte(u8 crc, u8 data)
  79 {
  80         return crc7_syndrome_table[(crc << 1) ^ data];
  81 }
  82
  83 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
  84 {
  85         while (len--)
  86                 crc = crc7_byte(crc, *buffer++);
  87         return crc;
  88 }
  89
  90 /********************************************
  91  *
  92  *      Spi protocol Function
  93  *
  94  ********************************************/
  95
  96 #define CMD_DMA_WRITE                           0xc1
  97 #define CMD_DMA_READ                            0xc2
  98 #define CMD_INTERNAL_WRITE              0xc3
  99 #define CMD_INTERNAL_READ               0xc4
 100 #define CMD_TERMINATE                           0xc5
 101 #define CMD_REPEAT                                      0xc6
 102 #define CMD_DMA_EXT_WRITE               0xc7
 103 #define CMD_DMA_EXT_READ                0xc8
 104 #define CMD_SINGLE_WRITE                        0xc9
 105 #define CMD_SINGLE_READ                 0xca
 106 #define CMD_RESET                                               0xcf
 107
 108 #define N_OK                                                            1
 109 #define N_FAIL                                                          0
 110 #define N_RESET                                                 -1
 111 #define N_RETRY                                                 -2
 112
 113 #define DATA_PKT_SZ_256                         256
 114 #define DATA_PKT_SZ_512                 512
 115 #define DATA_PKT_SZ_1K                          1024
 116 #define DATA_PKT_SZ_4K                          (4 * 1024)
 117 #define DATA_PKT_SZ_8K                          (8 * 1024)
 118 #define DATA_PKT_SZ                                     DATA_PKT_SZ_8K
 119
 120 #define USE_SPI_DMA     0
 121
 122 static int wilc_bus_probe(struct spi_device *spi)
 123 {
 124         int ret, gpio;
 125         struct wilc *wilc;
 126
 127         gpio = of_get_gpio(spi->dev.of_node, 0);
 128         if (gpio < 0)
 129                 gpio = GPIO_NUM;
 130
 131         ret = wilc_netdev_init(&wilc, NULL, HIF_SPI, GPIO_NUM, &wilc_hif_spi);
 132         if (ret)
 133                 return ret;
 134
 135         spi_set_drvdata(spi, wilc);
 136         wilc->dev = &spi->dev;
 137
 138         return 0;
 139 }
 140
 141 static int wilc_bus_remove(struct spi_device *spi)
 142 {
 143         wilc_netdev_cleanup(spi_get_drvdata(spi));
 144         return 0;
 145 }
 146
 147 static const struct of_device_id wilc1000_of_match[] = {
 148         { .compatible = "atmel,wilc_spi", },
 149         {}
 150 };
 151 MODULE_DEVICE_TABLE(of, wilc1000_of_match);
 152
 153 static struct spi_driver wilc1000_spi_driver = {
 154         .driver = {
 155                 .name = MODALIAS,
 156                 .of_match_table = wilc1000_of_match,
 157         },
 158         .probe =  wilc_bus_probe,
 159         .remove = wilc_bus_remove,
 160 };
 161 module_spi_driver(wilc1000_spi_driver);
 162 MODULE_LICENSE("GPL");
 163
 164 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
 165 {
 166         struct spi_device *spi = to_spi_device(wilc->dev);
 167         int ret;
 168         struct spi_message msg;
 169
 170         if (len > 0 && b) {
 171                 struct spi_transfer tr = {
 172                         .tx_buf = b,
 173                         .len = len,
 174                         .delay_usecs = 0,
 175                 };
 176                 char *r_buffer = kzalloc(len, GFP_KERNEL);
 177
 178                 if (!r_buffer)
 179                         return -ENOMEM;
 180
 181                 tr.rx_buf = r_buffer;
 182                 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
 183
 184                 memset(&msg, 0, sizeof(msg));
 185                 spi_message_init(&msg);
 186                 msg.spi = spi;
 187                 msg.is_dma_mapped = USE_SPI_DMA;
 188                 spi_message_add_tail(&tr, &msg);
 189
 190                 ret = spi_sync(spi, &msg);
 191                 if (ret < 0)
 192                         dev_err(&spi->dev, "SPI transaction failed\n");
 193
 194                 kfree(r_buffer);
 195         } else {
 196                 dev_err(&spi->dev,
 197                         "can't write data with the following length: %d\n",
 198                         len);
 199                 ret = -EINVAL;
 200         }
 201
 202         return ret;
 203 }
 204
 205 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
 206 {
 207         struct spi_device *spi = to_spi_device(wilc->dev);
 208         int ret;
 209
 210         if (rlen > 0) {
 211                 struct spi_message msg;
 212                 struct spi_transfer tr = {
 213                         .rx_buf = rb,
 214                         .len = rlen,
 215                         .delay_usecs = 0,
 216
 217                 };
 218                 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
 219
 220                 if (!t_buffer)
 221                         return -ENOMEM;
 222
 223                 tr.tx_buf = t_buffer;
 224
 225                 memset(&msg, 0, sizeof(msg));
 226                 spi_message_init(&msg);
 227                 msg.spi = spi;
 228                 msg.is_dma_mapped = USE_SPI_DMA;
 229                 spi_message_add_tail(&tr, &msg);
 230
 231                 ret = spi_sync(spi, &msg);
 232                 if (ret < 0)
 233                         dev_err(&spi->dev, "SPI transaction failed\n");
 234                 kfree(t_buffer);
 235         } else {
 236                 dev_err(&spi->dev,
 237                         "can't read data with the following length: %u\n",
 238                         rlen);
 239                 ret = -EINVAL;
 240         }
 241
 242         return ret;
 243 }
 244
 245 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
 246 {
 247         struct spi_device *spi = to_spi_device(wilc->dev);
 248         int ret;
 249
 250         if (rlen > 0) {
 251                 struct spi_message msg;
 252                 struct spi_transfer tr = {
 253                         .rx_buf = rb,
 254                         .tx_buf = wb,
 255                         .len = rlen,
 256                         .bits_per_word = 8,
 257                         .delay_usecs = 0,
 258
 259                 };
 260
 261                 memset(&msg, 0, sizeof(msg));
 262                 spi_message_init(&msg);
 263                 msg.spi = spi;
 264                 msg.is_dma_mapped = USE_SPI_DMA;
 265
 266                 spi_message_add_tail(&tr, &msg);
 267                 ret = spi_sync(spi, &msg);
 268                 if (ret < 0)
 269                         dev_err(&spi->dev, "SPI transaction failed\n");
 270         } else {
 271                 dev_err(&spi->dev,
 272                         "can't read data with the following length: %u\n",
 273                         rlen);
 274                 ret = -EINVAL;
 275         }
 276
 277         return ret;
 278 }
 279
 280 static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
 281                             u8 clockless)
 282 {
 283         struct spi_device *spi = to_spi_device(wilc->dev);
 284         u8 wb[32], rb[32];
 285         u8 wix, rix;
 286         u32 len2;
 287         u8 rsp;
 288         int len = 0;
 289         int result = N_OK;
 290
 291         wb[0] = cmd;
 292         switch (cmd) {
 293         case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
 294                 wb[1] = (u8)(adr >> 16);
 295                 wb[2] = (u8)(adr >> 8);
 296                 wb[3] = (u8)adr;
 297                 len = 5;
 298                 break;
 299
 300         case CMD_INTERNAL_READ:                 /* internal register read */
 301                 wb[1] = (u8)(adr >> 8);
 302                 if (clockless == 1)
 303                         wb[1] |= BIT(7);
 304                 wb[2] = (u8)adr;
 305                 wb[3] = 0x00;
 306                 len = 5;
 307                 break;
 308
 309         case CMD_TERMINATE:                                     /* termination */
 310                 wb[1] = 0x00;
 311                 wb[2] = 0x00;
 312                 wb[3] = 0x00;
 313                 len = 5;
 314                 break;
 315
 316         case CMD_REPEAT:                                                /* repeat */
 317                 wb[1] = 0x00;
 318                 wb[2] = 0x00;
 319                 wb[3] = 0x00;
 320                 len = 5;
 321                 break;
 322
 323         case CMD_RESET:                                                 /* reset */
 324                 wb[1] = 0xff;
 325                 wb[2] = 0xff;
 326                 wb[3] = 0xff;
 327                 len = 5;
 328                 break;
 329
 330         case CMD_DMA_WRITE:                                     /* dma write */
 331         case CMD_DMA_READ:                                      /* dma read */
 332                 wb[1] = (u8)(adr >> 16);
 333                 wb[2] = (u8)(adr >> 8);
 334                 wb[3] = (u8)adr;
 335                 wb[4] = (u8)(sz >> 8);
 336                 wb[5] = (u8)(sz);
 337                 len = 7;
 338                 break;
 339
 340         case CMD_DMA_EXT_WRITE:         /* dma extended write */
 341         case CMD_DMA_EXT_READ:                  /* dma extended read */
 342                 wb[1] = (u8)(adr >> 16);
 343                 wb[2] = (u8)(adr >> 8);
 344                 wb[3] = (u8)adr;
 345                 wb[4] = (u8)(sz >> 16);
 346                 wb[5] = (u8)(sz >> 8);
 347                 wb[6] = (u8)(sz);
 348                 len = 8;
 349                 break;
 350
 351         case CMD_INTERNAL_WRITE:                /* internal register write */
 352                 wb[1] = (u8)(adr >> 8);
 353                 if (clockless == 1)
 354                         wb[1] |= BIT(7);
 355                 wb[2] = (u8)(adr);
 356                 wb[3] = b[3];
 357                 wb[4] = b[2];
 358                 wb[5] = b[1];
 359                 wb[6] = b[0];
 360                 len = 8;
 361                 break;
 362
 363         case CMD_SINGLE_WRITE:                  /* single word write */
 364                 wb[1] = (u8)(adr >> 16);
 365                 wb[2] = (u8)(adr >> 8);
 366                 wb[3] = (u8)(adr);
 367                 wb[4] = b[3];
 368                 wb[5] = b[2];
 369                 wb[6] = b[1];
 370                 wb[7] = b[0];
 371                 len = 9;
 372                 break;
 373
 374         default:
 375                 result = N_FAIL;
 376                 break;
 377         }
 378
 379         if (result != N_OK)
 380                 return result;
 381
 382         if (!g_spi.crc_off)
 383                 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
 384         else
 385                 len -= 1;
 386
 387 #define NUM_SKIP_BYTES (1)
 388 #define NUM_RSP_BYTES (2)
 389 #define NUM_DATA_HDR_BYTES (1)
 390 #define NUM_DATA_BYTES (4)
 391 #define NUM_CRC_BYTES (2)
 392 #define NUM_DUMMY_BYTES (3)
 393         if ((cmd == CMD_RESET) ||
 394             (cmd == CMD_TERMINATE) ||
 395             (cmd == CMD_REPEAT)) {
 396                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 397         } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 398                 if (!g_spi.crc_off) {
 399                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 400                                       + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
 401                 } else {
 402                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 403                                       + NUM_DUMMY_BYTES);
 404                 }
 405         } else {
 406                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 407         }
 408 #undef NUM_DUMMY_BYTES
 409
 410         if (len2 > ARRAY_SIZE(wb)) {
 411                 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
 412                          len2, ARRAY_SIZE(wb));
 413                 return N_FAIL;
 414         }
 415         /* zero spi write buffers. */
 416         for (wix = len; wix < len2; wix++)
 417                 wb[wix] = 0;
 418         rix = len;
 419
 420         if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
 421                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 422                 return N_FAIL;
 423         }
 424
 425         /**
 426          * Command/Control response
 427          **/
 428         if ((cmd == CMD_RESET) ||
 429             (cmd == CMD_TERMINATE) ||
 430             (cmd == CMD_REPEAT)) {
 431                 rix++;         /* skip 1 byte */
 432         }
 433
 434         /* do { */
 435         rsp = rb[rix++];
 436         /*      if(rsp == cmd) break; */
 437         /* } while(&rptr[1] <= &rb[len2]); */
 438
 439         if (rsp != cmd) {
 440                 dev_err(&spi->dev,
 441                         "Failed cmd response, cmd (%02x), resp (%02x)\n",
 442                         cmd, rsp);
 443                 return N_FAIL;
 444         }
 445
 446         /**
 447          * State response
 448          **/
 449         rsp = rb[rix++];
 450         if (rsp != 0x00) {
 451                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 452                         rsp);
 453                 return N_FAIL;
 454         }
 455
 456         if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
 457             || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 458                 int retry;
 459                 /* u16 crc1, crc2; */
 460                 u8 crc[2];
 461                 /**
 462                  * Data Respnose header
 463                  **/
 464                 retry = 100;
 465                 do {
 466                         /* ensure there is room in buffer later to read data and crc */
 467                         if (rix < len2) {
 468                                 rsp = rb[rix++];
 469                         } else {
 470                                 retry = 0;
 471                                 break;
 472                         }
 473                         if (((rsp >> 4) & 0xf) == 0xf)
 474                                 break;
 475                 } while (retry--);
 476
 477                 if (retry <= 0) {
 478                         dev_err(&spi->dev,
 479                                 "Error, data read response (%02x)\n", rsp);
 480                         return N_RESET;
 481                 }
 482
 483                 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 484                         /**
 485                          * Read bytes
 486                          **/
 487                         if ((rix + 3) < len2) {
 488                                 b[0] = rb[rix++];
 489                                 b[1] = rb[rix++];
 490                                 b[2] = rb[rix++];
 491                                 b[3] = rb[rix++];
 492                         } else {
 493                                 dev_err(&spi->dev,
 494                                         "buffer overrun when reading data.\n");
 495                                 return N_FAIL;
 496                         }
 497
 498                         if (!g_spi.crc_off) {
 499                                 /**
 500                                  * Read Crc
 501                                  **/
 502                                 if ((rix + 1) < len2) {
 503                                         crc[0] = rb[rix++];
 504                                         crc[1] = rb[rix++];
 505                                 } else {
 506                                         dev_err(&spi->dev, "buffer overrun when reading crc.\n");
 507                                         return N_FAIL;
 508                                 }
 509                         }
 510                 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 511                         int ix;
 512
 513                         /* some data may be read in response to dummy bytes. */
 514                         for (ix = 0; (rix < len2) && (ix < sz); )
 515                                 b[ix++] = rb[rix++];
 516
 517                         sz -= ix;
 518
 519                         if (sz > 0) {
 520                                 int nbytes;
 521
 522                                 if (sz <= (DATA_PKT_SZ - ix))
 523                                         nbytes = sz;
 524                                 else
 525                                         nbytes = DATA_PKT_SZ - ix;
 526
 527                                 /**
 528                                  * Read bytes
 529                                  **/
 530                                 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 531                                         dev_err(&spi->dev, "Failed data block read, bus error...\n");
 532                                         result = N_FAIL;
 533                                         goto _error_;
 534                                 }
 535
 536                                 /**
 537                                  * Read Crc
 538                                  **/
 539                                 if (!g_spi.crc_off) {
 540                                         if (wilc_spi_rx(wilc, crc, 2)) {
 541                                                 dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
 542                                                 result = N_FAIL;
 543                                                 goto _error_;
 544                                         }
 545                                 }
 546
 547
 548                                 ix += nbytes;
 549                                 sz -= nbytes;
 550                         }
 551
 552                         /*  if any data in left unread, then read the rest using normal DMA code.*/
 553                         while (sz > 0) {
 554                                 int nbytes;
 555
 556                                 if (sz <= DATA_PKT_SZ)
 557                                         nbytes = sz;
 558                                 else
 559                                         nbytes = DATA_PKT_SZ;
 560
 561                                 /**
 562                                  * read data response only on the next DMA cycles not
 563                                  * the first DMA since data response header is already
 564                                  * handled above for the first DMA.
 565                                  **/
 566                                 /**
 567                                  * Data Respnose header
 568                                  **/
 569                                 retry = 10;
 570                                 do {
 571                                         if (wilc_spi_rx(wilc, &rsp, 1)) {
 572                                                 dev_err(&spi->dev, "Failed data response read, bus error...\n");
 573                                                 result = N_FAIL;
 574                                                 break;
 575                                         }
 576                                         if (((rsp >> 4) & 0xf) == 0xf)
 577                                                 break;
 578                                 } while (retry--);
 579
 580                                 if (result == N_FAIL)
 581                                         break;
 582
 583
 584                                 /**
 585                                  * Read bytes
 586                                  **/
 587                                 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 588                                         dev_err(&spi->dev, "Failed data block read, bus error...\n");
 589                                         result = N_FAIL;
 590                                         break;
 591                                 }
 592
 593                                 /**
 594                                  * Read Crc
 595                                  **/
 596                                 if (!g_spi.crc_off) {
 597                                         if (wilc_spi_rx(wilc, crc, 2)) {
 598                                                 dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
 599                                                 result = N_FAIL;
 600                                                 break;
 601                                         }
 602                                 }
 603
 604                                 ix += nbytes;
 605                                 sz -= nbytes;
 606                         }
 607                 }
 608         }
 609 _error_:
 610         return result;
 611 }
 612
 613 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
 614 {
 615         struct spi_device *spi = to_spi_device(wilc->dev);
 616         int ix, nbytes;
 617         int result = 1;
 618         u8 cmd, order, crc[2] = {0};
 619         /* u8 rsp; */
 620
 621         /**
 622          *      Data
 623          **/
 624         ix = 0;
 625         do {
 626                 if (sz <= DATA_PKT_SZ)
 627                         nbytes = sz;
 628                 else
 629                         nbytes = DATA_PKT_SZ;
 630
 631                 /**
 632                  *      Write command
 633                  **/
 634                 cmd = 0xf0;
 635                 if (ix == 0) {
 636                         if (sz <= DATA_PKT_SZ)
 637
 638                                 order = 0x3;
 639                         else
 640                                 order = 0x1;
 641                 } else {
 642                         if (sz <= DATA_PKT_SZ)
 643                                 order = 0x3;
 644                         else
 645                                 order = 0x2;
 646                 }
 647                 cmd |= order;
 648                 if (wilc_spi_tx(wilc, &cmd, 1)) {
 649                         dev_err(&spi->dev,
 650                                 "Failed data block cmd write, bus error...\n");
 651                         result = N_FAIL;
 652                         break;
 653                 }
 654
 655                 /**
 656                  *      Write data
 657                  **/
 658                 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
 659                         dev_err(&spi->dev,
 660                                 "Failed data block write, bus error...\n");
 661                         result = N_FAIL;
 662                         break;
 663                 }
 664
 665                 /**
 666                  *      Write Crc
 667                  **/
 668                 if (!g_spi.crc_off) {
 669                         if (wilc_spi_tx(wilc, crc, 2)) {
 670                                 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
 671                                 result = N_FAIL;
 672                                 break;
 673                         }
 674                 }
 675
 676                 /**
 677                  *      No need to wait for response
 678                  **/
 679                 ix += nbytes;
 680                 sz -= nbytes;
 681         } while (sz);
 682
 683
 684         return result;
 685 }
 686
 687 /********************************************
 688  *
 689  *      Spi Internal Read/Write Function
 690  *
 691  ********************************************/
 692
 693 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
 694 {
 695         struct spi_device *spi = to_spi_device(wilc->dev);
 696         int result;
 697
 698         dat = cpu_to_le32(dat);
 699         result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
 700                                   0);
 701         if (result != N_OK)
 702                 dev_err(&spi->dev, "Failed internal write cmd...\n");
 703
 704         return result;
 705 }
 706
 707 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
 708 {
 709         struct spi_device *spi = to_spi_device(wilc->dev);
 710         int result;
 711
 712         result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
 713                                   0);
 714         if (result != N_OK) {
 715                 dev_err(&spi->dev, "Failed internal read cmd...\n");
 716                 return 0;
 717         }
 718
 719         *data = cpu_to_le32(*data);
 720
 721         return 1;
 722 }
 723
 724 /********************************************
 725  *
 726  *      Spi interfaces
 727  *
 728  ********************************************/
 729
 730 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
 731 {
 732         struct spi_device *spi = to_spi_device(wilc->dev);
 733         int result = N_OK;
 734         u8 cmd = CMD_SINGLE_WRITE;
 735         u8 clockless = 0;
 736
 737         data = cpu_to_le32(data);
 738         if (addr < 0x30) {
 739                 /* Clockless register*/
 740                 cmd = CMD_INTERNAL_WRITE;
 741                 clockless = 1;
 742         }
 743
 744         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
 745         if (result != N_OK)
 746                 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
 747
 748         return result;
 749 }
 750
 751 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 752 {
 753         struct spi_device *spi = to_spi_device(wilc->dev);
 754         int result;
 755         u8 cmd = CMD_DMA_EXT_WRITE;
 756
 757         /**
 758          *      has to be greated than 4
 759          **/
 760         if (size <= 4)
 761                 return 0;
 762
 763         result = spi_cmd_complete(wilc, cmd, addr, NULL, size, 0);
 764         if (result != N_OK) {
 765                 dev_err(&spi->dev,
 766                         "Failed cmd, write block (%08x)...\n", addr);
 767                 return 0;
 768         }
 769
 770         /**
 771          *      Data
 772          **/
 773         result = spi_data_write(wilc, buf, size);
 774         if (result != N_OK)
 775                 dev_err(&spi->dev, "Failed block data write...\n");
 776
 777         return 1;
 778 }
 779
 780 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
 781 {
 782         struct spi_device *spi = to_spi_device(wilc->dev);
 783         int result = N_OK;
 784         u8 cmd = CMD_SINGLE_READ;
 785         u8 clockless = 0;
 786
 787         if (addr < 0x30) {
 788                 /* dev_err(&spi->dev, "***** read addr %d\n\n", addr); */
 789                 /* Clockless register*/
 790                 cmd = CMD_INTERNAL_READ;
 791                 clockless = 1;
 792         }
 793
 794         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
 795         if (result != N_OK) {
 796                 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
 797                 return 0;
 798         }
 799
 800         *data = cpu_to_le32(*data);
 801
 802         return 1;
 803 }
 804
 805 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 806 {
 807         struct spi_device *spi = to_spi_device(wilc->dev);
 808         u8 cmd = CMD_DMA_EXT_READ;
 809         int result;
 810
 811         if (size <= 4)
 812                 return 0;
 813
 814         result = spi_cmd_complete(wilc, cmd, addr, buf, size, 0);
 815         if (result != N_OK) {
 816                 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
 817                 return 0;
 818         }
 819
 820         return 1;
 821 }
 822
 823 /********************************************
 824  *
 825  *      Bus interfaces
 826  *
 827  ********************************************/
 828
 829 static int _wilc_spi_deinit(struct wilc *wilc)
 830 {
 831         /**
 832          *      TODO:
 833          **/
 834         return 1;
 835 }
 836
 837 static int wilc_spi_init(struct wilc *wilc, bool resume)
 838 {
 839         struct spi_device *spi = to_spi_device(wilc->dev);
 840         u32 reg;
 841         u32 chipid;
 842
 843         static int isinit;
 844
 845         if (isinit) {
 846
 847                 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 848                         dev_err(&spi->dev, "Fail cmd read chip id...\n");
 849                         return 0;
 850                 }
 851                 return 1;
 852         }
 853
 854         memset(&g_spi, 0, sizeof(struct wilc_spi));
 855
 856         /**
 857          *      configure protocol
 858          **/
 859         g_spi.crc_off = 0;
 860
 861         /* TODO: We can remove the CRC trials if there is a definite way to reset */
 862         /* the SPI to it's initial value. */
 863         if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 864                 /* Read failed. Try with CRC off. This might happen when module
 865                  * is removed but chip isn't reset*/
 866                 g_spi.crc_off = 1;
 867                 dev_err(&spi->dev, "Failed internal read protocol with CRC on, retrying with CRC off...\n");
 868                 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 869                         /* Reaad failed with both CRC on and off, something went bad */
 870                         dev_err(&spi->dev,
 871                                 "Failed internal read protocol...\n");
 872                         return 0;
 873                 }
 874         }
 875         if (g_spi.crc_off == 0) {
 876                 reg &= ~0xc;    /* disable crc checking */
 877                 reg &= ~0x70;
 878                 reg |= (0x5 << 4);
 879                 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
 880                         dev_err(&spi->dev, "[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
 881                         return 0;
 882                 }
 883                 g_spi.crc_off = 1;
 884         }
 885
 886
 887         /**
 888          *      make sure can read back chip id correctly
 889          **/
 890         if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 891                 dev_err(&spi->dev, "Fail cmd read chip id...\n");
 892                 return 0;
 893         }
 894         /* dev_err(&spi->dev, "chipid (%08x)\n", chipid); */
 895
 896         g_spi.has_thrpt_enh = 1;
 897
 898         isinit = 1;
 899
 900         return 1;
 901 }
 902
 903 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
 904 {
 905         struct spi_device *spi = to_spi_device(wilc->dev);
 906         int ret;
 907
 908         if (g_spi.has_thrpt_enh) {
 909                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 910                                         size);
 911                 *size = *size  & IRQ_DMA_WD_CNT_MASK;
 912         } else {
 913                 u32 tmp;
 914                 u32 byte_cnt;
 915
 916                 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
 917                                         &byte_cnt);
 918                 if (!ret) {
 919                         dev_err(&spi->dev,
 920                                 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 921                         goto _fail_;
 922                 }
 923                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 924                 *size = tmp;
 925         }
 926
 927
 928
 929 _fail_:
 930         return ret;
 931 }
 932
 933
 934
 935 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
 936 {
 937         struct spi_device *spi = to_spi_device(wilc->dev);
 938         int ret;
 939
 940         if (g_spi.has_thrpt_enh) {
 941                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 942                                         int_status);
 943         } else {
 944                 u32 tmp;
 945                 u32 byte_cnt;
 946
 947                 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
 948                                         &byte_cnt);
 949                 if (!ret) {
 950                         dev_err(&spi->dev,
 951                                 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 952                         goto _fail_;
 953                 }
 954                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 955
 956                 {
 957                         int happended, j;
 958
 959                         j = 0;
 960                         do {
 961                                 u32 irq_flags;
 962
 963                                 happended = 0;
 964
 965                                 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
 966                                 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
 967
 968                                 if (g_spi.nint > 5) {
 969                                         wilc_spi_read_reg(wilc, 0x1a94,
 970                                                           &irq_flags);
 971                                         tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
 972                                 }
 973
 974                                 {
 975                                         u32 unkmown_mask;
 976
 977                                         unkmown_mask = ~((1ul << g_spi.nint) - 1);
 978
 979                                         if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
 980                                                 dev_err(&spi->dev, "Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
 981                                                 happended = 1;
 982                                         }
 983                                 }
 984                                 j++;
 985                         } while (happended);
 986                 }
 987
 988                 *int_status = tmp;
 989
 990         }
 991
 992 _fail_:
 993         return ret;
 994 }
 995
 996 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
 997 {
 998         struct spi_device *spi = to_spi_device(wilc->dev);
 999         int ret;
1000
1001         if (g_spi.has_thrpt_enh) {
1002                 ret = spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
1003                                          val);
1004         } else {
1005                 u32 flags;
1006
1007                 flags = val & (BIT(MAX_NUM_INT) - 1);
1008                 if (flags) {
1009                         int i;
1010
1011                         ret = 1;
1012                         for (i = 0; i < g_spi.nint; i++) {
1013                                 /* No matter what you write 1 or 0, it will clear interrupt. */
1014                                 if (flags & 1)
1015                                         ret = wilc_spi_write_reg(wilc, 0x10c8 + i * 4, 1);
1016                                 if (!ret)
1017                                         break;
1018                                 flags >>= 1;
1019                         }
1020                         if (!ret) {
1021                                 dev_err(&spi->dev,
1022                                         "Failed wilc_spi_write_reg, set reg %x ...\n",
1023                                         0x10c8 + i * 4);
1024                                 goto _fail_;
1025                         }
1026                         for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1027                                 if (flags & 1)
1028                                         dev_err(&spi->dev,
1029                                                 "Unexpected interrupt cleared %d...\n",
1030                                                 i);
1031                                 flags >>= 1;
1032                         }
1033                 }
1034
1035                 {
1036                         u32 tbl_ctl;
1037
1038                         tbl_ctl = 0;
1039                         /* select VMM table 0 */
1040                         if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1041                                 tbl_ctl |= BIT(0);
1042                         /* select VMM table 1 */
1043                         if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1044                                 tbl_ctl |= BIT(1);
1045
1046                         ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL,
1047                                                  tbl_ctl);
1048                         if (!ret) {
1049                                 dev_err(&spi->dev,
1050                                         "fail write reg vmm_tbl_ctl...\n");
1051                                 goto _fail_;
1052                         }
1053
1054                         if ((val & EN_VMM) == EN_VMM) {
1055                                 /**
1056                                  *      enable vmm transfer.
1057                                  **/
1058                                 ret = wilc_spi_write_reg(wilc,
1059                                                          WILC_VMM_CORE_CTL, 1);
1060                                 if (!ret) {
1061                                         dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1062                                         goto _fail_;
1063                                 }
1064                         }
1065                 }
1066         }
1067 _fail_:
1068         return ret;
1069 }
1070
1071 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1072 {
1073         struct spi_device *spi = to_spi_device(wilc->dev);
1074         u32 reg;
1075         int ret, i;
1076
1077         if (nint > MAX_NUM_INT) {
1078                 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1079                 return 0;
1080         }
1081
1082         g_spi.nint = nint;
1083
1084         /**
1085          *      interrupt pin mux select
1086          **/
1087         ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1088         if (!ret) {
1089                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1090                         WILC_PIN_MUX_0);
1091                 return 0;
1092         }
1093         reg |= BIT(8);
1094         ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1095         if (!ret) {
1096                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1097                         WILC_PIN_MUX_0);
1098                 return 0;
1099         }
1100
1101         /**
1102          *      interrupt enable
1103          **/
1104         ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1105         if (!ret) {
1106                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1107                         WILC_INTR_ENABLE);
1108                 return 0;
1109         }
1110
1111         for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1112                 reg |= (BIT((27 + i)));
1113
1114         ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1115         if (!ret) {
1116                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1117                         WILC_INTR_ENABLE);
1118                 return 0;
1119         }
1120         if (nint) {
1121                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1122                 if (!ret) {
1123                         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1124                                 WILC_INTR2_ENABLE);
1125                         return 0;
1126                 }
1127
1128                 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1129                         reg |= BIT(i);
1130
1131                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1132                 if (!ret) {
1133                         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1134                                 WILC_INTR2_ENABLE);
1135                         return 0;
1136                 }
1137         }
1138
1139         return 1;
1140 }
1141 /********************************************
1142  *
1143  *      Global spi HIF function table
1144  *
1145  ********************************************/
1146 const struct wilc_hif_func wilc_hif_spi = {
1147         .hif_init = wilc_spi_init,
1148         .hif_deinit = _wilc_spi_deinit,
1149         .hif_read_reg = wilc_spi_read_reg,
1150         .hif_write_reg = wilc_spi_write_reg,
1151         .hif_block_rx = wilc_spi_read,
1152         .hif_block_tx = wilc_spi_write,
1153         .hif_read_int = wilc_spi_read_int,
1154         .hif_clear_int_ext = wilc_spi_clear_int_ext,
1155         .hif_read_size = wilc_spi_read_size,
1156         .hif_block_tx_ext = wilc_spi_write,
1157         .hif_block_rx_ext = wilc_spi_read,
1158         .hif_sync_ext = wilc_spi_sync_ext,
1159 };