2 * linux/drivers/misc/xillybus.h
4 * Copyright 2011 Xillybus Ltd, http://xillybus.com
6 * Header file for the Xillybus FPGA/host framework.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the smems of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
16 #include <linux/list.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/interrupt.h>
20 #include <linux/sched.h>
21 #include <linux/cdev.h>
22 #include <linux/spinlock.h>
23 #include <linux/mutex.h>
24 #include <linux/workqueue.h>
26 struct xilly_endpoint_hardware;
29 struct list_head node;
35 struct list_head node;
46 int end_offset; /* Counting elements, not bytes */
49 struct xilly_cleanup {
50 struct list_head to_kfree;
51 struct list_head to_pagefree;
52 struct list_head to_unmap;
55 struct xilly_idt_handle {
56 unsigned char *chandesc;
62 * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
63 * wr_* buffers are those consumed by read(), since the FPGA writes to them
67 struct xilly_channel {
68 struct xilly_endpoint *endpoint;
70 int log2_element_size;
73 struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
75 unsigned int wr_buf_size; /* In bytes */
80 int wr_ready; /* Significant only when wr_empty == 1 */
84 spinlock_t wr_spinlock;
85 struct mutex wr_mutex;
86 wait_queue_head_t wr_wait;
87 wait_queue_head_t wr_ready_wait;
91 int wr_exclusive_open;
92 int wr_supports_nonempty;
94 struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
96 unsigned int rd_buf_size; /* In bytes */
101 spinlock_t rd_spinlock;
102 struct mutex rd_mutex;
103 wait_queue_head_t rd_wait;
105 int rd_allow_partial;
107 int rd_exclusive_open;
108 struct delayed_work rd_workitem;
109 unsigned char rd_leftovers[4];
112 struct xilly_endpoint {
114 * One of pdev and dev is always NULL, and the other is a valid
115 * pointer, depending on the type of device
117 struct pci_dev *pdev;
119 struct resource res; /* OF devices only */
120 struct xilly_endpoint_hardware *ephw;
122 struct list_head ep_list;
123 int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
124 __iomem u32 *registers;
127 struct mutex register_mutex;
128 wait_queue_head_t ep_wait;
130 /* List of memory allocations, to make release easy */
131 struct xilly_cleanup cleanup;
133 /* Channels and message handling */
137 int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */
139 int num_channels; /* EXCLUDING message buffer */
140 struct xilly_channel **channels;
146 dma_addr_t msgbuf_dma_addr;
147 unsigned int msg_buf_size;
150 struct xilly_endpoint_hardware {
151 struct module *owner;
152 void (*hw_sync_sgl_for_cpu)(struct xilly_endpoint *,
156 void (*hw_sync_sgl_for_device)(struct xilly_endpoint *,
160 dma_addr_t (*map_single)(struct xilly_cleanup *,
161 struct xilly_endpoint *,
165 void (*unmap_single)(struct xilly_dma *entry);
168 irqreturn_t xillybus_isr(int irq, void *data);
170 void xillybus_do_cleanup(struct xilly_cleanup *mem,
171 struct xilly_endpoint *endpoint);
173 struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev,
175 struct xilly_endpoint_hardware
178 int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);
180 void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);
182 #endif /* __XILLYBUS_H */