2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/serial_8250.h>
15 #include <linux/serial_reg.h>
16 #include <linux/dmaengine.h>
18 struct uart_8250_dma {
19 int (*tx_dma)(struct uart_8250_port *p);
20 int (*rx_dma)(struct uart_8250_port *p);
24 /* Parameter to the filter function */
28 struct dma_slave_config rxconf;
29 struct dma_slave_config txconf;
31 struct dma_chan *rxchan;
32 struct dma_chan *txchan;
37 dma_cookie_t rx_cookie;
38 dma_cookie_t tx_cookie;
45 unsigned char tx_running;
47 unsigned char rx_running;
50 struct old_serial_port {
52 unsigned int baud_base;
57 unsigned char io_type;
58 unsigned char __iomem *iomem_base;
59 unsigned short iomem_reg_shift;
60 unsigned long irqflags;
63 struct serial8250_config {
65 unsigned short fifo_size;
66 unsigned short tx_loadsz;
68 unsigned char rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE];
72 #define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
73 #define UART_CAP_EFR (1 << 9) /* UART has EFR */
74 #define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
75 #define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
76 #define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
77 #define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
78 #define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */
79 #define UART_CAP_RPM (1 << 15) /* Runtime PM is active while idle */
81 #define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
82 #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
83 #define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
84 #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
85 #define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */
88 #ifdef CONFIG_SERIAL_8250_SHARE_IRQ
89 #define SERIAL8250_SHARE_IRQS 1
91 #define SERIAL8250_SHARE_IRQS 0
94 #define SERIAL8250_PORT_FLAGS(_base, _irq, _flags) \
99 .iotype = UPIO_PORT, \
100 .flags = UPF_BOOT_AUTOCONF | (_flags), \
103 #define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0)
106 static inline int serial_in(struct uart_8250_port *up, int offset)
108 return up->port.serial_in(&up->port, offset);
111 static inline void serial_out(struct uart_8250_port *up, int offset, int value)
113 up->port.serial_out(&up->port, offset, value);
116 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);
118 static inline int serial_dl_read(struct uart_8250_port *up)
120 return up->dl_read(up);
123 static inline void serial_dl_write(struct uart_8250_port *up, int value)
125 up->dl_write(up, value);
128 struct uart_8250_port *serial8250_get_port(int line);
129 void serial8250_rpm_get(struct uart_8250_port *p);
130 void serial8250_rpm_put(struct uart_8250_port *p);
131 int serial8250_em485_init(struct uart_8250_port *p);
132 void serial8250_em485_destroy(struct uart_8250_port *p);
134 #if defined(__alpha__) && !defined(CONFIG_PCI)
136 * Digital did something really horribly wrong with the OUT1 and OUT2
137 * lines on at least some ALPHA's. The failure mode is that if either
138 * is cleared, the machine locks up with endless interrupts.
140 #define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
142 #define ALPHA_KLUDGE_MCR 0
145 #ifdef CONFIG_SERIAL_8250_PNP
146 int serial8250_pnp_init(void);
147 void serial8250_pnp_exit(void);
149 static inline int serial8250_pnp_init(void) { return 0; }
150 static inline void serial8250_pnp_exit(void) { }
153 #ifdef CONFIG_SERIAL_8250_FINTEK
154 int fintek_8250_probe(struct uart_8250_port *uart);
156 static inline int fintek_8250_probe(struct uart_8250_port *uart) { return 0; }
159 #ifdef CONFIG_ARCH_OMAP1
160 static inline int is_omap1_8250(struct uart_8250_port *pt)
164 switch (pt->port.mapbase) {
165 case OMAP1_UART1_BASE:
166 case OMAP1_UART2_BASE:
167 case OMAP1_UART3_BASE:
178 static inline int is_omap1510_8250(struct uart_8250_port *pt)
180 if (!cpu_is_omap1510())
183 return is_omap1_8250(pt);
186 static inline int is_omap1_8250(struct uart_8250_port *pt)
190 static inline int is_omap1510_8250(struct uart_8250_port *pt)
196 #ifdef CONFIG_SERIAL_8250_DMA
197 extern int serial8250_tx_dma(struct uart_8250_port *);
198 extern int serial8250_rx_dma(struct uart_8250_port *);
199 extern void serial8250_rx_dma_flush(struct uart_8250_port *);
200 extern int serial8250_request_dma(struct uart_8250_port *);
201 extern void serial8250_release_dma(struct uart_8250_port *);
203 static inline int serial8250_tx_dma(struct uart_8250_port *p)
207 static inline int serial8250_rx_dma(struct uart_8250_port *p)
211 static inline void serial8250_rx_dma_flush(struct uart_8250_port *p) { }
212 static inline int serial8250_request_dma(struct uart_8250_port *p)
216 static inline void serial8250_release_dma(struct uart_8250_port *p) { }
219 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
221 unsigned char status;
223 status = serial_in(up, 0x04); /* EXCR2 */
224 #define PRESL(x) ((x) & 0x30)
225 if (PRESL(status) == 0x10) {
226 /* already in high speed mode */
229 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
230 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
231 serial_out(up, 0x04, status);
236 static inline int serial_index(struct uart_port *port)
238 return port->minor - 64;
242 #define DEBUG_INTR(fmt...) printk(fmt)
244 #define DEBUG_INTR(fmt...) do { } while (0)