2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/acpi.h>
27 #include <linux/clk.h>
28 #include <linux/reset.h>
29 #include <linux/pm_runtime.h>
31 #include <asm/byteorder.h>
35 /* Offsets for the DesignWare specific registers */
36 #define DW_UART_USR 0x1f /* UART Status Register */
37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
38 #define DW_UART_UCV 0xf8 /* UART Component Version */
40 /* Component Parameter Register bits */
41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
42 #define DW_UART_CPR_AFCE_MODE (1 << 4)
43 #define DW_UART_CPR_THRE_MODE (1 << 5)
44 #define DW_UART_CPR_SIR_MODE (1 << 6)
45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
48 #define DW_UART_CPR_FIFO_STAT (1 << 10)
49 #define DW_UART_CPR_SHADOW (1 << 11)
50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
51 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
52 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
53 /* Helper for fifo size calculation */
54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
64 struct reset_control *rst;
65 struct uart_8250_dma dma;
67 unsigned int skip_autocfg:1;
68 unsigned int uart_16550_compatible:1;
71 #define BYT_PRV_CLK 0x800
72 #define BYT_PRV_CLK_EN (1 << 0)
73 #define BYT_PRV_CLK_M_VAL_SHIFT 1
74 #define BYT_PRV_CLK_N_VAL_SHIFT 16
75 #define BYT_PRV_CLK_UPDATE (1 << 31)
77 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
79 struct dw8250_data *d = p->private_data;
81 /* Override any modem control signals if needed */
82 if (offset == UART_MSR) {
83 value |= d->msr_mask_on;
84 value &= ~d->msr_mask_off;
90 static void dw8250_force_idle(struct uart_port *p)
92 struct uart_8250_port *up = up_to_u8250p(p);
94 serial8250_clear_and_reinit_fifos(up);
95 (void)p->serial_in(p, UART_RX);
98 static void dw8250_check_lcr(struct uart_port *p, int value)
100 void __iomem *offset = p->membase + (UART_LCR << p->regshift);
103 /* Make sure LCR write wasn't ignored */
105 unsigned int lcr = p->serial_in(p, UART_LCR);
107 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
110 dw8250_force_idle(p);
113 __raw_writeq(value & 0xff, offset);
115 if (p->iotype == UPIO_MEM32)
116 writel(value, offset);
118 writeb(value, offset);
122 * FIXME: this deadlocks if port->lock is already held
123 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
127 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
129 struct dw8250_data *d = p->private_data;
131 writeb(value, p->membase + (offset << p->regshift));
133 if (offset == UART_LCR && !d->uart_16550_compatible)
134 dw8250_check_lcr(p, value);
137 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
139 unsigned int value = readb(p->membase + (offset << p->regshift));
141 return dw8250_modify_msr(p, offset, value);
145 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
149 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
151 return dw8250_modify_msr(p, offset, value);
154 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
156 struct dw8250_data *d = p->private_data;
159 __raw_writeq(value, p->membase + (offset << p->regshift));
160 /* Read back to ensure register write ordering. */
161 __raw_readq(p->membase + (UART_LCR << p->regshift));
163 if (offset == UART_LCR && !d->uart_16550_compatible)
164 dw8250_check_lcr(p, value);
166 #endif /* CONFIG_64BIT */
168 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
170 struct dw8250_data *d = p->private_data;
172 writel(value, p->membase + (offset << p->regshift));
174 if (offset == UART_LCR && !d->uart_16550_compatible)
175 dw8250_check_lcr(p, value);
178 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
180 unsigned int value = readl(p->membase + (offset << p->regshift));
182 return dw8250_modify_msr(p, offset, value);
185 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
187 struct dw8250_data *d = p->private_data;
189 iowrite32be(value, p->membase + (offset << p->regshift));
191 if (offset == UART_LCR && !d->uart_16550_compatible)
192 dw8250_check_lcr(p, value);
195 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
197 unsigned int value = ioread32be(p->membase + (offset << p->regshift));
199 return dw8250_modify_msr(p, offset, value);
203 static int dw8250_handle_irq(struct uart_port *p)
205 struct dw8250_data *d = p->private_data;
206 unsigned int iir = p->serial_in(p, UART_IIR);
208 if (serial8250_handle_irq(p, iir)) {
210 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
212 (void)p->serial_in(p, d->usr_reg);
221 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
224 pm_runtime_get_sync(port->dev);
226 serial8250_do_pm(port, state, old);
229 pm_runtime_put_sync_suspend(port->dev);
232 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
233 struct ktermios *old)
235 unsigned int baud = tty_termios_baud_rate(termios);
236 struct dw8250_data *d = p->private_data;
240 if (IS_ERR(d->clk) || !old)
243 clk_disable_unprepare(d->clk);
244 rate = clk_round_rate(d->clk, baud * 16);
245 ret = clk_set_rate(d->clk, rate);
246 clk_prepare_enable(d->clk);
251 p->status &= ~UPSTAT_AUTOCTS;
252 if (termios->c_cflag & CRTSCTS)
253 p->status |= UPSTAT_AUTOCTS;
256 serial8250_do_set_termios(p, termios, old);
260 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
261 * channel on platforms that have DMA engines, but don't have any channels
262 * assigned to the UART.
264 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
265 * core problem is fixed, this function is no longer needed.
267 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
272 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
274 return param == chan->device->dev->parent;
277 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
279 if (p->dev->of_node) {
280 struct device_node *np = p->dev->of_node;
283 /* get index of serial line, if found in DT aliases */
284 id = of_alias_get_id(np, "serial");
288 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
289 p->serial_in = dw8250_serial_inq;
290 p->serial_out = dw8250_serial_outq;
291 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
292 p->type = PORT_OCTEON;
293 data->usr_reg = 0x27;
294 data->skip_autocfg = true;
297 if (of_device_is_big_endian(p->dev->of_node)) {
298 p->iotype = UPIO_MEM32BE;
299 p->serial_in = dw8250_serial_in32be;
300 p->serial_out = dw8250_serial_out32be;
302 } else if (has_acpi_companion(p->dev)) {
303 p->iotype = UPIO_MEM32;
305 p->serial_in = dw8250_serial_in32;
306 p->set_termios = dw8250_set_termios;
307 /* So far none of there implement the Busy Functionality */
308 data->uart_16550_compatible = true;
311 /* Platforms with iDMA */
312 if (platform_get_resource_byname(to_platform_device(p->dev),
313 IORESOURCE_MEM, "lpss_priv")) {
314 p->set_termios = dw8250_set_termios;
315 data->dma.rx_param = p->dev->parent;
316 data->dma.tx_param = p->dev->parent;
317 data->dma.fn = dw8250_idma_filter;
321 static void dw8250_setup_port(struct uart_port *p)
323 struct uart_8250_port *up = up_to_u8250p(p);
327 * If the Component Version Register returns zero, we know that
328 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
330 reg = readl(p->membase + DW_UART_UCV);
334 dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
335 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
337 reg = readl(p->membase + DW_UART_CPR);
341 /* Select the type based on fifo */
342 if (reg & DW_UART_CPR_FIFO_MODE) {
343 p->type = PORT_16550A;
344 p->flags |= UPF_FIXED_TYPE;
345 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
346 up->capabilities = UART_CAP_FIFO;
349 if (reg & DW_UART_CPR_AFCE_MODE)
350 up->capabilities |= UART_CAP_AFE;
353 static int dw8250_probe(struct platform_device *pdev)
355 struct uart_8250_port uart = {};
356 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
357 int irq = platform_get_irq(pdev, 0);
358 struct uart_port *p = &uart.port;
359 struct dw8250_data *data;
364 dev_err(&pdev->dev, "no registers defined\n");
369 if (irq != -EPROBE_DEFER)
370 dev_err(&pdev->dev, "cannot get irq\n");
374 spin_lock_init(&p->lock);
375 p->mapbase = regs->start;
377 p->handle_irq = dw8250_handle_irq;
378 p->pm = dw8250_do_pm;
380 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
382 p->iotype = UPIO_MEM;
383 p->serial_in = dw8250_serial_in;
384 p->serial_out = dw8250_serial_out;
386 p->membase = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
390 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
394 data->dma.fn = dw8250_fallback_dma_filter;
395 data->usr_reg = DW_UART_USR;
396 p->private_data = data;
398 data->uart_16550_compatible = device_property_read_bool(p->dev,
399 "snps,uart-16550-compatible");
401 err = device_property_read_u32(p->dev, "reg-shift", &val);
405 err = device_property_read_u32(p->dev, "reg-io-width", &val);
406 if (!err && val == 4) {
407 p->iotype = UPIO_MEM32;
408 p->serial_in = dw8250_serial_in32;
409 p->serial_out = dw8250_serial_out32;
412 if (device_property_read_bool(p->dev, "dcd-override")) {
413 /* Always report DCD as active */
414 data->msr_mask_on |= UART_MSR_DCD;
415 data->msr_mask_off |= UART_MSR_DDCD;
418 if (device_property_read_bool(p->dev, "dsr-override")) {
419 /* Always report DSR as active */
420 data->msr_mask_on |= UART_MSR_DSR;
421 data->msr_mask_off |= UART_MSR_DDSR;
424 if (device_property_read_bool(p->dev, "cts-override")) {
425 /* Always report CTS as active */
426 data->msr_mask_on |= UART_MSR_CTS;
427 data->msr_mask_off |= UART_MSR_DCTS;
430 if (device_property_read_bool(p->dev, "ri-override")) {
431 /* Always report Ring indicator as inactive */
432 data->msr_mask_off |= UART_MSR_RI;
433 data->msr_mask_off |= UART_MSR_TERI;
436 /* Always ask for fixed clock rate from a property. */
437 device_property_read_u32(p->dev, "clock-frequency", &p->uartclk);
439 /* If there is separate baudclk, get the rate from it. */
440 data->clk = devm_clk_get(&pdev->dev, "baudclk");
441 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
442 data->clk = devm_clk_get(&pdev->dev, NULL);
443 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
444 return -EPROBE_DEFER;
445 if (!IS_ERR_OR_NULL(data->clk)) {
446 err = clk_prepare_enable(data->clk);
448 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
451 p->uartclk = clk_get_rate(data->clk);
454 /* If no clock rate is defined, fail. */
456 dev_err(&pdev->dev, "clock rate not defined\n");
460 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
461 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
465 if (!IS_ERR(data->pclk)) {
466 err = clk_prepare_enable(data->pclk);
468 dev_err(&pdev->dev, "could not enable apb_pclk\n");
473 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
474 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
478 if (!IS_ERR(data->rst))
479 reset_control_deassert(data->rst);
481 dw8250_quirks(p, data);
483 /* If the Busy Functionality is not implemented, don't handle it */
484 if (data->uart_16550_compatible)
485 p->handle_irq = NULL;
487 if (!data->skip_autocfg)
488 dw8250_setup_port(p);
490 /* If we have a valid fifosize, try hooking up DMA */
492 data->dma.rxconf.src_maxburst = p->fifosize / 4;
493 data->dma.txconf.dst_maxburst = p->fifosize / 4;
494 uart.dma = &data->dma;
497 data->line = serial8250_register_8250_port(&uart);
498 if (data->line < 0) {
503 platform_set_drvdata(pdev, data);
505 pm_runtime_set_active(&pdev->dev);
506 pm_runtime_enable(&pdev->dev);
511 if (!IS_ERR(data->rst))
512 reset_control_assert(data->rst);
515 if (!IS_ERR(data->pclk))
516 clk_disable_unprepare(data->pclk);
519 if (!IS_ERR(data->clk))
520 clk_disable_unprepare(data->clk);
525 static int dw8250_remove(struct platform_device *pdev)
527 struct dw8250_data *data = platform_get_drvdata(pdev);
529 pm_runtime_get_sync(&pdev->dev);
531 serial8250_unregister_port(data->line);
533 if (!IS_ERR(data->rst))
534 reset_control_assert(data->rst);
536 if (!IS_ERR(data->pclk))
537 clk_disable_unprepare(data->pclk);
539 if (!IS_ERR(data->clk))
540 clk_disable_unprepare(data->clk);
542 pm_runtime_disable(&pdev->dev);
543 pm_runtime_put_noidle(&pdev->dev);
548 #ifdef CONFIG_PM_SLEEP
549 static int dw8250_suspend(struct device *dev)
551 struct dw8250_data *data = dev_get_drvdata(dev);
553 serial8250_suspend_port(data->line);
558 static int dw8250_resume(struct device *dev)
560 struct dw8250_data *data = dev_get_drvdata(dev);
562 serial8250_resume_port(data->line);
566 #endif /* CONFIG_PM_SLEEP */
569 static int dw8250_runtime_suspend(struct device *dev)
571 struct dw8250_data *data = dev_get_drvdata(dev);
573 if (!IS_ERR(data->clk))
574 clk_disable_unprepare(data->clk);
576 if (!IS_ERR(data->pclk))
577 clk_disable_unprepare(data->pclk);
582 static int dw8250_runtime_resume(struct device *dev)
584 struct dw8250_data *data = dev_get_drvdata(dev);
586 if (!IS_ERR(data->pclk))
587 clk_prepare_enable(data->pclk);
589 if (!IS_ERR(data->clk))
590 clk_prepare_enable(data->clk);
596 static const struct dev_pm_ops dw8250_pm_ops = {
597 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
598 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
601 static const struct of_device_id dw8250_of_match[] = {
602 { .compatible = "snps,dw-apb-uart" },
603 { .compatible = "cavium,octeon-3860-uart" },
606 MODULE_DEVICE_TABLE(of, dw8250_of_match);
608 static const struct acpi_device_id dw8250_acpi_match[] = {
619 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
621 static struct platform_driver dw8250_platform_driver = {
623 .name = "dw-apb-uart",
624 .pm = &dw8250_pm_ops,
625 .of_match_table = dw8250_of_match,
626 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
628 .probe = dw8250_probe,
629 .remove = dw8250_remove,
632 module_platform_driver(dw8250_platform_driver);
634 MODULE_AUTHOR("Jamie Iles");
635 MODULE_LICENSE("GPL");
636 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
637 MODULE_ALIAS("platform:dw-apb-uart");