drivers/tty/serial/8250/8250_dw.c

   1 /*
   2  * Synopsys DesignWare 8250 driver.
   3  *
   4  * Copyright 2011 Picochip, Jamie Iles.
   5  * Copyright 2013 Intel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
  13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
  14  * raised, the LCR needs to be rewritten and the uart status register read.
  15  */
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/acpi.h>
  29 #include <linux/clk.h>
  30
  31 #include "8250.h"
  32
  33 /* Offsets for the DesignWare specific registers */
  34 #define DW_UART_USR     0x1f /* UART Status Register */
  35 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
  36 #define DW_UART_UCV     0xf8 /* UART Component Version */
  37
  38 /* Intel Low Power Subsystem specific */
  39 #define LPSS_PRV_CLOCK_PARAMS 0x800
  40
  41 /* Component Parameter Register bits */
  42 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
  43 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
  44 #define DW_UART_CPR_THRE_MODE           (1 << 5)
  45 #define DW_UART_CPR_SIR_MODE            (1 << 6)
  46 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
  47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
  48 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
  49 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
  50 #define DW_UART_CPR_SHADOW              (1 << 11)
  51 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
  52 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
  53 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
  54 /* Helper for fifo size calculation */
  55 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
  56
  57
  58 struct dw8250_data {
  59         int             last_lcr;
  60         int             line;
  61         struct clk      *clk;
  62 };
  63
  64 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
  65 {
  66         struct dw8250_data *d = p->private_data;
  67
  68         if (offset == UART_LCR)
  69                 d->last_lcr = value;
  70
  71         offset <<= p->regshift;
  72         writeb(value, p->membase + offset);
  73 }
  74
  75 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
  76 {
  77         offset <<= p->regshift;
  78
  79         return readb(p->membase + offset);
  80 }
  81
  82 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
  83 {
  84         struct dw8250_data *d = p->private_data;
  85
  86         if (offset == UART_LCR)
  87                 d->last_lcr = value;
  88
  89         offset <<= p->regshift;
  90         writel(value, p->membase + offset);
  91 }
  92
  93 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
  94 {
  95         offset <<= p->regshift;
  96
  97         return readl(p->membase + offset);
  98 }
  99
 100 static int dw8250_handle_irq(struct uart_port *p)
 101 {
 102         struct dw8250_data *d = p->private_data;
 103         unsigned int iir = p->serial_in(p, UART_IIR);
 104
 105         if (serial8250_handle_irq(p, iir)) {
 106                 return 1;
 107         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
 108                 /* Clear the USR and write the LCR again. */
 109                 (void)p->serial_in(p, DW_UART_USR);
 110                 p->serial_out(p, UART_LCR, d->last_lcr);
 111
 112                 return 1;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int dw8250_probe_of(struct uart_port *p)
 119 {
 120         struct device_node      *np = p->dev->of_node;
 121         u32                     val;
 122
 123         if (!of_property_read_u32(np, "reg-io-width", &val)) {
 124                 switch (val) {
 125                 case 1:
 126                         break;
 127                 case 4:
 128                         p->iotype = UPIO_MEM32;
 129                         p->serial_in = dw8250_serial_in32;
 130                         p->serial_out = dw8250_serial_out32;
 131                         break;
 132                 default:
 133                         dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
 134                         return -EINVAL;
 135                 }
 136         }
 137
 138         if (!of_property_read_u32(np, "reg-shift", &val))
 139                 p->regshift = val;
 140
 141         /* clock got configured through clk api, all done */
 142         if (p->uartclk)
 143                 return 0;
 144
 145         /* try to find out clock frequency from DT as fallback */
 146         if (of_property_read_u32(np, "clock-frequency", &val)) {
 147                 dev_err(p->dev, "clk or clock-frequency not defined\n");
 148                 return -EINVAL;
 149         }
 150         p->uartclk = val;
 151
 152         return 0;
 153 }
 154
 155 #ifdef CONFIG_ACPI
 156 static bool dw8250_acpi_dma_filter(struct dma_chan *chan, void *parm)
 157 {
 158         return chan->chan_id == *(int *)parm;
 159 }
 160
 161 static acpi_status
 162 dw8250_acpi_walk_resource(struct acpi_resource *res, void *data)
 163 {
 164         struct uart_port                *p = data;
 165         struct uart_8250_port           *port;
 166         struct uart_8250_dma            *dma;
 167         struct acpi_resource_fixed_dma  *fixed_dma;
 168         struct dma_slave_config         *slave;
 169
 170         port = container_of(p, struct uart_8250_port, port);
 171
 172         switch (res->type) {
 173         case ACPI_RESOURCE_TYPE_FIXED_DMA:
 174                 fixed_dma = &res->data.fixed_dma;
 175
 176                 /* TX comes first */
 177                 if (!port->dma) {
 178                         dma = devm_kzalloc(p->dev, sizeof(*dma), GFP_KERNEL);
 179                         if (!dma)
 180                                 return AE_NO_MEMORY;
 181
 182                         port->dma = dma;
 183                         slave = &dma->txconf;
 184
 185                         slave->direction        = DMA_MEM_TO_DEV;
 186                         slave->dst_addr_width   = DMA_SLAVE_BUSWIDTH_1_BYTE;
 187                         slave->slave_id         = fixed_dma->request_lines;
 188                         slave->dst_maxburst     = port->tx_loadsz / 4;
 189
 190                         dma->tx_chan_id         = fixed_dma->channels;
 191                         dma->tx_param           = &dma->tx_chan_id;
 192                         dma->fn                 = dw8250_acpi_dma_filter;
 193                 } else {
 194                         dma = port->dma;
 195                         slave = &dma->rxconf;
 196
 197                         slave->direction        = DMA_DEV_TO_MEM;
 198                         slave->src_addr_width   = DMA_SLAVE_BUSWIDTH_1_BYTE;
 199                         slave->slave_id         = fixed_dma->request_lines;
 200                         slave->src_maxburst     = p->fifosize / 4;
 201
 202                         dma->rx_chan_id         = fixed_dma->channels;
 203                         dma->rx_param           = &dma->rx_chan_id;
 204                 }
 205
 206                 break;
 207         }
 208
 209         return AE_OK;
 210 }
 211
 212 static int dw8250_probe_acpi(struct uart_port *p)
 213 {
 214         const struct acpi_device_id *id;
 215         acpi_status status;
 216         u32 reg;
 217
 218         id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
 219         if (!id)
 220                 return -ENODEV;
 221
 222         p->iotype = UPIO_MEM32;
 223         p->serial_in = dw8250_serial_in32;
 224         p->serial_out = dw8250_serial_out32;
 225         p->regshift = 2;
 226         p->uartclk = (unsigned int)id->driver_data;
 227
 228         status = acpi_walk_resources(ACPI_HANDLE(p->dev), METHOD_NAME__CRS,
 229                                      dw8250_acpi_walk_resource, p);
 230         if (ACPI_FAILURE(status)) {
 231                 dev_err_ratelimited(p->dev, "%s failed \"%s\"\n", __func__,
 232                                     acpi_format_exception(status));
 233                 return -ENODEV;
 234         }
 235
 236         /* Fix Haswell issue where the clocks do not get enabled */
 237         if (!strcmp(id->id, "INT33C4") || !strcmp(id->id, "INT33C5")) {
 238                 reg = readl(p->membase + LPSS_PRV_CLOCK_PARAMS);
 239                 writel(reg | 1, p->membase + LPSS_PRV_CLOCK_PARAMS);
 240         }
 241
 242         return 0;
 243 }
 244 #else
 245 static inline int dw8250_probe_acpi(struct uart_port *p)
 246 {
 247         return -ENODEV;
 248 }
 249 #endif /* CONFIG_ACPI */
 250
 251 static void dw8250_setup_port(struct uart_8250_port *up)
 252 {
 253         struct uart_port        *p = &up->port;
 254         u32                     reg = readl(p->membase + DW_UART_UCV);
 255
 256         /*
 257          * If the Component Version Register returns zero, we know that
 258          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
 259          */
 260         if (!reg)
 261                 return;
 262
 263         dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
 264                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
 265
 266         reg = readl(p->membase + DW_UART_CPR);
 267         if (!reg)
 268                 return;
 269
 270         /* Select the type based on fifo */
 271         if (reg & DW_UART_CPR_FIFO_MODE) {
 272                 p->type = PORT_16550A;
 273                 p->flags |= UPF_FIXED_TYPE;
 274                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
 275                 up->tx_loadsz = p->fifosize;
 276         }
 277 }
 278
 279 static int dw8250_probe(struct platform_device *pdev)
 280 {
 281         struct uart_8250_port uart = {};
 282         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 283         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 284         struct dw8250_data *data;
 285         int err;
 286
 287         if (!regs || !irq) {
 288                 dev_err(&pdev->dev, "no registers/irq defined\n");
 289                 return -EINVAL;
 290         }
 291
 292         spin_lock_init(&uart.port.lock);
 293         uart.port.mapbase = regs->start;
 294         uart.port.irq = irq->start;
 295         uart.port.handle_irq = dw8250_handle_irq;
 296         uart.port.type = PORT_8250;
 297         uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
 298         uart.port.dev = &pdev->dev;
 299
 300         uart.port.membase = ioremap(regs->start, resource_size(regs));
 301         if (!uart.port.membase)
 302                 return -ENOMEM;
 303
 304         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 305         if (!data)
 306                 return -ENOMEM;
 307
 308         data->clk = devm_clk_get(&pdev->dev, NULL);
 309         if (!IS_ERR(data->clk)) {
 310                 clk_prepare_enable(data->clk);
 311                 uart.port.uartclk = clk_get_rate(data->clk);
 312         }
 313
 314         uart.port.iotype = UPIO_MEM;
 315         uart.port.serial_in = dw8250_serial_in;
 316         uart.port.serial_out = dw8250_serial_out;
 317         uart.port.private_data = data;
 318
 319         dw8250_setup_port(&uart);
 320
 321         if (pdev->dev.of_node) {
 322                 err = dw8250_probe_of(&uart.port);
 323                 if (err)
 324                         return err;
 325         } else if (ACPI_HANDLE(&pdev->dev)) {
 326                 err = dw8250_probe_acpi(&uart.port);
 327                 if (err)
 328                         return err;
 329         } else {
 330                 return -ENODEV;
 331         }
 332
 333         data->line = serial8250_register_8250_port(&uart);
 334         if (data->line < 0)
 335                 return data->line;
 336
 337         platform_set_drvdata(pdev, data);
 338
 339         return 0;
 340 }
 341
 342 static int dw8250_remove(struct platform_device *pdev)
 343 {
 344         struct dw8250_data *data = platform_get_drvdata(pdev);
 345
 346         serial8250_unregister_port(data->line);
 347
 348         if (!IS_ERR(data->clk))
 349                 clk_disable_unprepare(data->clk);
 350
 351         return 0;
 352 }
 353
 354 #ifdef CONFIG_PM
 355 static int dw8250_suspend(struct platform_device *pdev, pm_message_t state)
 356 {
 357         struct dw8250_data *data = platform_get_drvdata(pdev);
 358
 359         serial8250_suspend_port(data->line);
 360
 361         return 0;
 362 }
 363
 364 static int dw8250_resume(struct platform_device *pdev)
 365 {
 366         struct dw8250_data *data = platform_get_drvdata(pdev);
 367
 368         serial8250_resume_port(data->line);
 369
 370         return 0;
 371 }
 372 #else
 373 #define dw8250_suspend NULL
 374 #define dw8250_resume NULL
 375 #endif /* CONFIG_PM */
 376
 377 static const struct of_device_id dw8250_of_match[] = {
 378         { .compatible = "snps,dw-apb-uart" },
 379         { /* Sentinel */ }
 380 };
 381 MODULE_DEVICE_TABLE(of, dw8250_of_match);
 382
 383 static const struct acpi_device_id dw8250_acpi_match[] = {
 384         { "INT33C4", 100000000 },
 385         { "INT33C5", 100000000 },
 386         { },
 387 };
 388 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
 389
 390 static struct platform_driver dw8250_platform_driver = {
 391         .driver = {
 392                 .name           = "dw-apb-uart",
 393                 .owner          = THIS_MODULE,
 394                 .of_match_table = dw8250_of_match,
 395                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
 396         },
 397         .probe                  = dw8250_probe,
 398         .remove                 = dw8250_remove,
 399         .suspend                = dw8250_suspend,
 400         .resume                 = dw8250_resume,
 401 };
 402
 403 module_platform_driver(dw8250_platform_driver);
 404
 405 MODULE_AUTHOR("Jamie Iles");
 406 MODULE_LICENSE("GPL");
 407 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");