2 * 8250-core based driver for the OMAP internal UART
4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 * Copyright (C) 2014 Sebastian Andrzej Siewior
10 #include <linux/device.h>
12 #include <linux/module.h>
13 #include <linux/serial_8250.h>
14 #include <linux/serial_reg.h>
15 #include <linux/tty_flip.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_irq.h>
22 #include <linux/delay.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/console.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_wakeirq.h>
27 #include <linux/dma-mapping.h>
31 #define DEFAULT_CLK_SPEED 48000000
33 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
34 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
35 #define OMAP_DMA_TX_KICK (1 << 2)
37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
38 * The same errata is applicable to AM335x and DRA7x processors too.
40 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
42 #define OMAP_UART_FCR_RX_TRIG 6
43 #define OMAP_UART_FCR_TX_TRIG 4
45 /* SCR register bitmasks */
46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
48 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
49 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
50 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
51 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
53 /* MVR register bitmasks */
54 #define OMAP_UART_MVR_SCHEME_SHIFT 30
55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
57 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
58 #define OMAP_UART_MVR_MAJ_MASK 0x700
59 #define OMAP_UART_MVR_MAJ_SHIFT 8
60 #define OMAP_UART_MVR_MIN_MASK 0x3f
62 /* SYSC register bitmasks */
63 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
65 /* SYSS register bitmasks */
66 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
68 #define UART_TI752_TLR_TX 0
69 #define UART_TI752_TLR_RX 4
71 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
72 #define TRIGGER_FCR_MASK(x) (x & 3)
74 /* Enable XON/XOFF flow control on output */
75 #define OMAP_UART_SW_TX 0x08
76 /* Enable XON/XOFF flow control on input */
77 #define OMAP_UART_SW_RX 0x02
79 #define OMAP_UART_WER_MOD_WKUP 0x7f
80 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
85 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
86 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
88 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
90 #define OMAP_UART_REV_46 0x0406
91 #define OMAP_UART_REV_52 0x0502
92 #define OMAP_UART_REV_63 0x0603
94 struct omap8250_priv {
111 struct pm_qos_request pm_qos_request;
112 struct work_struct qos_work;
113 struct uart_8250_dma omap8250_dma;
114 spinlock_t rx_dma_lock;
117 static u32 uart_read(struct uart_8250_port *up, u32 reg)
119 return readl(up->port.membase + (reg << up->port.regshift));
122 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
124 struct uart_8250_port *up = up_to_u8250p(port);
125 struct omap8250_priv *priv = up->port.private_data;
128 serial8250_do_set_mctrl(port, mctrl);
131 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
134 lcr = serial_in(up, UART_LCR);
135 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
136 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
137 priv->efr |= UART_EFR_RTS;
139 priv->efr &= ~UART_EFR_RTS;
140 serial_out(up, UART_EFR, priv->efr);
141 serial_out(up, UART_LCR, lcr);
145 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
146 * The access to uart register after MDR1 Access
147 * causes UART to corrupt data.
150 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
151 * give 10 times as much
153 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
154 struct omap8250_priv *priv)
159 old_mdr1 = serial_in(up, UART_OMAP_MDR1);
160 if (old_mdr1 == priv->mdr1)
163 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
165 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
166 UART_FCR_CLEAR_RCVR);
168 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
169 * TX_FIFO_E bit is 1.
171 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
172 (UART_LSR_THRE | UART_LSR_DR))) {
175 /* Should *never* happen. we warn and carry on */
176 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
177 serial_in(up, UART_LSR));
184 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
185 struct omap8250_priv *priv)
187 unsigned int uartclk = port->uartclk;
188 unsigned int div_13, div_16;
189 unsigned int abs_d13, abs_d16;
192 * Old custom speed handling.
194 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
195 priv->quot = port->custom_divisor & 0xffff;
197 * I assume that nobody is using this. But hey, if somebody
198 * would like to specify the divisor _and_ the mode then the
199 * driver is ready and waiting for it.
201 if (port->custom_divisor & (1 << 16))
202 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
204 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
207 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
208 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
215 abs_d13 = abs(baud - uartclk / 13 / div_13);
216 abs_d16 = abs(baud - uartclk / 16 / div_16);
218 if (abs_d13 >= abs_d16) {
219 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
222 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
227 static void omap8250_update_scr(struct uart_8250_port *up,
228 struct omap8250_priv *priv)
232 old_scr = serial_in(up, UART_OMAP_SCR);
233 if (old_scr == priv->scr)
237 * The manual recommends not to enable the DMA mode selector in the SCR
238 * (instead of the FCR) register _and_ selecting the DMA mode as one
239 * register write because this may lead to malfunction.
241 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
242 serial_out(up, UART_OMAP_SCR,
243 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
244 serial_out(up, UART_OMAP_SCR, priv->scr);
247 static void omap8250_update_mdr1(struct uart_8250_port *up,
248 struct omap8250_priv *priv)
250 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
251 omap_8250_mdr1_errataset(up, priv);
253 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
256 static void omap8250_restore_regs(struct uart_8250_port *up)
258 struct omap8250_priv *priv = up->port.private_data;
259 struct uart_8250_dma *dma = up->dma;
261 if (dma && dma->tx_running) {
263 * TCSANOW requests the change to occur immediately however if
264 * we have a TX-DMA operation in progress then it has been
265 * observed that it might stall and never complete. Therefore we
266 * delay DMA completes to prevent this hang from happen.
268 priv->delayed_restore = 1;
272 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
273 serial_out(up, UART_EFR, UART_EFR_ECB);
275 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
276 serial_out(up, UART_MCR, UART_MCR_TCRTLR);
277 serial_out(up, UART_FCR, up->fcr);
279 omap8250_update_scr(up, priv);
281 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
283 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
284 OMAP_UART_TCR_HALT(52));
285 serial_out(up, UART_TI752_TLR,
286 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
287 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
289 serial_out(up, UART_LCR, 0);
291 /* drop TCR + TLR access, we setup XON/XOFF later */
292 serial_out(up, UART_MCR, up->mcr);
293 serial_out(up, UART_IER, up->ier);
295 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
296 serial_dl_write(up, priv->quot);
298 serial_out(up, UART_EFR, priv->efr);
300 /* Configure flow control */
301 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
302 serial_out(up, UART_XON1, priv->xon);
303 serial_out(up, UART_XOFF1, priv->xoff);
305 serial_out(up, UART_LCR, up->lcr);
307 omap8250_update_mdr1(up, priv);
309 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
313 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
314 * some differences in how we want to handle flow control.
316 static void omap_8250_set_termios(struct uart_port *port,
317 struct ktermios *termios,
318 struct ktermios *old)
320 struct uart_8250_port *up =
321 container_of(port, struct uart_8250_port, port);
322 struct omap8250_priv *priv = up->port.private_data;
323 unsigned char cval = 0;
326 switch (termios->c_cflag & CSIZE) {
328 cval = UART_LCR_WLEN5;
331 cval = UART_LCR_WLEN6;
334 cval = UART_LCR_WLEN7;
338 cval = UART_LCR_WLEN8;
342 if (termios->c_cflag & CSTOPB)
343 cval |= UART_LCR_STOP;
344 if (termios->c_cflag & PARENB)
345 cval |= UART_LCR_PARITY;
346 if (!(termios->c_cflag & PARODD))
347 cval |= UART_LCR_EPAR;
348 if (termios->c_cflag & CMSPAR)
349 cval |= UART_LCR_SPAR;
352 * Ask the core to calculate the divisor for us.
354 baud = uart_get_baud_rate(port, termios, old,
355 port->uartclk / 16 / 0xffff,
357 omap_8250_get_divisor(port, baud, priv);
360 * Ok, we're now changing the port state. Do it with
361 * interrupts disabled.
363 pm_runtime_get_sync(port->dev);
364 spin_lock_irq(&port->lock);
367 * Update the per-port timeout.
369 uart_update_timeout(port, termios->c_cflag, baud);
371 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
372 if (termios->c_iflag & INPCK)
373 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
374 if (termios->c_iflag & (IGNBRK | PARMRK))
375 up->port.read_status_mask |= UART_LSR_BI;
378 * Characters to ignore
380 up->port.ignore_status_mask = 0;
381 if (termios->c_iflag & IGNPAR)
382 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
383 if (termios->c_iflag & IGNBRK) {
384 up->port.ignore_status_mask |= UART_LSR_BI;
386 * If we're ignoring parity and break indicators,
387 * ignore overruns too (for real raw support).
389 if (termios->c_iflag & IGNPAR)
390 up->port.ignore_status_mask |= UART_LSR_OE;
394 * ignore all characters if CREAD is not set
396 if ((termios->c_cflag & CREAD) == 0)
397 up->port.ignore_status_mask |= UART_LSR_DR;
400 * Modem status interrupts
402 up->ier &= ~UART_IER_MSI;
403 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
404 up->ier |= UART_IER_MSI;
407 /* Up to here it was mostly serial8250_do_set_termios() */
410 * We enable TRIG_GRANU for RX and TX and additionaly we set
411 * SCR_TX_EMPTY bit. The result is the following:
412 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
413 * - less than RX_TRIGGER number of bytes will also cause an interrupt
414 * once the UART decides that there no new bytes arriving.
415 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
416 * empty - the trigger level is ignored here.
418 * Once DMA is enabled:
419 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
420 * bytes in the TX FIFO. On each assert the DMA engine will move
421 * TX_TRIGGER bytes into the FIFO.
422 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
423 * the FIFO and move RX_TRIGGER bytes.
424 * This is because threshold and trigger values are the same.
426 up->fcr = UART_FCR_ENABLE_FIFO;
427 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
428 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
430 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
431 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
434 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
435 OMAP_UART_SCR_DMAMODE_CTL;
437 priv->xon = termios->c_cc[VSTART];
438 priv->xoff = termios->c_cc[VSTOP];
441 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY);
442 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
444 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
445 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
446 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
447 priv->efr |= UART_EFR_CTS;
448 } else if (up->port.flags & UPF_SOFT_FLOW) {
450 * OMAP rx s/w flow control is borked; the transmitter remains
451 * stuck off even if rx flow control is subsequently disabled
456 * Enable XON/XOFF flow control on output.
457 * Transmit XON1, XOFF1
459 if (termios->c_iflag & IXOFF) {
460 up->port.status |= UPSTAT_AUTOXOFF;
461 priv->efr |= OMAP_UART_SW_TX;
464 omap8250_restore_regs(up);
466 spin_unlock_irq(&up->port.lock);
467 pm_runtime_mark_last_busy(port->dev);
468 pm_runtime_put_autosuspend(port->dev);
470 /* calculate wakeup latency constraint */
471 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
472 priv->latency = priv->calc_latency;
474 schedule_work(&priv->qos_work);
476 /* Don't rewrite B0 */
477 if (tty_termios_baud_rate(termios))
478 tty_termios_encode_baud_rate(termios, baud, baud);
481 /* same as 8250 except that we may have extra flow bits set in EFR */
482 static void omap_8250_pm(struct uart_port *port, unsigned int state,
483 unsigned int oldstate)
485 struct uart_8250_port *up = up_to_u8250p(port);
488 pm_runtime_get_sync(port->dev);
489 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
490 efr = serial_in(up, UART_EFR);
491 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
492 serial_out(up, UART_LCR, 0);
494 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
495 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
496 serial_out(up, UART_EFR, efr);
497 serial_out(up, UART_LCR, 0);
499 pm_runtime_mark_last_busy(port->dev);
500 pm_runtime_put_autosuspend(port->dev);
503 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
504 struct omap8250_priv *priv)
507 u16 revision, major, minor;
509 mvr = uart_read(up, UART_OMAP_MVER);
511 /* Check revision register scheme */
512 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
515 case 0: /* Legacy Scheme: OMAP2/3 */
516 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
517 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
518 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
519 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
522 /* New Scheme: OMAP4+ */
523 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
524 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
525 OMAP_UART_MVR_MAJ_SHIFT;
526 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
529 dev_warn(up->port.dev,
530 "Unknown revision, defaulting to highest\n");
531 /* highest possible revision */
535 /* normalize revision for the driver */
536 revision = UART_BUILD_REVISION(major, minor);
539 case OMAP_UART_REV_46:
540 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
542 case OMAP_UART_REV_52:
543 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
544 OMAP_UART_WER_HAS_TX_WAKEUP;
546 case OMAP_UART_REV_63:
547 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
548 OMAP_UART_WER_HAS_TX_WAKEUP;
555 static void omap8250_uart_qos_work(struct work_struct *work)
557 struct omap8250_priv *priv;
559 priv = container_of(work, struct omap8250_priv, qos_work);
560 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
563 #ifdef CONFIG_SERIAL_8250_DMA
564 static int omap_8250_dma_handle_irq(struct uart_port *port);
567 static irqreturn_t omap8250_irq(int irq, void *dev_id)
569 struct uart_port *port = dev_id;
570 struct uart_8250_port *up = up_to_u8250p(port);
574 #ifdef CONFIG_SERIAL_8250_DMA
576 ret = omap_8250_dma_handle_irq(port);
577 return IRQ_RETVAL(ret);
581 serial8250_rpm_get(up);
582 iir = serial_port_in(port, UART_IIR);
583 ret = serial8250_handle_irq(port, iir);
584 serial8250_rpm_put(up);
586 return IRQ_RETVAL(ret);
589 static int omap_8250_startup(struct uart_port *port)
591 struct uart_8250_port *up = up_to_u8250p(port);
592 struct omap8250_priv *priv = port->private_data;
596 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
601 pm_runtime_get_sync(port->dev);
604 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
606 serial_out(up, UART_LCR, UART_LCR_WLEN8);
608 up->lsr_saved_flags = 0;
609 up->msr_saved_flags = 0;
612 ret = serial8250_request_dma(up);
614 dev_warn_ratelimited(port->dev,
615 "failed to request DMA\n");
620 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
621 dev_name(port->dev), port);
625 up->ier = UART_IER_RLSI | UART_IER_RDI;
626 serial_out(up, UART_IER, up->ier);
629 up->capabilities |= UART_CAP_RPM;
632 /* Enable module level wake up */
633 priv->wer = OMAP_UART_WER_MOD_WKUP;
634 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
635 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
636 serial_out(up, UART_OMAP_WER, priv->wer);
639 up->dma->rx_dma(up, 0);
641 pm_runtime_mark_last_busy(port->dev);
642 pm_runtime_put_autosuspend(port->dev);
645 pm_runtime_mark_last_busy(port->dev);
646 pm_runtime_put_autosuspend(port->dev);
647 dev_pm_clear_wake_irq(port->dev);
651 static void omap_8250_shutdown(struct uart_port *port)
653 struct uart_8250_port *up = up_to_u8250p(port);
654 struct omap8250_priv *priv = port->private_data;
656 flush_work(&priv->qos_work);
658 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT);
660 pm_runtime_get_sync(port->dev);
662 serial_out(up, UART_OMAP_WER, 0);
665 serial_out(up, UART_IER, 0);
668 serial8250_release_dma(up);
671 * Disable break condition and FIFOs
673 if (up->lcr & UART_LCR_SBC)
674 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
675 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
677 pm_runtime_mark_last_busy(port->dev);
678 pm_runtime_put_autosuspend(port->dev);
679 free_irq(port->irq, port);
680 dev_pm_clear_wake_irq(port->dev);
683 static void omap_8250_throttle(struct uart_port *port)
686 struct uart_8250_port *up =
687 container_of(port, struct uart_8250_port, port);
689 pm_runtime_get_sync(port->dev);
691 spin_lock_irqsave(&port->lock, flags);
692 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
693 serial_out(up, UART_IER, up->ier);
694 spin_unlock_irqrestore(&port->lock, flags);
696 pm_runtime_mark_last_busy(port->dev);
697 pm_runtime_put_autosuspend(port->dev);
700 static void omap_8250_unthrottle(struct uart_port *port)
703 struct uart_8250_port *up =
704 container_of(port, struct uart_8250_port, port);
706 pm_runtime_get_sync(port->dev);
708 spin_lock_irqsave(&port->lock, flags);
709 up->ier |= UART_IER_RLSI | UART_IER_RDI;
710 serial_out(up, UART_IER, up->ier);
711 spin_unlock_irqrestore(&port->lock, flags);
713 pm_runtime_mark_last_busy(port->dev);
714 pm_runtime_put_autosuspend(port->dev);
717 #ifdef CONFIG_SERIAL_8250_DMA
718 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir);
720 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error)
722 struct omap8250_priv *priv = p->port.private_data;
723 struct uart_8250_dma *dma = p->dma;
724 struct tty_port *tty_port = &p->port.state->port;
725 struct dma_tx_state state;
729 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,
730 dma->rx_size, DMA_FROM_DEVICE);
732 spin_lock_irqsave(&priv->rx_dma_lock, flags);
734 if (!dma->rx_running)
738 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
739 dmaengine_terminate_all(dma->rxchan);
741 count = dma->rx_size - state.residue;
743 tty_insert_flip_string(tty_port, dma->rx_buf, count);
744 p->port.icount.rx += count;
746 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
749 omap_8250_rx_dma(p, 0);
751 tty_flip_buffer_push(tty_port);
754 static void __dma_rx_complete(void *param)
756 __dma_rx_do_complete(param, false);
759 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
761 struct omap8250_priv *priv = p->port.private_data;
762 struct uart_8250_dma *dma = p->dma;
765 spin_lock_irqsave(&priv->rx_dma_lock, flags);
767 if (!dma->rx_running) {
768 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
772 dmaengine_pause(dma->rxchan);
774 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
776 __dma_rx_do_complete(p, true);
779 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
781 struct omap8250_priv *priv = p->port.private_data;
782 struct uart_8250_dma *dma = p->dma;
784 struct dma_async_tx_descriptor *desc;
787 switch (iir & 0x3f) {
789 /* 8250_core handles errors and break interrupts */
790 omap_8250_rx_dma_flush(p);
792 case UART_IIR_RX_TIMEOUT:
794 * If RCVR FIFO trigger level was not reached, complete the
795 * transfer and let 8250_core copy the remaining data.
797 omap_8250_rx_dma_flush(p);
801 * The OMAP UART is a special BEAST. If we receive RDI we _have_
802 * a DMA transfer programmed but it didn't work. One reason is
803 * that we were too slow and there were too many bytes in the
804 * FIFO, the UART counted wrong and never kicked the DMA engine
805 * to do anything. That means once we receive RDI on OMAP then
806 * the DMA won't do anything soon so we have to cancel the DMA
807 * transfer and purge the FIFO manually.
809 omap_8250_rx_dma_flush(p);
816 spin_lock_irqsave(&priv->rx_dma_lock, flags);
821 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
822 dma->rx_size, DMA_DEV_TO_MEM,
823 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
830 desc->callback = __dma_rx_complete;
831 desc->callback_param = p;
833 dma->rx_cookie = dmaengine_submit(desc);
835 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
836 dma->rx_size, DMA_FROM_DEVICE);
838 dma_async_issue_pending(dma->rxchan);
840 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
844 static int omap_8250_tx_dma(struct uart_8250_port *p);
846 static void omap_8250_dma_tx_complete(void *param)
848 struct uart_8250_port *p = param;
849 struct uart_8250_dma *dma = p->dma;
850 struct circ_buf *xmit = &p->port.state->xmit;
852 bool en_thri = false;
853 struct omap8250_priv *priv = p->port.private_data;
855 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
856 UART_XMIT_SIZE, DMA_TO_DEVICE);
858 spin_lock_irqsave(&p->port.lock, flags);
862 xmit->tail += dma->tx_size;
863 xmit->tail &= UART_XMIT_SIZE - 1;
864 p->port.icount.tx += dma->tx_size;
866 if (priv->delayed_restore) {
867 priv->delayed_restore = 0;
868 omap8250_restore_regs(p);
871 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
872 uart_write_wakeup(&p->port);
874 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
877 ret = omap_8250_tx_dma(p);
881 } else if (p->capabilities & UART_CAP_RPM) {
887 p->ier |= UART_IER_THRI;
888 serial_port_out(&p->port, UART_IER, p->ier);
891 spin_unlock_irqrestore(&p->port.lock, flags);
894 static int omap_8250_tx_dma(struct uart_8250_port *p)
896 struct uart_8250_dma *dma = p->dma;
897 struct omap8250_priv *priv = p->port.private_data;
898 struct circ_buf *xmit = &p->port.state->xmit;
899 struct dma_async_tx_descriptor *desc;
900 unsigned int skip_byte = 0;
905 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
908 * Even if no data, we need to return an error for the two cases
909 * below so serial8250_tx_chars() is invoked and properly clears
910 * THRI and/or runtime suspend.
912 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
916 if (p->ier & UART_IER_THRI) {
917 p->ier &= ~UART_IER_THRI;
918 serial_out(p, UART_IER, p->ier);
923 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
924 if (priv->habit & OMAP_DMA_TX_KICK) {
928 * We need to put the first byte into the FIFO in order to start
929 * the DMA transfer. For transfers smaller than four bytes we
930 * don't bother doing DMA at all. It seem not matter if there
931 * are still bytes in the FIFO from the last transfer (in case
932 * we got here directly from omap_8250_dma_tx_complete()). Bytes
933 * leaving the FIFO seem not to trigger the DMA transfer. It is
934 * really the byte that we put into the FIFO.
935 * If the FIFO is already full then we most likely got here from
936 * omap_8250_dma_tx_complete(). And this means the DMA engine
937 * just completed its work. We don't have to wait the complete
938 * 86us at 115200,8n1 but around 60us (not to mention lower
939 * baudrates). So in that case we take the interrupt and try
940 * again with an empty FIFO.
942 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
943 if (tx_lvl == p->tx_loadsz) {
947 if (dma->tx_size < 4) {
954 desc = dmaengine_prep_slave_single(dma->txchan,
955 dma->tx_addr + xmit->tail + skip_byte,
956 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
957 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
965 desc->callback = omap_8250_dma_tx_complete;
966 desc->callback_param = p;
968 dma->tx_cookie = dmaengine_submit(desc);
970 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
971 UART_XMIT_SIZE, DMA_TO_DEVICE);
973 dma_async_issue_pending(dma->txchan);
977 if (p->ier & UART_IER_THRI) {
978 p->ier &= ~UART_IER_THRI;
979 serial_out(p, UART_IER, p->ier);
982 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
990 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
991 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
992 * use the default routine in the non-DMA case and this one for with DMA.
994 static int omap_8250_dma_handle_irq(struct uart_port *port)
996 struct uart_8250_port *up = up_to_u8250p(port);
997 unsigned char status;
1002 serial8250_rpm_get(up);
1004 iir = serial_port_in(port, UART_IIR);
1005 if (iir & UART_IIR_NO_INT) {
1006 serial8250_rpm_put(up);
1010 spin_lock_irqsave(&port->lock, flags);
1012 status = serial_port_in(port, UART_LSR);
1014 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1016 dma_err = omap_8250_rx_dma(up, iir);
1018 status = serial8250_rx_chars(up, status);
1019 omap_8250_rx_dma(up, 0);
1022 serial8250_modem_status(up);
1023 if (status & UART_LSR_THRE && up->dma->tx_err) {
1024 if (uart_tx_stopped(&up->port) ||
1025 uart_circ_empty(&up->port.state->xmit)) {
1026 up->dma->tx_err = 0;
1027 serial8250_tx_chars(up);
1030 * try again due to an earlier failer which
1031 * might have been resolved by now.
1033 dma_err = omap_8250_tx_dma(up);
1035 serial8250_tx_chars(up);
1039 spin_unlock_irqrestore(&port->lock, flags);
1040 serial8250_rpm_put(up);
1044 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1051 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
1057 static int omap8250_no_handle_irq(struct uart_port *port)
1059 /* IRQ has not been requested but handling irq? */
1060 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1064 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1065 static const u8 am4372_habit = UART_ERRATA_CLOCK_DISABLE;
1067 static const struct of_device_id omap8250_dt_ids[] = {
1068 { .compatible = "ti,omap2-uart" },
1069 { .compatible = "ti,omap3-uart" },
1070 { .compatible = "ti,omap4-uart" },
1071 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1072 { .compatible = "ti,am4372-uart", .data = &am4372_habit, },
1073 { .compatible = "ti,dra742-uart", .data = &am4372_habit, },
1076 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1078 static int omap8250_probe(struct platform_device *pdev)
1080 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1081 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1082 struct omap8250_priv *priv;
1083 struct uart_8250_port up;
1085 void __iomem *membase;
1087 if (!regs || !irq) {
1088 dev_err(&pdev->dev, "missing registers or irq\n");
1092 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1096 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1097 resource_size(regs));
1101 memset(&up, 0, sizeof(up));
1102 up.port.dev = &pdev->dev;
1103 up.port.mapbase = regs->start;
1104 up.port.membase = membase;
1105 up.port.irq = irq->start;
1107 * It claims to be 16C750 compatible however it is a little different.
1108 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1109 * have) is enabled via EFR instead of MCR. The type is set here 8250
1110 * just to get things going. UNKNOWN does not work for a few reasons and
1111 * we don't need our own type since we don't use 8250's set_termios()
1114 up.port.type = PORT_8250;
1115 up.port.iotype = UPIO_MEM;
1116 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1118 up.port.private_data = priv;
1120 up.port.regshift = 2;
1121 up.port.fifosize = 64;
1123 up.capabilities = UART_CAP_FIFO;
1126 * Runtime PM is mostly transparent. However to do it right we need to a
1127 * TX empty interrupt before we can put the device to auto idle. So if
1128 * PM is not enabled we don't add that flag and can spare that one extra
1129 * interrupt in the TX path.
1131 up.capabilities |= UART_CAP_RPM;
1133 up.port.set_termios = omap_8250_set_termios;
1134 up.port.set_mctrl = omap8250_set_mctrl;
1135 up.port.pm = omap_8250_pm;
1136 up.port.startup = omap_8250_startup;
1137 up.port.shutdown = omap_8250_shutdown;
1138 up.port.throttle = omap_8250_throttle;
1139 up.port.unthrottle = omap_8250_unthrottle;
1141 if (pdev->dev.of_node) {
1142 const struct of_device_id *id;
1144 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1146 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1148 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1150 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1152 priv->habit |= *(u8 *)id->data;
1157 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1162 if (!up.port.uartclk) {
1163 up.port.uartclk = DEFAULT_CLK_SPEED;
1164 dev_warn(&pdev->dev,
1165 "No clock speed specified: using default: %d\n",
1169 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1170 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1171 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1173 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1175 spin_lock_init(&priv->rx_dma_lock);
1177 device_init_wakeup(&pdev->dev, true);
1178 pm_runtime_use_autosuspend(&pdev->dev);
1179 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1181 pm_runtime_irq_safe(&pdev->dev);
1182 pm_runtime_enable(&pdev->dev);
1184 pm_runtime_get_sync(&pdev->dev);
1186 omap_serial_fill_features_erratas(&up, priv);
1187 up.port.handle_irq = omap8250_no_handle_irq;
1188 #ifdef CONFIG_SERIAL_8250_DMA
1189 if (pdev->dev.of_node) {
1191 * Oh DMA support. If there are no DMA properties in the DT then
1192 * we will fall back to a generic DMA channel which does not
1193 * really work here. To ensure that we do not get a generic DMA
1194 * channel assigned, we have the the_no_dma_filter_fn() here.
1195 * To avoid "failed to request DMA" messages we check for DMA
1198 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1200 up.dma = &priv->omap8250_dma;
1201 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1202 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1203 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1204 priv->omap8250_dma.rx_size = RX_TRIGGER;
1205 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1206 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1208 if (of_machine_is_compatible("ti,am33xx"))
1209 priv->habit |= OMAP_DMA_TX_KICK;
1213 ret = serial8250_register_8250_port(&up);
1215 dev_err(&pdev->dev, "unable to register 8250 port\n");
1219 platform_set_drvdata(pdev, priv);
1220 pm_runtime_mark_last_busy(&pdev->dev);
1221 pm_runtime_put_autosuspend(&pdev->dev);
1224 pm_runtime_put(&pdev->dev);
1225 pm_runtime_disable(&pdev->dev);
1229 static int omap8250_remove(struct platform_device *pdev)
1231 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1233 pm_runtime_put_sync(&pdev->dev);
1234 pm_runtime_disable(&pdev->dev);
1235 serial8250_unregister_port(priv->line);
1236 pm_qos_remove_request(&priv->pm_qos_request);
1237 device_init_wakeup(&pdev->dev, false);
1241 #ifdef CONFIG_PM_SLEEP
1242 static int omap8250_prepare(struct device *dev)
1244 struct omap8250_priv *priv = dev_get_drvdata(dev);
1248 priv->is_suspending = true;
1252 static void omap8250_complete(struct device *dev)
1254 struct omap8250_priv *priv = dev_get_drvdata(dev);
1258 priv->is_suspending = false;
1261 static int omap8250_suspend(struct device *dev)
1263 struct omap8250_priv *priv = dev_get_drvdata(dev);
1265 serial8250_suspend_port(priv->line);
1266 flush_work(&priv->qos_work);
1270 static int omap8250_resume(struct device *dev)
1272 struct omap8250_priv *priv = dev_get_drvdata(dev);
1274 serial8250_resume_port(priv->line);
1278 #define omap8250_prepare NULL
1279 #define omap8250_complete NULL
1283 static int omap8250_lost_context(struct uart_8250_port *up)
1287 val = serial_in(up, UART_OMAP_SCR);
1289 * If we lose context, then SCR is set to its reset value of zero.
1290 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1291 * among other bits, to never set the register back to zero again.
1298 /* TODO: in future, this should happen via API in drivers/reset/ */
1299 static int omap8250_soft_reset(struct device *dev)
1301 struct omap8250_priv *priv = dev_get_drvdata(dev);
1302 struct uart_8250_port *up = serial8250_get_port(priv->line);
1307 sysc = serial_in(up, UART_OMAP_SYSC);
1309 /* softreset the UART */
1310 sysc |= OMAP_UART_SYSC_SOFTRESET;
1311 serial_out(up, UART_OMAP_SYSC, sysc);
1313 /* By experiments, 1us enough for reset complete on AM335x */
1316 syss = serial_in(up, UART_OMAP_SYSS);
1317 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1320 dev_err(dev, "timed out waiting for reset done\n");
1327 static int omap8250_runtime_suspend(struct device *dev)
1329 struct omap8250_priv *priv = dev_get_drvdata(dev);
1330 struct uart_8250_port *up;
1332 up = serial8250_get_port(priv->line);
1334 * When using 'no_console_suspend', the console UART must not be
1335 * suspended. Since driver suspend is managed by runtime suspend,
1336 * preventing runtime suspend (by returning error) will keep device
1337 * active during suspend.
1339 if (priv->is_suspending && !console_suspend_enabled) {
1340 if (uart_console(&up->port))
1344 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1347 ret = omap8250_soft_reset(dev);
1351 /* Restore to UART mode after reset (for wakeup) */
1352 omap8250_update_mdr1(up, priv);
1355 if (up->dma && up->dma->rxchan)
1356 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT);
1358 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1359 schedule_work(&priv->qos_work);
1364 static int omap8250_runtime_resume(struct device *dev)
1366 struct omap8250_priv *priv = dev_get_drvdata(dev);
1367 struct uart_8250_port *up;
1370 /* In case runtime-pm tries this before we are setup */
1374 up = serial8250_get_port(priv->line);
1375 loss_cntx = omap8250_lost_context(up);
1378 omap8250_restore_regs(up);
1380 if (up->dma && up->dma->rxchan)
1381 omap_8250_rx_dma(up, 0);
1383 priv->latency = priv->calc_latency;
1384 schedule_work(&priv->qos_work);
1389 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1390 static int __init omap8250_console_fixup(void)
1396 if (strstr(boot_command_line, "console=ttyS"))
1397 /* user set a ttyS based name for the console */
1400 omap_str = strstr(boot_command_line, "console=ttyO");
1402 /* user did not set ttyO based console, so we don't care */
1406 if ('0' <= *omap_str && *omap_str <= '9')
1407 idx = *omap_str - '0';
1412 if (omap_str[0] == ',') {
1419 add_preferred_console("ttyS", idx, options);
1420 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1422 pr_err("This ensures that you still see kernel messages. Please\n");
1423 pr_err("update your kernel commandline.\n");
1426 console_initcall(omap8250_console_fixup);
1429 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1430 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1431 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1432 omap8250_runtime_resume, NULL)
1433 .prepare = omap8250_prepare,
1434 .complete = omap8250_complete,
1437 static struct platform_driver omap8250_platform_driver = {
1440 .pm = &omap8250_dev_pm_ops,
1441 .of_match_table = omap8250_dt_ids,
1443 .probe = omap8250_probe,
1444 .remove = omap8250_remove,
1446 module_platform_driver(omap8250_platform_driver);
1448 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1449 MODULE_DESCRIPTION("OMAP 8250 Driver");
1450 MODULE_LICENSE("GPL v2");