2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/timer.h>
51 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
53 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
56 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
59 * Here we define the default xmit fifo size used for each type of UART.
61 static const struct serial8250_config uart_config[] = {
86 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
87 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
88 .rxtrig_bytes = {1, 4, 8, 14},
89 .flags = UART_CAP_FIFO,
100 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
106 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
108 .rxtrig_bytes = {8, 16, 24, 28},
109 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
115 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
117 .rxtrig_bytes = {1, 16, 32, 56},
118 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
126 .name = "16C950/954",
129 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
130 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
131 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
137 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
139 .rxtrig_bytes = {8, 16, 56, 60},
140 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
146 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
147 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
153 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
154 .flags = UART_CAP_FIFO,
160 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
161 .flags = UART_CAP_FIFO | UART_NATSEMI,
167 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
168 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
174 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
175 .flags = UART_CAP_FIFO,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
182 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
188 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
189 .flags = UART_CAP_FIFO | UART_CAP_AFE,
195 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
197 .rxtrig_bytes = {1, 4, 8, 14},
198 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
204 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
205 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
212 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
214 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
221 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
222 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
223 .flags = UART_CAP_FIFO,
225 [PORT_BRCM_TRUMANAGE] = {
229 .flags = UART_CAP_HFIFO,
234 [PORT_ALTR_16550_F32] = {
235 .name = "Altera 16550 FIFO32",
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
239 .flags = UART_CAP_FIFO | UART_CAP_AFE,
241 [PORT_ALTR_16550_F64] = {
242 .name = "Altera 16550 FIFO64",
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_AFE,
248 [PORT_ALTR_16550_F128] = {
249 .name = "Altera 16550 FIFO128",
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_AFE,
256 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
257 * workaround of errata A-008006 which states that tx_loadsz should
258 * be configured less than Maximum supported fifo bytes.
260 [PORT_16550A_FSL64] = {
261 .name = "16550A_FSL64",
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
266 .flags = UART_CAP_FIFO,
269 .name = "Palmchip BK-3103",
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .rxtrig_bytes = {1, 4, 8, 14},
274 .flags = UART_CAP_FIFO,
278 /* Uart divisor latch read */
279 static int default_serial_dl_read(struct uart_8250_port *up)
281 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
284 /* Uart divisor latch write */
285 static void default_serial_dl_write(struct uart_8250_port *up, int value)
287 serial_out(up, UART_DLL, value & 0xff);
288 serial_out(up, UART_DLM, value >> 8 & 0xff);
291 #ifdef CONFIG_SERIAL_8250_RT288X
293 /* Au1x00/RT288x UART hardware has a weird register layout */
294 static const s8 au_io_in_map[8] = {
302 -1, /* UART_SCR (unmapped) */
305 static const s8 au_io_out_map[8] = {
311 -1, /* UART_LSR (unmapped) */
312 -1, /* UART_MSR (unmapped) */
313 -1, /* UART_SCR (unmapped) */
316 static unsigned int au_serial_in(struct uart_port *p, int offset)
318 if (offset >= ARRAY_SIZE(au_io_in_map))
320 offset = au_io_in_map[offset];
323 return __raw_readl(p->membase + (offset << p->regshift));
326 static void au_serial_out(struct uart_port *p, int offset, int value)
328 if (offset >= ARRAY_SIZE(au_io_out_map))
330 offset = au_io_out_map[offset];
333 __raw_writel(value, p->membase + (offset << p->regshift));
336 /* Au1x00 haven't got a standard divisor latch */
337 static int au_serial_dl_read(struct uart_8250_port *up)
339 return __raw_readl(up->port.membase + 0x28);
342 static void au_serial_dl_write(struct uart_8250_port *up, int value)
344 __raw_writel(value, up->port.membase + 0x28);
349 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
351 offset = offset << p->regshift;
352 outb(p->hub6 - 1 + offset, p->iobase);
353 return inb(p->iobase + 1);
356 static void hub6_serial_out(struct uart_port *p, int offset, int value)
358 offset = offset << p->regshift;
359 outb(p->hub6 - 1 + offset, p->iobase);
360 outb(value, p->iobase + 1);
363 static unsigned int mem_serial_in(struct uart_port *p, int offset)
365 offset = offset << p->regshift;
366 return readb(p->membase + offset);
369 static void mem_serial_out(struct uart_port *p, int offset, int value)
371 offset = offset << p->regshift;
372 writeb(value, p->membase + offset);
375 static void mem16_serial_out(struct uart_port *p, int offset, int value)
377 offset = offset << p->regshift;
378 writew(value, p->membase + offset);
381 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
383 offset = offset << p->regshift;
384 return readw(p->membase + offset);
387 static void mem32_serial_out(struct uart_port *p, int offset, int value)
389 offset = offset << p->regshift;
390 writel(value, p->membase + offset);
393 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
395 offset = offset << p->regshift;
396 return readl(p->membase + offset);
399 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
401 offset = offset << p->regshift;
402 iowrite32be(value, p->membase + offset);
405 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
407 offset = offset << p->regshift;
408 return ioread32be(p->membase + offset);
411 static unsigned int io_serial_in(struct uart_port *p, int offset)
413 offset = offset << p->regshift;
414 return inb(p->iobase + offset);
417 static void io_serial_out(struct uart_port *p, int offset, int value)
419 offset = offset << p->regshift;
420 outb(value, p->iobase + offset);
423 static int serial8250_default_handle_irq(struct uart_port *port);
424 static int exar_handle_irq(struct uart_port *port);
426 static void set_io_from_upio(struct uart_port *p)
428 struct uart_8250_port *up = up_to_u8250p(p);
430 up->dl_read = default_serial_dl_read;
431 up->dl_write = default_serial_dl_write;
435 p->serial_in = hub6_serial_in;
436 p->serial_out = hub6_serial_out;
440 p->serial_in = mem_serial_in;
441 p->serial_out = mem_serial_out;
445 p->serial_in = mem16_serial_in;
446 p->serial_out = mem16_serial_out;
450 p->serial_in = mem32_serial_in;
451 p->serial_out = mem32_serial_out;
455 p->serial_in = mem32be_serial_in;
456 p->serial_out = mem32be_serial_out;
459 #ifdef CONFIG_SERIAL_8250_RT288X
461 p->serial_in = au_serial_in;
462 p->serial_out = au_serial_out;
463 up->dl_read = au_serial_dl_read;
464 up->dl_write = au_serial_dl_write;
469 p->serial_in = io_serial_in;
470 p->serial_out = io_serial_out;
473 /* Remember loaded iotype */
474 up->cur_iotype = p->iotype;
475 p->handle_irq = serial8250_default_handle_irq;
479 serial_port_out_sync(struct uart_port *p, int offset, int value)
487 p->serial_out(p, offset, value);
488 p->serial_in(p, UART_LCR); /* safe, no side-effects */
491 p->serial_out(p, offset, value);
498 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
500 serial_out(up, UART_SCR, offset);
501 serial_out(up, UART_ICR, value);
504 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
508 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
509 serial_out(up, UART_SCR, offset);
510 value = serial_in(up, UART_ICR);
511 serial_icr_write(up, UART_ACR, up->acr);
519 static void serial8250_clear_fifos(struct uart_8250_port *p)
521 if (p->capabilities & UART_CAP_FIFO) {
522 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
523 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
524 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
525 serial_out(p, UART_FCR, 0);
529 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
531 unsigned char mcr = serial8250_in_MCR(p);
533 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
536 mcr &= ~UART_MCR_RTS;
537 serial8250_out_MCR(p, mcr);
540 static void serial8250_em485_handle_start_tx(unsigned long arg);
541 static void serial8250_em485_handle_stop_tx(unsigned long arg);
543 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
545 serial8250_clear_fifos(p);
546 serial_out(p, UART_FCR, p->fcr);
548 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
550 void serial8250_rpm_get(struct uart_8250_port *p)
552 if (!(p->capabilities & UART_CAP_RPM))
554 pm_runtime_get_sync(p->port.dev);
556 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
558 void serial8250_rpm_put(struct uart_8250_port *p)
560 if (!(p->capabilities & UART_CAP_RPM))
562 pm_runtime_mark_last_busy(p->port.dev);
563 pm_runtime_put_autosuspend(p->port.dev);
565 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
568 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
569 * @p: uart_8250_port port instance
571 * The function is used to start rs485 software emulating on the
572 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
573 * transmission. The function is idempotent, so it is safe to call it
576 * The caller MUST enable interrupt on empty shift register before
577 * calling serial8250_em485_init(). This interrupt is not a part of
578 * 8250 standard, but implementation defined.
580 * The function is supposed to be called from .rs485_config callback
581 * or from any other callback protected with p->port.lock spinlock.
583 * See also serial8250_em485_destroy()
585 * Return 0 - success, -errno - otherwise
587 int serial8250_em485_init(struct uart_8250_port *p)
592 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
596 setup_timer(&p->em485->stop_tx_timer,
597 serial8250_em485_handle_stop_tx, (unsigned long)p);
598 setup_timer(&p->em485->start_tx_timer,
599 serial8250_em485_handle_start_tx, (unsigned long)p);
600 p->em485->active_timer = NULL;
602 serial8250_em485_rts_after_send(p);
606 EXPORT_SYMBOL_GPL(serial8250_em485_init);
609 * serial8250_em485_destroy() - put uart_8250_port into normal state
610 * @p: uart_8250_port port instance
612 * The function is used to stop rs485 software emulating on the
613 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
614 * call it multiple times.
616 * The function is supposed to be called from .rs485_config callback
617 * or from any other callback protected with p->port.lock spinlock.
619 * See also serial8250_em485_init()
621 void serial8250_em485_destroy(struct uart_8250_port *p)
626 del_timer(&p->em485->start_tx_timer);
627 del_timer(&p->em485->stop_tx_timer);
632 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
635 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
636 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
637 * empty and the HW can idle again.
639 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
641 unsigned char rpm_active;
643 if (!(p->capabilities & UART_CAP_RPM))
646 rpm_active = xchg(&p->rpm_tx_active, 1);
649 pm_runtime_get_sync(p->port.dev);
652 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
654 unsigned char rpm_active;
656 if (!(p->capabilities & UART_CAP_RPM))
659 rpm_active = xchg(&p->rpm_tx_active, 0);
662 pm_runtime_mark_last_busy(p->port.dev);
663 pm_runtime_put_autosuspend(p->port.dev);
667 * IER sleep support. UARTs which have EFRs need the "extended
668 * capability" bit enabled. Note that on XR16C850s, we need to
669 * reset LCR to write to IER.
671 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
673 unsigned char lcr = 0, efr = 0;
675 * Exar UARTs have a SLEEP register that enables or disables
676 * each UART to enter sleep mode separately. On the XR17V35x the
677 * register is accessible to each UART at the UART_EXAR_SLEEP
678 * offset but the UART channel may only write to the corresponding
681 serial8250_rpm_get(p);
682 if ((p->port.type == PORT_XR17V35X) ||
683 (p->port.type == PORT_XR17D15X)) {
684 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
688 if (p->capabilities & UART_CAP_SLEEP) {
689 if (p->capabilities & UART_CAP_EFR) {
690 lcr = serial_in(p, UART_LCR);
691 efr = serial_in(p, UART_EFR);
692 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
693 serial_out(p, UART_EFR, UART_EFR_ECB);
694 serial_out(p, UART_LCR, 0);
696 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
697 if (p->capabilities & UART_CAP_EFR) {
698 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
699 serial_out(p, UART_EFR, efr);
700 serial_out(p, UART_LCR, lcr);
704 serial8250_rpm_put(p);
707 #ifdef CONFIG_SERIAL_8250_RSA
709 * Attempts to turn on the RSA FIFO. Returns zero on failure.
710 * We set the port uart clock rate if we succeed.
712 static int __enable_rsa(struct uart_8250_port *up)
717 mode = serial_in(up, UART_RSA_MSR);
718 result = mode & UART_RSA_MSR_FIFO;
721 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
722 mode = serial_in(up, UART_RSA_MSR);
723 result = mode & UART_RSA_MSR_FIFO;
727 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
732 static void enable_rsa(struct uart_8250_port *up)
734 if (up->port.type == PORT_RSA) {
735 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
736 spin_lock_irq(&up->port.lock);
738 spin_unlock_irq(&up->port.lock);
740 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
741 serial_out(up, UART_RSA_FRR, 0);
746 * Attempts to turn off the RSA FIFO. Returns zero on failure.
747 * It is unknown why interrupts were disabled in here. However,
748 * the caller is expected to preserve this behaviour by grabbing
749 * the spinlock before calling this function.
751 static void disable_rsa(struct uart_8250_port *up)
756 if (up->port.type == PORT_RSA &&
757 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
758 spin_lock_irq(&up->port.lock);
760 mode = serial_in(up, UART_RSA_MSR);
761 result = !(mode & UART_RSA_MSR_FIFO);
764 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
765 mode = serial_in(up, UART_RSA_MSR);
766 result = !(mode & UART_RSA_MSR_FIFO);
770 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
771 spin_unlock_irq(&up->port.lock);
774 #endif /* CONFIG_SERIAL_8250_RSA */
777 * This is a quickie test to see how big the FIFO is.
778 * It doesn't work at all the time, more's the pity.
780 static int size_fifo(struct uart_8250_port *up)
782 unsigned char old_fcr, old_mcr, old_lcr;
783 unsigned short old_dl;
786 old_lcr = serial_in(up, UART_LCR);
787 serial_out(up, UART_LCR, 0);
788 old_fcr = serial_in(up, UART_FCR);
789 old_mcr = serial8250_in_MCR(up);
790 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
791 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
792 serial8250_out_MCR(up, UART_MCR_LOOP);
793 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
794 old_dl = serial_dl_read(up);
795 serial_dl_write(up, 0x0001);
796 serial_out(up, UART_LCR, 0x03);
797 for (count = 0; count < 256; count++)
798 serial_out(up, UART_TX, count);
799 mdelay(20);/* FIXME - schedule_timeout */
800 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
801 (count < 256); count++)
802 serial_in(up, UART_RX);
803 serial_out(up, UART_FCR, old_fcr);
804 serial8250_out_MCR(up, old_mcr);
805 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
806 serial_dl_write(up, old_dl);
807 serial_out(up, UART_LCR, old_lcr);
813 * Read UART ID using the divisor method - set DLL and DLM to zero
814 * and the revision will be in DLL and device type in DLM. We
815 * preserve the device state across this.
817 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
819 unsigned char old_lcr;
820 unsigned int id, old_dl;
822 old_lcr = serial_in(p, UART_LCR);
823 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
824 old_dl = serial_dl_read(p);
825 serial_dl_write(p, 0);
826 id = serial_dl_read(p);
827 serial_dl_write(p, old_dl);
829 serial_out(p, UART_LCR, old_lcr);
835 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
836 * When this function is called we know it is at least a StarTech
837 * 16650 V2, but it might be one of several StarTech UARTs, or one of
838 * its clones. (We treat the broken original StarTech 16650 V1 as a
839 * 16550, and why not? Startech doesn't seem to even acknowledge its
842 * What evil have men's minds wrought...
844 static void autoconfig_has_efr(struct uart_8250_port *up)
846 unsigned int id1, id2, id3, rev;
849 * Everything with an EFR has SLEEP
851 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
854 * First we check to see if it's an Oxford Semiconductor UART.
856 * If we have to do this here because some non-National
857 * Semiconductor clone chips lock up if you try writing to the
858 * LSR register (which serial_icr_read does)
862 * Check for Oxford Semiconductor 16C950.
864 * EFR [4] must be set else this test fails.
866 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
867 * claims that it's needed for 952 dual UART's (which are not
868 * recommended for new designs).
871 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
872 serial_out(up, UART_EFR, UART_EFR_ECB);
873 serial_out(up, UART_LCR, 0x00);
874 id1 = serial_icr_read(up, UART_ID1);
875 id2 = serial_icr_read(up, UART_ID2);
876 id3 = serial_icr_read(up, UART_ID3);
877 rev = serial_icr_read(up, UART_REV);
879 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
881 if (id1 == 0x16 && id2 == 0xC9 &&
882 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
883 up->port.type = PORT_16C950;
886 * Enable work around for the Oxford Semiconductor 952 rev B
887 * chip which causes it to seriously miscalculate baud rates
890 if (id3 == 0x52 && rev == 0x01)
891 up->bugs |= UART_BUG_QUOT;
896 * We check for a XR16C850 by setting DLL and DLM to 0, and then
897 * reading back DLL and DLM. The chip type depends on the DLM
899 * 0x10 - XR16C850 and the DLL contains the chip revision.
903 id1 = autoconfig_read_divisor_id(up);
904 DEBUG_AUTOCONF("850id=%04x ", id1);
907 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
908 up->port.type = PORT_16850;
913 * It wasn't an XR16C850.
915 * We distinguish between the '654 and the '650 by counting
916 * how many bytes are in the FIFO. I'm using this for now,
917 * since that's the technique that was sent to me in the
918 * serial driver update, but I'm not convinced this works.
919 * I've had problems doing this in the past. -TYT
921 if (size_fifo(up) == 64)
922 up->port.type = PORT_16654;
924 up->port.type = PORT_16650V2;
928 * We detected a chip without a FIFO. Only two fall into
929 * this category - the original 8250 and the 16450. The
930 * 16450 has a scratch register (accessible with LCR=0)
932 static void autoconfig_8250(struct uart_8250_port *up)
934 unsigned char scratch, status1, status2;
936 up->port.type = PORT_8250;
938 scratch = serial_in(up, UART_SCR);
939 serial_out(up, UART_SCR, 0xa5);
940 status1 = serial_in(up, UART_SCR);
941 serial_out(up, UART_SCR, 0x5a);
942 status2 = serial_in(up, UART_SCR);
943 serial_out(up, UART_SCR, scratch);
945 if (status1 == 0xa5 && status2 == 0x5a)
946 up->port.type = PORT_16450;
949 static int broken_efr(struct uart_8250_port *up)
952 * Exar ST16C2550 "A2" devices incorrectly detect as
953 * having an EFR, and report an ID of 0x0201. See
954 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
956 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
963 * We know that the chip has FIFOs. Does it have an EFR? The
964 * EFR is located in the same register position as the IIR and
965 * we know the top two bits of the IIR are currently set. The
966 * EFR should contain zero. Try to read the EFR.
968 static void autoconfig_16550a(struct uart_8250_port *up)
970 unsigned char status1, status2;
971 unsigned int iersave;
973 up->port.type = PORT_16550A;
974 up->capabilities |= UART_CAP_FIFO;
977 * XR17V35x UARTs have an extra divisor register, DLD
978 * that gets enabled with when DLAB is set which will
979 * cause the device to incorrectly match and assign
980 * port type to PORT_16650. The EFR for this UART is
981 * found at offset 0x09. Instead check the Deice ID (DVID)
982 * register for a 2, 4 or 8 port UART.
984 if (up->port.flags & UPF_EXAR_EFR) {
985 status1 = serial_in(up, UART_EXAR_DVID);
986 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
987 DEBUG_AUTOCONF("Exar XR17V35x ");
988 up->port.type = PORT_XR17V35X;
989 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
998 * Check for presence of the EFR when DLAB is set.
999 * Only ST16C650V1 UARTs pass this test.
1001 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1002 if (serial_in(up, UART_EFR) == 0) {
1003 serial_out(up, UART_EFR, 0xA8);
1004 if (serial_in(up, UART_EFR) != 0) {
1005 DEBUG_AUTOCONF("EFRv1 ");
1006 up->port.type = PORT_16650;
1007 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1009 serial_out(up, UART_LCR, 0);
1010 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1012 status1 = serial_in(up, UART_IIR) >> 5;
1013 serial_out(up, UART_FCR, 0);
1014 serial_out(up, UART_LCR, 0);
1017 up->port.type = PORT_16550A_FSL64;
1019 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1021 serial_out(up, UART_EFR, 0);
1026 * Maybe it requires 0xbf to be written to the LCR.
1027 * (other ST16C650V2 UARTs, TI16C752A, etc)
1029 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1030 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1031 DEBUG_AUTOCONF("EFRv2 ");
1032 autoconfig_has_efr(up);
1037 * Check for a National Semiconductor SuperIO chip.
1038 * Attempt to switch to bank 2, read the value of the LOOP bit
1039 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1040 * switch back to bank 2, read it from EXCR1 again and check
1041 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1043 serial_out(up, UART_LCR, 0);
1044 status1 = serial8250_in_MCR(up);
1045 serial_out(up, UART_LCR, 0xE0);
1046 status2 = serial_in(up, 0x02); /* EXCR1 */
1048 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1049 serial_out(up, UART_LCR, 0);
1050 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1051 serial_out(up, UART_LCR, 0xE0);
1052 status2 = serial_in(up, 0x02); /* EXCR1 */
1053 serial_out(up, UART_LCR, 0);
1054 serial8250_out_MCR(up, status1);
1056 if ((status2 ^ status1) & UART_MCR_LOOP) {
1057 unsigned short quot;
1059 serial_out(up, UART_LCR, 0xE0);
1061 quot = serial_dl_read(up);
1064 if (ns16550a_goto_highspeed(up))
1065 serial_dl_write(up, quot);
1067 serial_out(up, UART_LCR, 0);
1069 up->port.uartclk = 921600*16;
1070 up->port.type = PORT_NS16550A;
1071 up->capabilities |= UART_NATSEMI;
1077 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1078 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1079 * Try setting it with and without DLAB set. Cheap clones
1080 * set bit 5 without DLAB set.
1082 serial_out(up, UART_LCR, 0);
1083 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1084 status1 = serial_in(up, UART_IIR) >> 5;
1085 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1086 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1087 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1088 status2 = serial_in(up, UART_IIR) >> 5;
1089 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1090 serial_out(up, UART_LCR, 0);
1092 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1094 if (status1 == 6 && status2 == 7) {
1095 up->port.type = PORT_16750;
1096 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1101 * Try writing and reading the UART_IER_UUE bit (b6).
1102 * If it works, this is probably one of the Xscale platform's
1104 * We're going to explicitly set the UUE bit to 0 before
1105 * trying to write and read a 1 just to make sure it's not
1106 * already a 1 and maybe locked there before we even start start.
1108 iersave = serial_in(up, UART_IER);
1109 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1110 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1112 * OK it's in a known zero state, try writing and reading
1113 * without disturbing the current state of the other bits.
1115 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1116 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1119 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1121 DEBUG_AUTOCONF("Xscale ");
1122 up->port.type = PORT_XSCALE;
1123 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1128 * If we got here we couldn't force the IER_UUE bit to 0.
1129 * Log it and continue.
1131 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1133 serial_out(up, UART_IER, iersave);
1136 * Exar uarts have EFR in a weird location
1138 if (up->port.flags & UPF_EXAR_EFR) {
1139 DEBUG_AUTOCONF("Exar XR17D15x ");
1140 up->port.type = PORT_XR17D15X;
1141 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1148 * We distinguish between 16550A and U6 16550A by counting
1149 * how many bytes are in the FIFO.
1151 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1152 up->port.type = PORT_U6_16550A;
1153 up->capabilities |= UART_CAP_AFE;
1158 * This routine is called by rs_init() to initialize a specific serial
1159 * port. It determines what type of UART chip this serial port is
1160 * using: 8250, 16450, 16550, 16550A. The important question is
1161 * whether or not this UART is a 16550A or not, since this will
1162 * determine whether or not we can use its FIFO features or not.
1164 static void autoconfig(struct uart_8250_port *up)
1166 unsigned char status1, scratch, scratch2, scratch3;
1167 unsigned char save_lcr, save_mcr;
1168 struct uart_port *port = &up->port;
1169 unsigned long flags;
1170 unsigned int old_capabilities;
1172 if (!port->iobase && !port->mapbase && !port->membase)
1175 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1176 serial_index(port), port->iobase, port->membase);
1179 * We really do need global IRQs disabled here - we're going to
1180 * be frobbing the chips IRQ enable register to see if it exists.
1182 spin_lock_irqsave(&port->lock, flags);
1184 up->capabilities = 0;
1187 if (!(port->flags & UPF_BUGGY_UART)) {
1189 * Do a simple existence test first; if we fail this,
1190 * there's no point trying anything else.
1192 * 0x80 is used as a nonsense port to prevent against
1193 * false positives due to ISA bus float. The
1194 * assumption is that 0x80 is a non-existent port;
1195 * which should be safe since include/asm/io.h also
1196 * makes this assumption.
1198 * Note: this is safe as long as MCR bit 4 is clear
1199 * and the device is in "PC" mode.
1201 scratch = serial_in(up, UART_IER);
1202 serial_out(up, UART_IER, 0);
1207 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1208 * 16C754B) allow only to modify them if an EFR bit is set.
1210 scratch2 = serial_in(up, UART_IER) & 0x0f;
1211 serial_out(up, UART_IER, 0x0F);
1215 scratch3 = serial_in(up, UART_IER) & 0x0f;
1216 serial_out(up, UART_IER, scratch);
1217 if (scratch2 != 0 || scratch3 != 0x0F) {
1219 * We failed; there's nothing here
1221 spin_unlock_irqrestore(&port->lock, flags);
1222 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1223 scratch2, scratch3);
1228 save_mcr = serial8250_in_MCR(up);
1229 save_lcr = serial_in(up, UART_LCR);
1232 * Check to see if a UART is really there. Certain broken
1233 * internal modems based on the Rockwell chipset fail this
1234 * test, because they apparently don't implement the loopback
1235 * test mode. So this test is skipped on the COM 1 through
1236 * COM 4 ports. This *should* be safe, since no board
1237 * manufacturer would be stupid enough to design a board
1238 * that conflicts with COM 1-4 --- we hope!
1240 if (!(port->flags & UPF_SKIP_TEST)) {
1241 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1242 status1 = serial_in(up, UART_MSR) & 0xF0;
1243 serial8250_out_MCR(up, save_mcr);
1244 if (status1 != 0x90) {
1245 spin_unlock_irqrestore(&port->lock, flags);
1246 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1253 * We're pretty sure there's a port here. Lets find out what
1254 * type of port it is. The IIR top two bits allows us to find
1255 * out if it's 8250 or 16450, 16550, 16550A or later. This
1256 * determines what we test for next.
1258 * We also initialise the EFR (if any) to zero for later. The
1259 * EFR occupies the same register location as the FCR and IIR.
1261 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1262 serial_out(up, UART_EFR, 0);
1263 serial_out(up, UART_LCR, 0);
1265 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1266 scratch = serial_in(up, UART_IIR) >> 6;
1270 autoconfig_8250(up);
1273 port->type = PORT_UNKNOWN;
1276 port->type = PORT_16550;
1279 autoconfig_16550a(up);
1283 #ifdef CONFIG_SERIAL_8250_RSA
1285 * Only probe for RSA ports if we got the region.
1287 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1289 port->type = PORT_RSA;
1292 serial_out(up, UART_LCR, save_lcr);
1294 port->fifosize = uart_config[up->port.type].fifo_size;
1295 old_capabilities = up->capabilities;
1296 up->capabilities = uart_config[port->type].flags;
1297 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1299 if (port->type == PORT_UNKNOWN)
1305 #ifdef CONFIG_SERIAL_8250_RSA
1306 if (port->type == PORT_RSA)
1307 serial_out(up, UART_RSA_FRR, 0);
1309 serial8250_out_MCR(up, save_mcr);
1310 serial8250_clear_fifos(up);
1311 serial_in(up, UART_RX);
1312 if (up->capabilities & UART_CAP_UUE)
1313 serial_out(up, UART_IER, UART_IER_UUE);
1315 serial_out(up, UART_IER, 0);
1318 spin_unlock_irqrestore(&port->lock, flags);
1321 * Check if the device is a Fintek F81216A
1323 if (port->type == PORT_16550A)
1324 fintek_8250_probe(up);
1326 if (up->capabilities != old_capabilities) {
1327 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1328 serial_index(port), old_capabilities,
1332 DEBUG_AUTOCONF("iir=%d ", scratch);
1333 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1336 static void autoconfig_irq(struct uart_8250_port *up)
1338 struct uart_port *port = &up->port;
1339 unsigned char save_mcr, save_ier;
1340 unsigned char save_ICP = 0;
1341 unsigned int ICP = 0;
1345 if (port->flags & UPF_FOURPORT) {
1346 ICP = (port->iobase & 0xfe0) | 0x1f;
1347 save_ICP = inb_p(ICP);
1352 if (uart_console(port))
1355 /* forget possible initially masked and pending IRQ */
1356 probe_irq_off(probe_irq_on());
1357 save_mcr = serial8250_in_MCR(up);
1358 save_ier = serial_in(up, UART_IER);
1359 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1361 irqs = probe_irq_on();
1362 serial8250_out_MCR(up, 0);
1364 if (port->flags & UPF_FOURPORT) {
1365 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1367 serial8250_out_MCR(up,
1368 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1370 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1371 serial_in(up, UART_LSR);
1372 serial_in(up, UART_RX);
1373 serial_in(up, UART_IIR);
1374 serial_in(up, UART_MSR);
1375 serial_out(up, UART_TX, 0xFF);
1377 irq = probe_irq_off(irqs);
1379 serial8250_out_MCR(up, save_mcr);
1380 serial_out(up, UART_IER, save_ier);
1382 if (port->flags & UPF_FOURPORT)
1383 outb_p(save_ICP, ICP);
1385 if (uart_console(port))
1388 port->irq = (irq > 0) ? irq : 0;
1391 static void serial8250_stop_rx(struct uart_port *port)
1393 struct uart_8250_port *up = up_to_u8250p(port);
1395 serial8250_rpm_get(up);
1397 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1398 up->port.read_status_mask &= ~UART_LSR_DR;
1399 serial_port_out(port, UART_IER, up->ier);
1401 serial8250_rpm_put(up);
1404 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1406 serial8250_em485_rts_after_send(p);
1409 * Empty the RX FIFO, we are not interested in anything
1410 * received during the half-duplex transmission.
1411 * Enable previously disabled RX interrupts.
1413 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1414 serial8250_clear_fifos(p);
1416 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1417 serial_port_out(&p->port, UART_IER, p->ier);
1421 static void serial8250_em485_handle_stop_tx(unsigned long arg)
1423 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1424 struct uart_8250_em485 *em485 = p->em485;
1425 unsigned long flags;
1427 serial8250_rpm_get(p);
1428 spin_lock_irqsave(&p->port.lock, flags);
1430 em485->active_timer == &em485->stop_tx_timer) {
1431 __do_stop_tx_rs485(p);
1432 em485->active_timer = NULL;
1434 spin_unlock_irqrestore(&p->port.lock, flags);
1435 serial8250_rpm_put(p);
1438 static void __stop_tx_rs485(struct uart_8250_port *p)
1440 struct uart_8250_em485 *em485 = p->em485;
1443 * __do_stop_tx_rs485 is going to set RTS according to config
1444 * AND flush RX FIFO if required.
1446 if (p->port.rs485.delay_rts_after_send > 0) {
1447 em485->active_timer = &em485->stop_tx_timer;
1448 mod_timer(&em485->stop_tx_timer, jiffies +
1449 p->port.rs485.delay_rts_after_send * HZ / 1000);
1451 __do_stop_tx_rs485(p);
1455 static inline void __do_stop_tx(struct uart_8250_port *p)
1457 if (p->ier & UART_IER_THRI) {
1458 p->ier &= ~UART_IER_THRI;
1459 serial_out(p, UART_IER, p->ier);
1460 serial8250_rpm_put_tx(p);
1464 static inline void __stop_tx(struct uart_8250_port *p)
1466 struct uart_8250_em485 *em485 = p->em485;
1469 unsigned char lsr = serial_in(p, UART_LSR);
1471 * To provide required timeing and allow FIFO transfer,
1472 * __stop_tx_rs485() must be called only when both FIFO and
1473 * shift register are empty. It is for device driver to enable
1474 * interrupt on TEMT.
1476 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1479 del_timer(&em485->start_tx_timer);
1480 em485->active_timer = NULL;
1487 static void serial8250_stop_tx(struct uart_port *port)
1489 struct uart_8250_port *up = up_to_u8250p(port);
1491 serial8250_rpm_get(up);
1495 * We really want to stop the transmitter from sending.
1497 if (port->type == PORT_16C950) {
1498 up->acr |= UART_ACR_TXDIS;
1499 serial_icr_write(up, UART_ACR, up->acr);
1501 serial8250_rpm_put(up);
1504 static inline void __start_tx(struct uart_port *port)
1506 struct uart_8250_port *up = up_to_u8250p(port);
1508 if (up->dma && !up->dma->tx_dma(up))
1511 if (!(up->ier & UART_IER_THRI)) {
1512 up->ier |= UART_IER_THRI;
1513 serial_port_out(port, UART_IER, up->ier);
1515 if (up->bugs & UART_BUG_TXEN) {
1518 lsr = serial_in(up, UART_LSR);
1519 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1520 if (lsr & UART_LSR_THRE)
1521 serial8250_tx_chars(up);
1526 * Re-enable the transmitter if we disabled it.
1528 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1529 up->acr &= ~UART_ACR_TXDIS;
1530 serial_icr_write(up, UART_ACR, up->acr);
1534 static inline void start_tx_rs485(struct uart_port *port)
1536 struct uart_8250_port *up = up_to_u8250p(port);
1537 struct uart_8250_em485 *em485 = up->em485;
1540 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1541 serial8250_stop_rx(&up->port);
1543 del_timer(&em485->stop_tx_timer);
1544 em485->active_timer = NULL;
1546 mcr = serial8250_in_MCR(up);
1547 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1548 !!(mcr & UART_MCR_RTS)) {
1549 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1550 mcr |= UART_MCR_RTS;
1552 mcr &= ~UART_MCR_RTS;
1553 serial8250_out_MCR(up, mcr);
1555 if (up->port.rs485.delay_rts_before_send > 0) {
1556 em485->active_timer = &em485->start_tx_timer;
1557 mod_timer(&em485->start_tx_timer, jiffies +
1558 up->port.rs485.delay_rts_before_send * HZ / 1000);
1566 static void serial8250_em485_handle_start_tx(unsigned long arg)
1568 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1569 struct uart_8250_em485 *em485 = p->em485;
1570 unsigned long flags;
1572 spin_lock_irqsave(&p->port.lock, flags);
1574 em485->active_timer == &em485->start_tx_timer) {
1575 __start_tx(&p->port);
1576 em485->active_timer = NULL;
1578 spin_unlock_irqrestore(&p->port.lock, flags);
1581 static void serial8250_start_tx(struct uart_port *port)
1583 struct uart_8250_port *up = up_to_u8250p(port);
1584 struct uart_8250_em485 *em485 = up->em485;
1586 serial8250_rpm_get_tx(up);
1589 em485->active_timer == &em485->start_tx_timer)
1593 start_tx_rs485(port);
1598 static void serial8250_throttle(struct uart_port *port)
1600 port->throttle(port);
1603 static void serial8250_unthrottle(struct uart_port *port)
1605 port->unthrottle(port);
1608 static void serial8250_disable_ms(struct uart_port *port)
1610 struct uart_8250_port *up = up_to_u8250p(port);
1612 /* no MSR capabilities */
1613 if (up->bugs & UART_BUG_NOMSR)
1616 up->ier &= ~UART_IER_MSI;
1617 serial_port_out(port, UART_IER, up->ier);
1620 static void serial8250_enable_ms(struct uart_port *port)
1622 struct uart_8250_port *up = up_to_u8250p(port);
1624 /* no MSR capabilities */
1625 if (up->bugs & UART_BUG_NOMSR)
1628 up->ier |= UART_IER_MSI;
1630 serial8250_rpm_get(up);
1631 serial_port_out(port, UART_IER, up->ier);
1632 serial8250_rpm_put(up);
1635 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1637 struct uart_port *port = &up->port;
1639 char flag = TTY_NORMAL;
1641 if (likely(lsr & UART_LSR_DR))
1642 ch = serial_in(up, UART_RX);
1645 * Intel 82571 has a Serial Over Lan device that will
1646 * set UART_LSR_BI without setting UART_LSR_DR when
1647 * it receives a break. To avoid reading from the
1648 * receive buffer without UART_LSR_DR bit set, we
1649 * just force the read character to be 0
1655 lsr |= up->lsr_saved_flags;
1656 up->lsr_saved_flags = 0;
1658 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1659 if (lsr & UART_LSR_BI) {
1660 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1663 * We do the SysRQ and SAK checking
1664 * here because otherwise the break
1665 * may get masked by ignore_status_mask
1666 * or read_status_mask.
1668 if (uart_handle_break(port))
1670 } else if (lsr & UART_LSR_PE)
1671 port->icount.parity++;
1672 else if (lsr & UART_LSR_FE)
1673 port->icount.frame++;
1674 if (lsr & UART_LSR_OE)
1675 port->icount.overrun++;
1678 * Mask off conditions which should be ignored.
1680 lsr &= port->read_status_mask;
1682 if (lsr & UART_LSR_BI) {
1683 pr_debug("%s: handling break\n", __func__);
1685 } else if (lsr & UART_LSR_PE)
1687 else if (lsr & UART_LSR_FE)
1690 if (uart_handle_sysrq_char(port, ch))
1693 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1697 * serial8250_rx_chars: processes according to the passed in LSR
1698 * value, and returns the remaining LSR bits not handled
1699 * by this Rx routine.
1701 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1703 struct uart_port *port = &up->port;
1704 int max_count = 256;
1707 serial8250_read_char(up, lsr);
1708 if (--max_count == 0)
1710 lsr = serial_in(up, UART_LSR);
1711 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1713 tty_flip_buffer_push(&port->state->port);
1716 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1718 void serial8250_tx_chars(struct uart_8250_port *up)
1720 struct uart_port *port = &up->port;
1721 struct circ_buf *xmit = &port->state->xmit;
1725 serial_out(up, UART_TX, port->x_char);
1730 if (uart_tx_stopped(port)) {
1731 serial8250_stop_tx(port);
1734 if (uart_circ_empty(xmit)) {
1739 count = up->tx_loadsz;
1741 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1742 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1744 if (uart_circ_empty(xmit))
1746 if ((up->capabilities & UART_CAP_HFIFO) &&
1747 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1749 } while (--count > 0);
1751 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1752 uart_write_wakeup(port);
1754 pr_debug("%s: THRE\n", __func__);
1757 * With RPM enabled, we have to wait until the FIFO is empty before the
1758 * HW can go idle. So we get here once again with empty FIFO and disable
1759 * the interrupt and RPM in __stop_tx()
1761 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1764 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1766 /* Caller holds uart port lock */
1767 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1769 struct uart_port *port = &up->port;
1770 unsigned int status = serial_in(up, UART_MSR);
1772 status |= up->msr_saved_flags;
1773 up->msr_saved_flags = 0;
1774 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1775 port->state != NULL) {
1776 if (status & UART_MSR_TERI)
1778 if (status & UART_MSR_DDSR)
1780 if (status & UART_MSR_DDCD)
1781 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1782 if (status & UART_MSR_DCTS)
1783 uart_handle_cts_change(port, status & UART_MSR_CTS);
1785 wake_up_interruptible(&port->state->port.delta_msr_wait);
1790 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1792 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1794 switch (iir & 0x3f) {
1795 case UART_IIR_RX_TIMEOUT:
1796 serial8250_rx_dma_flush(up);
1801 return up->dma->rx_dma(up);
1805 * This handles the interrupt from one port.
1807 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1809 unsigned char status;
1810 unsigned long flags;
1811 struct uart_8250_port *up = up_to_u8250p(port);
1813 if (iir & UART_IIR_NO_INT)
1816 spin_lock_irqsave(&port->lock, flags);
1818 status = serial_port_in(port, UART_LSR);
1820 pr_debug("%s: status = %x\n", __func__, status);
1822 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1823 if (!up->dma || handle_rx_dma(up, iir))
1824 status = serial8250_rx_chars(up, status);
1826 serial8250_modem_status(up);
1827 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE))
1828 serial8250_tx_chars(up);
1830 spin_unlock_irqrestore(&port->lock, flags);
1833 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1835 static int serial8250_default_handle_irq(struct uart_port *port)
1837 struct uart_8250_port *up = up_to_u8250p(port);
1841 serial8250_rpm_get(up);
1843 iir = serial_port_in(port, UART_IIR);
1844 ret = serial8250_handle_irq(port, iir);
1846 serial8250_rpm_put(up);
1851 * These Exar UARTs have an extra interrupt indicator that could
1852 * fire for a few unimplemented interrupts. One of which is a
1853 * wakeup event when coming out of sleep. Put this here just
1854 * to be on the safe side that these interrupts don't go unhandled.
1856 static int exar_handle_irq(struct uart_port *port)
1858 unsigned int iir = serial_port_in(port, UART_IIR);
1861 ret = serial8250_handle_irq(port, iir);
1863 if ((port->type == PORT_XR17V35X) ||
1864 (port->type == PORT_XR17D15X)) {
1865 serial_port_in(port, 0x80);
1866 serial_port_in(port, 0x81);
1867 serial_port_in(port, 0x82);
1868 serial_port_in(port, 0x83);
1875 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1876 * have a programmable TX threshold that triggers the THRE interrupt in
1877 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1878 * has space available. Load it up with tx_loadsz bytes.
1880 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1882 unsigned long flags;
1883 unsigned int iir = serial_port_in(port, UART_IIR);
1885 /* TX Threshold IRQ triggered so load up FIFO */
1886 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1887 struct uart_8250_port *up = up_to_u8250p(port);
1889 spin_lock_irqsave(&port->lock, flags);
1890 serial8250_tx_chars(up);
1891 spin_unlock_irqrestore(&port->lock, flags);
1894 iir = serial_port_in(port, UART_IIR);
1895 return serial8250_handle_irq(port, iir);
1898 static unsigned int serial8250_tx_empty(struct uart_port *port)
1900 struct uart_8250_port *up = up_to_u8250p(port);
1901 unsigned long flags;
1904 serial8250_rpm_get(up);
1906 spin_lock_irqsave(&port->lock, flags);
1907 lsr = serial_port_in(port, UART_LSR);
1908 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1909 spin_unlock_irqrestore(&port->lock, flags);
1911 serial8250_rpm_put(up);
1913 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1916 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1918 struct uart_8250_port *up = up_to_u8250p(port);
1919 unsigned int status;
1922 serial8250_rpm_get(up);
1923 status = serial8250_modem_status(up);
1924 serial8250_rpm_put(up);
1927 if (status & UART_MSR_DCD)
1929 if (status & UART_MSR_RI)
1931 if (status & UART_MSR_DSR)
1933 if (status & UART_MSR_CTS)
1937 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1939 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1941 if (port->get_mctrl)
1942 return port->get_mctrl(port);
1943 return serial8250_do_get_mctrl(port);
1946 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1948 struct uart_8250_port *up = up_to_u8250p(port);
1949 unsigned char mcr = 0;
1951 if (mctrl & TIOCM_RTS)
1952 mcr |= UART_MCR_RTS;
1953 if (mctrl & TIOCM_DTR)
1954 mcr |= UART_MCR_DTR;
1955 if (mctrl & TIOCM_OUT1)
1956 mcr |= UART_MCR_OUT1;
1957 if (mctrl & TIOCM_OUT2)
1958 mcr |= UART_MCR_OUT2;
1959 if (mctrl & TIOCM_LOOP)
1960 mcr |= UART_MCR_LOOP;
1962 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1964 serial8250_out_MCR(up, mcr);
1966 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1968 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1970 if (port->set_mctrl)
1971 port->set_mctrl(port, mctrl);
1973 serial8250_do_set_mctrl(port, mctrl);
1976 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1978 struct uart_8250_port *up = up_to_u8250p(port);
1979 unsigned long flags;
1981 serial8250_rpm_get(up);
1982 spin_lock_irqsave(&port->lock, flags);
1983 if (break_state == -1)
1984 up->lcr |= UART_LCR_SBC;
1986 up->lcr &= ~UART_LCR_SBC;
1987 serial_port_out(port, UART_LCR, up->lcr);
1988 spin_unlock_irqrestore(&port->lock, flags);
1989 serial8250_rpm_put(up);
1993 * Wait for transmitter & holding register to empty
1995 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1997 unsigned int status, tmout = 10000;
1999 /* Wait up to 10ms for the character(s) to be sent. */
2001 status = serial_in(up, UART_LSR);
2003 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2005 if ((status & bits) == bits)
2010 touch_nmi_watchdog();
2013 /* Wait up to 1s for flow control if necessary */
2014 if (up->port.flags & UPF_CONS_FLOW) {
2015 for (tmout = 1000000; tmout; tmout--) {
2016 unsigned int msr = serial_in(up, UART_MSR);
2017 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2018 if (msr & UART_MSR_CTS)
2021 touch_nmi_watchdog();
2026 #ifdef CONFIG_CONSOLE_POLL
2028 * Console polling routines for writing and reading from the uart while
2029 * in an interrupt or debug context.
2032 static int serial8250_get_poll_char(struct uart_port *port)
2034 struct uart_8250_port *up = up_to_u8250p(port);
2038 serial8250_rpm_get(up);
2040 lsr = serial_port_in(port, UART_LSR);
2042 if (!(lsr & UART_LSR_DR)) {
2043 status = NO_POLL_CHAR;
2047 status = serial_port_in(port, UART_RX);
2049 serial8250_rpm_put(up);
2054 static void serial8250_put_poll_char(struct uart_port *port,
2058 struct uart_8250_port *up = up_to_u8250p(port);
2060 serial8250_rpm_get(up);
2062 * First save the IER then disable the interrupts
2064 ier = serial_port_in(port, UART_IER);
2065 if (up->capabilities & UART_CAP_UUE)
2066 serial_port_out(port, UART_IER, UART_IER_UUE);
2068 serial_port_out(port, UART_IER, 0);
2070 wait_for_xmitr(up, BOTH_EMPTY);
2072 * Send the character out.
2074 serial_port_out(port, UART_TX, c);
2077 * Finally, wait for transmitter to become empty
2078 * and restore the IER
2080 wait_for_xmitr(up, BOTH_EMPTY);
2081 serial_port_out(port, UART_IER, ier);
2082 serial8250_rpm_put(up);
2085 #endif /* CONFIG_CONSOLE_POLL */
2087 int serial8250_do_startup(struct uart_port *port)
2089 struct uart_8250_port *up = up_to_u8250p(port);
2090 unsigned long flags;
2091 unsigned char lsr, iir;
2094 if (!port->fifosize)
2095 port->fifosize = uart_config[port->type].fifo_size;
2097 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2098 if (!up->capabilities)
2099 up->capabilities = uart_config[port->type].flags;
2102 if (port->iotype != up->cur_iotype)
2103 set_io_from_upio(port);
2105 serial8250_rpm_get(up);
2106 if (port->type == PORT_16C950) {
2107 /* Wake up and initialize UART */
2109 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2110 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2111 serial_port_out(port, UART_IER, 0);
2112 serial_port_out(port, UART_LCR, 0);
2113 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2114 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2115 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2116 serial_port_out(port, UART_LCR, 0);
2119 #ifdef CONFIG_SERIAL_8250_RSA
2121 * If this is an RSA port, see if we can kick it up to the
2122 * higher speed clock.
2127 if (port->type == PORT_XR17V35X) {
2129 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2130 * MCR [7:5] and MSR [7:0]
2132 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2135 * Make sure all interrups are masked until initialization is
2136 * complete and the FIFOs are cleared
2138 serial_port_out(port, UART_IER, 0);
2142 * Clear the FIFO buffers and disable them.
2143 * (they will be reenabled in set_termios())
2145 serial8250_clear_fifos(up);
2148 * Clear the interrupt registers.
2150 serial_port_in(port, UART_LSR);
2151 serial_port_in(port, UART_RX);
2152 serial_port_in(port, UART_IIR);
2153 serial_port_in(port, UART_MSR);
2156 * At this point, there's no way the LSR could still be 0xff;
2157 * if it is, then bail out, because there's likely no UART
2160 if (!(port->flags & UPF_BUGGY_UART) &&
2161 (serial_port_in(port, UART_LSR) == 0xff)) {
2162 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2163 serial_index(port));
2169 * For a XR16C850, we need to set the trigger levels
2171 if (port->type == PORT_16850) {
2174 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2176 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2177 serial_port_out(port, UART_FCTR,
2178 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2179 serial_port_out(port, UART_TRG, UART_TRG_96);
2180 serial_port_out(port, UART_FCTR,
2181 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2182 serial_port_out(port, UART_TRG, UART_TRG_96);
2184 serial_port_out(port, UART_LCR, 0);
2188 * For the Altera 16550 variants, set TX threshold trigger level.
2190 if (((port->type == PORT_ALTR_16550_F32) ||
2191 (port->type == PORT_ALTR_16550_F64) ||
2192 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2193 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2194 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2195 pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2196 serial_index(port));
2198 serial_port_out(port, UART_ALTR_AFR,
2199 UART_ALTR_EN_TXFIFO_LW);
2200 serial_port_out(port, UART_ALTR_TX_LOW,
2201 port->fifosize - up->tx_loadsz);
2202 port->handle_irq = serial8250_tx_threshold_handle_irq;
2209 * Test for UARTs that do not reassert THRE when the
2210 * transmitter is idle and the interrupt has already
2211 * been cleared. Real 16550s should always reassert
2212 * this interrupt whenever the transmitter is idle and
2213 * the interrupt is enabled. Delays are necessary to
2214 * allow register changes to become visible.
2216 spin_lock_irqsave(&port->lock, flags);
2217 if (up->port.irqflags & IRQF_SHARED)
2218 disable_irq_nosync(port->irq);
2220 wait_for_xmitr(up, UART_LSR_THRE);
2221 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2222 udelay(1); /* allow THRE to set */
2223 iir1 = serial_port_in(port, UART_IIR);
2224 serial_port_out(port, UART_IER, 0);
2225 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2226 udelay(1); /* allow a working UART time to re-assert THRE */
2227 iir = serial_port_in(port, UART_IIR);
2228 serial_port_out(port, UART_IER, 0);
2230 if (port->irqflags & IRQF_SHARED)
2231 enable_irq(port->irq);
2232 spin_unlock_irqrestore(&port->lock, flags);
2235 * If the interrupt is not reasserted, or we otherwise
2236 * don't trust the iir, setup a timer to kick the UART
2237 * on a regular basis.
2239 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2240 up->port.flags & UPF_BUG_THRE) {
2241 up->bugs |= UART_BUG_THRE;
2245 retval = up->ops->setup_irq(up);
2250 * Now, initialize the UART
2252 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2254 spin_lock_irqsave(&port->lock, flags);
2255 if (up->port.flags & UPF_FOURPORT) {
2257 up->port.mctrl |= TIOCM_OUT1;
2260 * Most PC uarts need OUT2 raised to enable interrupts.
2263 up->port.mctrl |= TIOCM_OUT2;
2265 serial8250_set_mctrl(port, port->mctrl);
2268 * Serial over Lan (SoL) hack:
2269 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2270 * used for Serial Over Lan. Those chips take a longer time than a
2271 * normal serial device to signalize that a transmission data was
2272 * queued. Due to that, the above test generally fails. One solution
2273 * would be to delay the reading of iir. However, this is not
2274 * reliable, since the timeout is variable. So, let's just don't
2275 * test if we receive TX irq. This way, we'll never enable
2278 if (up->port.flags & UPF_NO_TXEN_TEST)
2279 goto dont_test_tx_en;
2282 * Do a quick test to see if we receive an interrupt when we enable
2285 serial_port_out(port, UART_IER, UART_IER_THRI);
2286 lsr = serial_port_in(port, UART_LSR);
2287 iir = serial_port_in(port, UART_IIR);
2288 serial_port_out(port, UART_IER, 0);
2290 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2291 if (!(up->bugs & UART_BUG_TXEN)) {
2292 up->bugs |= UART_BUG_TXEN;
2293 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2294 serial_index(port));
2297 up->bugs &= ~UART_BUG_TXEN;
2301 spin_unlock_irqrestore(&port->lock, flags);
2304 * Clear the interrupt registers again for luck, and clear the
2305 * saved flags to avoid getting false values from polling
2306 * routines or the previous session.
2308 serial_port_in(port, UART_LSR);
2309 serial_port_in(port, UART_RX);
2310 serial_port_in(port, UART_IIR);
2311 serial_port_in(port, UART_MSR);
2312 up->lsr_saved_flags = 0;
2313 up->msr_saved_flags = 0;
2316 * Request DMA channels for both RX and TX.
2319 retval = serial8250_request_dma(up);
2321 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2322 serial_index(port));
2328 * Set the IER shadow for rx interrupts but defer actual interrupt
2329 * enable until after the FIFOs are enabled; otherwise, an already-
2330 * active sender can swamp the interrupt handler with "too much work".
2332 up->ier = UART_IER_RLSI | UART_IER_RDI;
2334 if (port->flags & UPF_FOURPORT) {
2337 * Enable interrupts on the AST Fourport board
2339 icp = (port->iobase & 0xfe0) | 0x01f;
2345 serial8250_rpm_put(up);
2348 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2350 static int serial8250_startup(struct uart_port *port)
2353 return port->startup(port);
2354 return serial8250_do_startup(port);
2357 void serial8250_do_shutdown(struct uart_port *port)
2359 struct uart_8250_port *up = up_to_u8250p(port);
2360 unsigned long flags;
2362 serial8250_rpm_get(up);
2364 * Disable interrupts from this port
2366 spin_lock_irqsave(&port->lock, flags);
2368 serial_port_out(port, UART_IER, 0);
2369 spin_unlock_irqrestore(&port->lock, flags);
2371 synchronize_irq(port->irq);
2374 serial8250_release_dma(up);
2376 spin_lock_irqsave(&port->lock, flags);
2377 if (port->flags & UPF_FOURPORT) {
2378 /* reset interrupts on the AST Fourport board */
2379 inb((port->iobase & 0xfe0) | 0x1f);
2380 port->mctrl |= TIOCM_OUT1;
2382 port->mctrl &= ~TIOCM_OUT2;
2384 serial8250_set_mctrl(port, port->mctrl);
2385 spin_unlock_irqrestore(&port->lock, flags);
2388 * Disable break condition and FIFOs
2390 serial_port_out(port, UART_LCR,
2391 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2392 serial8250_clear_fifos(up);
2394 #ifdef CONFIG_SERIAL_8250_RSA
2396 * Reset the RSA board back to 115kbps compat mode.
2402 * Read data port to reset things, and then unlink from
2405 serial_port_in(port, UART_RX);
2406 serial8250_rpm_put(up);
2408 up->ops->release_irq(up);
2410 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2412 static void serial8250_shutdown(struct uart_port *port)
2415 port->shutdown(port);
2417 serial8250_do_shutdown(port);
2421 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2422 * Calculate divisor with extra 4-bit fractional portion
2424 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2428 struct uart_port *port = &up->port;
2429 unsigned int quot_16;
2431 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2432 *frac = quot_16 & 0x0f;
2434 return quot_16 >> 4;
2437 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2441 struct uart_port *port = &up->port;
2445 * Handle magic divisors for baud rates above baud_base on
2446 * SMSC SuperIO chips.
2449 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2450 baud == (port->uartclk/4))
2452 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2453 baud == (port->uartclk/8))
2455 else if (up->port.type == PORT_XR17V35X)
2456 quot = xr17v35x_get_divisor(up, baud, frac);
2458 quot = uart_get_divisor(port, baud);
2461 * Oxford Semi 952 rev B workaround
2463 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2469 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2474 switch (c_cflag & CSIZE) {
2476 cval = UART_LCR_WLEN5;
2479 cval = UART_LCR_WLEN6;
2482 cval = UART_LCR_WLEN7;
2486 cval = UART_LCR_WLEN8;
2490 if (c_cflag & CSTOPB)
2491 cval |= UART_LCR_STOP;
2492 if (c_cflag & PARENB) {
2493 cval |= UART_LCR_PARITY;
2494 if (up->bugs & UART_BUG_PARITY)
2495 up->fifo_bug = true;
2497 if (!(c_cflag & PARODD))
2498 cval |= UART_LCR_EPAR;
2500 if (c_cflag & CMSPAR)
2501 cval |= UART_LCR_SPAR;
2507 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2508 unsigned int quot, unsigned int quot_frac)
2510 struct uart_8250_port *up = up_to_u8250p(port);
2512 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2513 if (is_omap1510_8250(up)) {
2514 if (baud == 115200) {
2516 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2518 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2522 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2523 * otherwise just set DLAB
2525 if (up->capabilities & UART_NATSEMI)
2526 serial_port_out(port, UART_LCR, 0xe0);
2528 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2530 serial_dl_write(up, quot);
2532 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2533 if (up->port.type == PORT_XR17V35X)
2534 serial_port_out(port, 0x2, quot_frac);
2537 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2538 struct ktermios *termios,
2539 struct ktermios *old)
2542 * Ask the core to calculate the divisor for us.
2543 * Allow 1% tolerance at the upper limit so uart clks marginally
2544 * slower than nominal still match standard baud rates without
2545 * causing transmission errors.
2547 return uart_get_baud_rate(port, termios, old,
2548 port->uartclk / 16 / 0xffff,
2553 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2554 struct ktermios *old)
2556 struct uart_8250_port *up = up_to_u8250p(port);
2558 unsigned long flags;
2559 unsigned int baud, quot, frac = 0;
2561 cval = serial8250_compute_lcr(up, termios->c_cflag);
2563 baud = serial8250_get_baud_rate(port, termios, old);
2564 quot = serial8250_get_divisor(up, baud, &frac);
2567 * Ok, we're now changing the port state. Do it with
2568 * interrupts disabled.
2570 serial8250_rpm_get(up);
2571 spin_lock_irqsave(&port->lock, flags);
2573 up->lcr = cval; /* Save computed LCR */
2575 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2576 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2577 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2578 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2579 up->fcr |= UART_FCR_TRIGGER_1;
2584 * MCR-based auto flow control. When AFE is enabled, RTS will be
2585 * deasserted when the receive FIFO contains more characters than
2586 * the trigger, or the MCR RTS bit is cleared.
2588 if (up->capabilities & UART_CAP_AFE) {
2589 up->mcr &= ~UART_MCR_AFE;
2590 if (termios->c_cflag & CRTSCTS)
2591 up->mcr |= UART_MCR_AFE;
2595 * Update the per-port timeout.
2597 uart_update_timeout(port, termios->c_cflag, baud);
2599 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2600 if (termios->c_iflag & INPCK)
2601 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2602 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2603 port->read_status_mask |= UART_LSR_BI;
2606 * Characteres to ignore
2608 port->ignore_status_mask = 0;
2609 if (termios->c_iflag & IGNPAR)
2610 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2611 if (termios->c_iflag & IGNBRK) {
2612 port->ignore_status_mask |= UART_LSR_BI;
2614 * If we're ignoring parity and break indicators,
2615 * ignore overruns too (for real raw support).
2617 if (termios->c_iflag & IGNPAR)
2618 port->ignore_status_mask |= UART_LSR_OE;
2622 * ignore all characters if CREAD is not set
2624 if ((termios->c_cflag & CREAD) == 0)
2625 port->ignore_status_mask |= UART_LSR_DR;
2628 * CTS flow control flag and modem status interrupts
2630 up->ier &= ~UART_IER_MSI;
2631 if (!(up->bugs & UART_BUG_NOMSR) &&
2632 UART_ENABLE_MS(&up->port, termios->c_cflag))
2633 up->ier |= UART_IER_MSI;
2634 if (up->capabilities & UART_CAP_UUE)
2635 up->ier |= UART_IER_UUE;
2636 if (up->capabilities & UART_CAP_RTOIE)
2637 up->ier |= UART_IER_RTOIE;
2639 serial_port_out(port, UART_IER, up->ier);
2641 if (up->capabilities & UART_CAP_EFR) {
2642 unsigned char efr = 0;
2644 * TI16C752/Startech hardware flow control. FIXME:
2645 * - TI16C752 requires control thresholds to be set.
2646 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2648 if (termios->c_cflag & CRTSCTS)
2649 efr |= UART_EFR_CTS;
2651 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2652 if (port->flags & UPF_EXAR_EFR)
2653 serial_port_out(port, UART_XR_EFR, efr);
2655 serial_port_out(port, UART_EFR, efr);
2658 serial8250_set_divisor(port, baud, quot, frac);
2661 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2662 * is written without DLAB set, this mode will be disabled.
2664 if (port->type == PORT_16750)
2665 serial_port_out(port, UART_FCR, up->fcr);
2667 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2668 if (port->type != PORT_16750) {
2669 /* emulated UARTs (Lucent Venus 167x) need two steps */
2670 if (up->fcr & UART_FCR_ENABLE_FIFO)
2671 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2672 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2674 serial8250_set_mctrl(port, port->mctrl);
2675 spin_unlock_irqrestore(&port->lock, flags);
2676 serial8250_rpm_put(up);
2678 /* Don't rewrite B0 */
2679 if (tty_termios_baud_rate(termios))
2680 tty_termios_encode_baud_rate(termios, baud, baud);
2682 EXPORT_SYMBOL(serial8250_do_set_termios);
2685 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2686 struct ktermios *old)
2688 if (port->set_termios)
2689 port->set_termios(port, termios, old);
2691 serial8250_do_set_termios(port, termios, old);
2695 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2697 if (termios->c_line == N_PPS) {
2698 port->flags |= UPF_HARDPPS_CD;
2699 spin_lock_irq(&port->lock);
2700 serial8250_enable_ms(port);
2701 spin_unlock_irq(&port->lock);
2703 port->flags &= ~UPF_HARDPPS_CD;
2704 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2705 spin_lock_irq(&port->lock);
2706 serial8250_disable_ms(port);
2707 spin_unlock_irq(&port->lock);
2713 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2714 unsigned int oldstate)
2716 struct uart_8250_port *p = up_to_u8250p(port);
2718 serial8250_set_sleep(p, state != 0);
2720 EXPORT_SYMBOL(serial8250_do_pm);
2723 serial8250_pm(struct uart_port *port, unsigned int state,
2724 unsigned int oldstate)
2727 port->pm(port, state, oldstate);
2729 serial8250_do_pm(port, state, oldstate);
2732 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2734 if (pt->port.mapsize)
2735 return pt->port.mapsize;
2736 if (pt->port.iotype == UPIO_AU) {
2737 if (pt->port.type == PORT_RT2880)
2741 if (is_omap1_8250(pt))
2742 return 0x16 << pt->port.regshift;
2744 return 8 << pt->port.regshift;
2748 * Resource handling.
2750 static int serial8250_request_std_resource(struct uart_8250_port *up)
2752 unsigned int size = serial8250_port_size(up);
2753 struct uart_port *port = &up->port;
2756 switch (port->iotype) {
2766 if (!request_mem_region(port->mapbase, size, "serial")) {
2771 if (port->flags & UPF_IOREMAP) {
2772 port->membase = ioremap_nocache(port->mapbase, size);
2773 if (!port->membase) {
2774 release_mem_region(port->mapbase, size);
2782 if (!request_region(port->iobase, size, "serial"))
2789 static void serial8250_release_std_resource(struct uart_8250_port *up)
2791 unsigned int size = serial8250_port_size(up);
2792 struct uart_port *port = &up->port;
2794 switch (port->iotype) {
2804 if (port->flags & UPF_IOREMAP) {
2805 iounmap(port->membase);
2806 port->membase = NULL;
2809 release_mem_region(port->mapbase, size);
2814 release_region(port->iobase, size);
2819 static void serial8250_release_port(struct uart_port *port)
2821 struct uart_8250_port *up = up_to_u8250p(port);
2823 serial8250_release_std_resource(up);
2826 static int serial8250_request_port(struct uart_port *port)
2828 struct uart_8250_port *up = up_to_u8250p(port);
2830 return serial8250_request_std_resource(up);
2833 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2835 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2836 unsigned char bytes;
2838 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2840 return bytes ? bytes : -EOPNOTSUPP;
2843 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2845 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2848 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2851 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2852 if (bytes < conf_type->rxtrig_bytes[i])
2853 /* Use the nearest lower value */
2854 return (--i) << UART_FCR_R_TRIG_SHIFT;
2857 return UART_FCR_R_TRIG_11;
2860 static int do_get_rxtrig(struct tty_port *port)
2862 struct uart_state *state = container_of(port, struct uart_state, port);
2863 struct uart_port *uport = state->uart_port;
2864 struct uart_8250_port *up = up_to_u8250p(uport);
2866 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2869 return fcr_get_rxtrig_bytes(up);
2872 static int do_serial8250_get_rxtrig(struct tty_port *port)
2876 mutex_lock(&port->mutex);
2877 rxtrig_bytes = do_get_rxtrig(port);
2878 mutex_unlock(&port->mutex);
2880 return rxtrig_bytes;
2883 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2884 struct device_attribute *attr, char *buf)
2886 struct tty_port *port = dev_get_drvdata(dev);
2889 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2890 if (rxtrig_bytes < 0)
2891 return rxtrig_bytes;
2893 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2896 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2898 struct uart_state *state = container_of(port, struct uart_state, port);
2899 struct uart_port *uport = state->uart_port;
2900 struct uart_8250_port *up = up_to_u8250p(uport);
2903 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2907 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2911 serial8250_clear_fifos(up);
2912 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2913 up->fcr |= (unsigned char)rxtrig;
2914 serial_out(up, UART_FCR, up->fcr);
2918 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2922 mutex_lock(&port->mutex);
2923 ret = do_set_rxtrig(port, bytes);
2924 mutex_unlock(&port->mutex);
2929 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2930 struct device_attribute *attr, const char *buf, size_t count)
2932 struct tty_port *port = dev_get_drvdata(dev);
2933 unsigned char bytes;
2939 ret = kstrtou8(buf, 10, &bytes);
2943 ret = do_serial8250_set_rxtrig(port, bytes);
2950 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2951 serial8250_get_attr_rx_trig_bytes,
2952 serial8250_set_attr_rx_trig_bytes);
2954 static struct attribute *serial8250_dev_attrs[] = {
2955 &dev_attr_rx_trig_bytes.attr,
2959 static struct attribute_group serial8250_dev_attr_group = {
2960 .attrs = serial8250_dev_attrs,
2963 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2965 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2967 if (conf_type->rxtrig_bytes[0])
2968 up->port.attr_group = &serial8250_dev_attr_group;
2971 static void serial8250_config_port(struct uart_port *port, int flags)
2973 struct uart_8250_port *up = up_to_u8250p(port);
2977 * Find the region that we can probe for. This in turn
2978 * tells us whether we can probe for the type of port.
2980 ret = serial8250_request_std_resource(up);
2984 if (port->iotype != up->cur_iotype)
2985 set_io_from_upio(port);
2987 if (flags & UART_CONFIG_TYPE)
2990 /* if access method is AU, it is a 16550 with a quirk */
2991 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2992 up->bugs |= UART_BUG_NOMSR;
2994 /* HW bugs may trigger IRQ while IIR == NO_INT */
2995 if (port->type == PORT_TEGRA)
2996 up->bugs |= UART_BUG_NOMSR;
2998 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3001 if (port->type == PORT_UNKNOWN)
3002 serial8250_release_std_resource(up);
3004 /* Fixme: probably not the best place for this */
3005 if ((port->type == PORT_XR17V35X) ||
3006 (port->type == PORT_XR17D15X))
3007 port->handle_irq = exar_handle_irq;
3009 register_dev_spec_attr_grp(up);
3010 up->fcr = uart_config[up->port.type].fcr;
3014 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3016 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3017 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3018 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3019 ser->type == PORT_STARTECH)
3024 static const char *serial8250_type(struct uart_port *port)
3026 int type = port->type;
3028 if (type >= ARRAY_SIZE(uart_config))
3030 return uart_config[type].name;
3033 static const struct uart_ops serial8250_pops = {
3034 .tx_empty = serial8250_tx_empty,
3035 .set_mctrl = serial8250_set_mctrl,
3036 .get_mctrl = serial8250_get_mctrl,
3037 .stop_tx = serial8250_stop_tx,
3038 .start_tx = serial8250_start_tx,
3039 .throttle = serial8250_throttle,
3040 .unthrottle = serial8250_unthrottle,
3041 .stop_rx = serial8250_stop_rx,
3042 .enable_ms = serial8250_enable_ms,
3043 .break_ctl = serial8250_break_ctl,
3044 .startup = serial8250_startup,
3045 .shutdown = serial8250_shutdown,
3046 .set_termios = serial8250_set_termios,
3047 .set_ldisc = serial8250_set_ldisc,
3048 .pm = serial8250_pm,
3049 .type = serial8250_type,
3050 .release_port = serial8250_release_port,
3051 .request_port = serial8250_request_port,
3052 .config_port = serial8250_config_port,
3053 .verify_port = serial8250_verify_port,
3054 #ifdef CONFIG_CONSOLE_POLL
3055 .poll_get_char = serial8250_get_poll_char,
3056 .poll_put_char = serial8250_put_poll_char,
3060 void serial8250_init_port(struct uart_8250_port *up)
3062 struct uart_port *port = &up->port;
3064 spin_lock_init(&port->lock);
3065 port->ops = &serial8250_pops;
3067 up->cur_iotype = 0xFF;
3069 EXPORT_SYMBOL_GPL(serial8250_init_port);
3071 void serial8250_set_defaults(struct uart_8250_port *up)
3073 struct uart_port *port = &up->port;
3075 if (up->port.flags & UPF_FIXED_TYPE) {
3076 unsigned int type = up->port.type;
3078 if (!up->port.fifosize)
3079 up->port.fifosize = uart_config[type].fifo_size;
3081 up->tx_loadsz = uart_config[type].tx_loadsz;
3082 if (!up->capabilities)
3083 up->capabilities = uart_config[type].flags;
3086 set_io_from_upio(port);
3088 /* default dma handlers */
3090 if (!up->dma->tx_dma)
3091 up->dma->tx_dma = serial8250_tx_dma;
3092 if (!up->dma->rx_dma)
3093 up->dma->rx_dma = serial8250_rx_dma;
3096 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3098 #ifdef CONFIG_SERIAL_8250_CONSOLE
3100 static void serial8250_console_putchar(struct uart_port *port, int ch)
3102 struct uart_8250_port *up = up_to_u8250p(port);
3104 wait_for_xmitr(up, UART_LSR_THRE);
3105 serial_port_out(port, UART_TX, ch);
3109 * Restore serial console when h/w power-off detected
3111 static void serial8250_console_restore(struct uart_8250_port *up)
3113 struct uart_port *port = &up->port;
3114 struct ktermios termios;
3115 unsigned int baud, quot, frac = 0;
3117 termios.c_cflag = port->cons->cflag;
3118 if (port->state->port.tty && termios.c_cflag == 0)
3119 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3121 baud = serial8250_get_baud_rate(port, &termios, NULL);
3122 quot = serial8250_get_divisor(up, baud, &frac);
3124 serial8250_set_divisor(port, baud, quot, frac);
3125 serial_port_out(port, UART_LCR, up->lcr);
3126 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3130 * Print a string to the serial port trying not to disturb
3131 * any possible real use of the port...
3133 * The console_lock must be held when we get here.
3135 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3138 struct uart_port *port = &up->port;
3139 unsigned long flags;
3143 touch_nmi_watchdog();
3145 serial8250_rpm_get(up);
3149 else if (oops_in_progress)
3150 locked = spin_trylock_irqsave(&port->lock, flags);
3152 spin_lock_irqsave(&port->lock, flags);
3155 * First save the IER then disable the interrupts
3157 ier = serial_port_in(port, UART_IER);
3159 if (up->capabilities & UART_CAP_UUE)
3160 serial_port_out(port, UART_IER, UART_IER_UUE);
3162 serial_port_out(port, UART_IER, 0);
3164 /* check scratch reg to see if port powered off during system sleep */
3165 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3166 serial8250_console_restore(up);
3170 uart_console_write(port, s, count, serial8250_console_putchar);
3173 * Finally, wait for transmitter to become empty
3174 * and restore the IER
3176 wait_for_xmitr(up, BOTH_EMPTY);
3177 serial_port_out(port, UART_IER, ier);
3180 * The receive handling will happen properly because the
3181 * receive ready bit will still be set; it is not cleared
3182 * on read. However, modem control will not, we must
3183 * call it if we have saved something in the saved flags
3184 * while processing with interrupts off.
3186 if (up->msr_saved_flags)
3187 serial8250_modem_status(up);
3190 spin_unlock_irqrestore(&port->lock, flags);
3191 serial8250_rpm_put(up);
3194 static unsigned int probe_baud(struct uart_port *port)
3196 unsigned char lcr, dll, dlm;
3199 lcr = serial_port_in(port, UART_LCR);
3200 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3201 dll = serial_port_in(port, UART_DLL);
3202 dlm = serial_port_in(port, UART_DLM);
3203 serial_port_out(port, UART_LCR, lcr);
3205 quot = (dlm << 8) | dll;
3206 return (port->uartclk / 16) / quot;
3209 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3216 if (!port->iobase && !port->membase)
3220 uart_parse_options(options, &baud, &parity, &bits, &flow);
3222 baud = probe_baud(port);
3224 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3227 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3229 MODULE_LICENSE("GPL");