2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmaengine.h>
41 #include <linux/atmel_pdc.h>
42 #include <linux/atmel_serial.h>
43 #include <linux/uaccess.h>
44 #include <linux/platform_data/atmel.h>
45 #include <linux/timer.h>
46 #include <linux/gpio.h>
47 #include <linux/gpio/consumer.h>
48 #include <linux/err.h>
49 #include <linux/irq.h>
50 #include <linux/suspend.h>
53 #include <asm/ioctls.h>
55 #define PDC_BUFFER_SIZE 512
56 /* Revisit: We should calculate this based on the actual port settings */
57 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
59 /* The minium number of data FIFOs should be able to contain */
60 #define ATMEL_MIN_FIFO_SIZE 8
62 * These two offsets are substracted from the RX FIFO size to define the RTS
63 * high and low thresholds
65 #define ATMEL_RTS_HIGH_OFFSET 16
66 #define ATMEL_RTS_LOW_OFFSET 20
68 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
72 #include <linux/serial_core.h>
74 #include "serial_mctrl_gpio.h"
76 static void atmel_start_rx(struct uart_port *port);
77 static void atmel_stop_rx(struct uart_port *port);
79 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
81 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
82 * should coexist with the 8250 driver, such as if we have an external 16C550
84 #define SERIAL_ATMEL_MAJOR 204
85 #define MINOR_START 154
86 #define ATMEL_DEVICENAME "ttyAT"
90 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
91 * name, but it is legally reserved for the 8250 driver. */
92 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
93 #define MINOR_START 64
94 #define ATMEL_DEVICENAME "ttyS"
98 #define ATMEL_ISR_PASS_LIMIT 256
100 struct atmel_dma_buffer {
103 unsigned int dma_size;
107 struct atmel_uart_char {
112 #define ATMEL_SERIAL_RINGSIZE 1024
115 * at91: 6 USARTs and one DBGU port (SAM9260)
118 #define ATMEL_MAX_UART 7
121 * We wrap our port structure around the generic uart_port.
123 struct atmel_uart_port {
124 struct uart_port uart; /* uart */
125 struct clk *clk; /* uart clock */
126 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
127 u32 backup_imr; /* IMR saved during suspend */
128 int break_active; /* break being received */
130 bool use_dma_rx; /* enable DMA receiver */
131 bool use_pdc_rx; /* enable PDC receiver */
132 short pdc_rx_idx; /* current PDC RX buffer */
133 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
135 bool use_dma_tx; /* enable DMA transmitter */
136 bool use_pdc_tx; /* enable PDC transmitter */
137 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
139 spinlock_t lock_tx; /* port lock */
140 spinlock_t lock_rx; /* port lock */
141 struct dma_chan *chan_tx;
142 struct dma_chan *chan_rx;
143 struct dma_async_tx_descriptor *desc_tx;
144 struct dma_async_tx_descriptor *desc_rx;
145 dma_cookie_t cookie_tx;
146 dma_cookie_t cookie_rx;
147 struct scatterlist sg_tx;
148 struct scatterlist sg_rx;
149 struct tasklet_struct tasklet;
150 unsigned int irq_status;
151 unsigned int irq_status_prev;
152 unsigned int status_change;
155 struct circ_buf rx_ring;
157 struct mctrl_gpios *gpios;
158 unsigned int tx_done_mask;
163 bool is_usart; /* usart or uart */
164 struct timer_list uart_timer; /* uart timer */
167 unsigned int pending;
168 unsigned int pending_status;
169 spinlock_t lock_suspended;
171 int (*prepare_rx)(struct uart_port *port);
172 int (*prepare_tx)(struct uart_port *port);
173 void (*schedule_rx)(struct uart_port *port);
174 void (*schedule_tx)(struct uart_port *port);
175 void (*release_rx)(struct uart_port *port);
176 void (*release_tx)(struct uart_port *port);
179 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
180 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
183 static struct console atmel_console;
186 #if defined(CONFIG_OF)
187 static const struct of_device_id atmel_serial_dt_ids[] = {
188 { .compatible = "atmel,at91rm9200-usart" },
189 { .compatible = "atmel,at91sam9260-usart" },
193 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
196 static inline struct atmel_uart_port *
197 to_atmel_uart_port(struct uart_port *uart)
199 return container_of(uart, struct atmel_uart_port, uart);
202 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
204 return __raw_readl(port->membase + reg);
207 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
209 __raw_writel(value, port->membase + reg);
214 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
215 static inline u8 atmel_uart_read_char(struct uart_port *port)
217 return __raw_readl(port->membase + ATMEL_US_RHR);
220 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
222 __raw_writel(value, port->membase + ATMEL_US_THR);
227 static inline u8 atmel_uart_read_char(struct uart_port *port)
229 return __raw_readb(port->membase + ATMEL_US_RHR);
232 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
234 __raw_writeb(value, port->membase + ATMEL_US_THR);
239 #ifdef CONFIG_SERIAL_ATMEL_PDC
240 static bool atmel_use_pdc_rx(struct uart_port *port)
242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
244 return atmel_port->use_pdc_rx;
247 static bool atmel_use_pdc_tx(struct uart_port *port)
249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
251 return atmel_port->use_pdc_tx;
254 static bool atmel_use_pdc_rx(struct uart_port *port)
259 static bool atmel_use_pdc_tx(struct uart_port *port)
265 static bool atmel_use_dma_tx(struct uart_port *port)
267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
269 return atmel_port->use_dma_tx;
272 static bool atmel_use_dma_rx(struct uart_port *port)
274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
276 return atmel_port->use_dma_rx;
279 static unsigned int atmel_get_lines_status(struct uart_port *port)
281 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
282 unsigned int status, ret = 0;
284 status = atmel_uart_readl(port, ATMEL_US_CSR);
286 mctrl_gpio_get(atmel_port->gpios, &ret);
288 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
291 status &= ~ATMEL_US_CTS;
293 status |= ATMEL_US_CTS;
296 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
299 status &= ~ATMEL_US_DSR;
301 status |= ATMEL_US_DSR;
304 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
307 status &= ~ATMEL_US_RI;
309 status |= ATMEL_US_RI;
312 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
315 status &= ~ATMEL_US_DCD;
317 status |= ATMEL_US_DCD;
323 /* Enable or disable the rs485 support */
324 static int atmel_config_rs485(struct uart_port *port,
325 struct serial_rs485 *rs485conf)
327 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
330 /* Disable interrupts */
331 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
333 mode = atmel_uart_readl(port, ATMEL_US_MR);
335 /* Resetting serial mode to RS232 (0x0) */
336 mode &= ~ATMEL_US_USMODE;
338 port->rs485 = *rs485conf;
340 if (rs485conf->flags & SER_RS485_ENABLED) {
341 dev_dbg(port->dev, "Setting UART to RS485\n");
342 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
343 atmel_uart_writel(port, ATMEL_US_TTGR,
344 rs485conf->delay_rts_after_send);
345 mode |= ATMEL_US_USMODE_RS485;
347 dev_dbg(port->dev, "Setting UART to RS232\n");
348 if (atmel_use_pdc_tx(port))
349 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
352 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
354 atmel_uart_writel(port, ATMEL_US_MR, mode);
356 /* Enable interrupts */
357 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
363 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
365 static u_int atmel_tx_empty(struct uart_port *port)
367 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
373 * Set state of the modem control output lines
375 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
377 unsigned int control = 0;
378 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
379 unsigned int rts_paused, rts_ready;
380 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
382 /* override mode to RS485 if needed, otherwise keep the current mode */
383 if (port->rs485.flags & SER_RS485_ENABLED) {
384 atmel_uart_writel(port, ATMEL_US_TTGR,
385 port->rs485.delay_rts_after_send);
386 mode &= ~ATMEL_US_USMODE;
387 mode |= ATMEL_US_USMODE_RS485;
390 /* set the RTS line state according to the mode */
391 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
392 /* force RTS line to high level */
393 rts_paused = ATMEL_US_RTSEN;
395 /* give the control of the RTS line back to the hardware */
396 rts_ready = ATMEL_US_RTSDIS;
398 /* force RTS line to high level */
399 rts_paused = ATMEL_US_RTSDIS;
401 /* force RTS line to low level */
402 rts_ready = ATMEL_US_RTSEN;
405 if (mctrl & TIOCM_RTS)
406 control |= rts_ready;
408 control |= rts_paused;
410 if (mctrl & TIOCM_DTR)
411 control |= ATMEL_US_DTREN;
413 control |= ATMEL_US_DTRDIS;
415 atmel_uart_writel(port, ATMEL_US_CR, control);
417 mctrl_gpio_set(atmel_port->gpios, mctrl);
419 /* Local loopback mode? */
420 mode &= ~ATMEL_US_CHMODE;
421 if (mctrl & TIOCM_LOOP)
422 mode |= ATMEL_US_CHMODE_LOC_LOOP;
424 mode |= ATMEL_US_CHMODE_NORMAL;
426 atmel_uart_writel(port, ATMEL_US_MR, mode);
430 * Get state of the modem control input lines
432 static u_int atmel_get_mctrl(struct uart_port *port)
434 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
435 unsigned int ret = 0, status;
437 status = atmel_uart_readl(port, ATMEL_US_CSR);
440 * The control signals are active low.
442 if (!(status & ATMEL_US_DCD))
444 if (!(status & ATMEL_US_CTS))
446 if (!(status & ATMEL_US_DSR))
448 if (!(status & ATMEL_US_RI))
451 return mctrl_gpio_get(atmel_port->gpios, &ret);
457 static void atmel_stop_tx(struct uart_port *port)
459 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
461 if (atmel_use_pdc_tx(port)) {
462 /* disable PDC transmit */
463 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
465 /* Disable interrupts */
466 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
468 if ((port->rs485.flags & SER_RS485_ENABLED) &&
469 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
470 atmel_start_rx(port);
474 * Start transmitting.
476 static void atmel_start_tx(struct uart_port *port)
478 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
480 if (atmel_use_pdc_tx(port)) {
481 if (atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN)
482 /* The transmitter is already running. Yes, we
486 if ((port->rs485.flags & SER_RS485_ENABLED) &&
487 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
490 /* re-enable PDC transmit */
491 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
493 /* Enable interrupts */
494 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
498 * start receiving - port is in process of being opened.
500 static void atmel_start_rx(struct uart_port *port)
502 /* reset status and receiver */
503 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
505 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
507 if (atmel_use_pdc_rx(port)) {
508 /* enable PDC controller */
509 atmel_uart_writel(port, ATMEL_US_IER,
510 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
511 port->read_status_mask);
512 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
514 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
519 * Stop receiving - port is in process of being closed.
521 static void atmel_stop_rx(struct uart_port *port)
523 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
525 if (atmel_use_pdc_rx(port)) {
526 /* disable PDC receive */
527 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
528 atmel_uart_writel(port, ATMEL_US_IDR,
529 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
530 port->read_status_mask);
532 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
537 * Enable modem status interrupts
539 static void atmel_enable_ms(struct uart_port *port)
541 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
545 * Interrupt should not be enabled twice
547 if (atmel_port->ms_irq_enabled)
550 atmel_port->ms_irq_enabled = true;
552 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
553 ier |= ATMEL_US_CTSIC;
555 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
556 ier |= ATMEL_US_DSRIC;
558 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
559 ier |= ATMEL_US_RIIC;
561 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
562 ier |= ATMEL_US_DCDIC;
564 atmel_uart_writel(port, ATMEL_US_IER, ier);
566 mctrl_gpio_enable_ms(atmel_port->gpios);
570 * Disable modem status interrupts
572 static void atmel_disable_ms(struct uart_port *port)
574 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
578 * Interrupt should not be disabled twice
580 if (!atmel_port->ms_irq_enabled)
583 atmel_port->ms_irq_enabled = false;
585 mctrl_gpio_disable_ms(atmel_port->gpios);
587 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
588 idr |= ATMEL_US_CTSIC;
590 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
591 idr |= ATMEL_US_DSRIC;
593 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
594 idr |= ATMEL_US_RIIC;
596 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
597 idr |= ATMEL_US_DCDIC;
599 atmel_uart_writel(port, ATMEL_US_IDR, idr);
603 * Control the transmission of a break signal
605 static void atmel_break_ctl(struct uart_port *port, int break_state)
607 if (break_state != 0)
609 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
616 * Stores the incoming character in the ring buffer
619 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
622 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
623 struct circ_buf *ring = &atmel_port->rx_ring;
624 struct atmel_uart_char *c;
626 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
627 /* Buffer overflow, ignore char */
630 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
634 /* Make sure the character is stored before we update head. */
637 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
641 * Deal with parity, framing and overrun errors.
643 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
646 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
648 if (status & ATMEL_US_RXBRK) {
649 /* ignore side-effect */
650 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
653 if (status & ATMEL_US_PARE)
654 port->icount.parity++;
655 if (status & ATMEL_US_FRAME)
656 port->icount.frame++;
657 if (status & ATMEL_US_OVRE)
658 port->icount.overrun++;
662 * Characters received (called from interrupt handler)
664 static void atmel_rx_chars(struct uart_port *port)
666 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
667 unsigned int status, ch;
669 status = atmel_uart_readl(port, ATMEL_US_CSR);
670 while (status & ATMEL_US_RXRDY) {
671 ch = atmel_uart_read_char(port);
674 * note that the error handling code is
675 * out of the main execution path
677 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
678 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
679 || atmel_port->break_active)) {
682 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
684 if (status & ATMEL_US_RXBRK
685 && !atmel_port->break_active) {
686 atmel_port->break_active = 1;
687 atmel_uart_writel(port, ATMEL_US_IER,
691 * This is either the end-of-break
692 * condition or we've received at
693 * least one character without RXBRK
694 * being set. In both cases, the next
695 * RXBRK will indicate start-of-break.
697 atmel_uart_writel(port, ATMEL_US_IDR,
699 status &= ~ATMEL_US_RXBRK;
700 atmel_port->break_active = 0;
704 atmel_buffer_rx_char(port, status, ch);
705 status = atmel_uart_readl(port, ATMEL_US_CSR);
708 tasklet_schedule(&atmel_port->tasklet);
712 * Transmit characters (called from tasklet with TXRDY interrupt
715 static void atmel_tx_chars(struct uart_port *port)
717 struct circ_buf *xmit = &port->state->xmit;
718 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
721 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
722 atmel_uart_write_char(port, port->x_char);
726 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
729 while (atmel_uart_readl(port, ATMEL_US_CSR) &
730 atmel_port->tx_done_mask) {
731 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
732 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
734 if (uart_circ_empty(xmit))
738 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
739 uart_write_wakeup(port);
741 if (!uart_circ_empty(xmit))
742 /* Enable interrupts */
743 atmel_uart_writel(port, ATMEL_US_IER,
744 atmel_port->tx_done_mask);
747 static void atmel_complete_tx_dma(void *arg)
749 struct atmel_uart_port *atmel_port = arg;
750 struct uart_port *port = &atmel_port->uart;
751 struct circ_buf *xmit = &port->state->xmit;
752 struct dma_chan *chan = atmel_port->chan_tx;
755 spin_lock_irqsave(&port->lock, flags);
758 dmaengine_terminate_all(chan);
759 xmit->tail += atmel_port->tx_len;
760 xmit->tail &= UART_XMIT_SIZE - 1;
762 port->icount.tx += atmel_port->tx_len;
764 spin_lock_irq(&atmel_port->lock_tx);
765 async_tx_ack(atmel_port->desc_tx);
766 atmel_port->cookie_tx = -EINVAL;
767 atmel_port->desc_tx = NULL;
768 spin_unlock_irq(&atmel_port->lock_tx);
770 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
771 uart_write_wakeup(port);
774 * xmit is a circular buffer so, if we have just send data from
775 * xmit->tail to the end of xmit->buf, now we have to transmit the
776 * remaining data from the beginning of xmit->buf to xmit->head.
778 if (!uart_circ_empty(xmit))
779 tasklet_schedule(&atmel_port->tasklet);
781 spin_unlock_irqrestore(&port->lock, flags);
784 static void atmel_release_tx_dma(struct uart_port *port)
786 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
787 struct dma_chan *chan = atmel_port->chan_tx;
790 dmaengine_terminate_all(chan);
791 dma_release_channel(chan);
792 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
796 atmel_port->desc_tx = NULL;
797 atmel_port->chan_tx = NULL;
798 atmel_port->cookie_tx = -EINVAL;
802 * Called from tasklet with TXRDY interrupt is disabled.
804 static void atmel_tx_dma(struct uart_port *port)
806 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
807 struct circ_buf *xmit = &port->state->xmit;
808 struct dma_chan *chan = atmel_port->chan_tx;
809 struct dma_async_tx_descriptor *desc;
810 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
811 unsigned int tx_len, part1_len, part2_len, sg_len;
812 dma_addr_t phys_addr;
814 /* Make sure we have an idle channel */
815 if (atmel_port->desc_tx != NULL)
818 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
821 * Port xmit buffer is already mapped,
822 * and it is one page... Just adjust
823 * offsets and lengths. Since it is a circular buffer,
824 * we have to transmit till the end, and then the rest.
825 * Take the port lock to get a
826 * consistent xmit buffer state.
828 tx_len = CIRC_CNT_TO_END(xmit->head,
832 if (atmel_port->fifo_size) {
833 /* multi data mode */
834 part1_len = (tx_len & ~0x3); /* DWORD access */
835 part2_len = (tx_len & 0x3); /* BYTE access */
837 /* single data (legacy) mode */
839 part2_len = tx_len; /* BYTE access only */
842 sg_init_table(sgl, 2);
844 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
847 sg_dma_address(sg) = phys_addr;
848 sg_dma_len(sg) = part1_len;
850 phys_addr += part1_len;
855 sg_dma_address(sg) = phys_addr;
856 sg_dma_len(sg) = part2_len;
860 * save tx_len so atmel_complete_tx_dma() will increase
861 * xmit->tail correctly
863 atmel_port->tx_len = tx_len;
865 desc = dmaengine_prep_slave_sg(chan,
872 dev_err(port->dev, "Failed to send via dma!\n");
876 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
878 atmel_port->desc_tx = desc;
879 desc->callback = atmel_complete_tx_dma;
880 desc->callback_param = atmel_port;
881 atmel_port->cookie_tx = dmaengine_submit(desc);
884 if (port->rs485.flags & SER_RS485_ENABLED) {
885 /* DMA done, stop TX, start RX for RS485 */
886 atmel_start_rx(port);
890 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
891 uart_write_wakeup(port);
894 static int atmel_prepare_tx_dma(struct uart_port *port)
896 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
898 struct dma_slave_config config;
902 dma_cap_set(DMA_SLAVE, mask);
904 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
905 if (atmel_port->chan_tx == NULL)
907 dev_info(port->dev, "using %s for tx DMA transfers\n",
908 dma_chan_name(atmel_port->chan_tx));
910 spin_lock_init(&atmel_port->lock_tx);
911 sg_init_table(&atmel_port->sg_tx, 1);
912 /* UART circular tx buffer is an aligned page. */
913 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
914 sg_set_page(&atmel_port->sg_tx,
915 virt_to_page(port->state->xmit.buf),
917 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
918 nent = dma_map_sg(port->dev,
924 dev_dbg(port->dev, "need to release resource of dma\n");
927 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
928 sg_dma_len(&atmel_port->sg_tx),
929 port->state->xmit.buf,
930 &sg_dma_address(&atmel_port->sg_tx));
933 /* Configure the slave DMA */
934 memset(&config, 0, sizeof(config));
935 config.direction = DMA_MEM_TO_DEV;
936 config.dst_addr_width = (atmel_port->fifo_size) ?
937 DMA_SLAVE_BUSWIDTH_4_BYTES :
938 DMA_SLAVE_BUSWIDTH_1_BYTE;
939 config.dst_addr = port->mapbase + ATMEL_US_THR;
940 config.dst_maxburst = 1;
942 ret = dmaengine_slave_config(atmel_port->chan_tx,
945 dev_err(port->dev, "DMA tx slave configuration failed\n");
952 dev_err(port->dev, "TX channel not available, switch to pio\n");
953 atmel_port->use_dma_tx = 0;
954 if (atmel_port->chan_tx)
955 atmel_release_tx_dma(port);
959 static void atmel_complete_rx_dma(void *arg)
961 struct uart_port *port = arg;
962 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
964 tasklet_schedule(&atmel_port->tasklet);
967 static void atmel_release_rx_dma(struct uart_port *port)
969 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
970 struct dma_chan *chan = atmel_port->chan_rx;
973 dmaengine_terminate_all(chan);
974 dma_release_channel(chan);
975 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
979 atmel_port->desc_rx = NULL;
980 atmel_port->chan_rx = NULL;
981 atmel_port->cookie_rx = -EINVAL;
984 static void atmel_rx_from_dma(struct uart_port *port)
986 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
987 struct tty_port *tport = &port->state->port;
988 struct circ_buf *ring = &atmel_port->rx_ring;
989 struct dma_chan *chan = atmel_port->chan_rx;
990 struct dma_tx_state state;
991 enum dma_status dmastat;
995 /* Reset the UART timeout early so that we don't miss one */
996 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
997 dmastat = dmaengine_tx_status(chan,
998 atmel_port->cookie_rx,
1000 /* Restart a new tasklet if DMA status is error */
1001 if (dmastat == DMA_ERROR) {
1002 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1003 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1004 tasklet_schedule(&atmel_port->tasklet);
1008 /* CPU claims ownership of RX DMA buffer */
1009 dma_sync_sg_for_cpu(port->dev,
1015 * ring->head points to the end of data already written by the DMA.
1016 * ring->tail points to the beginning of data to be read by the
1018 * The current transfer size should not be larger than the dma buffer
1021 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1022 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1024 * At this point ring->head may point to the first byte right after the
1025 * last byte of the dma buffer:
1026 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1028 * However ring->tail must always points inside the dma buffer:
1029 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1031 * Since we use a ring buffer, we have to handle the case
1032 * where head is lower than tail. In such a case, we first read from
1033 * tail to the end of the buffer then reset tail.
1035 if (ring->head < ring->tail) {
1036 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1038 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1040 port->icount.rx += count;
1043 /* Finally we read data from tail to head */
1044 if (ring->tail < ring->head) {
1045 count = ring->head - ring->tail;
1047 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1048 /* Wrap ring->head if needed */
1049 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1051 ring->tail = ring->head;
1052 port->icount.rx += count;
1055 /* USART retreives ownership of RX DMA buffer */
1056 dma_sync_sg_for_device(port->dev,
1062 * Drop the lock here since it might end up calling
1063 * uart_start(), which takes the lock.
1065 spin_unlock(&port->lock);
1066 tty_flip_buffer_push(tport);
1067 spin_lock(&port->lock);
1069 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1072 static int atmel_prepare_rx_dma(struct uart_port *port)
1074 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1075 struct dma_async_tx_descriptor *desc;
1076 dma_cap_mask_t mask;
1077 struct dma_slave_config config;
1078 struct circ_buf *ring;
1081 ring = &atmel_port->rx_ring;
1084 dma_cap_set(DMA_CYCLIC, mask);
1086 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1087 if (atmel_port->chan_rx == NULL)
1089 dev_info(port->dev, "using %s for rx DMA transfers\n",
1090 dma_chan_name(atmel_port->chan_rx));
1092 spin_lock_init(&atmel_port->lock_rx);
1093 sg_init_table(&atmel_port->sg_rx, 1);
1094 /* UART circular rx buffer is an aligned page. */
1095 BUG_ON(!PAGE_ALIGNED(ring->buf));
1096 sg_set_page(&atmel_port->sg_rx,
1097 virt_to_page(ring->buf),
1098 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1099 (unsigned long)ring->buf & ~PAGE_MASK);
1100 nent = dma_map_sg(port->dev,
1106 dev_dbg(port->dev, "need to release resource of dma\n");
1109 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1110 sg_dma_len(&atmel_port->sg_rx),
1112 &sg_dma_address(&atmel_port->sg_rx));
1115 /* Configure the slave DMA */
1116 memset(&config, 0, sizeof(config));
1117 config.direction = DMA_DEV_TO_MEM;
1118 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1119 config.src_addr = port->mapbase + ATMEL_US_RHR;
1120 config.src_maxburst = 1;
1122 ret = dmaengine_slave_config(atmel_port->chan_rx,
1125 dev_err(port->dev, "DMA rx slave configuration failed\n");
1129 * Prepare a cyclic dma transfer, assign 2 descriptors,
1130 * each one is half ring buffer size
1132 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1133 sg_dma_address(&atmel_port->sg_rx),
1134 sg_dma_len(&atmel_port->sg_rx),
1135 sg_dma_len(&atmel_port->sg_rx)/2,
1137 DMA_PREP_INTERRUPT);
1138 desc->callback = atmel_complete_rx_dma;
1139 desc->callback_param = port;
1140 atmel_port->desc_rx = desc;
1141 atmel_port->cookie_rx = dmaengine_submit(desc);
1146 dev_err(port->dev, "RX channel not available, switch to pio\n");
1147 atmel_port->use_dma_rx = 0;
1148 if (atmel_port->chan_rx)
1149 atmel_release_rx_dma(port);
1153 static void atmel_uart_timer_callback(unsigned long data)
1155 struct uart_port *port = (void *)data;
1156 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1158 tasklet_schedule(&atmel_port->tasklet);
1159 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1163 * receive interrupt handler.
1166 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1168 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1170 if (atmel_use_pdc_rx(port)) {
1172 * PDC receive. Just schedule the tasklet and let it
1173 * figure out the details.
1175 * TODO: We're not handling error flags correctly at
1178 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1179 atmel_uart_writel(port, ATMEL_US_IDR,
1180 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1181 tasklet_schedule(&atmel_port->tasklet);
1184 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1185 ATMEL_US_FRAME | ATMEL_US_PARE))
1186 atmel_pdc_rxerr(port, pending);
1189 if (atmel_use_dma_rx(port)) {
1190 if (pending & ATMEL_US_TIMEOUT) {
1191 atmel_uart_writel(port, ATMEL_US_IDR,
1193 tasklet_schedule(&atmel_port->tasklet);
1197 /* Interrupt receive */
1198 if (pending & ATMEL_US_RXRDY)
1199 atmel_rx_chars(port);
1200 else if (pending & ATMEL_US_RXBRK) {
1202 * End of break detected. If it came along with a
1203 * character, atmel_rx_chars will handle it.
1205 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1206 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1207 atmel_port->break_active = 0;
1212 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1215 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1219 if (pending & atmel_port->tx_done_mask) {
1220 /* Either PDC or interrupt transmission */
1221 atmel_uart_writel(port, ATMEL_US_IDR,
1222 atmel_port->tx_done_mask);
1223 tasklet_schedule(&atmel_port->tasklet);
1228 * status flags interrupt handler.
1231 atmel_handle_status(struct uart_port *port, unsigned int pending,
1232 unsigned int status)
1234 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1236 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1237 | ATMEL_US_CTSIC)) {
1238 atmel_port->irq_status = status;
1239 atmel_port->status_change = atmel_port->irq_status ^
1240 atmel_port->irq_status_prev;
1241 atmel_port->irq_status_prev = status;
1242 tasklet_schedule(&atmel_port->tasklet);
1249 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1251 struct uart_port *port = dev_id;
1252 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1253 unsigned int status, pending, mask, pass_counter = 0;
1255 spin_lock(&atmel_port->lock_suspended);
1258 status = atmel_get_lines_status(port);
1259 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1260 pending = status & mask;
1264 if (atmel_port->suspended) {
1265 atmel_port->pending |= pending;
1266 atmel_port->pending_status = status;
1267 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1272 atmel_handle_receive(port, pending);
1273 atmel_handle_status(port, pending, status);
1274 atmel_handle_transmit(port, pending);
1275 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1277 spin_unlock(&atmel_port->lock_suspended);
1279 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1282 static void atmel_release_tx_pdc(struct uart_port *port)
1284 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1285 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1287 dma_unmap_single(port->dev,
1294 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1296 static void atmel_tx_pdc(struct uart_port *port)
1298 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1299 struct circ_buf *xmit = &port->state->xmit;
1300 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1303 /* nothing left to transmit? */
1304 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1307 xmit->tail += pdc->ofs;
1308 xmit->tail &= UART_XMIT_SIZE - 1;
1310 port->icount.tx += pdc->ofs;
1313 /* more to transmit - setup next transfer */
1315 /* disable PDC transmit */
1316 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1318 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1319 dma_sync_single_for_device(port->dev,
1324 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1327 atmel_uart_writel(port, ATMEL_PDC_TPR,
1328 pdc->dma_addr + xmit->tail);
1329 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1330 /* re-enable PDC transmit */
1331 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1332 /* Enable interrupts */
1333 atmel_uart_writel(port, ATMEL_US_IER,
1334 atmel_port->tx_done_mask);
1336 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1337 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1338 /* DMA done, stop TX, start RX for RS485 */
1339 atmel_start_rx(port);
1343 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1344 uart_write_wakeup(port);
1347 static int atmel_prepare_tx_pdc(struct uart_port *port)
1349 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1350 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1351 struct circ_buf *xmit = &port->state->xmit;
1353 pdc->buf = xmit->buf;
1354 pdc->dma_addr = dma_map_single(port->dev,
1358 pdc->dma_size = UART_XMIT_SIZE;
1364 static void atmel_rx_from_ring(struct uart_port *port)
1366 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1367 struct circ_buf *ring = &atmel_port->rx_ring;
1369 unsigned int status;
1371 while (ring->head != ring->tail) {
1372 struct atmel_uart_char c;
1374 /* Make sure c is loaded after head. */
1377 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1379 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1386 * note that the error handling code is
1387 * out of the main execution path
1389 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1390 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1391 if (status & ATMEL_US_RXBRK) {
1392 /* ignore side-effect */
1393 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1396 if (uart_handle_break(port))
1399 if (status & ATMEL_US_PARE)
1400 port->icount.parity++;
1401 if (status & ATMEL_US_FRAME)
1402 port->icount.frame++;
1403 if (status & ATMEL_US_OVRE)
1404 port->icount.overrun++;
1406 status &= port->read_status_mask;
1408 if (status & ATMEL_US_RXBRK)
1410 else if (status & ATMEL_US_PARE)
1412 else if (status & ATMEL_US_FRAME)
1417 if (uart_handle_sysrq_char(port, c.ch))
1420 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1424 * Drop the lock here since it might end up calling
1425 * uart_start(), which takes the lock.
1427 spin_unlock(&port->lock);
1428 tty_flip_buffer_push(&port->state->port);
1429 spin_lock(&port->lock);
1432 static void atmel_release_rx_pdc(struct uart_port *port)
1434 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1437 for (i = 0; i < 2; i++) {
1438 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1440 dma_unmap_single(port->dev,
1448 static void atmel_rx_from_pdc(struct uart_port *port)
1450 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1451 struct tty_port *tport = &port->state->port;
1452 struct atmel_dma_buffer *pdc;
1453 int rx_idx = atmel_port->pdc_rx_idx;
1459 /* Reset the UART timeout early so that we don't miss one */
1460 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1462 pdc = &atmel_port->pdc_rx[rx_idx];
1463 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1466 /* If the PDC has switched buffers, RPR won't contain
1467 * any address within the current buffer. Since head
1468 * is unsigned, we just need a one-way comparison to
1471 * In this case, we just need to consume the entire
1472 * buffer and resubmit it for DMA. This will clear the
1473 * ENDRX bit as well, so that we can safely re-enable
1474 * all interrupts below.
1476 head = min(head, pdc->dma_size);
1478 if (likely(head != tail)) {
1479 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1480 pdc->dma_size, DMA_FROM_DEVICE);
1483 * head will only wrap around when we recycle
1484 * the DMA buffer, and when that happens, we
1485 * explicitly set tail to 0. So head will
1486 * always be greater than tail.
1488 count = head - tail;
1490 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1493 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1494 pdc->dma_size, DMA_FROM_DEVICE);
1496 port->icount.rx += count;
1501 * If the current buffer is full, we need to check if
1502 * the next one contains any additional data.
1504 if (head >= pdc->dma_size) {
1506 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1507 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1510 atmel_port->pdc_rx_idx = rx_idx;
1512 } while (head >= pdc->dma_size);
1515 * Drop the lock here since it might end up calling
1516 * uart_start(), which takes the lock.
1518 spin_unlock(&port->lock);
1519 tty_flip_buffer_push(tport);
1520 spin_lock(&port->lock);
1522 atmel_uart_writel(port, ATMEL_US_IER,
1523 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1526 static int atmel_prepare_rx_pdc(struct uart_port *port)
1528 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1531 for (i = 0; i < 2; i++) {
1532 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1534 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1535 if (pdc->buf == NULL) {
1537 dma_unmap_single(port->dev,
1538 atmel_port->pdc_rx[0].dma_addr,
1541 kfree(atmel_port->pdc_rx[0].buf);
1543 atmel_port->use_pdc_rx = 0;
1546 pdc->dma_addr = dma_map_single(port->dev,
1550 pdc->dma_size = PDC_BUFFER_SIZE;
1554 atmel_port->pdc_rx_idx = 0;
1556 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1557 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1559 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1560 atmel_port->pdc_rx[1].dma_addr);
1561 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1567 * tasklet handling tty stuff outside the interrupt handler.
1569 static void atmel_tasklet_func(unsigned long data)
1571 struct uart_port *port = (struct uart_port *)data;
1572 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1573 unsigned int status = atmel_port->irq_status;
1574 unsigned int status_change = atmel_port->status_change;
1576 /* The interrupt handler does not take the lock */
1577 spin_lock(&port->lock);
1579 atmel_port->schedule_tx(port);
1581 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1582 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1583 /* TODO: All reads to CSR will clear these interrupts! */
1584 if (status_change & ATMEL_US_RI)
1586 if (status_change & ATMEL_US_DSR)
1588 if (status_change & ATMEL_US_DCD)
1589 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1590 if (status_change & ATMEL_US_CTS)
1591 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1593 wake_up_interruptible(&port->state->port.delta_msr_wait);
1595 atmel_port->status_change = 0;
1598 atmel_port->schedule_rx(port);
1600 spin_unlock(&port->lock);
1603 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1604 struct platform_device *pdev)
1606 struct device_node *np = pdev->dev.of_node;
1607 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1610 /* DMA/PDC usage specification */
1611 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1612 if (of_get_property(np, "dmas", NULL)) {
1613 atmel_port->use_dma_rx = true;
1614 atmel_port->use_pdc_rx = false;
1616 atmel_port->use_dma_rx = false;
1617 atmel_port->use_pdc_rx = true;
1620 atmel_port->use_dma_rx = false;
1621 atmel_port->use_pdc_rx = false;
1624 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1625 if (of_get_property(np, "dmas", NULL)) {
1626 atmel_port->use_dma_tx = true;
1627 atmel_port->use_pdc_tx = false;
1629 atmel_port->use_dma_tx = false;
1630 atmel_port->use_pdc_tx = true;
1633 atmel_port->use_dma_tx = false;
1634 atmel_port->use_pdc_tx = false;
1638 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1639 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1640 atmel_port->use_dma_rx = false;
1641 atmel_port->use_dma_tx = false;
1646 static void atmel_init_rs485(struct uart_port *port,
1647 struct platform_device *pdev)
1649 struct device_node *np = pdev->dev.of_node;
1650 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1653 struct serial_rs485 *rs485conf = &port->rs485;
1655 /* rs485 properties */
1656 if (of_property_read_u32_array(np, "rs485-rts-delay",
1657 rs485_delay, 2) == 0) {
1658 rs485conf->delay_rts_before_send = rs485_delay[0];
1659 rs485conf->delay_rts_after_send = rs485_delay[1];
1660 rs485conf->flags = 0;
1663 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1664 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1666 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1668 rs485conf->flags |= SER_RS485_ENABLED;
1670 port->rs485 = pdata->rs485;
1675 static void atmel_set_ops(struct uart_port *port)
1677 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1679 if (atmel_use_dma_rx(port)) {
1680 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1681 atmel_port->schedule_rx = &atmel_rx_from_dma;
1682 atmel_port->release_rx = &atmel_release_rx_dma;
1683 } else if (atmel_use_pdc_rx(port)) {
1684 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1685 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1686 atmel_port->release_rx = &atmel_release_rx_pdc;
1688 atmel_port->prepare_rx = NULL;
1689 atmel_port->schedule_rx = &atmel_rx_from_ring;
1690 atmel_port->release_rx = NULL;
1693 if (atmel_use_dma_tx(port)) {
1694 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1695 atmel_port->schedule_tx = &atmel_tx_dma;
1696 atmel_port->release_tx = &atmel_release_tx_dma;
1697 } else if (atmel_use_pdc_tx(port)) {
1698 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1699 atmel_port->schedule_tx = &atmel_tx_pdc;
1700 atmel_port->release_tx = &atmel_release_tx_pdc;
1702 atmel_port->prepare_tx = NULL;
1703 atmel_port->schedule_tx = &atmel_tx_chars;
1704 atmel_port->release_tx = NULL;
1709 * Get ip name usart or uart
1711 static void atmel_get_ip_name(struct uart_port *port)
1713 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1714 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1717 /* usart and uart ascii */
1721 atmel_port->is_usart = false;
1723 if (name == usart) {
1724 dev_dbg(port->dev, "This is usart\n");
1725 atmel_port->is_usart = true;
1726 } else if (name == uart) {
1727 dev_dbg(port->dev, "This is uart\n");
1728 atmel_port->is_usart = false;
1730 /* fallback for older SoCs: use version field */
1731 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1735 dev_dbg(port->dev, "This version is usart\n");
1736 atmel_port->is_usart = true;
1740 dev_dbg(port->dev, "This version is uart\n");
1741 atmel_port->is_usart = false;
1744 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1750 * Perform initialization and enable port for reception
1752 static int atmel_startup(struct uart_port *port)
1754 struct platform_device *pdev = to_platform_device(port->dev);
1755 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1756 struct tty_struct *tty = port->state->port.tty;
1760 * Ensure that no interrupts are enabled otherwise when
1761 * request_irq() is called we could get stuck trying to
1762 * handle an unexpected interrupt
1764 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1765 atmel_port->ms_irq_enabled = false;
1770 retval = request_irq(port->irq, atmel_interrupt,
1771 IRQF_SHARED | IRQF_COND_SUSPEND,
1772 tty ? tty->name : "atmel_serial", port);
1774 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1778 tasklet_enable(&atmel_port->tasklet);
1781 * Initialize DMA (if necessary)
1783 atmel_init_property(atmel_port, pdev);
1784 atmel_set_ops(port);
1786 if (atmel_port->prepare_rx) {
1787 retval = atmel_port->prepare_rx(port);
1789 atmel_set_ops(port);
1792 if (atmel_port->prepare_tx) {
1793 retval = atmel_port->prepare_tx(port);
1795 atmel_set_ops(port);
1799 * Enable FIFO when available
1801 if (atmel_port->fifo_size) {
1802 unsigned int txrdym = ATMEL_US_ONE_DATA;
1803 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1806 atmel_uart_writel(port, ATMEL_US_CR,
1811 if (atmel_use_dma_tx(port))
1812 txrdym = ATMEL_US_FOUR_DATA;
1814 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1815 if (atmel_port->rts_high &&
1816 atmel_port->rts_low)
1817 fmr |= ATMEL_US_FRTSC |
1818 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1819 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1821 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1824 /* Save current CSR for comparison in atmel_tasklet_func() */
1825 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1826 atmel_port->irq_status = atmel_port->irq_status_prev;
1829 * Finally, enable the serial port
1831 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1832 /* enable xmit & rcvr */
1833 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1835 setup_timer(&atmel_port->uart_timer,
1836 atmel_uart_timer_callback,
1837 (unsigned long)port);
1839 if (atmel_use_pdc_rx(port)) {
1840 /* set UART timeout */
1841 if (!atmel_port->is_usart) {
1842 mod_timer(&atmel_port->uart_timer,
1843 jiffies + uart_poll_timeout(port));
1844 /* set USART timeout */
1846 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1847 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1849 atmel_uart_writel(port, ATMEL_US_IER,
1850 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1852 /* enable PDC controller */
1853 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1854 } else if (atmel_use_dma_rx(port)) {
1855 /* set UART timeout */
1856 if (!atmel_port->is_usart) {
1857 mod_timer(&atmel_port->uart_timer,
1858 jiffies + uart_poll_timeout(port));
1859 /* set USART timeout */
1861 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1862 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1864 atmel_uart_writel(port, ATMEL_US_IER,
1868 /* enable receive only */
1869 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1876 * Flush any TX data submitted for DMA. Called when the TX circular
1879 static void atmel_flush_buffer(struct uart_port *port)
1881 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1883 if (atmel_use_pdc_tx(port)) {
1884 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1885 atmel_port->pdc_tx.ofs = 0;
1892 static void atmel_shutdown(struct uart_port *port)
1894 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1897 * Prevent any tasklets being scheduled during
1900 del_timer_sync(&atmel_port->uart_timer);
1903 * Clear out any scheduled tasklets before
1904 * we destroy the buffers
1906 tasklet_disable(&atmel_port->tasklet);
1907 tasklet_kill(&atmel_port->tasklet);
1910 * Ensure everything is stopped and
1911 * disable all interrupts, port and break condition.
1913 atmel_stop_rx(port);
1914 atmel_stop_tx(port);
1916 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1917 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1921 * Shut-down the DMA.
1923 if (atmel_port->release_rx)
1924 atmel_port->release_rx(port);
1925 if (atmel_port->release_tx)
1926 atmel_port->release_tx(port);
1929 * Reset ring buffer pointers
1931 atmel_port->rx_ring.head = 0;
1932 atmel_port->rx_ring.tail = 0;
1935 * Free the interrupts
1937 free_irq(port->irq, port);
1939 atmel_port->ms_irq_enabled = false;
1941 atmel_flush_buffer(port);
1945 * Power / Clock management.
1947 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1948 unsigned int oldstate)
1950 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1955 * Enable the peripheral clock for this serial port.
1956 * This is called on uart_open() or a resume event.
1958 clk_prepare_enable(atmel_port->clk);
1960 /* re-enable interrupts if we disabled some on suspend */
1961 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
1964 /* Back up the interrupt mask and disable all interrupts */
1965 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
1966 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1969 * Disable the peripheral clock for this serial port.
1970 * This is called on uart_close() or a suspend event.
1972 clk_disable_unprepare(atmel_port->clk);
1975 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1980 * Change the port parameters
1982 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1983 struct ktermios *old)
1985 unsigned long flags;
1986 unsigned int old_mode, mode, imr, quot, baud;
1988 /* save the current mode register */
1989 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1991 /* reset the mode, clock divisor, parity, stop bits and data size */
1992 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
1993 ATMEL_US_PAR | ATMEL_US_USMODE);
1995 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1996 quot = uart_get_divisor(port, baud);
1998 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2000 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2004 switch (termios->c_cflag & CSIZE) {
2006 mode |= ATMEL_US_CHRL_5;
2009 mode |= ATMEL_US_CHRL_6;
2012 mode |= ATMEL_US_CHRL_7;
2015 mode |= ATMEL_US_CHRL_8;
2020 if (termios->c_cflag & CSTOPB)
2021 mode |= ATMEL_US_NBSTOP_2;
2024 if (termios->c_cflag & PARENB) {
2025 /* Mark or Space parity */
2026 if (termios->c_cflag & CMSPAR) {
2027 if (termios->c_cflag & PARODD)
2028 mode |= ATMEL_US_PAR_MARK;
2030 mode |= ATMEL_US_PAR_SPACE;
2031 } else if (termios->c_cflag & PARODD)
2032 mode |= ATMEL_US_PAR_ODD;
2034 mode |= ATMEL_US_PAR_EVEN;
2036 mode |= ATMEL_US_PAR_NONE;
2038 spin_lock_irqsave(&port->lock, flags);
2040 port->read_status_mask = ATMEL_US_OVRE;
2041 if (termios->c_iflag & INPCK)
2042 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2043 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2044 port->read_status_mask |= ATMEL_US_RXBRK;
2046 if (atmel_use_pdc_rx(port))
2047 /* need to enable error interrupts */
2048 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2051 * Characters to ignore
2053 port->ignore_status_mask = 0;
2054 if (termios->c_iflag & IGNPAR)
2055 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2056 if (termios->c_iflag & IGNBRK) {
2057 port->ignore_status_mask |= ATMEL_US_RXBRK;
2059 * If we're ignoring parity and break indicators,
2060 * ignore overruns too (for real raw support).
2062 if (termios->c_iflag & IGNPAR)
2063 port->ignore_status_mask |= ATMEL_US_OVRE;
2065 /* TODO: Ignore all characters if CREAD is set.*/
2067 /* update the per-port timeout */
2068 uart_update_timeout(port, termios->c_cflag, baud);
2071 * save/disable interrupts. The tty layer will ensure that the
2072 * transmitter is empty if requested by the caller, so there's
2073 * no need to wait for it here.
2075 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2076 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2078 /* disable receiver and transmitter */
2079 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2082 if (port->rs485.flags & SER_RS485_ENABLED) {
2083 atmel_uart_writel(port, ATMEL_US_TTGR,
2084 port->rs485.delay_rts_after_send);
2085 mode |= ATMEL_US_USMODE_RS485;
2086 } else if (termios->c_cflag & CRTSCTS) {
2087 /* RS232 with hardware handshake (RTS/CTS) */
2088 mode |= ATMEL_US_USMODE_HWHS;
2090 /* RS232 without hadware handshake */
2091 mode |= ATMEL_US_USMODE_NORMAL;
2094 /* set the mode, clock divisor, parity, stop bits and data size */
2095 atmel_uart_writel(port, ATMEL_US_MR, mode);
2098 * when switching the mode, set the RTS line state according to the
2099 * new mode, otherwise keep the former state
2101 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2102 unsigned int rts_state;
2104 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2105 /* let the hardware control the RTS line */
2106 rts_state = ATMEL_US_RTSDIS;
2108 /* force RTS line to low level */
2109 rts_state = ATMEL_US_RTSEN;
2112 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2115 /* set the baud rate */
2116 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2117 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2118 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2120 /* restore interrupts */
2121 atmel_uart_writel(port, ATMEL_US_IER, imr);
2123 /* CTS flow-control and modem-status interrupts */
2124 if (UART_ENABLE_MS(port, termios->c_cflag))
2125 atmel_enable_ms(port);
2127 atmel_disable_ms(port);
2129 spin_unlock_irqrestore(&port->lock, flags);
2132 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2134 if (termios->c_line == N_PPS) {
2135 port->flags |= UPF_HARDPPS_CD;
2136 spin_lock_irq(&port->lock);
2137 atmel_enable_ms(port);
2138 spin_unlock_irq(&port->lock);
2140 port->flags &= ~UPF_HARDPPS_CD;
2141 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2142 spin_lock_irq(&port->lock);
2143 atmel_disable_ms(port);
2144 spin_unlock_irq(&port->lock);
2150 * Return string describing the specified port
2152 static const char *atmel_type(struct uart_port *port)
2154 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2158 * Release the memory region(s) being used by 'port'.
2160 static void atmel_release_port(struct uart_port *port)
2162 struct platform_device *pdev = to_platform_device(port->dev);
2163 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2165 release_mem_region(port->mapbase, size);
2167 if (port->flags & UPF_IOREMAP) {
2168 iounmap(port->membase);
2169 port->membase = NULL;
2174 * Request the memory region(s) being used by 'port'.
2176 static int atmel_request_port(struct uart_port *port)
2178 struct platform_device *pdev = to_platform_device(port->dev);
2179 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2181 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2184 if (port->flags & UPF_IOREMAP) {
2185 port->membase = ioremap(port->mapbase, size);
2186 if (port->membase == NULL) {
2187 release_mem_region(port->mapbase, size);
2196 * Configure/autoconfigure the port.
2198 static void atmel_config_port(struct uart_port *port, int flags)
2200 if (flags & UART_CONFIG_TYPE) {
2201 port->type = PORT_ATMEL;
2202 atmel_request_port(port);
2207 * Verify the new serial_struct (for TIOCSSERIAL).
2209 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2212 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2214 if (port->irq != ser->irq)
2216 if (ser->io_type != SERIAL_IO_MEM)
2218 if (port->uartclk / 16 != ser->baud_base)
2220 if (port->mapbase != (unsigned long)ser->iomem_base)
2222 if (port->iobase != ser->port)
2229 #ifdef CONFIG_CONSOLE_POLL
2230 static int atmel_poll_get_char(struct uart_port *port)
2232 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2235 return atmel_uart_read_char(port);
2238 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2240 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2243 atmel_uart_write_char(port, ch);
2247 static struct uart_ops atmel_pops = {
2248 .tx_empty = atmel_tx_empty,
2249 .set_mctrl = atmel_set_mctrl,
2250 .get_mctrl = atmel_get_mctrl,
2251 .stop_tx = atmel_stop_tx,
2252 .start_tx = atmel_start_tx,
2253 .stop_rx = atmel_stop_rx,
2254 .enable_ms = atmel_enable_ms,
2255 .break_ctl = atmel_break_ctl,
2256 .startup = atmel_startup,
2257 .shutdown = atmel_shutdown,
2258 .flush_buffer = atmel_flush_buffer,
2259 .set_termios = atmel_set_termios,
2260 .set_ldisc = atmel_set_ldisc,
2262 .release_port = atmel_release_port,
2263 .request_port = atmel_request_port,
2264 .config_port = atmel_config_port,
2265 .verify_port = atmel_verify_port,
2266 .pm = atmel_serial_pm,
2267 #ifdef CONFIG_CONSOLE_POLL
2268 .poll_get_char = atmel_poll_get_char,
2269 .poll_put_char = atmel_poll_put_char,
2274 * Configure the port from the platform device resource info.
2276 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2277 struct platform_device *pdev)
2280 struct uart_port *port = &atmel_port->uart;
2281 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2283 atmel_init_property(atmel_port, pdev);
2284 atmel_set_ops(port);
2286 atmel_init_rs485(port, pdev);
2288 port->iotype = UPIO_MEM;
2289 port->flags = UPF_BOOT_AUTOCONF;
2290 port->ops = &atmel_pops;
2292 port->dev = &pdev->dev;
2293 port->mapbase = pdev->resource[0].start;
2294 port->irq = pdev->resource[1].start;
2295 port->rs485_config = atmel_config_rs485;
2297 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2298 (unsigned long)port);
2299 tasklet_disable(&atmel_port->tasklet);
2301 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2303 if (pdata && pdata->regs) {
2304 /* Already mapped by setup code */
2305 port->membase = pdata->regs;
2307 port->flags |= UPF_IOREMAP;
2308 port->membase = NULL;
2311 /* for console, the clock could already be configured */
2312 if (!atmel_port->clk) {
2313 atmel_port->clk = clk_get(&pdev->dev, "usart");
2314 if (IS_ERR(atmel_port->clk)) {
2315 ret = PTR_ERR(atmel_port->clk);
2316 atmel_port->clk = NULL;
2319 ret = clk_prepare_enable(atmel_port->clk);
2321 clk_put(atmel_port->clk);
2322 atmel_port->clk = NULL;
2325 port->uartclk = clk_get_rate(atmel_port->clk);
2326 clk_disable_unprepare(atmel_port->clk);
2327 /* only enable clock when USART is in use */
2330 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2331 if (port->rs485.flags & SER_RS485_ENABLED)
2332 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2333 else if (atmel_use_pdc_tx(port)) {
2334 port->fifosize = PDC_BUFFER_SIZE;
2335 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2337 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2343 struct platform_device *atmel_default_console_device; /* the serial console device */
2345 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2346 static void atmel_console_putchar(struct uart_port *port, int ch)
2348 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2350 atmel_uart_write_char(port, ch);
2354 * Interrupts are disabled on entering
2356 static void atmel_console_write(struct console *co, const char *s, u_int count)
2358 struct uart_port *port = &atmel_ports[co->index].uart;
2359 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2360 unsigned int status, imr;
2361 unsigned int pdc_tx;
2364 * First, save IMR and then disable interrupts
2366 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2367 atmel_uart_writel(port, ATMEL_US_IDR,
2368 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2370 /* Store PDC transmit status and disable it */
2371 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2372 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2374 uart_console_write(port, s, count, atmel_console_putchar);
2377 * Finally, wait for transmitter to become empty
2381 status = atmel_uart_readl(port, ATMEL_US_CSR);
2382 } while (!(status & ATMEL_US_TXRDY));
2384 /* Restore PDC transmit status */
2386 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2388 /* set interrupts back the way they were */
2389 atmel_uart_writel(port, ATMEL_US_IER, imr);
2393 * If the port was already initialised (eg, by a boot loader),
2394 * try to determine the current setup.
2396 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2397 int *parity, int *bits)
2399 unsigned int mr, quot;
2402 * If the baud rate generator isn't running, the port wasn't
2403 * initialized by the boot loader.
2405 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2409 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2410 if (mr == ATMEL_US_CHRL_8)
2415 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2416 if (mr == ATMEL_US_PAR_EVEN)
2418 else if (mr == ATMEL_US_PAR_ODD)
2422 * The serial core only rounds down when matching this to a
2423 * supported baud rate. Make sure we don't end up slightly
2424 * lower than one of those, as it would make us fall through
2425 * to a much lower baud rate than we really want.
2427 *baud = port->uartclk / (16 * (quot - 1));
2430 static int __init atmel_console_setup(struct console *co, char *options)
2433 struct uart_port *port = &atmel_ports[co->index].uart;
2439 if (port->membase == NULL) {
2440 /* Port not initialized yet - delay setup */
2444 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2448 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2449 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2450 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2453 uart_parse_options(options, &baud, &parity, &bits, &flow);
2455 atmel_console_get_options(port, &baud, &parity, &bits);
2457 return uart_set_options(port, co, baud, parity, bits, flow);
2460 static struct uart_driver atmel_uart;
2462 static struct console atmel_console = {
2463 .name = ATMEL_DEVICENAME,
2464 .write = atmel_console_write,
2465 .device = uart_console_device,
2466 .setup = atmel_console_setup,
2467 .flags = CON_PRINTBUFFER,
2469 .data = &atmel_uart,
2472 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2475 * Early console initialization (before VM subsystem initialized).
2477 static int __init atmel_console_init(void)
2480 if (atmel_default_console_device) {
2481 struct atmel_uart_data *pdata =
2482 dev_get_platdata(&atmel_default_console_device->dev);
2483 int id = pdata->num;
2484 struct atmel_uart_port *port = &atmel_ports[id];
2486 port->backup_imr = 0;
2487 port->uart.line = id;
2489 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2490 ret = atmel_init_port(port, atmel_default_console_device);
2493 register_console(&atmel_console);
2499 console_initcall(atmel_console_init);
2502 * Late console initialization.
2504 static int __init atmel_late_console_init(void)
2506 if (atmel_default_console_device
2507 && !(atmel_console.flags & CON_ENABLED))
2508 register_console(&atmel_console);
2513 core_initcall(atmel_late_console_init);
2515 static inline bool atmel_is_console_port(struct uart_port *port)
2517 return port->cons && port->cons->index == port->line;
2521 #define ATMEL_CONSOLE_DEVICE NULL
2523 static inline bool atmel_is_console_port(struct uart_port *port)
2529 static struct uart_driver atmel_uart = {
2530 .owner = THIS_MODULE,
2531 .driver_name = "atmel_serial",
2532 .dev_name = ATMEL_DEVICENAME,
2533 .major = SERIAL_ATMEL_MAJOR,
2534 .minor = MINOR_START,
2535 .nr = ATMEL_MAX_UART,
2536 .cons = ATMEL_CONSOLE_DEVICE,
2540 static bool atmel_serial_clk_will_stop(void)
2542 #ifdef CONFIG_ARCH_AT91
2543 return at91_suspend_entering_slow_clock();
2549 static int atmel_serial_suspend(struct platform_device *pdev,
2552 struct uart_port *port = platform_get_drvdata(pdev);
2553 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2555 if (atmel_is_console_port(port) && console_suspend_enabled) {
2556 /* Drain the TX shifter */
2557 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2562 /* we can not wake up if we're running on slow clock */
2563 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2564 if (atmel_serial_clk_will_stop()) {
2565 unsigned long flags;
2567 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2568 atmel_port->suspended = true;
2569 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2570 device_set_wakeup_enable(&pdev->dev, 0);
2573 uart_suspend_port(&atmel_uart, port);
2578 static int atmel_serial_resume(struct platform_device *pdev)
2580 struct uart_port *port = platform_get_drvdata(pdev);
2581 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2582 unsigned long flags;
2584 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2585 if (atmel_port->pending) {
2586 atmel_handle_receive(port, atmel_port->pending);
2587 atmel_handle_status(port, atmel_port->pending,
2588 atmel_port->pending_status);
2589 atmel_handle_transmit(port, atmel_port->pending);
2590 atmel_port->pending = 0;
2592 atmel_port->suspended = false;
2593 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2595 uart_resume_port(&atmel_uart, port);
2596 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2601 #define atmel_serial_suspend NULL
2602 #define atmel_serial_resume NULL
2605 static void atmel_serial_probe_fifos(struct atmel_uart_port *port,
2606 struct platform_device *pdev)
2608 port->fifo_size = 0;
2612 if (of_property_read_u32(pdev->dev.of_node,
2617 if (!port->fifo_size)
2620 if (port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2621 port->fifo_size = 0;
2622 dev_err(&pdev->dev, "Invalid FIFO size\n");
2627 * 0 <= rts_low <= rts_high <= fifo_size
2628 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2629 * to flush their internal TX FIFO, commonly up to 16 data, before
2630 * actually stopping to send new data. So we try to set the RTS High
2631 * Threshold to a reasonably high value respecting this 16 data
2632 * empirical rule when possible.
2634 port->rts_high = max_t(int, port->fifo_size >> 1,
2635 port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2636 port->rts_low = max_t(int, port->fifo_size >> 2,
2637 port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2639 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2641 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2643 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2647 static int atmel_serial_probe(struct platform_device *pdev)
2649 struct atmel_uart_port *port;
2650 struct device_node *np = pdev->dev.of_node;
2651 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2656 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2659 ret = of_alias_get_id(np, "serial");
2665 /* port id not found in platform data nor device-tree aliases:
2666 * auto-enumerate it */
2667 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2669 if (ret >= ATMEL_MAX_UART) {
2674 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2675 /* port already in use */
2680 port = &atmel_ports[ret];
2681 port->backup_imr = 0;
2682 port->uart.line = ret;
2683 atmel_serial_probe_fifos(port, pdev);
2685 spin_lock_init(&port->lock_suspended);
2687 ret = atmel_init_port(port, pdev);
2691 port->gpios = mctrl_gpio_init(&port->uart, 0);
2692 if (IS_ERR(port->gpios)) {
2693 ret = PTR_ERR(port->gpios);
2697 if (!atmel_use_pdc_rx(&port->uart)) {
2699 data = kmalloc(sizeof(struct atmel_uart_char)
2700 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2702 goto err_alloc_ring;
2703 port->rx_ring.buf = data;
2706 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED;
2708 ret = uart_add_one_port(&atmel_uart, &port->uart);
2712 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2713 if (atmel_is_console_port(&port->uart)
2714 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2716 * The serial core enabled the clock for us, so undo
2717 * the clk_prepare_enable() in atmel_console_setup()
2719 clk_disable_unprepare(port->clk);
2723 device_init_wakeup(&pdev->dev, 1);
2724 platform_set_drvdata(pdev, port);
2727 * The peripheral clock has been disabled by atmel_init_port():
2728 * enable it before accessing I/O registers
2730 clk_prepare_enable(port->clk);
2732 if (rs485_enabled) {
2733 atmel_uart_writel(&port->uart, ATMEL_US_MR,
2734 ATMEL_US_USMODE_NORMAL);
2735 atmel_uart_writel(&port->uart, ATMEL_US_CR, ATMEL_US_RTSEN);
2739 * Get port name of usart or uart
2741 atmel_get_ip_name(&port->uart);
2744 * The peripheral clock can now safely be disabled till the port
2747 clk_disable_unprepare(port->clk);
2752 kfree(port->rx_ring.buf);
2753 port->rx_ring.buf = NULL;
2755 if (!atmel_is_console_port(&port->uart)) {
2760 clear_bit(port->uart.line, atmel_ports_in_use);
2765 static int atmel_serial_remove(struct platform_device *pdev)
2767 struct uart_port *port = platform_get_drvdata(pdev);
2768 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2771 tasklet_kill(&atmel_port->tasklet);
2773 device_init_wakeup(&pdev->dev, 0);
2775 ret = uart_remove_one_port(&atmel_uart, port);
2777 kfree(atmel_port->rx_ring.buf);
2779 /* "port" is allocated statically, so we shouldn't free it */
2781 clear_bit(port->line, atmel_ports_in_use);
2783 clk_put(atmel_port->clk);
2788 static struct platform_driver atmel_serial_driver = {
2789 .probe = atmel_serial_probe,
2790 .remove = atmel_serial_remove,
2791 .suspend = atmel_serial_suspend,
2792 .resume = atmel_serial_resume,
2794 .name = "atmel_usart",
2795 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2799 static int __init atmel_serial_init(void)
2803 ret = uart_register_driver(&atmel_uart);
2807 ret = platform_driver_register(&atmel_serial_driver);
2809 uart_unregister_driver(&atmel_uart);
2814 static void __exit atmel_serial_exit(void)
2816 platform_driver_unregister(&atmel_serial_driver);
2817 uart_unregister_driver(&atmel_uart);
2820 module_init(atmel_serial_init);
2821 module_exit(atmel_serial_exit);
2823 MODULE_AUTHOR("Rick Bronson");
2824 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
2825 MODULE_LICENSE("GPL");
2826 MODULE_ALIAS("platform:atmel_usart");