2 * Cadence UART driver (found in Xilinx Zynq)
4 * 2011 - 2014 (C) Xilinx Inc.
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
32 #include <linux/module.h>
34 #define CDNS_UART_TTY_NAME "ttyPS"
35 #define CDNS_UART_NAME "xuartps"
36 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38 #define CDNS_UART_NR_PORTS 2
39 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40 #define CDNS_UART_REGISTER_SPACE 0x1000
42 /* Rx Trigger level */
43 static int rx_trigger_level = 56;
44 module_param(rx_trigger_level, uint, S_IRUGO);
45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
48 static int rx_timeout = 10;
49 module_param(rx_timeout, uint, S_IRUGO);
50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
52 /* Register offsets for the UART. */
53 #define CDNS_UART_CR 0x00 /* Control Register */
54 #define CDNS_UART_MR 0x04 /* Mode Register */
55 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
56 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
57 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
58 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
59 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
60 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
61 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
62 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
63 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
64 #define CDNS_UART_SR 0x2C /* Channel Status */
65 #define CDNS_UART_FIFO 0x30 /* FIFO */
66 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
67 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
68 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
69 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
70 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
71 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
73 /* Control Register Bit Definitions */
74 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
75 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
76 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
77 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
78 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
79 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
80 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
81 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
82 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
83 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
84 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
85 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
89 * The mode register (MR) defines the mode of transfer as well as the data
90 * format. If this register is modified during transmission or reception,
91 * data validity cannot be guaranteed.
93 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
94 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
95 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
97 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
98 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
100 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
101 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
102 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
103 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
104 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
106 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
107 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
108 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
111 * Interrupt Registers:
112 * Interrupt control logic uses the interrupt enable register (IER) and the
113 * interrupt disable register (IDR) to set the value of the bits in the
114 * interrupt mask register (IMR). The IMR determines whether to pass an
115 * interrupt to the interrupt status register (ISR).
116 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
117 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
118 * Reading either IER or IDR returns 0x00.
119 * All four registers have the same bit definitions.
121 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
122 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
123 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
124 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
125 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
126 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
127 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
128 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
129 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
130 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
131 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
133 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_PARITY | CDNS_UART_IXR_FRAMING | \
134 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_RXTRIG | \
137 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
138 #define CDNS_UART_IXR_BRK 0x00002000
140 #define CDNS_UART_RXBS_SUPPORT BIT(1)
142 * Modem Control register:
143 * The read/write Modem Control register controls the interface with the modem
144 * or data set, or a peripheral device emulating a modem.
146 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
147 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
148 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
151 * Channel Status Register:
152 * The channel status register (CSR) is provided to enable the control logic
153 * to monitor the status of bits in the channel interrupt status register,
154 * even if these are masked out by the interrupt mask register.
156 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
157 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
158 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
159 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
161 /* baud dividers min/max values */
162 #define CDNS_UART_BDIV_MIN 4
163 #define CDNS_UART_BDIV_MAX 255
164 #define CDNS_UART_CD_MAX 65535
167 * struct cdns_uart - device data
168 * @port: Pointer to the UART port
169 * @uartclk: Reference clock
171 * @baud: Current baud rate
172 * @clk_rate_change_nb: Notifier block for clock changes
175 struct uart_port *port;
179 struct notifier_block clk_rate_change_nb;
182 struct cdns_platform_data {
185 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
188 static void cdns_uart_handle_rx(struct uart_port *port, unsigned int isrstatus)
190 struct cdns_uart *cdns_uart = port->private_data;
191 bool is_rxbs_support;
192 unsigned int rxbs_status = 0;
193 unsigned int status_mask;
195 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
198 * There is no hardware break detection, so we interpret framing
199 * error with all-zeros data as a break sequence. Most of the time,
200 * there's another non-zero byte at the end of the sequence.
202 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
203 while (!(readl(port->membase + CDNS_UART_SR) &
204 CDNS_UART_SR_RXEMPTY)) {
205 if (!readl(port->membase + CDNS_UART_FIFO)) {
206 port->read_status_mask |= CDNS_UART_IXR_BRK;
207 isrstatus &= ~CDNS_UART_IXR_FRAMING;
210 writel(CDNS_UART_IXR_FRAMING, port->membase + CDNS_UART_ISR);
213 /* drop byte with parity error if IGNPAR specified */
214 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
215 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
217 isrstatus &= port->read_status_mask;
218 isrstatus &= ~port->ignore_status_mask;
219 status_mask = port->read_status_mask;
220 status_mask &= ~port->ignore_status_mask;
222 if (!(isrstatus & (CDNS_UART_IXR_TOUT | CDNS_UART_IXR_RXTRIG)))
225 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)) {
227 char status = TTY_NORMAL;
230 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
232 data = readl(port->membase + CDNS_UART_FIFO);
234 /* Non-NULL byte after BREAK is garbage (99%) */
235 if (data && (port->read_status_mask & CDNS_UART_IXR_BRK)) {
236 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
238 if (uart_handle_break(port))
241 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
244 if (uart_handle_break(port))
248 if (uart_handle_sysrq_char(port, data))
253 if (is_rxbs_support) {
254 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
255 && (status_mask & CDNS_UART_IXR_PARITY)) {
256 port->icount.parity++;
259 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
260 && (status_mask & CDNS_UART_IXR_PARITY)) {
261 port->icount.frame++;
265 if (isrstatus & CDNS_UART_IXR_PARITY) {
266 port->icount.parity++;
269 if (isrstatus & CDNS_UART_IXR_FRAMING) {
270 port->icount.frame++;
274 if (isrstatus & CDNS_UART_IXR_OVERRUN)
275 port->icount.overrun++;
277 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
280 tty_flip_buffer_push(&port->state->port);
283 static void cdns_uart_handle_tx(struct uart_port *port)
285 unsigned int numbytes;
287 if (uart_circ_empty(&port->state->xmit)) {
288 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
292 numbytes = port->fifosize;
293 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
294 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
296 * Get the data from the UART circular buffer
297 * and write it to the cdns_uart's TX_FIFO
300 writel(port->state->xmit.buf[port->state->xmit.tail],
301 port->membase + CDNS_UART_FIFO);
305 * Adjust the tail of the UART buffer and wrap
306 * the buffer if it reaches limit.
308 port->state->xmit.tail =
309 (port->state->xmit.tail + 1) & (UART_XMIT_SIZE - 1);
314 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
315 uart_write_wakeup(port);
319 * cdns_uart_isr - Interrupt handler
321 * @dev_id: Id of the port
325 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
327 struct uart_port *port = (struct uart_port *)dev_id;
329 unsigned int isrstatus;
331 spin_lock_irqsave(&port->lock, flags);
333 /* Read the interrupt status register to determine which
334 * interrupt(s) is/are active.
336 isrstatus = readl(port->membase + CDNS_UART_ISR);
338 if (isrstatus & CDNS_UART_RX_IRQS)
339 cdns_uart_handle_rx(port, isrstatus);
341 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY)
342 cdns_uart_handle_tx(port);
344 writel(isrstatus, port->membase + CDNS_UART_ISR);
346 /* be sure to release the lock and tty before leaving */
347 spin_unlock_irqrestore(&port->lock, flags);
353 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
354 * @clk: UART module input clock
355 * @baud: Desired baud rate
356 * @rbdiv: BDIV value (return value)
357 * @rcd: CD value (return value)
358 * @div8: Value for clk_sel bit in mod (return value)
359 * Return: baud rate, requested baud when possible, or actual baud when there
360 * was too much error, zero if no valid divisors are found.
362 * Formula to obtain baud rate is
363 * baud_tx/rx rate = clk/CD * (BDIV + 1)
364 * input_clk = (Uart User Defined Clock or Apb Clock)
365 * depends on UCLKEN in MR Reg
366 * clk = input_clk or input_clk/8;
367 * depends on CLKS in MR reg
368 * CD and BDIV depends on values in
369 * baud rate generate register
370 * baud rate clock divisor register
372 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
373 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
376 unsigned int calc_baud;
377 unsigned int bestbaud = 0;
378 unsigned int bauderror;
379 unsigned int besterror = ~0;
381 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
388 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
389 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
390 if (cd < 1 || cd > CDNS_UART_CD_MAX)
393 calc_baud = clk / (cd * (bdiv + 1));
395 if (baud > calc_baud)
396 bauderror = baud - calc_baud;
398 bauderror = calc_baud - baud;
400 if (besterror > bauderror) {
403 bestbaud = calc_baud;
404 besterror = bauderror;
407 /* use the values when percent error is acceptable */
408 if (((besterror * 100) / baud) < 3)
415 * cdns_uart_set_baud_rate - Calculate and set the baud rate
416 * @port: Handle to the uart port structure
417 * @baud: Baud rate to set
418 * Return: baud rate, requested baud when possible, or actual baud when there
419 * was too much error, zero if no valid divisors are found.
421 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
424 unsigned int calc_baud;
425 u32 cd = 0, bdiv = 0;
428 struct cdns_uart *cdns_uart = port->private_data;
430 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
433 /* Write new divisors to hardware */
434 mreg = readl(port->membase + CDNS_UART_MR);
436 mreg |= CDNS_UART_MR_CLKSEL;
438 mreg &= ~CDNS_UART_MR_CLKSEL;
439 writel(mreg, port->membase + CDNS_UART_MR);
440 writel(cd, port->membase + CDNS_UART_BAUDGEN);
441 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
442 cdns_uart->baud = baud;
447 #ifdef CONFIG_COMMON_CLK
449 * cdns_uart_clk_notitifer_cb - Clock notifier callback
450 * @nb: Notifier block
451 * @event: Notify event
452 * @data: Notifier data
453 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
455 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
456 unsigned long event, void *data)
459 struct uart_port *port;
461 struct clk_notifier_data *ndata = data;
462 unsigned long flags = 0;
463 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
465 port = cdns_uart->port;
470 case PRE_RATE_CHANGE:
476 * Find out if current baud-rate can be achieved with new clock
479 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
480 &bdiv, &cd, &div8)) {
481 dev_warn(port->dev, "clock rate change rejected\n");
485 spin_lock_irqsave(&cdns_uart->port->lock, flags);
487 /* Disable the TX and RX to set baud rate */
488 ctrl_reg = readl(port->membase + CDNS_UART_CR);
489 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
490 writel(ctrl_reg, port->membase + CDNS_UART_CR);
492 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
496 case POST_RATE_CHANGE:
498 * Set clk dividers to generate correct baud with new clock
502 spin_lock_irqsave(&cdns_uart->port->lock, flags);
505 port->uartclk = ndata->new_rate;
507 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
510 case ABORT_RATE_CHANGE:
512 spin_lock_irqsave(&cdns_uart->port->lock, flags);
514 /* Set TX/RX Reset */
515 ctrl_reg = readl(port->membase + CDNS_UART_CR);
516 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
517 writel(ctrl_reg, port->membase + CDNS_UART_CR);
519 while (readl(port->membase + CDNS_UART_CR) &
520 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
524 * Clear the RX disable and TX disable bits and then set the TX
525 * enable bit and RX enable bit to enable the transmitter and
528 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
529 ctrl_reg = readl(port->membase + CDNS_UART_CR);
530 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
531 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
532 writel(ctrl_reg, port->membase + CDNS_UART_CR);
534 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
544 * cdns_uart_start_tx - Start transmitting bytes
545 * @port: Handle to the uart port structure
547 static void cdns_uart_start_tx(struct uart_port *port)
551 if (uart_tx_stopped(port))
555 * Set the TX enable bit and clear the TX disable bit to enable the
558 status = readl(port->membase + CDNS_UART_CR);
559 status &= ~CDNS_UART_CR_TX_DIS;
560 status |= CDNS_UART_CR_TX_EN;
561 writel(status, port->membase + CDNS_UART_CR);
563 if (uart_circ_empty(&port->state->xmit))
566 cdns_uart_handle_tx(port);
568 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
569 /* Enable the TX Empty interrupt */
570 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
574 * cdns_uart_stop_tx - Stop TX
575 * @port: Handle to the uart port structure
577 static void cdns_uart_stop_tx(struct uart_port *port)
581 regval = readl(port->membase + CDNS_UART_CR);
582 regval |= CDNS_UART_CR_TX_DIS;
583 /* Disable the transmitter */
584 writel(regval, port->membase + CDNS_UART_CR);
588 * cdns_uart_stop_rx - Stop RX
589 * @port: Handle to the uart port structure
591 static void cdns_uart_stop_rx(struct uart_port *port)
595 /* Disable RX IRQs */
596 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
598 /* Disable the receiver */
599 regval = readl(port->membase + CDNS_UART_CR);
600 regval |= CDNS_UART_CR_RX_DIS;
601 writel(regval, port->membase + CDNS_UART_CR);
605 * cdns_uart_tx_empty - Check whether TX is empty
606 * @port: Handle to the uart port structure
608 * Return: TIOCSER_TEMT on success, 0 otherwise
610 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
614 status = readl(port->membase + CDNS_UART_SR) &
615 CDNS_UART_SR_TXEMPTY;
616 return status ? TIOCSER_TEMT : 0;
620 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
621 * transmitting char breaks
622 * @port: Handle to the uart port structure
623 * @ctl: Value based on which start or stop decision is taken
625 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
630 spin_lock_irqsave(&port->lock, flags);
632 status = readl(port->membase + CDNS_UART_CR);
635 writel(CDNS_UART_CR_STARTBRK | status,
636 port->membase + CDNS_UART_CR);
638 if ((status & CDNS_UART_CR_STOPBRK) == 0)
639 writel(CDNS_UART_CR_STOPBRK | status,
640 port->membase + CDNS_UART_CR);
642 spin_unlock_irqrestore(&port->lock, flags);
646 * cdns_uart_set_termios - termios operations, handling data length, parity,
647 * stop bits, flow control, baud rate
648 * @port: Handle to the uart port structure
649 * @termios: Handle to the input termios structure
650 * @old: Values of the previously saved termios structure
652 static void cdns_uart_set_termios(struct uart_port *port,
653 struct ktermios *termios, struct ktermios *old)
655 unsigned int cval = 0;
656 unsigned int baud, minbaud, maxbaud;
658 unsigned int ctrl_reg, mode_reg;
660 spin_lock_irqsave(&port->lock, flags);
662 /* Wait for the transmit FIFO to empty before making changes */
663 if (!(readl(port->membase + CDNS_UART_CR) &
664 CDNS_UART_CR_TX_DIS)) {
665 while (!(readl(port->membase + CDNS_UART_SR) &
666 CDNS_UART_SR_TXEMPTY)) {
671 /* Disable the TX and RX to set baud rate */
672 ctrl_reg = readl(port->membase + CDNS_UART_CR);
673 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
674 writel(ctrl_reg, port->membase + CDNS_UART_CR);
677 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
678 * min and max baud should be calculated here based on port->uartclk.
679 * this way we get a valid baud and can safely call set_baud()
681 minbaud = port->uartclk /
682 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
683 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
684 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
685 baud = cdns_uart_set_baud_rate(port, baud);
686 if (tty_termios_baud_rate(termios))
687 tty_termios_encode_baud_rate(termios, baud, baud);
689 /* Update the per-port timeout. */
690 uart_update_timeout(port, termios->c_cflag, baud);
692 /* Set TX/RX Reset */
693 ctrl_reg = readl(port->membase + CDNS_UART_CR);
694 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
695 writel(ctrl_reg, port->membase + CDNS_UART_CR);
698 * Clear the RX disable and TX disable bits and then set the TX enable
699 * bit and RX enable bit to enable the transmitter and receiver.
701 ctrl_reg = readl(port->membase + CDNS_UART_CR);
702 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
703 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
704 writel(ctrl_reg, port->membase + CDNS_UART_CR);
706 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
708 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
709 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
710 port->ignore_status_mask = 0;
712 if (termios->c_iflag & INPCK)
713 port->read_status_mask |= CDNS_UART_IXR_PARITY |
714 CDNS_UART_IXR_FRAMING;
716 if (termios->c_iflag & IGNPAR)
717 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
718 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
720 /* ignore all characters if CREAD is not set */
721 if ((termios->c_cflag & CREAD) == 0)
722 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
723 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
724 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
726 mode_reg = readl(port->membase + CDNS_UART_MR);
728 /* Handling Data Size */
729 switch (termios->c_cflag & CSIZE) {
731 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
734 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
738 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
739 termios->c_cflag &= ~CSIZE;
740 termios->c_cflag |= CS8;
744 /* Handling Parity and Stop Bits length */
745 if (termios->c_cflag & CSTOPB)
746 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
748 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
750 if (termios->c_cflag & PARENB) {
751 /* Mark or Space parity */
752 if (termios->c_cflag & CMSPAR) {
753 if (termios->c_cflag & PARODD)
754 cval |= CDNS_UART_MR_PARITY_MARK;
756 cval |= CDNS_UART_MR_PARITY_SPACE;
758 if (termios->c_cflag & PARODD)
759 cval |= CDNS_UART_MR_PARITY_ODD;
761 cval |= CDNS_UART_MR_PARITY_EVEN;
764 cval |= CDNS_UART_MR_PARITY_NONE;
766 cval |= mode_reg & 1;
767 writel(cval, port->membase + CDNS_UART_MR);
769 spin_unlock_irqrestore(&port->lock, flags);
773 * cdns_uart_startup - Called when an application opens a cdns_uart port
774 * @port: Handle to the uart port structure
776 * Return: 0 on success, negative errno otherwise
778 static int cdns_uart_startup(struct uart_port *port)
780 struct cdns_uart *cdns_uart = port->private_data;
784 unsigned int status = 0;
786 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
788 spin_lock_irqsave(&port->lock, flags);
790 /* Disable the TX and RX */
791 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
792 port->membase + CDNS_UART_CR);
794 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
797 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
798 port->membase + CDNS_UART_CR);
801 * Clear the RX disable bit and then set the RX enable bit to enable
804 status = readl(port->membase + CDNS_UART_CR);
805 status &= CDNS_UART_CR_RX_DIS;
806 status |= CDNS_UART_CR_RX_EN;
807 writel(status, port->membase + CDNS_UART_CR);
809 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
812 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
813 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
814 port->membase + CDNS_UART_MR);
817 * Set the RX FIFO Trigger level to use most of the FIFO, but it
818 * can be tuned with a module parameter
820 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
823 * Receive Timeout register is enabled but it
824 * can be tuned with a module parameter
826 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
828 /* Clear out any pending interrupts before enabling them */
829 writel(readl(port->membase + CDNS_UART_ISR),
830 port->membase + CDNS_UART_ISR);
832 spin_unlock_irqrestore(&port->lock, flags);
834 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
836 dev_err(port->dev, "request_irq '%d' failed with %d\n",
841 /* Set the Interrupt Registers with desired interrupts */
843 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
844 port->membase + CDNS_UART_IER);
846 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
852 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
853 * @port: Handle to the uart port structure
855 static void cdns_uart_shutdown(struct uart_port *port)
860 spin_lock_irqsave(&port->lock, flags);
862 /* Disable interrupts */
863 status = readl(port->membase + CDNS_UART_IMR);
864 writel(status, port->membase + CDNS_UART_IDR);
865 writel(0xffffffff, port->membase + CDNS_UART_ISR);
867 /* Disable the TX and RX */
868 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
869 port->membase + CDNS_UART_CR);
871 spin_unlock_irqrestore(&port->lock, flags);
873 free_irq(port->irq, port);
877 * cdns_uart_type - Set UART type to cdns_uart port
878 * @port: Handle to the uart port structure
880 * Return: string on success, NULL otherwise
882 static const char *cdns_uart_type(struct uart_port *port)
884 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
888 * cdns_uart_verify_port - Verify the port params
889 * @port: Handle to the uart port structure
890 * @ser: Handle to the structure whose members are compared
892 * Return: 0 on success, negative errno otherwise.
894 static int cdns_uart_verify_port(struct uart_port *port,
895 struct serial_struct *ser)
897 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
899 if (port->irq != ser->irq)
901 if (ser->io_type != UPIO_MEM)
903 if (port->iobase != ser->port)
911 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
912 * called when the driver adds a cdns_uart port via
913 * uart_add_one_port()
914 * @port: Handle to the uart port structure
916 * Return: 0 on success, negative errno otherwise.
918 static int cdns_uart_request_port(struct uart_port *port)
920 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
925 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
926 if (!port->membase) {
927 dev_err(port->dev, "Unable to map registers\n");
928 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
935 * cdns_uart_release_port - Release UART port
936 * @port: Handle to the uart port structure
938 * Release the memory region attached to a cdns_uart port. Called when the
939 * driver removes a cdns_uart port via uart_remove_one_port().
941 static void cdns_uart_release_port(struct uart_port *port)
943 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
944 iounmap(port->membase);
945 port->membase = NULL;
949 * cdns_uart_config_port - Configure UART port
950 * @port: Handle to the uart port structure
953 static void cdns_uart_config_port(struct uart_port *port, int flags)
955 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
956 port->type = PORT_XUARTPS;
960 * cdns_uart_get_mctrl - Get the modem control state
961 * @port: Handle to the uart port structure
963 * Return: the modem control state
965 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
967 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
970 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
974 val = readl(port->membase + CDNS_UART_MODEMCR);
976 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
978 if (mctrl & TIOCM_RTS)
979 val |= CDNS_UART_MODEMCR_RTS;
980 if (mctrl & TIOCM_DTR)
981 val |= CDNS_UART_MODEMCR_DTR;
983 writel(val, port->membase + CDNS_UART_MODEMCR);
986 #ifdef CONFIG_CONSOLE_POLL
987 static int cdns_uart_poll_get_char(struct uart_port *port)
992 spin_lock_irqsave(&port->lock, flags);
994 /* Check if FIFO is empty */
995 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
997 else /* Read a character */
998 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1000 spin_unlock_irqrestore(&port->lock, flags);
1005 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1007 unsigned long flags;
1009 spin_lock_irqsave(&port->lock, flags);
1011 /* Wait until FIFO is empty */
1012 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1015 /* Write a character */
1016 writel(c, port->membase + CDNS_UART_FIFO);
1018 /* Wait until FIFO is empty */
1019 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1022 spin_unlock_irqrestore(&port->lock, flags);
1028 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1029 unsigned int oldstate)
1031 struct cdns_uart *cdns_uart = port->private_data;
1034 case UART_PM_STATE_OFF:
1035 clk_disable(cdns_uart->uartclk);
1036 clk_disable(cdns_uart->pclk);
1039 clk_enable(cdns_uart->pclk);
1040 clk_enable(cdns_uart->uartclk);
1045 static const struct uart_ops cdns_uart_ops = {
1046 .set_mctrl = cdns_uart_set_mctrl,
1047 .get_mctrl = cdns_uart_get_mctrl,
1048 .start_tx = cdns_uart_start_tx,
1049 .stop_tx = cdns_uart_stop_tx,
1050 .stop_rx = cdns_uart_stop_rx,
1051 .tx_empty = cdns_uart_tx_empty,
1052 .break_ctl = cdns_uart_break_ctl,
1053 .set_termios = cdns_uart_set_termios,
1054 .startup = cdns_uart_startup,
1055 .shutdown = cdns_uart_shutdown,
1057 .type = cdns_uart_type,
1058 .verify_port = cdns_uart_verify_port,
1059 .request_port = cdns_uart_request_port,
1060 .release_port = cdns_uart_release_port,
1061 .config_port = cdns_uart_config_port,
1062 #ifdef CONFIG_CONSOLE_POLL
1063 .poll_get_char = cdns_uart_poll_get_char,
1064 .poll_put_char = cdns_uart_poll_put_char,
1068 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1071 * cdns_uart_get_port - Configure the port from platform device resource info
1074 * Return: a pointer to a uart_port or NULL for failure
1076 static struct uart_port *cdns_uart_get_port(int id)
1078 struct uart_port *port;
1080 /* Try the given port id if failed use default method */
1081 if (cdns_uart_port[id].mapbase != 0) {
1082 /* Find the next unused port */
1083 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1084 if (cdns_uart_port[id].mapbase == 0)
1088 if (id >= CDNS_UART_NR_PORTS)
1091 port = &cdns_uart_port[id];
1093 /* At this point, we've got an empty uart_port struct, initialize it */
1094 spin_lock_init(&port->lock);
1095 port->membase = NULL;
1097 port->type = PORT_UNKNOWN;
1098 port->iotype = UPIO_MEM32;
1099 port->flags = UPF_BOOT_AUTOCONF;
1100 port->ops = &cdns_uart_ops;
1101 port->fifosize = CDNS_UART_FIFO_SIZE;
1107 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1109 * cdns_uart_console_wait_tx - Wait for the TX to be full
1110 * @port: Handle to the uart port structure
1112 static void cdns_uart_console_wait_tx(struct uart_port *port)
1114 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1119 * cdns_uart_console_putchar - write the character to the FIFO buffer
1120 * @port: Handle to the uart port structure
1121 * @ch: Character to be written
1123 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1125 cdns_uart_console_wait_tx(port);
1126 writel(ch, port->membase + CDNS_UART_FIFO);
1129 static void __init cdns_early_write(struct console *con, const char *s,
1132 struct earlycon_device *dev = con->data;
1134 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1137 static int __init cdns_early_console_setup(struct earlycon_device *device,
1140 if (!device->port.membase)
1143 device->con->write = cdns_early_write;
1147 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1148 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1149 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1152 * cdns_uart_console_write - perform write operation
1153 * @co: Console handle
1154 * @s: Pointer to character array
1155 * @count: No of characters
1157 static void cdns_uart_console_write(struct console *co, const char *s,
1160 struct uart_port *port = &cdns_uart_port[co->index];
1161 unsigned long flags;
1162 unsigned int imr, ctrl;
1167 else if (oops_in_progress)
1168 locked = spin_trylock_irqsave(&port->lock, flags);
1170 spin_lock_irqsave(&port->lock, flags);
1172 /* save and disable interrupt */
1173 imr = readl(port->membase + CDNS_UART_IMR);
1174 writel(imr, port->membase + CDNS_UART_IDR);
1177 * Make sure that the tx part is enabled. Set the TX enable bit and
1178 * clear the TX disable bit to enable the transmitter.
1180 ctrl = readl(port->membase + CDNS_UART_CR);
1181 ctrl &= ~CDNS_UART_CR_TX_DIS;
1182 ctrl |= CDNS_UART_CR_TX_EN;
1183 writel(ctrl, port->membase + CDNS_UART_CR);
1185 uart_console_write(port, s, count, cdns_uart_console_putchar);
1186 cdns_uart_console_wait_tx(port);
1188 writel(ctrl, port->membase + CDNS_UART_CR);
1190 /* restore interrupt state */
1191 writel(imr, port->membase + CDNS_UART_IER);
1194 spin_unlock_irqrestore(&port->lock, flags);
1198 * cdns_uart_console_setup - Initialize the uart to default config
1199 * @co: Console handle
1200 * @options: Initial settings of uart
1202 * Return: 0 on success, negative errno otherwise.
1204 static int __init cdns_uart_console_setup(struct console *co, char *options)
1206 struct uart_port *port = &cdns_uart_port[co->index];
1212 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1215 if (!port->membase) {
1216 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1222 uart_parse_options(options, &baud, &parity, &bits, &flow);
1224 return uart_set_options(port, co, baud, parity, bits, flow);
1227 static struct uart_driver cdns_uart_uart_driver;
1229 static struct console cdns_uart_console = {
1230 .name = CDNS_UART_TTY_NAME,
1231 .write = cdns_uart_console_write,
1232 .device = uart_console_device,
1233 .setup = cdns_uart_console_setup,
1234 .flags = CON_PRINTBUFFER,
1235 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1236 .data = &cdns_uart_uart_driver,
1240 * cdns_uart_console_init - Initialization call
1242 * Return: 0 on success, negative errno otherwise
1244 static int __init cdns_uart_console_init(void)
1246 register_console(&cdns_uart_console);
1250 console_initcall(cdns_uart_console_init);
1252 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1254 static struct uart_driver cdns_uart_uart_driver = {
1255 .owner = THIS_MODULE,
1256 .driver_name = CDNS_UART_NAME,
1257 .dev_name = CDNS_UART_TTY_NAME,
1258 .major = CDNS_UART_MAJOR,
1259 .minor = CDNS_UART_MINOR,
1260 .nr = CDNS_UART_NR_PORTS,
1261 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1262 .cons = &cdns_uart_console,
1266 #ifdef CONFIG_PM_SLEEP
1268 * cdns_uart_suspend - suspend event
1269 * @device: Pointer to the device structure
1273 static int cdns_uart_suspend(struct device *device)
1275 struct uart_port *port = dev_get_drvdata(device);
1276 struct tty_struct *tty;
1277 struct device *tty_dev;
1280 /* Get the tty which could be NULL so don't assume it's valid */
1281 tty = tty_port_tty_get(&port->state->port);
1284 may_wake = device_may_wakeup(tty_dev);
1289 * Call the API provided in serial_core.c file which handles
1292 uart_suspend_port(&cdns_uart_uart_driver, port);
1293 if (console_suspend_enabled && !may_wake) {
1294 struct cdns_uart *cdns_uart = port->private_data;
1296 clk_disable(cdns_uart->uartclk);
1297 clk_disable(cdns_uart->pclk);
1299 unsigned long flags = 0;
1301 spin_lock_irqsave(&port->lock, flags);
1302 /* Empty the receive FIFO 1st before making changes */
1303 while (!(readl(port->membase + CDNS_UART_SR) &
1304 CDNS_UART_SR_RXEMPTY))
1305 readl(port->membase + CDNS_UART_FIFO);
1306 /* set RX trigger level to 1 */
1307 writel(1, port->membase + CDNS_UART_RXWM);
1308 /* disable RX timeout interrups */
1309 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1310 spin_unlock_irqrestore(&port->lock, flags);
1317 * cdns_uart_resume - Resume after a previous suspend
1318 * @device: Pointer to the device structure
1322 static int cdns_uart_resume(struct device *device)
1324 struct uart_port *port = dev_get_drvdata(device);
1325 unsigned long flags = 0;
1327 struct tty_struct *tty;
1328 struct device *tty_dev;
1331 /* Get the tty which could be NULL so don't assume it's valid */
1332 tty = tty_port_tty_get(&port->state->port);
1335 may_wake = device_may_wakeup(tty_dev);
1339 if (console_suspend_enabled && !may_wake) {
1340 struct cdns_uart *cdns_uart = port->private_data;
1342 clk_enable(cdns_uart->pclk);
1343 clk_enable(cdns_uart->uartclk);
1345 spin_lock_irqsave(&port->lock, flags);
1347 /* Set TX/RX Reset */
1348 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1349 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1350 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1351 while (readl(port->membase + CDNS_UART_CR) &
1352 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1355 /* restore rx timeout value */
1356 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1358 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1359 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1360 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1361 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1363 spin_unlock_irqrestore(&port->lock, flags);
1365 spin_lock_irqsave(&port->lock, flags);
1366 /* restore original rx trigger level */
1367 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1368 /* enable RX timeout interrupt */
1369 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1370 spin_unlock_irqrestore(&port->lock, flags);
1373 return uart_resume_port(&cdns_uart_uart_driver, port);
1375 #endif /* ! CONFIG_PM_SLEEP */
1377 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1380 static const struct cdns_platform_data zynqmp_uart_def = {
1381 .quirks = CDNS_UART_RXBS_SUPPORT, };
1383 /* Match table for of_platform binding */
1384 static const struct of_device_id cdns_uart_of_match[] = {
1385 { .compatible = "xlnx,xuartps", },
1386 { .compatible = "cdns,uart-r1p8", },
1387 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1390 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1393 * cdns_uart_probe - Platform driver probe
1394 * @pdev: Pointer to the platform device structure
1396 * Return: 0 on success, negative errno otherwise
1398 static int cdns_uart_probe(struct platform_device *pdev)
1401 struct uart_port *port;
1402 struct resource *res;
1403 struct cdns_uart *cdns_uart_data;
1404 const struct of_device_id *match;
1406 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1408 if (!cdns_uart_data)
1411 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1412 if (match && match->data) {
1413 const struct cdns_platform_data *data = match->data;
1415 cdns_uart_data->quirks = data->quirks;
1418 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1419 if (IS_ERR(cdns_uart_data->pclk)) {
1420 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1421 if (!IS_ERR(cdns_uart_data->pclk))
1422 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1424 if (IS_ERR(cdns_uart_data->pclk)) {
1425 dev_err(&pdev->dev, "pclk clock not found.\n");
1426 return PTR_ERR(cdns_uart_data->pclk);
1429 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1430 if (IS_ERR(cdns_uart_data->uartclk)) {
1431 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1432 if (!IS_ERR(cdns_uart_data->uartclk))
1433 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1435 if (IS_ERR(cdns_uart_data->uartclk)) {
1436 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1437 return PTR_ERR(cdns_uart_data->uartclk);
1440 rc = clk_prepare(cdns_uart_data->pclk);
1442 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1445 rc = clk_prepare(cdns_uart_data->uartclk);
1447 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1448 goto err_out_clk_dis_pclk;
1451 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1454 goto err_out_clk_disable;
1457 irq = platform_get_irq(pdev, 0);
1460 goto err_out_clk_disable;
1463 #ifdef CONFIG_COMMON_CLK
1464 cdns_uart_data->clk_rate_change_nb.notifier_call =
1465 cdns_uart_clk_notifier_cb;
1466 if (clk_notifier_register(cdns_uart_data->uartclk,
1467 &cdns_uart_data->clk_rate_change_nb))
1468 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1470 /* Look for a serialN alias */
1471 id = of_alias_get_id(pdev->dev.of_node, "serial");
1475 /* Initialize the port structure */
1476 port = cdns_uart_get_port(id);
1479 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1481 goto err_out_notif_unreg;
1485 * Register the port.
1486 * This function also registers this device with the tty layer
1487 * and triggers invocation of the config_port() entry point.
1489 port->mapbase = res->start;
1491 port->dev = &pdev->dev;
1492 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1493 port->private_data = cdns_uart_data;
1494 cdns_uart_data->port = port;
1495 platform_set_drvdata(pdev, port);
1497 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1500 "uart_add_one_port() failed; err=%i\n", rc);
1501 goto err_out_notif_unreg;
1506 err_out_notif_unreg:
1507 #ifdef CONFIG_COMMON_CLK
1508 clk_notifier_unregister(cdns_uart_data->uartclk,
1509 &cdns_uart_data->clk_rate_change_nb);
1511 err_out_clk_disable:
1512 clk_unprepare(cdns_uart_data->uartclk);
1513 err_out_clk_dis_pclk:
1514 clk_unprepare(cdns_uart_data->pclk);
1520 * cdns_uart_remove - called when the platform driver is unregistered
1521 * @pdev: Pointer to the platform device structure
1523 * Return: 0 on success, negative errno otherwise
1525 static int cdns_uart_remove(struct platform_device *pdev)
1527 struct uart_port *port = platform_get_drvdata(pdev);
1528 struct cdns_uart *cdns_uart_data = port->private_data;
1531 /* Remove the cdns_uart port from the serial core */
1532 #ifdef CONFIG_COMMON_CLK
1533 clk_notifier_unregister(cdns_uart_data->uartclk,
1534 &cdns_uart_data->clk_rate_change_nb);
1536 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1538 clk_unprepare(cdns_uart_data->uartclk);
1539 clk_unprepare(cdns_uart_data->pclk);
1543 static struct platform_driver cdns_uart_platform_driver = {
1544 .probe = cdns_uart_probe,
1545 .remove = cdns_uart_remove,
1547 .name = CDNS_UART_NAME,
1548 .of_match_table = cdns_uart_of_match,
1549 .pm = &cdns_uart_dev_pm_ops,
1553 static int __init cdns_uart_init(void)
1557 /* Register the cdns_uart driver with the serial core */
1558 retval = uart_register_driver(&cdns_uart_uart_driver);
1562 /* Register the platform driver */
1563 retval = platform_driver_register(&cdns_uart_platform_driver);
1565 uart_unregister_driver(&cdns_uart_uart_driver);
1570 static void __exit cdns_uart_exit(void)
1572 /* Unregister the platform driver */
1573 platform_driver_unregister(&cdns_uart_platform_driver);
1575 /* Unregister the cdns_uart driver */
1576 uart_unregister_driver(&cdns_uart_uart_driver);
1579 module_init(cdns_uart_init);
1580 module_exit(cdns_uart_exit);
1582 MODULE_DESCRIPTION("Driver for Cadence UART");
1583 MODULE_AUTHOR("Xilinx Inc.");
1584 MODULE_LICENSE("GPL");