2 * ci.h - common structures, functions, and macros of the ChipIdea driver
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14 #define __DRIVERS_USB_CHIPIDEA_CI_H
16 #include <linux/list.h>
17 #include <linux/irqreturn.h>
18 #include <linux/usb.h>
19 #include <linux/usb/gadget.h>
20 #include <linux/usb/otg-fsm.h>
22 /******************************************************************************
24 *****************************************************************************/
25 #define TD_PAGE_COUNT 5
26 #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
29 /******************************************************************************
31 *****************************************************************************/
32 /* Identification Registers */
34 #define ID_HWGENERAL 0x4
36 #define ID_HWDEVICE 0xc
37 #define ID_HWTXBUF 0x10
38 #define ID_HWRXBUF 0x14
39 #define ID_SBUSCFG 0x90
41 /* register indices */
47 CAP_LAST = CAP_TESTMODE,
63 /* endptctrl1..15 follow */
64 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
67 /******************************************************************************
69 *****************************************************************************/
71 * struct ci_hw_ep - endpoint representation
72 * @ep: endpoint structure for gadget drivers
73 * @dir: endpoint direction (TX/RX)
74 * @num: endpoint number
75 * @type: endpoint type
76 * @name: string description of the endpoint
77 * @qh: queue head for this endpoint
78 * @wedge: is the endpoint wedged
79 * @ci: pointer to the controller
80 * @lock: pointer to controller's spinlock
81 * @td_pool: pointer to controller's TD pool
90 struct list_head queue;
96 /* global resources */
99 struct dma_pool *td_pool;
100 struct td_node *pending_td;
110 CI_REVISION_1X = 10, /* Revision 1.x */
111 CI_REVISION_20 = 20, /* Revision 2.0 */
112 CI_REVISION_21, /* Revision 2.1 */
113 CI_REVISION_22, /* Revision 2.2 */
114 CI_REVISION_23, /* Revision 2.3 */
115 CI_REVISION_24, /* Revision 2.4 */
116 CI_REVISION_25, /* Revision 2.5 */
117 CI_REVISION_25_PLUS, /* Revision above than 2.5 */
118 CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
122 * struct ci_role_driver - host/gadget role driver
123 * @start: start this role
124 * @stop: stop this role
125 * @irq: irq handler for this role
126 * @name: role name string (host/gadget)
128 struct ci_role_driver {
129 int (*start)(struct ci_hdrc *);
130 void (*stop)(struct ci_hdrc *);
131 irqreturn_t (*irq)(struct ci_hdrc *);
136 * struct hw_bank - hardware register mapping representation
137 * @lpm: set if the device is LPM capable
138 * @phys: physical address of the controller's registers
139 * @abs: absolute address of the beginning of register window
140 * @cap: capability registers
141 * @op: operational registers
142 * @size: size of the register window
143 * @regmap: register lookup table
147 resource_size_t phys;
152 void __iomem *regmap[OP_LAST + 1];
156 * struct ci_hdrc - chipidea device representation
157 * @dev: pointer to parent device
158 * @lock: access synchronization
159 * @hw_bank: hardware register mapping
161 * @roles: array of supported roles for this controller
162 * @role: current role
163 * @is_otg: if the device is otg-capable
164 * @fsm: otg finite state machine
165 * @fsm_timer: pointer to timer list of otg fsm
166 * @work: work for role changing
167 * @wq: workqueue thread
168 * @qh_pool: allocation pool for queue heads
169 * @td_pool: allocation pool for transfer descriptors
170 * @gadget: device side representation for peripheral controller
171 * @driver: gadget driver
172 * @hw_ep_max: total number of endpoints supported by hardware
173 * @ci_hw_ep: array of endpoints
174 * @ep0_dir: ep0 direction
175 * @ep0out: pointer to ep0 OUT endpoint
176 * @ep0in: pointer to ep0 IN endpoint
177 * @status: ep0 status request
178 * @setaddr: if we should set the address on status completion
179 * @address: usb address received from the host
180 * @remote_wakeup: host-enabled remote wakeup
181 * @suspended: suspended by host
182 * @test_mode: the selected test mode
183 * @platdata: platform specific information supplied by parent device
184 * @vbus_active: is VBUS active
185 * @phy: pointer to PHY, if any
186 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
187 * @hcd: pointer to usb_hcd for ehci host driver
188 * @debugfs: root dentry for this controller in debugfs
189 * @id_event: indicates there is an id event, and handled at ci_otg_work
190 * @b_sess_valid_event: indicates there is a vbus event, and handled
192 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
193 * @supports_runtime_pm: if runtime pm is supported
194 * @in_lpm: if the core in low power mode
195 * @wakeup_int: if wakeup interrupt occur
196 * @rev: The revision number for controller
201 struct hw_bank hw_bank;
203 struct ci_role_driver *roles[CI_ROLE_END];
208 struct ci_otg_fsm_timer_list *fsm_timer;
209 struct work_struct work;
210 struct workqueue_struct *wq;
212 struct dma_pool *qh_pool;
213 struct dma_pool *td_pool;
215 struct usb_gadget gadget;
216 struct usb_gadget_driver *driver;
218 struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
220 struct ci_hw_ep *ep0out, *ep0in;
222 struct usb_request *status;
229 struct ci_hdrc_platform_data *platdata;
232 /* old usb_phy interface */
233 struct usb_phy *usb_phy;
235 struct dentry *debugfs;
237 bool b_sess_valid_event;
238 bool imx28_write_fix;
239 bool supports_runtime_pm;
242 enum ci_revision rev;
245 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
247 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
248 return ci->roles[ci->role];
251 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
255 if (role >= CI_ROLE_END)
258 if (!ci->roles[role])
261 ret = ci->roles[role]->start(ci);
267 static inline void ci_role_stop(struct ci_hdrc *ci)
269 enum ci_role role = ci->role;
271 if (role == CI_ROLE_END)
274 ci->role = CI_ROLE_END;
276 ci->roles[role]->stop(ci);
280 * hw_read_id_reg: reads from a identification register
281 * @ci: the controller
282 * @offset: offset from the beginning of identification registers region
283 * @mask: bitfield mask
285 * This function returns register contents
287 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
289 return ioread32(ci->hw_bank.abs + offset) & mask;
293 * hw_write_id_reg: writes to a identification register
294 * @ci: the controller
295 * @offset: offset from the beginning of identification registers region
296 * @mask: bitfield mask
299 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
303 data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
306 iowrite32(data, ci->hw_bank.abs + offset);
310 * hw_read: reads from a hw register
311 * @ci: the controller
312 * @reg: register index
313 * @mask: bitfield mask
315 * This function returns register contents
317 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
319 return ioread32(ci->hw_bank.regmap[reg]) & mask;
322 #ifdef CONFIG_SOC_IMX28
323 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
325 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
328 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
333 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
336 if (ci->imx28_write_fix)
337 imx28_ci_writel(val, addr);
339 iowrite32(val, addr);
343 * hw_write: writes to a hw register
344 * @ci: the controller
345 * @reg: register index
346 * @mask: bitfield mask
349 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
353 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
356 __hw_write(ci, data, ci->hw_bank.regmap[reg]);
360 * hw_test_and_clear: tests & clears a hw register
361 * @ci: the controller
362 * @reg: register index
363 * @mask: bitfield mask
365 * This function returns register contents
367 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
370 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
372 __hw_write(ci, val, ci->hw_bank.regmap[reg]);
377 * hw_test_and_write: tests & writes a hw register
378 * @ci: the controller
379 * @reg: register index
380 * @mask: bitfield mask
383 * This function returns register contents
385 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
388 u32 val = hw_read(ci, reg, ~0);
390 hw_write(ci, reg, mask, data);
391 return (val & mask) >> __ffs(mask);
395 * ci_otg_is_fsm_mode: runtime check if otg controller
396 * is in otg fsm mode.
398 * @ci: chipidea device
400 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
402 #ifdef CONFIG_USB_OTG_FSM
403 return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
404 ci->roles[CI_ROLE_GADGET];
410 u32 hw_read_intr_enable(struct ci_hdrc *ci);
412 u32 hw_read_intr_status(struct ci_hdrc *ci);
414 int hw_device_reset(struct ci_hdrc *ci);
416 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
418 u8 hw_port_test_get(struct ci_hdrc *ci);
420 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
421 u32 value, unsigned int timeout_ms);
423 #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */