drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "core.h"
  45 #include "gadget.h"
  46 #include "io.h"
  47
  48 #include "debug.h"
  49
  50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  51
  52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  53 {
  54         u32 reg;
  55
  56         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  57         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  58         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  59         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  60 }
  61
  62 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
  63 {
  64         struct dwc3             *dwc = dep->dwc;
  65         u32                     reg;
  66
  67         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
  68                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
  69                         DWC3_GDBGFIFOSPACE_TYPE(type));
  70
  71         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
  72
  73         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
  74 }
  75
  76 /**
  77  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  78  * @dwc: pointer to our context structure
  79  */
  80 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  81 {
  82         u32             reg;
  83         int             retries = 1000;
  84         int             ret;
  85
  86         usb_phy_init(dwc->usb2_phy);
  87         usb_phy_init(dwc->usb3_phy);
  88         ret = phy_init(dwc->usb2_generic_phy);
  89         if (ret < 0)
  90                 return ret;
  91
  92         ret = phy_init(dwc->usb3_generic_phy);
  93         if (ret < 0) {
  94                 phy_exit(dwc->usb2_generic_phy);
  95                 return ret;
  96         }
  97
  98         /*
  99          * We're resetting only the device side because, if we're in host mode,
 100          * XHCI driver will reset the host block. If dwc3 was configured for
 101          * host-only mode, then we can return early.
 102          */
 103         if (dwc->dr_mode == USB_DR_MODE_HOST)
 104                 return 0;
 105
 106         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 107         reg |= DWC3_DCTL_CSFTRST;
 108         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 109
 110         do {
 111                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 112                 if (!(reg & DWC3_DCTL_CSFTRST))
 113                         return 0;
 114
 115                 udelay(1);
 116         } while (--retries);
 117
 118         return -ETIMEDOUT;
 119 }
 120
 121 /**
 122  * dwc3_soft_reset - Issue soft reset
 123  * @dwc: Pointer to our controller context structure
 124  */
 125 static int dwc3_soft_reset(struct dwc3 *dwc)
 126 {
 127         unsigned long timeout;
 128         u32 reg;
 129
 130         timeout = jiffies + msecs_to_jiffies(500);
 131         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 132         do {
 133                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 134                 if (!(reg & DWC3_DCTL_CSFTRST))
 135                         break;
 136
 137                 if (time_after(jiffies, timeout)) {
 138                         dev_err(dwc->dev, "Reset Timed Out\n");
 139                         return -ETIMEDOUT;
 140                 }
 141
 142                 cpu_relax();
 143         } while (true);
 144
 145         return 0;
 146 }
 147
 148 /*
 149  * dwc3_frame_length_adjustment - Adjusts frame length if required
 150  * @dwc3: Pointer to our controller context structure
 151  */
 152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 153 {
 154         u32 reg;
 155         u32 dft;
 156
 157         if (dwc->revision < DWC3_REVISION_250A)
 158                 return;
 159
 160         if (dwc->fladj == 0)
 161                 return;
 162
 163         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 164         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 165         if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
 166             "request value same as default, ignoring\n")) {
 167                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 168                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 169                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 170         }
 171 }
 172
 173 /**
 174  * dwc3_free_one_event_buffer - Frees one event buffer
 175  * @dwc: Pointer to our controller context structure
 176  * @evt: Pointer to event buffer to be freed
 177  */
 178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 179                 struct dwc3_event_buffer *evt)
 180 {
 181         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 182 }
 183
 184 /**
 185  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 186  * @dwc: Pointer to our controller context structure
 187  * @length: size of the event buffer
 188  *
 189  * Returns a pointer to the allocated event buffer structure on success
 190  * otherwise ERR_PTR(errno).
 191  */
 192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 193                 unsigned length)
 194 {
 195         struct dwc3_event_buffer        *evt;
 196
 197         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 198         if (!evt)
 199                 return ERR_PTR(-ENOMEM);
 200
 201         evt->dwc        = dwc;
 202         evt->length     = length;
 203         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 204                         &evt->dma, GFP_KERNEL);
 205         if (!evt->buf)
 206                 return ERR_PTR(-ENOMEM);
 207
 208         return evt;
 209 }
 210
 211 /**
 212  * dwc3_free_event_buffers - frees all allocated event buffers
 213  * @dwc: Pointer to our controller context structure
 214  */
 215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 216 {
 217         struct dwc3_event_buffer        *evt;
 218
 219         evt = dwc->ev_buf;
 220         if (evt)
 221                 dwc3_free_one_event_buffer(dwc, evt);
 222 }
 223
 224 /**
 225  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 226  * @dwc: pointer to our controller context structure
 227  * @length: size of event buffer
 228  *
 229  * Returns 0 on success otherwise negative errno. In the error case, dwc
 230  * may contain some buffers allocated but not all which were requested.
 231  */
 232 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 233 {
 234         struct dwc3_event_buffer *evt;
 235
 236         evt = dwc3_alloc_one_event_buffer(dwc, length);
 237         if (IS_ERR(evt)) {
 238                 dev_err(dwc->dev, "can't allocate event buffer\n");
 239                 return PTR_ERR(evt);
 240         }
 241         dwc->ev_buf = evt;
 242
 243         return 0;
 244 }
 245
 246 /**
 247  * dwc3_event_buffers_setup - setup our allocated event buffers
 248  * @dwc: pointer to our controller context structure
 249  *
 250  * Returns 0 on success otherwise negative errno.
 251  */
 252 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 253 {
 254         struct dwc3_event_buffer        *evt;
 255
 256         evt = dwc->ev_buf;
 257         dwc3_trace(trace_dwc3_core,
 258                         "Event buf %p dma %08llx length %d\n",
 259                         evt->buf, (unsigned long long) evt->dma,
 260                         evt->length);
 261
 262         evt->lpos = 0;
 263
 264         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 265                         lower_32_bits(evt->dma));
 266         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 267                         upper_32_bits(evt->dma));
 268         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 269                         DWC3_GEVNTSIZ_SIZE(evt->length));
 270         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 271
 272         return 0;
 273 }
 274
 275 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 276 {
 277         struct dwc3_event_buffer        *evt;
 278
 279         evt = dwc->ev_buf;
 280
 281         evt->lpos = 0;
 282
 283         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 284         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 285         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 286                         | DWC3_GEVNTSIZ_SIZE(0));
 287         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 288 }
 289
 290 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 291 {
 292         if (!dwc->has_hibernation)
 293                 return 0;
 294
 295         if (!dwc->nr_scratch)
 296                 return 0;
 297
 298         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 299                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 300         if (!dwc->scratchbuf)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 307 {
 308         dma_addr_t scratch_addr;
 309         u32 param;
 310         int ret;
 311
 312         if (!dwc->has_hibernation)
 313                 return 0;
 314
 315         if (!dwc->nr_scratch)
 316                 return 0;
 317
 318          /* should never fall here */
 319         if (!WARN_ON(dwc->scratchbuf))
 320                 return 0;
 321
 322         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 323                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 324                         DMA_BIDIRECTIONAL);
 325         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 326                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 327                 ret = -EFAULT;
 328                 goto err0;
 329         }
 330
 331         dwc->scratch_addr = scratch_addr;
 332
 333         param = lower_32_bits(scratch_addr);
 334
 335         ret = dwc3_send_gadget_generic_command(dwc,
 336                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 337         if (ret < 0)
 338                 goto err1;
 339
 340         param = upper_32_bits(scratch_addr);
 341
 342         ret = dwc3_send_gadget_generic_command(dwc,
 343                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 344         if (ret < 0)
 345                 goto err1;
 346
 347         return 0;
 348
 349 err1:
 350         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 351                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 352
 353 err0:
 354         return ret;
 355 }
 356
 357 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 358 {
 359         if (!dwc->has_hibernation)
 360                 return;
 361
 362         if (!dwc->nr_scratch)
 363                 return;
 364
 365          /* should never fall here */
 366         if (!WARN_ON(dwc->scratchbuf))
 367                 return;
 368
 369         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 370                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 371         kfree(dwc->scratchbuf);
 372 }
 373
 374 static void dwc3_core_num_eps(struct dwc3 *dwc)
 375 {
 376         struct dwc3_hwparams    *parms = &dwc->hwparams;
 377
 378         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 379         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 380
 381         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 382                         dwc->num_in_eps, dwc->num_out_eps);
 383 }
 384
 385 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 386 {
 387         struct dwc3_hwparams    *parms = &dwc->hwparams;
 388
 389         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 390         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 391         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 392         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 393         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 394         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 395         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 396         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 397         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 398 }
 399
 400 /**
 401  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 402  * @dwc: Pointer to our controller context structure
 403  *
 404  * Returns 0 on success. The USB PHY interfaces are configured but not
 405  * initialized. The PHY interfaces and the PHYs get initialized together with
 406  * the core in dwc3_core_init.
 407  */
 408 static int dwc3_phy_setup(struct dwc3 *dwc)
 409 {
 410         u32 reg;
 411         int ret;
 412
 413         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 414
 415         /*
 416          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 417          * to '0' during coreConsultant configuration. So default value
 418          * will be '0' when the core is reset. Application needs to set it
 419          * to '1' after the core initialization is completed.
 420          */
 421         if (dwc->revision > DWC3_REVISION_194A)
 422                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 423
 424         if (dwc->u2ss_inp3_quirk)
 425                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 426
 427         if (dwc->dis_rxdet_inp3_quirk)
 428                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 429
 430         if (dwc->req_p1p2p3_quirk)
 431                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 432
 433         if (dwc->del_p1p2p3_quirk)
 434                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 435
 436         if (dwc->del_phy_power_chg_quirk)
 437                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 438
 439         if (dwc->lfps_filter_quirk)
 440                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 441
 442         if (dwc->rx_detect_poll_quirk)
 443                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 444
 445         if (dwc->tx_de_emphasis_quirk)
 446                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 447
 448         if (dwc->dis_u3_susphy_quirk)
 449                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 450
 451         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 452
 453         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 454
 455         /* Select the HS PHY interface */
 456         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 457         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 458                 if (dwc->hsphy_interface &&
 459                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 460                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 461                         break;
 462                 } else if (dwc->hsphy_interface &&
 463                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 464                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 465                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 466                 } else {
 467                         /* Relying on default value. */
 468                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 469                                 break;
 470                 }
 471                 /* FALLTHROUGH */
 472         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 473                 /* Making sure the interface and PHY are operational */
 474                 ret = dwc3_soft_reset(dwc);
 475                 if (ret)
 476                         return ret;
 477
 478                 udelay(1);
 479
 480                 ret = dwc3_ulpi_init(dwc);
 481                 if (ret)
 482                         return ret;
 483                 /* FALLTHROUGH */
 484         default:
 485                 break;
 486         }
 487
 488         switch (dwc->hsphy_mode) {
 489         case USBPHY_INTERFACE_MODE_UTMI:
 490                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 491                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 492                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 493                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 494                 break;
 495         case USBPHY_INTERFACE_MODE_UTMIW:
 496                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 497                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 498                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 499                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 500                 break;
 501         default:
 502                 break;
 503         }
 504
 505         /*
 506          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 507          * '0' during coreConsultant configuration. So default value will
 508          * be '0' when the core is reset. Application needs to set it to
 509          * '1' after the core initialization is completed.
 510          */
 511         if (dwc->revision > DWC3_REVISION_194A)
 512                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 513
 514         if (dwc->dis_u2_susphy_quirk)
 515                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 516
 517         if (dwc->dis_enblslpm_quirk)
 518                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 519
 520         if (dwc->dis_u2_freeclk_exists_quirk)
 521                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 522
 523         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 524
 525         return 0;
 526 }
 527
 528 static void dwc3_core_exit(struct dwc3 *dwc)
 529 {
 530         dwc3_event_buffers_cleanup(dwc);
 531
 532         usb_phy_shutdown(dwc->usb2_phy);
 533         usb_phy_shutdown(dwc->usb3_phy);
 534         phy_exit(dwc->usb2_generic_phy);
 535         phy_exit(dwc->usb3_generic_phy);
 536
 537         usb_phy_set_suspend(dwc->usb2_phy, 1);
 538         usb_phy_set_suspend(dwc->usb3_phy, 1);
 539         phy_power_off(dwc->usb2_generic_phy);
 540         phy_power_off(dwc->usb3_generic_phy);
 541 }
 542
 543 /**
 544  * dwc3_core_init - Low-level initialization of DWC3 Core
 545  * @dwc: Pointer to our controller context structure
 546  *
 547  * Returns 0 on success otherwise negative errno.
 548  */
 549 static int dwc3_core_init(struct dwc3 *dwc)
 550 {
 551         u32                     hwparams4 = dwc->hwparams.hwparams4;
 552         u32                     reg;
 553         int                     ret;
 554
 555         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 556         /* This should read as U3 followed by revision number */
 557         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 558                 /* Detected DWC_usb3 IP */
 559                 dwc->revision = reg;
 560         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 561                 /* Detected DWC_usb31 IP */
 562                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 563                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 564         } else {
 565                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 566                 ret = -ENODEV;
 567                 goto err0;
 568         }
 569
 570         /*
 571          * Write Linux Version Code to our GUID register so it's easy to figure
 572          * out which kernel version a bug was found.
 573          */
 574         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 575
 576         /* Handle USB2.0-only core configuration */
 577         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 578                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 579                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 580                         dwc->maximum_speed = USB_SPEED_HIGH;
 581         }
 582
 583         /* issue device SoftReset too */
 584         ret = dwc3_soft_reset(dwc);
 585         if (ret)
 586                 goto err0;
 587
 588         ret = dwc3_core_soft_reset(dwc);
 589         if (ret)
 590                 goto err0;
 591
 592         ret = dwc3_phy_setup(dwc);
 593         if (ret)
 594                 goto err0;
 595
 596         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 597         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 598
 599         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 600         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 601                 /**
 602                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 603                  * issue which would cause xHCI compliance tests to fail.
 604                  *
 605                  * Because of that we cannot enable clock gating on such
 606                  * configurations.
 607                  *
 608                  * Refers to:
 609                  *
 610                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 611                  * SOF/ITP Mode Used
 612                  */
 613                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 614                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 615                                 (dwc->revision >= DWC3_REVISION_210A &&
 616                                 dwc->revision <= DWC3_REVISION_250A))
 617                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 618                 else
 619                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 620                 break;
 621         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 622                 /* enable hibernation here */
 623                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 624
 625                 /*
 626                  * REVISIT Enabling this bit so that host-mode hibernation
 627                  * will work. Device-mode hibernation is not yet implemented.
 628                  */
 629                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 630                 break;
 631         default:
 632                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 633         }
 634
 635         /* check if current dwc3 is on simulation board */
 636         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 637                 dwc3_trace(trace_dwc3_core,
 638                                 "running on FPGA platform\n");
 639                 dwc->is_fpga = true;
 640         }
 641
 642         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 643                         "disable_scramble cannot be used on non-FPGA builds\n");
 644
 645         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 646                 reg |= DWC3_GCTL_DISSCRAMBLE;
 647         else
 648                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 649
 650         if (dwc->u2exit_lfps_quirk)
 651                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 652
 653         /*
 654          * WORKAROUND: DWC3 revisions <1.90a have a bug
 655          * where the device can fail to connect at SuperSpeed
 656          * and falls back to high-speed mode which causes
 657          * the device to enter a Connect/Disconnect loop
 658          */
 659         if (dwc->revision < DWC3_REVISION_190A)
 660                 reg |= DWC3_GCTL_U2RSTECN;
 661
 662         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 663
 664         dwc3_core_num_eps(dwc);
 665
 666         ret = dwc3_setup_scratch_buffers(dwc);
 667         if (ret)
 668                 goto err1;
 669
 670         /* Adjust Frame Length */
 671         dwc3_frame_length_adjustment(dwc);
 672
 673         usb_phy_set_suspend(dwc->usb2_phy, 0);
 674         usb_phy_set_suspend(dwc->usb3_phy, 0);
 675         ret = phy_power_on(dwc->usb2_generic_phy);
 676         if (ret < 0)
 677                 goto err2;
 678
 679         ret = phy_power_on(dwc->usb3_generic_phy);
 680         if (ret < 0)
 681                 goto err3;
 682
 683         ret = dwc3_event_buffers_setup(dwc);
 684         if (ret) {
 685                 dev_err(dwc->dev, "failed to setup event buffers\n");
 686                 goto err4;
 687         }
 688
 689         return 0;
 690
 691 err4:
 692         phy_power_off(dwc->usb2_generic_phy);
 693
 694 err3:
 695         phy_power_off(dwc->usb3_generic_phy);
 696
 697 err2:
 698         usb_phy_set_suspend(dwc->usb2_phy, 1);
 699         usb_phy_set_suspend(dwc->usb3_phy, 1);
 700         dwc3_core_exit(dwc);
 701
 702 err1:
 703         usb_phy_shutdown(dwc->usb2_phy);
 704         usb_phy_shutdown(dwc->usb3_phy);
 705         phy_exit(dwc->usb2_generic_phy);
 706         phy_exit(dwc->usb3_generic_phy);
 707
 708 err0:
 709         return ret;
 710 }
 711
 712 static int dwc3_core_get_phy(struct dwc3 *dwc)
 713 {
 714         struct device           *dev = dwc->dev;
 715         struct device_node      *node = dev->of_node;
 716         int ret;
 717
 718         if (node) {
 719                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 720                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 721         } else {
 722                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 723                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 724         }
 725
 726         if (IS_ERR(dwc->usb2_phy)) {
 727                 ret = PTR_ERR(dwc->usb2_phy);
 728                 if (ret == -ENXIO || ret == -ENODEV) {
 729                         dwc->usb2_phy = NULL;
 730                 } else if (ret == -EPROBE_DEFER) {
 731                         return ret;
 732                 } else {
 733                         dev_err(dev, "no usb2 phy configured\n");
 734                         return ret;
 735                 }
 736         }
 737
 738         if (IS_ERR(dwc->usb3_phy)) {
 739                 ret = PTR_ERR(dwc->usb3_phy);
 740                 if (ret == -ENXIO || ret == -ENODEV) {
 741                         dwc->usb3_phy = NULL;
 742                 } else if (ret == -EPROBE_DEFER) {
 743                         return ret;
 744                 } else {
 745                         dev_err(dev, "no usb3 phy configured\n");
 746                         return ret;
 747                 }
 748         }
 749
 750         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 751         if (IS_ERR(dwc->usb2_generic_phy)) {
 752                 ret = PTR_ERR(dwc->usb2_generic_phy);
 753                 if (ret == -ENOSYS || ret == -ENODEV) {
 754                         dwc->usb2_generic_phy = NULL;
 755                 } else if (ret == -EPROBE_DEFER) {
 756                         return ret;
 757                 } else {
 758                         dev_err(dev, "no usb2 phy configured\n");
 759                         return ret;
 760                 }
 761         }
 762
 763         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 764         if (IS_ERR(dwc->usb3_generic_phy)) {
 765                 ret = PTR_ERR(dwc->usb3_generic_phy);
 766                 if (ret == -ENOSYS || ret == -ENODEV) {
 767                         dwc->usb3_generic_phy = NULL;
 768                 } else if (ret == -EPROBE_DEFER) {
 769                         return ret;
 770                 } else {
 771                         dev_err(dev, "no usb3 phy configured\n");
 772                         return ret;
 773                 }
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int dwc3_core_init_mode(struct dwc3 *dwc)
 780 {
 781         struct device *dev = dwc->dev;
 782         int ret;
 783
 784         switch (dwc->dr_mode) {
 785         case USB_DR_MODE_PERIPHERAL:
 786                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 787                 ret = dwc3_gadget_init(dwc);
 788                 if (ret) {
 789                         if (ret != -EPROBE_DEFER)
 790                                 dev_err(dev, "failed to initialize gadget\n");
 791                         return ret;
 792                 }
 793                 break;
 794         case USB_DR_MODE_HOST:
 795                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 796                 ret = dwc3_host_init(dwc);
 797                 if (ret) {
 798                         if (ret != -EPROBE_DEFER)
 799                                 dev_err(dev, "failed to initialize host\n");
 800                         return ret;
 801                 }
 802                 break;
 803         case USB_DR_MODE_OTG:
 804                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 805                 ret = dwc3_host_init(dwc);
 806                 if (ret) {
 807                         if (ret != -EPROBE_DEFER)
 808                                 dev_err(dev, "failed to initialize host\n");
 809                         return ret;
 810                 }
 811
 812                 ret = dwc3_gadget_init(dwc);
 813                 if (ret) {
 814                         if (ret != -EPROBE_DEFER)
 815                                 dev_err(dev, "failed to initialize gadget\n");
 816                         return ret;
 817                 }
 818                 break;
 819         default:
 820                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 821                 return -EINVAL;
 822         }
 823
 824         return 0;
 825 }
 826
 827 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 828 {
 829         switch (dwc->dr_mode) {
 830         case USB_DR_MODE_PERIPHERAL:
 831                 dwc3_gadget_exit(dwc);
 832                 break;
 833         case USB_DR_MODE_HOST:
 834                 dwc3_host_exit(dwc);
 835                 break;
 836         case USB_DR_MODE_OTG:
 837                 dwc3_host_exit(dwc);
 838                 dwc3_gadget_exit(dwc);
 839                 break;
 840         default:
 841                 /* do nothing */
 842                 break;
 843         }
 844 }
 845
 846 #define DWC3_ALIGN_MASK         (16 - 1)
 847
 848 static int dwc3_probe(struct platform_device *pdev)
 849 {
 850         struct device           *dev = &pdev->dev;
 851         struct resource         *res;
 852         struct dwc3             *dwc;
 853         u8                      lpm_nyet_threshold;
 854         u8                      tx_de_emphasis;
 855         u8                      hird_threshold;
 856
 857         int                     ret;
 858
 859         void __iomem            *regs;
 860         void                    *mem;
 861
 862         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 863         if (!mem)
 864                 return -ENOMEM;
 865
 866         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 867         dwc->mem = mem;
 868         dwc->dev = dev;
 869
 870         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 871         if (!res) {
 872                 dev_err(dev, "missing memory resource\n");
 873                 return -ENODEV;
 874         }
 875
 876         dwc->xhci_resources[0].start = res->start;
 877         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 878                                         DWC3_XHCI_REGS_END;
 879         dwc->xhci_resources[0].flags = res->flags;
 880         dwc->xhci_resources[0].name = res->name;
 881
 882         res->start += DWC3_GLOBALS_REGS_START;
 883
 884         /*
 885          * Request memory region but exclude xHCI regs,
 886          * since it will be requested by the xhci-plat driver.
 887          */
 888         regs = devm_ioremap_resource(dev, res);
 889         if (IS_ERR(regs)) {
 890                 ret = PTR_ERR(regs);
 891                 goto err0;
 892         }
 893
 894         dwc->regs       = regs;
 895         dwc->regs_size  = resource_size(res);
 896
 897         /* default to highest possible threshold */
 898         lpm_nyet_threshold = 0xff;
 899
 900         /* default to -3.5dB de-emphasis */
 901         tx_de_emphasis = 1;
 902
 903         /*
 904          * default to assert utmi_sleep_n and use maximum allowed HIRD
 905          * threshold value of 0b1100
 906          */
 907         hird_threshold = 12;
 908
 909         dwc->maximum_speed = usb_get_maximum_speed(dev);
 910         dwc->dr_mode = usb_get_dr_mode(dev);
 911         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
 912
 913         dwc->has_lpm_erratum = device_property_read_bool(dev,
 914                                 "snps,has-lpm-erratum");
 915         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 916                                 &lpm_nyet_threshold);
 917         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 918                                 "snps,is-utmi-l1-suspend");
 919         device_property_read_u8(dev, "snps,hird-threshold",
 920                                 &hird_threshold);
 921         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 922                                 "snps,usb3_lpm_capable");
 923
 924         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 925                                 "snps,disable_scramble_quirk");
 926         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 927                                 "snps,u2exit_lfps_quirk");
 928         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
 929                                 "snps,u2ss_inp3_quirk");
 930         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
 931                                 "snps,req_p1p2p3_quirk");
 932         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
 933                                 "snps,del_p1p2p3_quirk");
 934         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
 935                                 "snps,del_phy_power_chg_quirk");
 936         dwc->lfps_filter_quirk = device_property_read_bool(dev,
 937                                 "snps,lfps_filter_quirk");
 938         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
 939                                 "snps,rx_detect_poll_quirk");
 940         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
 941                                 "snps,dis_u3_susphy_quirk");
 942         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
 943                                 "snps,dis_u2_susphy_quirk");
 944         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
 945                                 "snps,dis_enblslpm_quirk");
 946         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
 947                                 "snps,dis_rxdet_inp3_quirk");
 948         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 949                                 "snps,dis-u2-freeclk-exists-quirk");
 950
 951         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 952                                 "snps,tx_de_emphasis_quirk");
 953         device_property_read_u8(dev, "snps,tx_de_emphasis",
 954                                 &tx_de_emphasis);
 955         device_property_read_string(dev, "snps,hsphy_interface",
 956                                     &dwc->hsphy_interface);
 957         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
 958                                  &dwc->fladj);
 959
 960         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 961         dwc->tx_de_emphasis = tx_de_emphasis;
 962
 963         dwc->hird_threshold = hird_threshold
 964                 | (dwc->is_utmi_l1_suspend << 4);
 965
 966         platform_set_drvdata(pdev, dwc);
 967         dwc3_cache_hwparams(dwc);
 968
 969         ret = dwc3_core_get_phy(dwc);
 970         if (ret)
 971                 goto err0;
 972
 973         spin_lock_init(&dwc->lock);
 974
 975         if (!dev->dma_mask) {
 976                 dev->dma_mask = dev->parent->dma_mask;
 977                 dev->dma_parms = dev->parent->dma_parms;
 978                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 979         }
 980
 981         pm_runtime_set_active(dev);
 982         pm_runtime_use_autosuspend(dev);
 983         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
 984         pm_runtime_enable(dev);
 985         ret = pm_runtime_get_sync(dev);
 986         if (ret < 0)
 987                 goto err1;
 988
 989         pm_runtime_forbid(dev);
 990
 991         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 992         if (ret) {
 993                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 994                 ret = -ENOMEM;
 995                 goto err2;
 996         }
 997
 998         if (IS_ENABLED(CONFIG_USB_DWC3_HOST) &&
 999                         (dwc->dr_mode == USB_DR_MODE_OTG ||
1000                                         dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1001                 dwc->dr_mode = USB_DR_MODE_HOST;
1002         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET) &&
1003                         (dwc->dr_mode == USB_DR_MODE_OTG ||
1004                                         dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1005                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1006
1007         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1008                 dwc->dr_mode = USB_DR_MODE_OTG;
1009
1010         ret = dwc3_alloc_scratch_buffers(dwc);
1011         if (ret)
1012                 goto err3;
1013
1014         ret = dwc3_core_init(dwc);
1015         if (ret) {
1016                 dev_err(dev, "failed to initialize core\n");
1017                 goto err4;
1018         }
1019
1020         /* Check the maximum_speed parameter */
1021         switch (dwc->maximum_speed) {
1022         case USB_SPEED_LOW:
1023         case USB_SPEED_FULL:
1024         case USB_SPEED_HIGH:
1025         case USB_SPEED_SUPER:
1026         case USB_SPEED_SUPER_PLUS:
1027                 break;
1028         default:
1029                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1030                         dwc->maximum_speed);
1031                 /* fall through */
1032         case USB_SPEED_UNKNOWN:
1033                 /* default to superspeed */
1034                 dwc->maximum_speed = USB_SPEED_SUPER;
1035
1036                 /*
1037                  * default to superspeed plus if we are capable.
1038                  */
1039                 if (dwc3_is_usb31(dwc) &&
1040                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1041                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1042                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1043
1044                 break;
1045         }
1046
1047         ret = dwc3_core_init_mode(dwc);
1048         if (ret)
1049                 goto err5;
1050
1051         dwc3_debugfs_init(dwc);
1052         pm_runtime_put(dev);
1053
1054         return 0;
1055
1056 err5:
1057         dwc3_event_buffers_cleanup(dwc);
1058
1059 err4:
1060         dwc3_free_scratch_buffers(dwc);
1061
1062 err3:
1063         dwc3_free_event_buffers(dwc);
1064         dwc3_ulpi_exit(dwc);
1065
1066 err2:
1067         pm_runtime_allow(&pdev->dev);
1068
1069 err1:
1070         pm_runtime_put_sync(&pdev->dev);
1071         pm_runtime_disable(&pdev->dev);
1072
1073 err0:
1074         /*
1075          * restore res->start back to its original value so that, in case the
1076          * probe is deferred, we don't end up getting error in request the
1077          * memory region the next time probe is called.
1078          */
1079         res->start -= DWC3_GLOBALS_REGS_START;
1080
1081         return ret;
1082 }
1083
1084 static int dwc3_remove(struct platform_device *pdev)
1085 {
1086         struct dwc3     *dwc = platform_get_drvdata(pdev);
1087         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1088
1089         pm_runtime_get_sync(&pdev->dev);
1090         /*
1091          * restore res->start back to its original value so that, in case the
1092          * probe is deferred, we don't end up getting error in request the
1093          * memory region the next time probe is called.
1094          */
1095         res->start -= DWC3_GLOBALS_REGS_START;
1096
1097         dwc3_debugfs_exit(dwc);
1098         dwc3_core_exit_mode(dwc);
1099
1100         dwc3_core_exit(dwc);
1101         dwc3_ulpi_exit(dwc);
1102
1103         pm_runtime_put_sync(&pdev->dev);
1104         pm_runtime_allow(&pdev->dev);
1105         pm_runtime_disable(&pdev->dev);
1106
1107         dwc3_free_event_buffers(dwc);
1108         dwc3_free_scratch_buffers(dwc);
1109
1110         return 0;
1111 }
1112
1113 #ifdef CONFIG_PM
1114 static int dwc3_suspend_common(struct dwc3 *dwc)
1115 {
1116         unsigned long   flags;
1117
1118         switch (dwc->dr_mode) {
1119         case USB_DR_MODE_PERIPHERAL:
1120         case USB_DR_MODE_OTG:
1121                 spin_lock_irqsave(&dwc->lock, flags);
1122                 dwc3_gadget_suspend(dwc);
1123                 spin_unlock_irqrestore(&dwc->lock, flags);
1124                 break;
1125         case USB_DR_MODE_HOST:
1126         default:
1127                 /* do nothing */
1128                 break;
1129         }
1130
1131         dwc3_core_exit(dwc);
1132
1133         return 0;
1134 }
1135
1136 static int dwc3_resume_common(struct dwc3 *dwc)
1137 {
1138         unsigned long   flags;
1139         int             ret;
1140
1141         ret = dwc3_core_init(dwc);
1142         if (ret)
1143                 return ret;
1144
1145         switch (dwc->dr_mode) {
1146         case USB_DR_MODE_PERIPHERAL:
1147         case USB_DR_MODE_OTG:
1148                 spin_lock_irqsave(&dwc->lock, flags);
1149                 dwc3_gadget_resume(dwc);
1150                 spin_unlock_irqrestore(&dwc->lock, flags);
1151                 /* FALLTHROUGH */
1152         case USB_DR_MODE_HOST:
1153         default:
1154                 /* do nothing */
1155                 break;
1156         }
1157
1158         return 0;
1159 }
1160
1161 static int dwc3_runtime_checks(struct dwc3 *dwc)
1162 {
1163         switch (dwc->dr_mode) {
1164         case USB_DR_MODE_PERIPHERAL:
1165         case USB_DR_MODE_OTG:
1166                 if (dwc->connected)
1167                         return -EBUSY;
1168                 break;
1169         case USB_DR_MODE_HOST:
1170         default:
1171                 /* do nothing */
1172                 break;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int dwc3_runtime_suspend(struct device *dev)
1179 {
1180         struct dwc3     *dwc = dev_get_drvdata(dev);
1181         int             ret;
1182
1183         if (dwc3_runtime_checks(dwc))
1184                 return -EBUSY;
1185
1186         ret = dwc3_suspend_common(dwc);
1187         if (ret)
1188                 return ret;
1189
1190         device_init_wakeup(dev, true);
1191
1192         return 0;
1193 }
1194
1195 static int dwc3_runtime_resume(struct device *dev)
1196 {
1197         struct dwc3     *dwc = dev_get_drvdata(dev);
1198         int             ret;
1199
1200         device_init_wakeup(dev, false);
1201
1202         ret = dwc3_resume_common(dwc);
1203         if (ret)
1204                 return ret;
1205
1206         switch (dwc->dr_mode) {
1207         case USB_DR_MODE_PERIPHERAL:
1208         case USB_DR_MODE_OTG:
1209                 dwc3_gadget_process_pending_events(dwc);
1210                 break;
1211         case USB_DR_MODE_HOST:
1212         default:
1213                 /* do nothing */
1214                 break;
1215         }
1216
1217         pm_runtime_mark_last_busy(dev);
1218
1219         return 0;
1220 }
1221
1222 static int dwc3_runtime_idle(struct device *dev)
1223 {
1224         struct dwc3     *dwc = dev_get_drvdata(dev);
1225
1226         switch (dwc->dr_mode) {
1227         case USB_DR_MODE_PERIPHERAL:
1228         case USB_DR_MODE_OTG:
1229                 if (dwc3_runtime_checks(dwc))
1230                         return -EBUSY;
1231                 break;
1232         case USB_DR_MODE_HOST:
1233         default:
1234                 /* do nothing */
1235                 break;
1236         }
1237
1238         pm_runtime_mark_last_busy(dev);
1239         pm_runtime_autosuspend(dev);
1240
1241         return 0;
1242 }
1243 #endif /* CONFIG_PM */
1244
1245 #ifdef CONFIG_PM_SLEEP
1246 static int dwc3_suspend(struct device *dev)
1247 {
1248         struct dwc3     *dwc = dev_get_drvdata(dev);
1249         int             ret;
1250
1251         ret = dwc3_suspend_common(dwc);
1252         if (ret)
1253                 return ret;
1254
1255         pinctrl_pm_select_sleep_state(dev);
1256
1257         return 0;
1258 }
1259
1260 static int dwc3_resume(struct device *dev)
1261 {
1262         struct dwc3     *dwc = dev_get_drvdata(dev);
1263         int             ret;
1264
1265         pinctrl_pm_select_default_state(dev);
1266
1267         ret = dwc3_resume_common(dwc);
1268         if (ret)
1269                 return ret;
1270
1271         pm_runtime_disable(dev);
1272         pm_runtime_set_active(dev);
1273         pm_runtime_enable(dev);
1274
1275         return 0;
1276 }
1277 #endif /* CONFIG_PM_SLEEP */
1278
1279 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1280         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1281         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1282                         dwc3_runtime_idle)
1283 };
1284
1285 #ifdef CONFIG_OF
1286 static const struct of_device_id of_dwc3_match[] = {
1287         {
1288                 .compatible = "snps,dwc3"
1289         },
1290         {
1291                 .compatible = "synopsys,dwc3"
1292         },
1293         { },
1294 };
1295 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1296 #endif
1297
1298 #ifdef CONFIG_ACPI
1299
1300 #define ACPI_ID_INTEL_BSW       "808622B7"
1301
1302 static const struct acpi_device_id dwc3_acpi_match[] = {
1303         { ACPI_ID_INTEL_BSW, 0 },
1304         { },
1305 };
1306 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1307 #endif
1308
1309 static struct platform_driver dwc3_driver = {
1310         .probe          = dwc3_probe,
1311         .remove         = dwc3_remove,
1312         .driver         = {
1313                 .name   = "dwc3",
1314                 .of_match_table = of_match_ptr(of_dwc3_match),
1315                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1316                 .pm     = &dwc3_dev_pm_ops,
1317         },
1318 };
1319
1320 module_platform_driver(dwc3_driver);
1321
1322 MODULE_ALIAS("platform:dwc3");
1323 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1324 MODULE_LICENSE("GPL v2");
1325 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");