drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  59                 u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_gadget_ep_cmd_params params;
  62         struct dwc3_trb                 *trb;
  63         struct dwc3_ep                  *dep;
  64
  65         int                             ret;
  66
  67         dep = dwc->eps[epnum];
  68         if (dep->flags & DWC3_EP_BUSY) {
  69                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  70                 return 0;
  71         }
  72
  73         trb = &dwc->ep0_trb[dep->trb_enqueue];
  74
  75         if (chain)
  76                 dep->trb_enqueue++;
  77
  78         trb->bpl = lower_32_bits(buf_dma);
  79         trb->bph = upper_32_bits(buf_dma);
  80         trb->size = len;
  81         trb->ctrl = type;
  82
  83         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  84                         | DWC3_TRB_CTRL_ISP_IMI);
  85
  86         if (chain)
  87                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  88         else
  89                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  90                                 | DWC3_TRB_CTRL_LST);
  91
  92         if (chain)
  93                 return 0;
  94
  95         memset(&params, 0, sizeof(params));
  96         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  97         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  98
  99         trace_dwc3_prepare_trb(dep, trb);
 100
 101         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 102                         DWC3_DEPCMD_STARTTRANSFER, &params);
 103         if (ret < 0) {
 104                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 105                                 dep->name);
 106                 return ret;
 107         }
 108
 109         dep->flags |= DWC3_EP_BUSY;
 110         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 111                         dep->number);
 112
 113         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 114
 115         return 0;
 116 }
 117
 118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 119                 struct dwc3_request *req)
 120 {
 121         struct dwc3             *dwc = dep->dwc;
 122
 123         req->request.actual     = 0;
 124         req->request.status     = -EINPROGRESS;
 125         req->epnum              = dep->number;
 126
 127         list_add_tail(&req->list, &dep->pending_list);
 128
 129         /*
 130          * Gadget driver might not be quick enough to queue a request
 131          * before we get a Transfer Not Ready event on this endpoint.
 132          *
 133          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 134          * flag is set, it's telling us that as soon as Gadget queues the
 135          * required request, we should kick the transfer here because the
 136          * IRQ we were waiting for is long gone.
 137          */
 138         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 139                 unsigned        direction;
 140
 141                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 142
 143                 if (dwc->ep0state != EP0_DATA_PHASE) {
 144                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 145                         return 0;
 146                 }
 147
 148                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 149
 150                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 151                                 DWC3_EP0_DIR_IN);
 152
 153                 return 0;
 154         }
 155
 156         /*
 157          * In case gadget driver asked us to delay the STATUS phase,
 158          * handle it here.
 159          */
 160         if (dwc->delayed_status) {
 161                 unsigned        direction;
 162
 163                 direction = !dwc->ep0_expect_in;
 164                 dwc->delayed_status = false;
 165                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 166
 167                 if (dwc->ep0state == EP0_STATUS_PHASE)
 168                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 169                 else
 170                         dwc3_trace(trace_dwc3_ep0,
 171                                         "too early for delayed status");
 172
 173                 return 0;
 174         }
 175
 176         /*
 177          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 178          *
 179          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 180          * come before issueing Start Transfer command, but if we do, we will
 181          * miss situations where the host starts another SETUP phase instead of
 182          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 183          * Layer Compliance Suite.
 184          *
 185          * The problem surfaces due to the fact that in case of back-to-back
 186          * SETUP packets there will be no XferNotReady(DATA) generated and we
 187          * will be stuck waiting for XferNotReady(DATA) forever.
 188          *
 189          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 190          * it tells us to start Data Phase right away. It also mentions that if
 191          * we receive a SETUP phase instead of the DATA phase, core will issue
 192          * XferComplete for the DATA phase, before actually initiating it in
 193          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 194          * can only be used to print some debugging logs, as the core expects
 195          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 196          * just so it completes right away, without transferring anything and,
 197          * only then, we can go back to the SETUP phase.
 198          *
 199          * Because of this scenario, SNPS decided to change the programming
 200          * model of control transfers and support on-demand transfers only for
 201          * the STATUS phase. To fix the issue we have now, we will always wait
 202          * for gadget driver to queue the DATA phase's struct usb_request, then
 203          * start it right away.
 204          *
 205          * If we're actually in a 2-stage transfer, we will wait for
 206          * XferNotReady(STATUS).
 207          */
 208         if (dwc->three_stage_setup) {
 209                 unsigned        direction;
 210
 211                 direction = dwc->ep0_expect_in;
 212                 dwc->ep0state = EP0_DATA_PHASE;
 213
 214                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 215
 216                 dep->flags &= ~DWC3_EP0_DIR_IN;
 217         }
 218
 219         return 0;
 220 }
 221
 222 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 223                 gfp_t gfp_flags)
 224 {
 225         struct dwc3_request             *req = to_dwc3_request(request);
 226         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 227         struct dwc3                     *dwc = dep->dwc;
 228
 229         unsigned long                   flags;
 230
 231         int                             ret;
 232
 233         spin_lock_irqsave(&dwc->lock, flags);
 234         if (!dep->endpoint.desc) {
 235                 dwc3_trace(trace_dwc3_ep0,
 236                                 "trying to queue request %p to disabled %s",
 237                                 request, dep->name);
 238                 ret = -ESHUTDOWN;
 239                 goto out;
 240         }
 241
 242         /* we share one TRB for ep0/1 */
 243         if (!list_empty(&dep->pending_list)) {
 244                 ret = -EBUSY;
 245                 goto out;
 246         }
 247
 248         dwc3_trace(trace_dwc3_ep0,
 249                         "queueing request %p to %s length %d state '%s'",
 250                         request, dep->name, request->length,
 251                         dwc3_ep0_state_string(dwc->ep0state));
 252
 253         ret = __dwc3_gadget_ep0_queue(dep, req);
 254
 255 out:
 256         spin_unlock_irqrestore(&dwc->lock, flags);
 257
 258         return ret;
 259 }
 260
 261 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 262 {
 263         struct dwc3_ep          *dep;
 264
 265         /* reinitialize physical ep1 */
 266         dep = dwc->eps[1];
 267         dep->flags = DWC3_EP_ENABLED;
 268
 269         /* stall is always issued on EP0 */
 270         dep = dwc->eps[0];
 271         __dwc3_gadget_ep_set_halt(dep, 1, false);
 272         dep->flags = DWC3_EP_ENABLED;
 273         dwc->delayed_status = false;
 274
 275         if (!list_empty(&dep->pending_list)) {
 276                 struct dwc3_request     *req;
 277
 278                 req = next_request(&dep->pending_list);
 279                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 280         }
 281
 282         dwc->ep0state = EP0_SETUP_PHASE;
 283         dwc3_ep0_out_start(dwc);
 284 }
 285
 286 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 287 {
 288         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 289         struct dwc3                     *dwc = dep->dwc;
 290
 291         dwc3_ep0_stall_and_restart(dwc);
 292
 293         return 0;
 294 }
 295
 296 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 297 {
 298         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 299         struct dwc3                     *dwc = dep->dwc;
 300         unsigned long                   flags;
 301         int                             ret;
 302
 303         spin_lock_irqsave(&dwc->lock, flags);
 304         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 305         spin_unlock_irqrestore(&dwc->lock, flags);
 306
 307         return ret;
 308 }
 309
 310 void dwc3_ep0_out_start(struct dwc3 *dwc)
 311 {
 312         int                             ret;
 313
 314         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 315                         DWC3_TRBCTL_CONTROL_SETUP, false);
 316         WARN_ON(ret < 0);
 317 }
 318
 319 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 320 {
 321         struct dwc3_ep          *dep;
 322         u32                     windex = le16_to_cpu(wIndex_le);
 323         u32                     epnum;
 324
 325         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 326         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 327                 epnum |= 1;
 328
 329         dep = dwc->eps[epnum];
 330         if (dep->flags & DWC3_EP_ENABLED)
 331                 return dep;
 332
 333         return NULL;
 334 }
 335
 336 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 337 {
 338 }
 339 /*
 340  * ch 9.4.5
 341  */
 342 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 343                 struct usb_ctrlrequest *ctrl)
 344 {
 345         struct dwc3_ep          *dep;
 346         u32                     recip;
 347         u32                     reg;
 348         u16                     usb_status = 0;
 349         __le16                  *response_pkt;
 350
 351         recip = ctrl->bRequestType & USB_RECIP_MASK;
 352         switch (recip) {
 353         case USB_RECIP_DEVICE:
 354                 /*
 355                  * LTM will be set once we know how to set this in HW.
 356                  */
 357                 usb_status |= dwc->gadget.is_selfpowered;
 358
 359                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 360                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 361                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 362                         if (reg & DWC3_DCTL_INITU1ENA)
 363                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 364                         if (reg & DWC3_DCTL_INITU2ENA)
 365                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 366                 }
 367
 368                 break;
 369
 370         case USB_RECIP_INTERFACE:
 371                 /*
 372                  * Function Remote Wake Capable D0
 373                  * Function Remote Wakeup       D1
 374                  */
 375                 break;
 376
 377         case USB_RECIP_ENDPOINT:
 378                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 379                 if (!dep)
 380                         return -EINVAL;
 381
 382                 if (dep->flags & DWC3_EP_STALL)
 383                         usb_status = 1 << USB_ENDPOINT_HALT;
 384                 break;
 385         default:
 386                 return -EINVAL;
 387         }
 388
 389         response_pkt = (__le16 *) dwc->setup_buf;
 390         *response_pkt = cpu_to_le16(usb_status);
 391
 392         dep = dwc->eps[0];
 393         dwc->ep0_usb_req.dep = dep;
 394         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 395         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 396         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 397
 398         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 399 }
 400
 401 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 402                 struct usb_ctrlrequest *ctrl, int set)
 403 {
 404         struct dwc3_ep          *dep;
 405         u32                     recip;
 406         u32                     wValue;
 407         u32                     wIndex;
 408         u32                     reg;
 409         int                     ret;
 410         enum usb_device_state   state;
 411
 412         wValue = le16_to_cpu(ctrl->wValue);
 413         wIndex = le16_to_cpu(ctrl->wIndex);
 414         recip = ctrl->bRequestType & USB_RECIP_MASK;
 415         state = dwc->gadget.state;
 416
 417         switch (recip) {
 418         case USB_RECIP_DEVICE:
 419
 420                 switch (wValue) {
 421                 case USB_DEVICE_REMOTE_WAKEUP:
 422                         break;
 423                 /*
 424                  * 9.4.1 says only only for SS, in AddressState only for
 425                  * default control pipe
 426                  */
 427                 case USB_DEVICE_U1_ENABLE:
 428                         if (state != USB_STATE_CONFIGURED)
 429                                 return -EINVAL;
 430                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 431                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 432                                 return -EINVAL;
 433
 434                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 435                         if (set)
 436                                 reg |= DWC3_DCTL_INITU1ENA;
 437                         else
 438                                 reg &= ~DWC3_DCTL_INITU1ENA;
 439                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 440                         break;
 441
 442                 case USB_DEVICE_U2_ENABLE:
 443                         if (state != USB_STATE_CONFIGURED)
 444                                 return -EINVAL;
 445                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 446                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 447                                 return -EINVAL;
 448
 449                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 450                         if (set)
 451                                 reg |= DWC3_DCTL_INITU2ENA;
 452                         else
 453                                 reg &= ~DWC3_DCTL_INITU2ENA;
 454                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 455                         break;
 456
 457                 case USB_DEVICE_LTM_ENABLE:
 458                         return -EINVAL;
 459
 460                 case USB_DEVICE_TEST_MODE:
 461                         if ((wIndex & 0xff) != 0)
 462                                 return -EINVAL;
 463                         if (!set)
 464                                 return -EINVAL;
 465
 466                         switch (wIndex >> 8) {
 467                         case TEST_J:
 468                         case TEST_K:
 469                         case TEST_SE0_NAK:
 470                         case TEST_PACKET:
 471                         case TEST_FORCE_EN:
 472                                 dwc->test_mode_nr = wIndex >> 8;
 473                                 dwc->test_mode = true;
 474                                 break;
 475                         default:
 476                                 return -EINVAL;
 477                         }
 478                         break;
 479                 default:
 480                         return -EINVAL;
 481                 }
 482                 break;
 483
 484         case USB_RECIP_INTERFACE:
 485                 switch (wValue) {
 486                 case USB_INTRF_FUNC_SUSPEND:
 487                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 488                                 /* XXX enable Low power suspend */
 489                                 ;
 490                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 491                                 /* XXX enable remote wakeup */
 492                                 ;
 493                         break;
 494                 default:
 495                         return -EINVAL;
 496                 }
 497                 break;
 498
 499         case USB_RECIP_ENDPOINT:
 500                 switch (wValue) {
 501                 case USB_ENDPOINT_HALT:
 502                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 503                         if (!dep)
 504                                 return -EINVAL;
 505                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 506                                 break;
 507                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 508                         if (ret)
 509                                 return -EINVAL;
 510                         break;
 511                 default:
 512                         return -EINVAL;
 513                 }
 514                 break;
 515
 516         default:
 517                 return -EINVAL;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 524 {
 525         enum usb_device_state state = dwc->gadget.state;
 526         u32 addr;
 527         u32 reg;
 528
 529         addr = le16_to_cpu(ctrl->wValue);
 530         if (addr > 127) {
 531                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 532                 return -EINVAL;
 533         }
 534
 535         if (state == USB_STATE_CONFIGURED) {
 536                 dwc3_trace(trace_dwc3_ep0,
 537                                 "trying to set address when configured");
 538                 return -EINVAL;
 539         }
 540
 541         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 542         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 543         reg |= DWC3_DCFG_DEVADDR(addr);
 544         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 545
 546         if (addr)
 547                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 548         else
 549                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 550
 551         return 0;
 552 }
 553
 554 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 555 {
 556         int ret;
 557
 558         spin_unlock(&dwc->lock);
 559         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 560         spin_lock(&dwc->lock);
 561         return ret;
 562 }
 563
 564 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 565 {
 566         enum usb_device_state state = dwc->gadget.state;
 567         u32 cfg;
 568         int ret;
 569         u32 reg;
 570
 571         cfg = le16_to_cpu(ctrl->wValue);
 572
 573         switch (state) {
 574         case USB_STATE_DEFAULT:
 575                 return -EINVAL;
 576
 577         case USB_STATE_ADDRESS:
 578                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 579                 /* if the cfg matches and the cfg is non zero */
 580                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 581
 582                         /*
 583                          * only change state if set_config has already
 584                          * been processed. If gadget driver returns
 585                          * USB_GADGET_DELAYED_STATUS, we will wait
 586                          * to change the state on the next usb_ep_queue()
 587                          */
 588                         if (ret == 0)
 589                                 usb_gadget_set_state(&dwc->gadget,
 590                                                 USB_STATE_CONFIGURED);
 591
 592                         /*
 593                          * Enable transition to U1/U2 state when
 594                          * nothing is pending from application.
 595                          */
 596                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 597                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 598                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 599                 }
 600                 break;
 601
 602         case USB_STATE_CONFIGURED:
 603                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 604                 if (!cfg && !ret)
 605                         usb_gadget_set_state(&dwc->gadget,
 606                                         USB_STATE_ADDRESS);
 607                 break;
 608         default:
 609                 ret = -EINVAL;
 610         }
 611         return ret;
 612 }
 613
 614 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 615 {
 616         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 617         struct dwc3     *dwc = dep->dwc;
 618
 619         u32             param = 0;
 620         u32             reg;
 621
 622         struct timing {
 623                 u8      u1sel;
 624                 u8      u1pel;
 625                 u16     u2sel;
 626                 u16     u2pel;
 627         } __packed timing;
 628
 629         int             ret;
 630
 631         memcpy(&timing, req->buf, sizeof(timing));
 632
 633         dwc->u1sel = timing.u1sel;
 634         dwc->u1pel = timing.u1pel;
 635         dwc->u2sel = le16_to_cpu(timing.u2sel);
 636         dwc->u2pel = le16_to_cpu(timing.u2pel);
 637
 638         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 639         if (reg & DWC3_DCTL_INITU2ENA)
 640                 param = dwc->u2pel;
 641         if (reg & DWC3_DCTL_INITU1ENA)
 642                 param = dwc->u1pel;
 643
 644         /*
 645          * According to Synopsys Databook, if parameter is
 646          * greater than 125, a value of zero should be
 647          * programmed in the register.
 648          */
 649         if (param > 125)
 650                 param = 0;
 651
 652         /* now that we have the time, issue DGCMD Set Sel */
 653         ret = dwc3_send_gadget_generic_command(dwc,
 654                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 655         WARN_ON(ret < 0);
 656 }
 657
 658 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 659 {
 660         struct dwc3_ep  *dep;
 661         enum usb_device_state state = dwc->gadget.state;
 662         u16             wLength;
 663         u16             wValue;
 664
 665         if (state == USB_STATE_DEFAULT)
 666                 return -EINVAL;
 667
 668         wValue = le16_to_cpu(ctrl->wValue);
 669         wLength = le16_to_cpu(ctrl->wLength);
 670
 671         if (wLength != 6) {
 672                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 673                                 wLength);
 674                 return -EINVAL;
 675         }
 676
 677         /*
 678          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 679          * queue a usb_request for 6 bytes.
 680          *
 681          * Remember, though, this controller can't handle non-wMaxPacketSize
 682          * aligned transfers on the OUT direction, so we queue a request for
 683          * wMaxPacketSize instead.
 684          */
 685         dep = dwc->eps[0];
 686         dwc->ep0_usb_req.dep = dep;
 687         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 688         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 689         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 690
 691         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 692 }
 693
 694 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 695 {
 696         u16             wLength;
 697         u16             wValue;
 698         u16             wIndex;
 699
 700         wValue = le16_to_cpu(ctrl->wValue);
 701         wLength = le16_to_cpu(ctrl->wLength);
 702         wIndex = le16_to_cpu(ctrl->wIndex);
 703
 704         if (wIndex || wLength)
 705                 return -EINVAL;
 706
 707         /*
 708          * REVISIT It's unclear from Databook what to do with this
 709          * value. For now, just cache it.
 710          */
 711         dwc->isoch_delay = wValue;
 712
 713         return 0;
 714 }
 715
 716 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 717 {
 718         int ret;
 719
 720         switch (ctrl->bRequest) {
 721         case USB_REQ_GET_STATUS:
 722                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 723                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 724                 break;
 725         case USB_REQ_CLEAR_FEATURE:
 726                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 727                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 728                 break;
 729         case USB_REQ_SET_FEATURE:
 730                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 731                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 732                 break;
 733         case USB_REQ_SET_ADDRESS:
 734                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 735                 ret = dwc3_ep0_set_address(dwc, ctrl);
 736                 break;
 737         case USB_REQ_SET_CONFIGURATION:
 738                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 739                 ret = dwc3_ep0_set_config(dwc, ctrl);
 740                 break;
 741         case USB_REQ_SET_SEL:
 742                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 743                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 744                 break;
 745         case USB_REQ_SET_ISOCH_DELAY:
 746                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 747                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 748                 break;
 749         default:
 750                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 751                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 752                 break;
 753         }
 754
 755         return ret;
 756 }
 757
 758 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 759                 const struct dwc3_event_depevt *event)
 760 {
 761         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 762         int ret = -EINVAL;
 763         u32 len;
 764
 765         if (!dwc->gadget_driver)
 766                 goto out;
 767
 768         trace_dwc3_ctrl_req(ctrl);
 769
 770         len = le16_to_cpu(ctrl->wLength);
 771         if (!len) {
 772                 dwc->three_stage_setup = false;
 773                 dwc->ep0_expect_in = false;
 774                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 775         } else {
 776                 dwc->three_stage_setup = true;
 777                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 778                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 779         }
 780
 781         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 782                 ret = dwc3_ep0_std_request(dwc, ctrl);
 783         else
 784                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 785
 786         if (ret == USB_GADGET_DELAYED_STATUS)
 787                 dwc->delayed_status = true;
 788
 789 out:
 790         if (ret < 0)
 791                 dwc3_ep0_stall_and_restart(dwc);
 792 }
 793
 794 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 795                 const struct dwc3_event_depevt *event)
 796 {
 797         struct dwc3_request     *r = NULL;
 798         struct usb_request      *ur;
 799         struct dwc3_trb         *trb;
 800         struct dwc3_ep          *ep0;
 801         unsigned                transfer_size = 0;
 802         unsigned                maxp;
 803         unsigned                remaining_ur_length;
 804         void                    *buf;
 805         u32                     transferred = 0;
 806         u32                     status;
 807         u32                     length;
 808         u8                      epnum;
 809
 810         epnum = event->endpoint_number;
 811         ep0 = dwc->eps[0];
 812
 813         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 814
 815         trb = dwc->ep0_trb;
 816
 817         trace_dwc3_complete_trb(ep0, trb);
 818
 819         r = next_request(&ep0->pending_list);
 820         if (!r)
 821                 return;
 822
 823         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 824         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 825                 dwc->setup_packet_pending = true;
 826
 827                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 828
 829                 if (r)
 830                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 831
 832                 return;
 833         }
 834
 835         ur = &r->request;
 836         buf = ur->buf;
 837         remaining_ur_length = ur->length;
 838
 839         length = trb->size & DWC3_TRB_SIZE_MASK;
 840
 841         maxp = ep0->endpoint.maxpacket;
 842
 843         if (dwc->ep0_bounced) {
 844                 /*
 845                  * Handle the first TRB before handling the bounce buffer if
 846                  * the request length is greater than the bounce buffer size
 847                  */
 848                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 849                         transfer_size = ALIGN(ur->length - maxp, maxp);
 850                         transferred = transfer_size - length;
 851                         buf = (u8 *)buf + transferred;
 852                         ur->actual += transferred;
 853                         remaining_ur_length -= transferred;
 854
 855                         trb++;
 856                         length = trb->size & DWC3_TRB_SIZE_MASK;
 857
 858                         ep0->trb_enqueue = 0;
 859                 }
 860
 861                 transfer_size = roundup((ur->length - transfer_size),
 862                                         maxp);
 863
 864                 transferred = min_t(u32, remaining_ur_length,
 865                                     transfer_size - length);
 866                 memcpy(buf, dwc->ep0_bounce, transferred);
 867         } else {
 868                 transferred = ur->length - length;
 869         }
 870
 871         ur->actual += transferred;
 872
 873         if ((epnum & 1) && ur->actual < ur->length) {
 874                 /* for some reason we did not get everything out */
 875
 876                 dwc3_ep0_stall_and_restart(dwc);
 877         } else {
 878                 dwc3_gadget_giveback(ep0, r, 0);
 879
 880                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 881                                 ur->length && ur->zero) {
 882                         int ret;
 883
 884                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 885
 886                         ret = dwc3_ep0_start_trans(dwc, epnum,
 887                                         dwc->ctrl_req_addr, 0,
 888                                         DWC3_TRBCTL_CONTROL_DATA, false);
 889                         WARN_ON(ret < 0);
 890                 }
 891         }
 892 }
 893
 894 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 895                 const struct dwc3_event_depevt *event)
 896 {
 897         struct dwc3_request     *r;
 898         struct dwc3_ep          *dep;
 899         struct dwc3_trb         *trb;
 900         u32                     status;
 901
 902         dep = dwc->eps[0];
 903         trb = dwc->ep0_trb;
 904
 905         trace_dwc3_complete_trb(dep, trb);
 906
 907         if (!list_empty(&dep->pending_list)) {
 908                 r = next_request(&dep->pending_list);
 909
 910                 dwc3_gadget_giveback(dep, r, 0);
 911         }
 912
 913         if (dwc->test_mode) {
 914                 int ret;
 915
 916                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 917                 if (ret < 0) {
 918                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 919                                         dwc->test_mode_nr);
 920                         dwc3_ep0_stall_and_restart(dwc);
 921                         return;
 922                 }
 923         }
 924
 925         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 926         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 927                 dwc->setup_packet_pending = true;
 928                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 929         }
 930
 931         dwc->ep0state = EP0_SETUP_PHASE;
 932         dwc3_ep0_out_start(dwc);
 933 }
 934
 935 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 936                         const struct dwc3_event_depevt *event)
 937 {
 938         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 939
 940         dep->flags &= ~DWC3_EP_BUSY;
 941         dep->resource_index = 0;
 942         dwc->setup_packet_pending = false;
 943
 944         switch (dwc->ep0state) {
 945         case EP0_SETUP_PHASE:
 946                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 947                 dwc3_ep0_inspect_setup(dwc, event);
 948                 break;
 949
 950         case EP0_DATA_PHASE:
 951                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 952                 dwc3_ep0_complete_data(dwc, event);
 953                 break;
 954
 955         case EP0_STATUS_PHASE:
 956                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 957                 dwc3_ep0_complete_status(dwc, event);
 958                 break;
 959         default:
 960                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 961         }
 962 }
 963
 964 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 965                 struct dwc3_ep *dep, struct dwc3_request *req)
 966 {
 967         int                     ret;
 968
 969         req->direction = !!dep->number;
 970
 971         if (req->request.length == 0) {
 972                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 973                                 dwc->ctrl_req_addr, 0,
 974                                 DWC3_TRBCTL_CONTROL_DATA, false);
 975         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 976                         && (dep->number == 0)) {
 977                 u32     transfer_size = 0;
 978                 u32     maxpacket;
 979
 980                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 981                                 dep->number);
 982                 if (ret) {
 983                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
 984                         return;
 985                 }
 986
 987                 maxpacket = dep->endpoint.maxpacket;
 988
 989                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 990                         transfer_size = ALIGN(req->request.length - maxpacket,
 991                                               maxpacket);
 992                         ret = dwc3_ep0_start_trans(dwc, dep->number,
 993                                                    req->request.dma,
 994                                                    transfer_size,
 995                                                    DWC3_TRBCTL_CONTROL_DATA,
 996                                                    true);
 997                 }
 998
 999                 transfer_size = roundup((req->request.length - transfer_size),
1000                                         maxpacket);
1001
1002                 dwc->ep0_bounced = true;
1003
1004                 ret = dwc3_ep0_start_trans(dwc, dep->number,
1005                                 dwc->ep0_bounce_addr, transfer_size,
1006                                 DWC3_TRBCTL_CONTROL_DATA, false);
1007         } else {
1008                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1009                                 dep->number);
1010                 if (ret) {
1011                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
1012                         return;
1013                 }
1014
1015                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1016                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1017                                 false);
1018         }
1019
1020         WARN_ON(ret < 0);
1021 }
1022
1023 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1024 {
1025         struct dwc3             *dwc = dep->dwc;
1026         u32                     type;
1027
1028         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1029                 : DWC3_TRBCTL_CONTROL_STATUS2;
1030
1031         return dwc3_ep0_start_trans(dwc, dep->number,
1032                         dwc->ctrl_req_addr, 0, type, false);
1033 }
1034
1035 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1036 {
1037         WARN_ON(dwc3_ep0_start_control_status(dep));
1038 }
1039
1040 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1041                 const struct dwc3_event_depevt *event)
1042 {
1043         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1044
1045         __dwc3_ep0_do_control_status(dwc, dep);
1046 }
1047
1048 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1049 {
1050         struct dwc3_gadget_ep_cmd_params params;
1051         u32                     cmd;
1052         int                     ret;
1053
1054         if (!dep->resource_index)
1055                 return;
1056
1057         cmd = DWC3_DEPCMD_ENDTRANSFER;
1058         cmd |= DWC3_DEPCMD_CMDIOC;
1059         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1060         memset(&params, 0, sizeof(params));
1061         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1062         WARN_ON_ONCE(ret);
1063         dep->resource_index = 0;
1064 }
1065
1066 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1067                 const struct dwc3_event_depevt *event)
1068 {
1069         switch (event->status) {
1070         case DEPEVT_STATUS_CONTROL_DATA:
1071                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1072
1073                 /*
1074                  * We already have a DATA transfer in the controller's cache,
1075                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1076                  * it's for the wrong direction.
1077                  *
1078                  * In that case, we must issue END_TRANSFER command to the Data
1079                  * Phase we already have started and issue SetStall on the
1080                  * control endpoint.
1081                  */
1082                 if (dwc->ep0_expect_in != event->endpoint_number) {
1083                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1084
1085                         dwc3_trace(trace_dwc3_ep0,
1086                                         "Wrong direction for Data phase");
1087                         dwc3_ep0_end_control_data(dwc, dep);
1088                         dwc3_ep0_stall_and_restart(dwc);
1089                         return;
1090                 }
1091
1092                 break;
1093
1094         case DEPEVT_STATUS_CONTROL_STATUS:
1095                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1096                         return;
1097
1098                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1099
1100                 dwc->ep0state = EP0_STATUS_PHASE;
1101
1102                 if (dwc->delayed_status) {
1103                         WARN_ON_ONCE(event->endpoint_number != 1);
1104                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1105                         return;
1106                 }
1107
1108                 dwc3_ep0_do_control_status(dwc, event);
1109         }
1110 }
1111
1112 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1113                 const struct dwc3_event_depevt *event)
1114 {
1115         u8                      epnum = event->endpoint_number;
1116
1117         dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1118                         dwc3_ep_event_string(event->endpoint_event),
1119                         epnum >> 1, (epnum & 1) ? "in" : "out",
1120                         dwc3_ep0_state_string(dwc->ep0state));
1121
1122         switch (event->endpoint_event) {
1123         case DWC3_DEPEVT_XFERCOMPLETE:
1124                 dwc3_ep0_xfer_complete(dwc, event);
1125                 break;
1126
1127         case DWC3_DEPEVT_XFERNOTREADY:
1128                 dwc3_ep0_xfernotready(dwc, event);
1129                 break;
1130
1131         case DWC3_DEPEVT_XFERINPROGRESS:
1132         case DWC3_DEPEVT_RXTXFIFOEVT:
1133         case DWC3_DEPEVT_STREAMEVT:
1134         case DWC3_DEPEVT_EPCMDCMPLT:
1135                 break;
1136         }
1137 }