drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 149 {
 150         dep->trb_enqueue++;
 151         dep->trb_enqueue %= DWC3_TRB_NUM;
 152 }
 153
 154 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 155 {
 156         dep->trb_dequeue++;
 157         dep->trb_dequeue %= DWC3_TRB_NUM;
 158 }
 159
 160 static int dwc3_ep_is_last_trb(unsigned int index)
 161 {
 162         return index == DWC3_TRB_NUM - 1;
 163 }
 164
 165 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 166                 int status)
 167 {
 168         struct dwc3                     *dwc = dep->dwc;
 169         int                             i;
 170
 171         if (req->started) {
 172                 i = 0;
 173                 do {
 174                         dwc3_ep_inc_deq(dep);
 175                         /*
 176                          * Skip LINK TRB. We can't use req->trb and check for
 177                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 178                          * just completed (not the LINK TRB).
 179                          */
 180                         if (dwc3_ep_is_last_trb(dep->trb_dequeue))
 181                                 dwc3_ep_inc_deq(dep);
 182                 } while(++i < req->request.num_mapped_sgs);
 183                 req->started = false;
 184         }
 185         list_del(&req->list);
 186         req->trb = NULL;
 187
 188         if (req->request.status == -EINPROGRESS)
 189                 req->request.status = status;
 190
 191         if (dwc->ep0_bounced && dep->number == 0)
 192                 dwc->ep0_bounced = false;
 193         else
 194                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 195                                 req->direction);
 196
 197         trace_dwc3_gadget_giveback(req);
 198
 199         spin_unlock(&dwc->lock);
 200         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 201         spin_lock(&dwc->lock);
 202 }
 203
 204 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 205 {
 206         u32             timeout = 500;
 207         u32             reg;
 208
 209         trace_dwc3_gadget_generic_cmd(cmd, param);
 210
 211         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 212         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 213
 214         do {
 215                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 216                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 217                         dwc3_trace(trace_dwc3_gadget,
 218                                         "Command Complete --> %d",
 219                                         DWC3_DGCMD_STATUS(reg));
 220                         if (DWC3_DGCMD_STATUS(reg))
 221                                 return -EINVAL;
 222                         return 0;
 223                 }
 224
 225                 /*
 226                  * We can't sleep here, because it's also called from
 227                  * interrupt context.
 228                  */
 229                 timeout--;
 230                 if (!timeout) {
 231                         dwc3_trace(trace_dwc3_gadget,
 232                                         "Command Timed Out");
 233                         return -ETIMEDOUT;
 234                 }
 235                 udelay(1);
 236         } while (1);
 237 }
 238
 239 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 240
 241 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 242                 struct dwc3_gadget_ep_cmd_params *params)
 243 {
 244         struct dwc3             *dwc = dep->dwc;
 245         u32                     timeout = 500;
 246         u32                     reg;
 247
 248         int                     susphy = false;
 249         int                     ret = -EINVAL;
 250
 251         unsigned                ep = dep->number;
 252
 253         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 254
 255         /*
 256          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 257          * we're issuing an endpoint command, we must check if
 258          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 259          *
 260          * We will also set SUSPHY bit to what it was before returning as stated
 261          * by the same section on Synopsys databook.
 262          */
 263         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 264         if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 265                 susphy = true;
 266                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 267                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 268         }
 269
 270         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 271                 int             needs_wakeup;
 272
 273                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 274                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 275                                 dwc->link_state == DWC3_LINK_STATE_U3);
 276
 277                 if (unlikely(needs_wakeup)) {
 278                         ret = __dwc3_gadget_wakeup(dwc);
 279                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 280                                         ret);
 281                 }
 282         }
 283
 284         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 285         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 286         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 287
 288         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 289         do {
 290                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 291                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 292                         int cmd_status = DWC3_DEPCMD_STATUS(reg);
 293
 294                         dwc3_trace(trace_dwc3_gadget,
 295                                         "Command Complete --> %d",
 296                                         cmd_status);
 297
 298                         switch (cmd_status) {
 299                         case 0:
 300                                 ret = 0;
 301                                 break;
 302                         case DEPEVT_TRANSFER_NO_RESOURCE:
 303                                 dwc3_trace(trace_dwc3_gadget, "%s: no resource available");
 304                                 ret = -EINVAL;
 305                                 break;
 306                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 307                                 /*
 308                                  * SW issues START TRANSFER command to
 309                                  * isochronous ep with future frame interval. If
 310                                  * future interval time has already passed when
 311                                  * core receives the command, it will respond
 312                                  * with an error status of 'Bus Expiry'.
 313                                  *
 314                                  * Instead of always returning -EINVAL, let's
 315                                  * give a hint to the gadget driver that this is
 316                                  * the case by returning -EAGAIN.
 317                                  */
 318                                 dwc3_trace(trace_dwc3_gadget, "%s: bus expiry");
 319                                 ret = -EAGAIN;
 320                                 break;
 321                         default:
 322                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 323                         }
 324
 325                         break;
 326                 }
 327
 328                 /*
 329                  * We can't sleep here, because it is also called from
 330                  * interrupt context.
 331                  */
 332                 timeout--;
 333                 if (!timeout) {
 334                         dwc3_trace(trace_dwc3_gadget,
 335                                         "Command Timed Out");
 336                         ret = -ETIMEDOUT;
 337                         break;
 338                 }
 339         } while (1);
 340
 341         if (unlikely(susphy)) {
 342                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 343                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 344                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 345         }
 346
 347         return ret;
 348 }
 349
 350 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 351 {
 352         struct dwc3 *dwc = dep->dwc;
 353         struct dwc3_gadget_ep_cmd_params params;
 354         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 355
 356         /*
 357          * As of core revision 2.60a the recommended programming model
 358          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 359          * command for IN endpoints. This is to prevent an issue where
 360          * some (non-compliant) hosts may not send ACK TPs for pending
 361          * IN transfers due to a mishandled error condition. Synopsys
 362          * STAR 9000614252.
 363          */
 364         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
 365                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 366
 367         memset(&params, 0, sizeof(params));
 368
 369         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 370 }
 371
 372 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 373                 struct dwc3_trb *trb)
 374 {
 375         u32             offset = (char *) trb - (char *) dep->trb_pool;
 376
 377         return dep->trb_pool_dma + offset;
 378 }
 379
 380 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 381 {
 382         struct dwc3             *dwc = dep->dwc;
 383
 384         if (dep->trb_pool)
 385                 return 0;
 386
 387         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 388                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 389                         &dep->trb_pool_dma, GFP_KERNEL);
 390         if (!dep->trb_pool) {
 391                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 392                                 dep->name);
 393                 return -ENOMEM;
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 400 {
 401         struct dwc3             *dwc = dep->dwc;
 402
 403         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 404                         dep->trb_pool, dep->trb_pool_dma);
 405
 406         dep->trb_pool = NULL;
 407         dep->trb_pool_dma = 0;
 408 }
 409
 410 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 411
 412 /**
 413  * dwc3_gadget_start_config - Configure EP resources
 414  * @dwc: pointer to our controller context structure
 415  * @dep: endpoint that is being enabled
 416  *
 417  * The assignment of transfer resources cannot perfectly follow the
 418  * data book due to the fact that the controller driver does not have
 419  * all knowledge of the configuration in advance. It is given this
 420  * information piecemeal by the composite gadget framework after every
 421  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 422  * programming model in this scenario can cause errors. For two
 423  * reasons:
 424  *
 425  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 426  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 427  * multiple interfaces.
 428  *
 429  * 2) The databook does not mention doing more DEPXFERCFG for new
 430  * endpoint on alt setting (8.1.6).
 431  *
 432  * The following simplified method is used instead:
 433  *
 434  * All hardware endpoints can be assigned a transfer resource and this
 435  * setting will stay persistent until either a core reset or
 436  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 437  * do DEPXFERCFG for every hardware endpoint as well. We are
 438  * guaranteed that there are as many transfer resources as endpoints.
 439  *
 440  * This function is called for each endpoint when it is being enabled
 441  * but is triggered only when called for EP0-out, which always happens
 442  * first, and which should only happen in one of the above conditions.
 443  */
 444 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 445 {
 446         struct dwc3_gadget_ep_cmd_params params;
 447         u32                     cmd;
 448         int                     i;
 449         int                     ret;
 450
 451         if (dep->number)
 452                 return 0;
 453
 454         memset(&params, 0x00, sizeof(params));
 455         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 456
 457         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 458         if (ret)
 459                 return ret;
 460
 461         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 462                 struct dwc3_ep *dep = dwc->eps[i];
 463
 464                 if (!dep)
 465                         continue;
 466
 467                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 468                 if (ret)
 469                         return ret;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 476                 const struct usb_endpoint_descriptor *desc,
 477                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 478                 bool ignore, bool restore)
 479 {
 480         struct dwc3_gadget_ep_cmd_params params;
 481
 482         memset(&params, 0x00, sizeof(params));
 483
 484         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 485                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 486
 487         /* Burst size is only needed in SuperSpeed mode */
 488         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 489                 u32 burst = dep->endpoint.maxburst;
 490                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 491         }
 492
 493         if (ignore)
 494                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 495
 496         if (restore) {
 497                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 498                 params.param2 |= dep->saved_state;
 499         }
 500
 501         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 502                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 503
 504         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 505                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 506                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 507                 dep->stream_capable = true;
 508         }
 509
 510         if (!usb_endpoint_xfer_control(desc))
 511                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 512
 513         /*
 514          * We are doing 1:1 mapping for endpoints, meaning
 515          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 516          * so on. We consider the direction bit as part of the physical
 517          * endpoint number. So USB endpoint 0x81 is 0x03.
 518          */
 519         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 520
 521         /*
 522          * We must use the lower 16 TX FIFOs even though
 523          * HW might have more
 524          */
 525         if (dep->direction)
 526                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 527
 528         if (desc->bInterval) {
 529                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 530                 dep->interval = 1 << (desc->bInterval - 1);
 531         }
 532
 533         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 534 }
 535
 536 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 537 {
 538         struct dwc3_gadget_ep_cmd_params params;
 539
 540         memset(&params, 0x00, sizeof(params));
 541
 542         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 543
 544         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 545                         &params);
 546 }
 547
 548 /**
 549  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 550  * @dep: endpoint to be initialized
 551  * @desc: USB Endpoint Descriptor
 552  *
 553  * Caller should take care of locking
 554  */
 555 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 556                 const struct usb_endpoint_descriptor *desc,
 557                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 558                 bool ignore, bool restore)
 559 {
 560         struct dwc3             *dwc = dep->dwc;
 561         u32                     reg;
 562         int                     ret;
 563
 564         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 565
 566         if (!(dep->flags & DWC3_EP_ENABLED)) {
 567                 ret = dwc3_gadget_start_config(dwc, dep);
 568                 if (ret)
 569                         return ret;
 570         }
 571
 572         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 573                         restore);
 574         if (ret)
 575                 return ret;
 576
 577         if (!(dep->flags & DWC3_EP_ENABLED)) {
 578                 struct dwc3_trb *trb_st_hw;
 579                 struct dwc3_trb *trb_link;
 580
 581                 dep->endpoint.desc = desc;
 582                 dep->comp_desc = comp_desc;
 583                 dep->type = usb_endpoint_type(desc);
 584                 dep->flags |= DWC3_EP_ENABLED;
 585
 586                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 587                 reg |= DWC3_DALEPENA_EP(dep->number);
 588                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 589
 590                 if (usb_endpoint_xfer_control(desc))
 591                         goto out;
 592
 593                 /* Link TRB. The HWO bit is never reset */
 594                 trb_st_hw = &dep->trb_pool[0];
 595
 596                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 597                 memset(trb_link, 0, sizeof(*trb_link));
 598
 599                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 600                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 601                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 602                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 603         }
 604
 605 out:
 606         switch (usb_endpoint_type(desc)) {
 607         case USB_ENDPOINT_XFER_CONTROL:
 608                 /* don't change name */
 609                 break;
 610         case USB_ENDPOINT_XFER_ISOC:
 611                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 612                 break;
 613         case USB_ENDPOINT_XFER_BULK:
 614                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 615                 break;
 616         case USB_ENDPOINT_XFER_INT:
 617                 strlcat(dep->name, "-int", sizeof(dep->name));
 618                 break;
 619         default:
 620                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 621         }
 622
 623         return 0;
 624 }
 625
 626 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 627 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 628 {
 629         struct dwc3_request             *req;
 630
 631         if (!list_empty(&dep->started_list)) {
 632                 dwc3_stop_active_transfer(dwc, dep->number, true);
 633
 634                 /* - giveback all requests to gadget driver */
 635                 while (!list_empty(&dep->started_list)) {
 636                         req = next_request(&dep->started_list);
 637
 638                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 639                 }
 640         }
 641
 642         while (!list_empty(&dep->pending_list)) {
 643                 req = next_request(&dep->pending_list);
 644
 645                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 646         }
 647 }
 648
 649 /**
 650  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 651  * @dep: the endpoint to disable
 652  *
 653  * This function also removes requests which are currently processed ny the
 654  * hardware and those which are not yet scheduled.
 655  * Caller should take care of locking.
 656  */
 657 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 658 {
 659         struct dwc3             *dwc = dep->dwc;
 660         u32                     reg;
 661
 662         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 663
 664         dwc3_remove_requests(dwc, dep);
 665
 666         /* make sure HW endpoint isn't stalled */
 667         if (dep->flags & DWC3_EP_STALL)
 668                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 669
 670         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 671         reg &= ~DWC3_DALEPENA_EP(dep->number);
 672         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 673
 674         dep->stream_capable = false;
 675         dep->endpoint.desc = NULL;
 676         dep->comp_desc = NULL;
 677         dep->type = 0;
 678         dep->flags = 0;
 679
 680         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 681                         dep->number >> 1,
 682                         (dep->number & 1) ? "in" : "out");
 683
 684         return 0;
 685 }
 686
 687 /* -------------------------------------------------------------------------- */
 688
 689 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 690                 const struct usb_endpoint_descriptor *desc)
 691 {
 692         return -EINVAL;
 693 }
 694
 695 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 696 {
 697         return -EINVAL;
 698 }
 699
 700 /* -------------------------------------------------------------------------- */
 701
 702 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 703                 const struct usb_endpoint_descriptor *desc)
 704 {
 705         struct dwc3_ep                  *dep;
 706         struct dwc3                     *dwc;
 707         unsigned long                   flags;
 708         int                             ret;
 709
 710         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 711                 pr_debug("dwc3: invalid parameters\n");
 712                 return -EINVAL;
 713         }
 714
 715         if (!desc->wMaxPacketSize) {
 716                 pr_debug("dwc3: missing wMaxPacketSize\n");
 717                 return -EINVAL;
 718         }
 719
 720         dep = to_dwc3_ep(ep);
 721         dwc = dep->dwc;
 722
 723         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 724                                         "%s is already enabled\n",
 725                                         dep->name))
 726                 return 0;
 727
 728         spin_lock_irqsave(&dwc->lock, flags);
 729         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 730         spin_unlock_irqrestore(&dwc->lock, flags);
 731
 732         return ret;
 733 }
 734
 735 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 736 {
 737         struct dwc3_ep                  *dep;
 738         struct dwc3                     *dwc;
 739         unsigned long                   flags;
 740         int                             ret;
 741
 742         if (!ep) {
 743                 pr_debug("dwc3: invalid parameters\n");
 744                 return -EINVAL;
 745         }
 746
 747         dep = to_dwc3_ep(ep);
 748         dwc = dep->dwc;
 749
 750         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 751                                         "%s is already disabled\n",
 752                                         dep->name))
 753                 return 0;
 754
 755         spin_lock_irqsave(&dwc->lock, flags);
 756         ret = __dwc3_gadget_ep_disable(dep);
 757         spin_unlock_irqrestore(&dwc->lock, flags);
 758
 759         return ret;
 760 }
 761
 762 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 763         gfp_t gfp_flags)
 764 {
 765         struct dwc3_request             *req;
 766         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 767
 768         req = kzalloc(sizeof(*req), gfp_flags);
 769         if (!req)
 770                 return NULL;
 771
 772         req->epnum      = dep->number;
 773         req->dep        = dep;
 774
 775         trace_dwc3_alloc_request(req);
 776
 777         return &req->request;
 778 }
 779
 780 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 781                 struct usb_request *request)
 782 {
 783         struct dwc3_request             *req = to_dwc3_request(request);
 784
 785         trace_dwc3_free_request(req);
 786         kfree(req);
 787 }
 788
 789 /**
 790  * dwc3_prepare_one_trb - setup one TRB from one request
 791  * @dep: endpoint for which this request is prepared
 792  * @req: dwc3_request pointer
 793  */
 794 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 795                 struct dwc3_request *req, dma_addr_t dma,
 796                 unsigned length, unsigned last, unsigned chain, unsigned node)
 797 {
 798         struct dwc3_trb         *trb;
 799
 800         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 801                         dep->name, req, (unsigned long long) dma,
 802                         length, last ? " last" : "",
 803                         chain ? " chain" : "");
 804
 805
 806         trb = &dep->trb_pool[dep->trb_enqueue];
 807
 808         if (!req->trb) {
 809                 dwc3_gadget_move_started_request(req);
 810                 req->trb = trb;
 811                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 812                 req->first_trb_index = dep->trb_enqueue;
 813         }
 814
 815         dwc3_ep_inc_enq(dep);
 816         /* Skip the LINK-TRB */
 817         if (dwc3_ep_is_last_trb(dep->trb_enqueue))
 818                 dwc3_ep_inc_enq(dep);
 819
 820         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 821         trb->bpl = lower_32_bits(dma);
 822         trb->bph = upper_32_bits(dma);
 823
 824         switch (usb_endpoint_type(dep->endpoint.desc)) {
 825         case USB_ENDPOINT_XFER_CONTROL:
 826                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 827                 break;
 828
 829         case USB_ENDPOINT_XFER_ISOC:
 830                 if (!node)
 831                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 832                 else
 833                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 834
 835                 /* always enable Interrupt on Missed ISOC */
 836                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 837                 break;
 838
 839         case USB_ENDPOINT_XFER_BULK:
 840         case USB_ENDPOINT_XFER_INT:
 841                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 842                 break;
 843         default:
 844                 /*
 845                  * This is only possible with faulty memory because we
 846                  * checked it already :)
 847                  */
 848                 BUG();
 849         }
 850
 851         /* always enable Continue on Short Packet */
 852         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 853
 854         if (!req->request.no_interrupt && !chain)
 855                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 856
 857         if (last)
 858                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 859
 860         if (chain)
 861                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 862
 863         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 864                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 865
 866         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 867
 868         trace_dwc3_prepare_trb(dep, trb);
 869 }
 870
 871 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 872 {
 873         struct dwc3_trb         *tmp;
 874
 875         /*
 876          * If enqueue & dequeue are equal than it is either full or empty.
 877          *
 878          * One way to know for sure is if the TRB right before us has HWO bit
 879          * set or not. If it has, then we're definitely full and can't fit any
 880          * more transfers in our ring.
 881          */
 882         if (dep->trb_enqueue == dep->trb_dequeue) {
 883                 /* If we're full, enqueue/dequeue are > 0 */
 884                 if (dep->trb_enqueue) {
 885                         tmp = &dep->trb_pool[dep->trb_enqueue - 1];
 886                         if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 887                                 return 0;
 888                 }
 889
 890                 return DWC3_TRB_NUM - 1;
 891         }
 892
 893         return dep->trb_dequeue - dep->trb_enqueue;
 894 }
 895
 896 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 897                 struct dwc3_request *req, unsigned int trbs_left)
 898 {
 899         struct usb_request *request = &req->request;
 900         struct scatterlist *sg = request->sg;
 901         struct scatterlist *s;
 902         unsigned int    last = false;
 903         unsigned int    length;
 904         dma_addr_t      dma;
 905         int             i;
 906
 907         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 908                 unsigned chain = true;
 909
 910                 length = sg_dma_len(s);
 911                 dma = sg_dma_address(s);
 912
 913                 if (sg_is_last(s)) {
 914                         if (list_is_last(&req->list, &dep->pending_list))
 915                                 last = true;
 916
 917                         chain = false;
 918                 }
 919
 920                 if (!trbs_left)
 921                         last = true;
 922
 923                 if (last)
 924                         chain = false;
 925
 926                 dwc3_prepare_one_trb(dep, req, dma, length,
 927                                 last, chain, i);
 928
 929                 if (last)
 930                         break;
 931         }
 932 }
 933
 934 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
 935                 struct dwc3_request *req, unsigned int trbs_left)
 936 {
 937         unsigned int    last = false;
 938         unsigned int    length;
 939         dma_addr_t      dma;
 940
 941         dma = req->request.dma;
 942         length = req->request.length;
 943
 944         if (!trbs_left)
 945                 last = true;
 946
 947         /* Is this the last request? */
 948         if (list_is_last(&req->list, &dep->pending_list))
 949                 last = true;
 950
 951         dwc3_prepare_one_trb(dep, req, dma, length,
 952                         last, false, 0);
 953 }
 954
 955 /*
 956  * dwc3_prepare_trbs - setup TRBs from requests
 957  * @dep: endpoint for which requests are being prepared
 958  *
 959  * The function goes through the requests list and sets up TRBs for the
 960  * transfers. The function returns once there are no more TRBs available or
 961  * it runs out of requests.
 962  */
 963 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
 964 {
 965         struct dwc3_request     *req, *n;
 966         u32                     trbs_left;
 967
 968         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 969
 970         trbs_left = dwc3_calc_trbs_left(dep);
 971
 972         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 973                 if (req->request.num_mapped_sgs > 0)
 974                         dwc3_prepare_one_trb_sg(dep, req, trbs_left--);
 975                 else
 976                         dwc3_prepare_one_trb_linear(dep, req, trbs_left--);
 977
 978                 if (!trbs_left)
 979                         return;
 980         }
 981 }
 982
 983 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
 984 {
 985         struct dwc3_gadget_ep_cmd_params params;
 986         struct dwc3_request             *req;
 987         struct dwc3                     *dwc = dep->dwc;
 988         int                             starting;
 989         int                             ret;
 990         u32                             cmd;
 991
 992         starting = !(dep->flags & DWC3_EP_BUSY);
 993
 994         dwc3_prepare_trbs(dep);
 995         req = next_request(&dep->started_list);
 996         if (!req) {
 997                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 998                 return 0;
 999         }
1000
1001         memset(&params, 0, sizeof(params));
1002
1003         if (starting) {
1004                 params.param0 = upper_32_bits(req->trb_dma);
1005                 params.param1 = lower_32_bits(req->trb_dma);
1006                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1007         } else {
1008                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1009         }
1010
1011         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1012         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1013         if (ret < 0) {
1014                 /*
1015                  * FIXME we need to iterate over the list of requests
1016                  * here and stop, unmap, free and del each of the linked
1017                  * requests instead of what we do now.
1018                  */
1019                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1020                                 req->direction);
1021                 list_del(&req->list);
1022                 return ret;
1023         }
1024
1025         dep->flags |= DWC3_EP_BUSY;
1026
1027         if (starting) {
1028                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1029                                 dep->number);
1030                 WARN_ON_ONCE(!dep->resource_index);
1031         }
1032
1033         return 0;
1034 }
1035
1036 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1037                 struct dwc3_ep *dep, u32 cur_uf)
1038 {
1039         u32 uf;
1040
1041         if (list_empty(&dep->pending_list)) {
1042                 dwc3_trace(trace_dwc3_gadget,
1043                                 "ISOC ep %s run out for requests",
1044                                 dep->name);
1045                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1046                 return;
1047         }
1048
1049         /* 4 micro frames in the future */
1050         uf = cur_uf + dep->interval * 4;
1051
1052         __dwc3_gadget_kick_transfer(dep, uf);
1053 }
1054
1055 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1056                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1057 {
1058         u32 cur_uf, mask;
1059
1060         mask = ~(dep->interval - 1);
1061         cur_uf = event->parameters & mask;
1062
1063         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1064 }
1065
1066 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1067 {
1068         struct dwc3             *dwc = dep->dwc;
1069         int                     ret;
1070
1071         if (!dep->endpoint.desc) {
1072                 dwc3_trace(trace_dwc3_gadget,
1073                                 "trying to queue request %p to disabled %s\n",
1074                                 &req->request, dep->endpoint.name);
1075                 return -ESHUTDOWN;
1076         }
1077
1078         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1079                                 &req->request, req->dep->name)) {
1080                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1081                                 &req->request, req->dep->name);
1082                 return -EINVAL;
1083         }
1084
1085         req->request.actual     = 0;
1086         req->request.status     = -EINPROGRESS;
1087         req->direction          = dep->direction;
1088         req->epnum              = dep->number;
1089
1090         trace_dwc3_ep_queue(req);
1091
1092         /*
1093          * We only add to our list of requests now and
1094          * start consuming the list once we get XferNotReady
1095          * IRQ.
1096          *
1097          * That way, we avoid doing anything that we don't need
1098          * to do now and defer it until the point we receive a
1099          * particular token from the Host side.
1100          *
1101          * This will also avoid Host cancelling URBs due to too
1102          * many NAKs.
1103          */
1104         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1105                         dep->direction);
1106         if (ret)
1107                 return ret;
1108
1109         list_add_tail(&req->list, &dep->pending_list);
1110
1111         /*
1112          * If there are no pending requests and the endpoint isn't already
1113          * busy, we will just start the request straight away.
1114          *
1115          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1116          * little bit faster.
1117          */
1118         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1119                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1120                         !(dep->flags & DWC3_EP_BUSY)) {
1121                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1122                 goto out;
1123         }
1124
1125         /*
1126          * There are a few special cases:
1127          *
1128          * 1. XferNotReady with empty list of requests. We need to kick the
1129          *    transfer here in that situation, otherwise we will be NAKing
1130          *    forever. If we get XferNotReady before gadget driver has a
1131          *    chance to queue a request, we will ACK the IRQ but won't be
1132          *    able to receive the data until the next request is queued.
1133          *    The following code is handling exactly that.
1134          *
1135          */
1136         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1137                 /*
1138                  * If xfernotready is already elapsed and it is a case
1139                  * of isoc transfer, then issue END TRANSFER, so that
1140                  * you can receive xfernotready again and can have
1141                  * notion of current microframe.
1142                  */
1143                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1144                         if (list_empty(&dep->started_list)) {
1145                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1146                                 dep->flags = DWC3_EP_ENABLED;
1147                         }
1148                         return 0;
1149                 }
1150
1151                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1152                 if (!ret)
1153                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1154
1155                 goto out;
1156         }
1157
1158         /*
1159          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1160          *    kick the transfer here after queuing a request, otherwise the
1161          *    core may not see the modified TRB(s).
1162          */
1163         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1164                         (dep->flags & DWC3_EP_BUSY) &&
1165                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1166                 WARN_ON_ONCE(!dep->resource_index);
1167                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1168                 goto out;
1169         }
1170
1171         /*
1172          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1173          * right away, otherwise host will not know we have streams to be
1174          * handled.
1175          */
1176         if (dep->stream_capable)
1177                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1178
1179 out:
1180         if (ret && ret != -EBUSY)
1181                 dwc3_trace(trace_dwc3_gadget,
1182                                 "%s: failed to kick transfers\n",
1183                                 dep->name);
1184         if (ret == -EBUSY)
1185                 ret = 0;
1186
1187         return ret;
1188 }
1189
1190 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1191                 struct usb_request *request)
1192 {
1193         dwc3_gadget_ep_free_request(ep, request);
1194 }
1195
1196 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1197 {
1198         struct dwc3_request             *req;
1199         struct usb_request              *request;
1200         struct usb_ep                   *ep = &dep->endpoint;
1201
1202         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1203         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1204         if (!request)
1205                 return -ENOMEM;
1206
1207         request->length = 0;
1208         request->buf = dwc->zlp_buf;
1209         request->complete = __dwc3_gadget_ep_zlp_complete;
1210
1211         req = to_dwc3_request(request);
1212
1213         return __dwc3_gadget_ep_queue(dep, req);
1214 }
1215
1216 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1217         gfp_t gfp_flags)
1218 {
1219         struct dwc3_request             *req = to_dwc3_request(request);
1220         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1221         struct dwc3                     *dwc = dep->dwc;
1222
1223         unsigned long                   flags;
1224
1225         int                             ret;
1226
1227         spin_lock_irqsave(&dwc->lock, flags);
1228         ret = __dwc3_gadget_ep_queue(dep, req);
1229
1230         /*
1231          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1232          * setting request->zero, instead of doing magic, we will just queue an
1233          * extra usb_request ourselves so that it gets handled the same way as
1234          * any other request.
1235          */
1236         if (ret == 0 && request->zero && request->length &&
1237             (request->length % ep->maxpacket == 0))
1238                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1239
1240         spin_unlock_irqrestore(&dwc->lock, flags);
1241
1242         return ret;
1243 }
1244
1245 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1246                 struct usb_request *request)
1247 {
1248         struct dwc3_request             *req = to_dwc3_request(request);
1249         struct dwc3_request             *r = NULL;
1250
1251         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1252         struct dwc3                     *dwc = dep->dwc;
1253
1254         unsigned long                   flags;
1255         int                             ret = 0;
1256
1257         trace_dwc3_ep_dequeue(req);
1258
1259         spin_lock_irqsave(&dwc->lock, flags);
1260
1261         list_for_each_entry(r, &dep->pending_list, list) {
1262                 if (r == req)
1263                         break;
1264         }
1265
1266         if (r != req) {
1267                 list_for_each_entry(r, &dep->started_list, list) {
1268                         if (r == req)
1269                                 break;
1270                 }
1271                 if (r == req) {
1272                         /* wait until it is processed */
1273                         dwc3_stop_active_transfer(dwc, dep->number, true);
1274                         goto out1;
1275                 }
1276                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1277                                 request, ep->name);
1278                 ret = -EINVAL;
1279                 goto out0;
1280         }
1281
1282 out1:
1283         /* giveback the request */
1284         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1285
1286 out0:
1287         spin_unlock_irqrestore(&dwc->lock, flags);
1288
1289         return ret;
1290 }
1291
1292 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1293 {
1294         struct dwc3_gadget_ep_cmd_params        params;
1295         struct dwc3                             *dwc = dep->dwc;
1296         int                                     ret;
1297
1298         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1299                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1300                 return -EINVAL;
1301         }
1302
1303         memset(&params, 0x00, sizeof(params));
1304
1305         if (value) {
1306                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1307                                 (!list_empty(&dep->started_list) ||
1308                                  !list_empty(&dep->pending_list)))) {
1309                         dwc3_trace(trace_dwc3_gadget,
1310                                         "%s: pending request, cannot halt",
1311                                         dep->name);
1312                         return -EAGAIN;
1313                 }
1314
1315                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1316                                 &params);
1317                 if (ret)
1318                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1319                                         dep->name);
1320                 else
1321                         dep->flags |= DWC3_EP_STALL;
1322         } else {
1323
1324                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1325                 if (ret)
1326                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1327                                         dep->name);
1328                 else
1329                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1330         }
1331
1332         return ret;
1333 }
1334
1335 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1336 {
1337         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1338         struct dwc3                     *dwc = dep->dwc;
1339
1340         unsigned long                   flags;
1341
1342         int                             ret;
1343
1344         spin_lock_irqsave(&dwc->lock, flags);
1345         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1346         spin_unlock_irqrestore(&dwc->lock, flags);
1347
1348         return ret;
1349 }
1350
1351 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1352 {
1353         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1354         struct dwc3                     *dwc = dep->dwc;
1355         unsigned long                   flags;
1356         int                             ret;
1357
1358         spin_lock_irqsave(&dwc->lock, flags);
1359         dep->flags |= DWC3_EP_WEDGE;
1360
1361         if (dep->number == 0 || dep->number == 1)
1362                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1363         else
1364                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1365         spin_unlock_irqrestore(&dwc->lock, flags);
1366
1367         return ret;
1368 }
1369
1370 /* -------------------------------------------------------------------------- */
1371
1372 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1373         .bLength        = USB_DT_ENDPOINT_SIZE,
1374         .bDescriptorType = USB_DT_ENDPOINT,
1375         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1376 };
1377
1378 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1379         .enable         = dwc3_gadget_ep0_enable,
1380         .disable        = dwc3_gadget_ep0_disable,
1381         .alloc_request  = dwc3_gadget_ep_alloc_request,
1382         .free_request   = dwc3_gadget_ep_free_request,
1383         .queue          = dwc3_gadget_ep0_queue,
1384         .dequeue        = dwc3_gadget_ep_dequeue,
1385         .set_halt       = dwc3_gadget_ep0_set_halt,
1386         .set_wedge      = dwc3_gadget_ep_set_wedge,
1387 };
1388
1389 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1390         .enable         = dwc3_gadget_ep_enable,
1391         .disable        = dwc3_gadget_ep_disable,
1392         .alloc_request  = dwc3_gadget_ep_alloc_request,
1393         .free_request   = dwc3_gadget_ep_free_request,
1394         .queue          = dwc3_gadget_ep_queue,
1395         .dequeue        = dwc3_gadget_ep_dequeue,
1396         .set_halt       = dwc3_gadget_ep_set_halt,
1397         .set_wedge      = dwc3_gadget_ep_set_wedge,
1398 };
1399
1400 /* -------------------------------------------------------------------------- */
1401
1402 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1403 {
1404         struct dwc3             *dwc = gadget_to_dwc(g);
1405         u32                     reg;
1406
1407         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1408         return DWC3_DSTS_SOFFN(reg);
1409 }
1410
1411 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1412 {
1413         unsigned long           timeout;
1414
1415         int                     ret;
1416         u32                     reg;
1417
1418         u8                      link_state;
1419         u8                      speed;
1420
1421         /*
1422          * According to the Databook Remote wakeup request should
1423          * be issued only when the device is in early suspend state.
1424          *
1425          * We can check that via USB Link State bits in DSTS register.
1426          */
1427         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1428
1429         speed = reg & DWC3_DSTS_CONNECTSPD;
1430         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1431             (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1432                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1433                 return 0;
1434         }
1435
1436         link_state = DWC3_DSTS_USBLNKST(reg);
1437
1438         switch (link_state) {
1439         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1440         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1441                 break;
1442         default:
1443                 dwc3_trace(trace_dwc3_gadget,
1444                                 "can't wakeup from '%s'\n",
1445                                 dwc3_gadget_link_string(link_state));
1446                 return -EINVAL;
1447         }
1448
1449         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1450         if (ret < 0) {
1451                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1452                 return ret;
1453         }
1454
1455         /* Recent versions do this automatically */
1456         if (dwc->revision < DWC3_REVISION_194A) {
1457                 /* write zeroes to Link Change Request */
1458                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1459                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1460                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1461         }
1462
1463         /* poll until Link State changes to ON */
1464         timeout = jiffies + msecs_to_jiffies(100);
1465
1466         while (!time_after(jiffies, timeout)) {
1467                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1468
1469                 /* in HS, means ON */
1470                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1471                         break;
1472         }
1473
1474         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1475                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1476                 return -EINVAL;
1477         }
1478
1479         return 0;
1480 }
1481
1482 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1483 {
1484         struct dwc3             *dwc = gadget_to_dwc(g);
1485         unsigned long           flags;
1486         int                     ret;
1487
1488         spin_lock_irqsave(&dwc->lock, flags);
1489         ret = __dwc3_gadget_wakeup(dwc);
1490         spin_unlock_irqrestore(&dwc->lock, flags);
1491
1492         return ret;
1493 }
1494
1495 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1496                 int is_selfpowered)
1497 {
1498         struct dwc3             *dwc = gadget_to_dwc(g);
1499         unsigned long           flags;
1500
1501         spin_lock_irqsave(&dwc->lock, flags);
1502         g->is_selfpowered = !!is_selfpowered;
1503         spin_unlock_irqrestore(&dwc->lock, flags);
1504
1505         return 0;
1506 }
1507
1508 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1509 {
1510         u32                     reg;
1511         u32                     timeout = 500;
1512
1513         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1514         if (is_on) {
1515                 if (dwc->revision <= DWC3_REVISION_187A) {
1516                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1517                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1518                 }
1519
1520                 if (dwc->revision >= DWC3_REVISION_194A)
1521                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1522                 reg |= DWC3_DCTL_RUN_STOP;
1523
1524                 if (dwc->has_hibernation)
1525                         reg |= DWC3_DCTL_KEEP_CONNECT;
1526
1527                 dwc->pullups_connected = true;
1528         } else {
1529                 reg &= ~DWC3_DCTL_RUN_STOP;
1530
1531                 if (dwc->has_hibernation && !suspend)
1532                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1533
1534                 dwc->pullups_connected = false;
1535         }
1536
1537         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1538
1539         do {
1540                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1541                 if (is_on) {
1542                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1543                                 break;
1544                 } else {
1545                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1546                                 break;
1547                 }
1548                 timeout--;
1549                 if (!timeout)
1550                         return -ETIMEDOUT;
1551                 udelay(1);
1552         } while (1);
1553
1554         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1555                         dwc->gadget_driver
1556                         ? dwc->gadget_driver->function : "no-function",
1557                         is_on ? "connect" : "disconnect");
1558
1559         return 0;
1560 }
1561
1562 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1563 {
1564         struct dwc3             *dwc = gadget_to_dwc(g);
1565         unsigned long           flags;
1566         int                     ret;
1567
1568         is_on = !!is_on;
1569
1570         spin_lock_irqsave(&dwc->lock, flags);
1571         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1572         spin_unlock_irqrestore(&dwc->lock, flags);
1573
1574         return ret;
1575 }
1576
1577 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1578 {
1579         u32                     reg;
1580
1581         /* Enable all but Start and End of Frame IRQs */
1582         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1583                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1584                         DWC3_DEVTEN_CMDCMPLTEN |
1585                         DWC3_DEVTEN_ERRTICERREN |
1586                         DWC3_DEVTEN_WKUPEVTEN |
1587                         DWC3_DEVTEN_ULSTCNGEN |
1588                         DWC3_DEVTEN_CONNECTDONEEN |
1589                         DWC3_DEVTEN_USBRSTEN |
1590                         DWC3_DEVTEN_DISCONNEVTEN);
1591
1592         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1593 }
1594
1595 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1596 {
1597         /* mask all interrupts */
1598         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1599 }
1600
1601 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1602 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1603
1604 /**
1605  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1606  * dwc: pointer to our context structure
1607  *
1608  * The following looks like complex but it's actually very simple. In order to
1609  * calculate the number of packets we can burst at once on OUT transfers, we're
1610  * gonna use RxFIFO size.
1611  *
1612  * To calculate RxFIFO size we need two numbers:
1613  * MDWIDTH = size, in bits, of the internal memory bus
1614  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1615  *
1616  * Given these two numbers, the formula is simple:
1617  *
1618  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1619  *
1620  * 24 bytes is for 3x SETUP packets
1621  * 16 bytes is a clock domain crossing tolerance
1622  *
1623  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1624  */
1625 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1626 {
1627         u32 ram2_depth;
1628         u32 mdwidth;
1629         u32 nump;
1630         u32 reg;
1631
1632         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1633         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1634
1635         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1636         nump = min_t(u32, nump, 16);
1637
1638         /* update NumP */
1639         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1640         reg &= ~DWC3_DCFG_NUMP_MASK;
1641         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1642         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1643 }
1644
1645 static int __dwc3_gadget_start(struct dwc3 *dwc)
1646 {
1647         struct dwc3_ep          *dep;
1648         int                     ret = 0;
1649         u32                     reg;
1650
1651         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1652         reg &= ~(DWC3_DCFG_SPEED_MASK);
1653
1654         /**
1655          * WORKAROUND: DWC3 revision < 2.20a have an issue
1656          * which would cause metastability state on Run/Stop
1657          * bit if we try to force the IP to USB2-only mode.
1658          *
1659          * Because of that, we cannot configure the IP to any
1660          * speed other than the SuperSpeed
1661          *
1662          * Refers to:
1663          *
1664          * STAR#9000525659: Clock Domain Crossing on DCTL in
1665          * USB 2.0 Mode
1666          */
1667         if (dwc->revision < DWC3_REVISION_220A) {
1668                 reg |= DWC3_DCFG_SUPERSPEED;
1669         } else {
1670                 switch (dwc->maximum_speed) {
1671                 case USB_SPEED_LOW:
1672                         reg |= DWC3_DSTS_LOWSPEED;
1673                         break;
1674                 case USB_SPEED_FULL:
1675                         reg |= DWC3_DSTS_FULLSPEED1;
1676                         break;
1677                 case USB_SPEED_HIGH:
1678                         reg |= DWC3_DSTS_HIGHSPEED;
1679                         break;
1680                 case USB_SPEED_SUPER_PLUS:
1681                         reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1682                         break;
1683                 default:
1684                         dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1685                                 dwc->maximum_speed);
1686                         /* fall through */
1687                 case USB_SPEED_SUPER:
1688                         reg |= DWC3_DCFG_SUPERSPEED;
1689                         break;
1690                 }
1691         }
1692         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1693
1694         /*
1695          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1696          * field instead of letting dwc3 itself calculate that automatically.
1697          *
1698          * This way, we maximize the chances that we'll be able to get several
1699          * bursts of data without going through any sort of endpoint throttling.
1700          */
1701         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1702         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1703         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1704
1705         dwc3_gadget_setup_nump(dwc);
1706
1707         /* Start with SuperSpeed Default */
1708         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1709
1710         dep = dwc->eps[0];
1711         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1712                         false);
1713         if (ret) {
1714                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1715                 goto err0;
1716         }
1717
1718         dep = dwc->eps[1];
1719         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1720                         false);
1721         if (ret) {
1722                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1723                 goto err1;
1724         }
1725
1726         /* begin to receive SETUP packets */
1727         dwc->ep0state = EP0_SETUP_PHASE;
1728         dwc3_ep0_out_start(dwc);
1729
1730         dwc3_gadget_enable_irq(dwc);
1731
1732         return 0;
1733
1734 err1:
1735         __dwc3_gadget_ep_disable(dwc->eps[0]);
1736
1737 err0:
1738         return ret;
1739 }
1740
1741 static int dwc3_gadget_start(struct usb_gadget *g,
1742                 struct usb_gadget_driver *driver)
1743 {
1744         struct dwc3             *dwc = gadget_to_dwc(g);
1745         unsigned long           flags;
1746         int                     ret = 0;
1747         int                     irq;
1748
1749         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1750         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1751                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1752         if (ret) {
1753                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1754                                 irq, ret);
1755                 goto err0;
1756         }
1757
1758         spin_lock_irqsave(&dwc->lock, flags);
1759         if (dwc->gadget_driver) {
1760                 dev_err(dwc->dev, "%s is already bound to %s\n",
1761                                 dwc->gadget.name,
1762                                 dwc->gadget_driver->driver.name);
1763                 ret = -EBUSY;
1764                 goto err1;
1765         }
1766
1767         dwc->gadget_driver      = driver;
1768
1769         __dwc3_gadget_start(dwc);
1770         spin_unlock_irqrestore(&dwc->lock, flags);
1771
1772         return 0;
1773
1774 err1:
1775         spin_unlock_irqrestore(&dwc->lock, flags);
1776         free_irq(irq, dwc);
1777
1778 err0:
1779         return ret;
1780 }
1781
1782 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1783 {
1784         dwc3_gadget_disable_irq(dwc);
1785         __dwc3_gadget_ep_disable(dwc->eps[0]);
1786         __dwc3_gadget_ep_disable(dwc->eps[1]);
1787 }
1788
1789 static int dwc3_gadget_stop(struct usb_gadget *g)
1790 {
1791         struct dwc3             *dwc = gadget_to_dwc(g);
1792         unsigned long           flags;
1793         int                     irq;
1794
1795         spin_lock_irqsave(&dwc->lock, flags);
1796         __dwc3_gadget_stop(dwc);
1797         dwc->gadget_driver      = NULL;
1798         spin_unlock_irqrestore(&dwc->lock, flags);
1799
1800         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1801         free_irq(irq, dwc->ev_buf);
1802
1803         return 0;
1804 }
1805
1806 static const struct usb_gadget_ops dwc3_gadget_ops = {
1807         .get_frame              = dwc3_gadget_get_frame,
1808         .wakeup                 = dwc3_gadget_wakeup,
1809         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1810         .pullup                 = dwc3_gadget_pullup,
1811         .udc_start              = dwc3_gadget_start,
1812         .udc_stop               = dwc3_gadget_stop,
1813 };
1814
1815 /* -------------------------------------------------------------------------- */
1816
1817 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1818                 u8 num, u32 direction)
1819 {
1820         struct dwc3_ep                  *dep;
1821         u8                              i;
1822
1823         for (i = 0; i < num; i++) {
1824                 u8 epnum = (i << 1) | (!!direction);
1825
1826                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1827                 if (!dep)
1828                         return -ENOMEM;
1829
1830                 dep->dwc = dwc;
1831                 dep->number = epnum;
1832                 dep->direction = !!direction;
1833                 dwc->eps[epnum] = dep;
1834
1835                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1836                                 (epnum & 1) ? "in" : "out");
1837
1838                 dep->endpoint.name = dep->name;
1839
1840                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1841
1842                 if (epnum == 0 || epnum == 1) {
1843                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1844                         dep->endpoint.maxburst = 1;
1845                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1846                         if (!epnum)
1847                                 dwc->gadget.ep0 = &dep->endpoint;
1848                 } else {
1849                         int             ret;
1850
1851                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1852                         dep->endpoint.max_streams = 15;
1853                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1854                         list_add_tail(&dep->endpoint.ep_list,
1855                                         &dwc->gadget.ep_list);
1856
1857                         ret = dwc3_alloc_trb_pool(dep);
1858                         if (ret)
1859                                 return ret;
1860                 }
1861
1862                 if (epnum == 0 || epnum == 1) {
1863                         dep->endpoint.caps.type_control = true;
1864                 } else {
1865                         dep->endpoint.caps.type_iso = true;
1866                         dep->endpoint.caps.type_bulk = true;
1867                         dep->endpoint.caps.type_int = true;
1868                 }
1869
1870                 dep->endpoint.caps.dir_in = !!direction;
1871                 dep->endpoint.caps.dir_out = !direction;
1872
1873                 INIT_LIST_HEAD(&dep->pending_list);
1874                 INIT_LIST_HEAD(&dep->started_list);
1875         }
1876
1877         return 0;
1878 }
1879
1880 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1881 {
1882         int                             ret;
1883
1884         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1885
1886         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1887         if (ret < 0) {
1888                 dwc3_trace(trace_dwc3_gadget,
1889                                 "failed to allocate OUT endpoints");
1890                 return ret;
1891         }
1892
1893         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1894         if (ret < 0) {
1895                 dwc3_trace(trace_dwc3_gadget,
1896                                 "failed to allocate IN endpoints");
1897                 return ret;
1898         }
1899
1900         return 0;
1901 }
1902
1903 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1904 {
1905         struct dwc3_ep                  *dep;
1906         u8                              epnum;
1907
1908         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1909                 dep = dwc->eps[epnum];
1910                 if (!dep)
1911                         continue;
1912                 /*
1913                  * Physical endpoints 0 and 1 are special; they form the
1914                  * bi-directional USB endpoint 0.
1915                  *
1916                  * For those two physical endpoints, we don't allocate a TRB
1917                  * pool nor do we add them the endpoints list. Due to that, we
1918                  * shouldn't do these two operations otherwise we would end up
1919                  * with all sorts of bugs when removing dwc3.ko.
1920                  */
1921                 if (epnum != 0 && epnum != 1) {
1922                         dwc3_free_trb_pool(dep);
1923                         list_del(&dep->endpoint.ep_list);
1924                 }
1925
1926                 kfree(dep);
1927         }
1928 }
1929
1930 /* -------------------------------------------------------------------------- */
1931
1932 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1933                 struct dwc3_request *req, struct dwc3_trb *trb,
1934                 const struct dwc3_event_depevt *event, int status)
1935 {
1936         unsigned int            count;
1937         unsigned int            s_pkt = 0;
1938         unsigned int            trb_status;
1939
1940         trace_dwc3_complete_trb(dep, trb);
1941
1942         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1943                 /*
1944                  * We continue despite the error. There is not much we
1945                  * can do. If we don't clean it up we loop forever. If
1946                  * we skip the TRB then it gets overwritten after a
1947                  * while since we use them in a ring buffer. A BUG()
1948                  * would help. Lets hope that if this occurs, someone
1949                  * fixes the root cause instead of looking away :)
1950                  */
1951                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1952                                 dep->name, trb);
1953         count = trb->size & DWC3_TRB_SIZE_MASK;
1954
1955         if (dep->direction) {
1956                 if (count) {
1957                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1958                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1959                                 dwc3_trace(trace_dwc3_gadget,
1960                                                 "%s: incomplete IN transfer\n",
1961                                                 dep->name);
1962                                 /*
1963                                  * If missed isoc occurred and there is
1964                                  * no request queued then issue END
1965                                  * TRANSFER, so that core generates
1966                                  * next xfernotready and we will issue
1967                                  * a fresh START TRANSFER.
1968                                  * If there are still queued request
1969                                  * then wait, do not issue either END
1970                                  * or UPDATE TRANSFER, just attach next
1971                                  * request in pending_list during
1972                                  * giveback.If any future queued request
1973                                  * is successfully transferred then we
1974                                  * will issue UPDATE TRANSFER for all
1975                                  * request in the pending_list.
1976                                  */
1977                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1978                         } else {
1979                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1980                                                 dep->name);
1981                                 status = -ECONNRESET;
1982                         }
1983                 } else {
1984                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1985                 }
1986         } else {
1987                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1988                         s_pkt = 1;
1989         }
1990
1991         /*
1992          * We assume here we will always receive the entire data block
1993          * which we should receive. Meaning, if we program RX to
1994          * receive 4K but we receive only 2K, we assume that's all we
1995          * should receive and we simply bounce the request back to the
1996          * gadget driver for further processing.
1997          */
1998         req->request.actual += req->request.length - count;
1999         if (s_pkt)
2000                 return 1;
2001         if ((event->status & DEPEVT_STATUS_LST) &&
2002                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
2003                                 DWC3_TRB_CTRL_HWO)))
2004                 return 1;
2005         if ((event->status & DEPEVT_STATUS_IOC) &&
2006                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2007                 return 1;
2008         return 0;
2009 }
2010
2011 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2012                 const struct dwc3_event_depevt *event, int status)
2013 {
2014         struct dwc3_request     *req;
2015         struct dwc3_trb         *trb;
2016         unsigned int            slot;
2017         unsigned int            i;
2018         int                     ret;
2019
2020         do {
2021                 req = next_request(&dep->started_list);
2022                 if (WARN_ON_ONCE(!req))
2023                         return 1;
2024
2025                 i = 0;
2026                 do {
2027                         slot = req->first_trb_index + i;
2028                         if (slot == DWC3_TRB_NUM - 1)
2029                                 slot++;
2030                         slot %= DWC3_TRB_NUM;
2031                         trb = &dep->trb_pool[slot];
2032
2033                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2034                                         event, status);
2035                         if (ret)
2036                                 break;
2037                 } while (++i < req->request.num_mapped_sgs);
2038
2039                 dwc3_gadget_giveback(dep, req, status);
2040
2041                 if (ret)
2042                         break;
2043         } while (1);
2044
2045         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2046                         list_empty(&dep->started_list)) {
2047                 if (list_empty(&dep->pending_list)) {
2048                         /*
2049                          * If there is no entry in request list then do
2050                          * not issue END TRANSFER now. Just set PENDING
2051                          * flag, so that END TRANSFER is issued when an
2052                          * entry is added into request list.
2053                          */
2054                         dep->flags = DWC3_EP_PENDING_REQUEST;
2055                 } else {
2056                         dwc3_stop_active_transfer(dwc, dep->number, true);
2057                         dep->flags = DWC3_EP_ENABLED;
2058                 }
2059                 return 1;
2060         }
2061
2062         return 1;
2063 }
2064
2065 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2066                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2067 {
2068         unsigned                status = 0;
2069         int                     clean_busy;
2070         u32                     is_xfer_complete;
2071
2072         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2073
2074         if (event->status & DEPEVT_STATUS_BUSERR)
2075                 status = -ECONNRESET;
2076
2077         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2078         if (clean_busy && (is_xfer_complete ||
2079                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2080                 dep->flags &= ~DWC3_EP_BUSY;
2081
2082         /*
2083          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2084          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2085          */
2086         if (dwc->revision < DWC3_REVISION_183A) {
2087                 u32             reg;
2088                 int             i;
2089
2090                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2091                         dep = dwc->eps[i];
2092
2093                         if (!(dep->flags & DWC3_EP_ENABLED))
2094                                 continue;
2095
2096                         if (!list_empty(&dep->started_list))
2097                                 return;
2098                 }
2099
2100                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2101                 reg |= dwc->u1u2;
2102                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2103
2104                 dwc->u1u2 = 0;
2105         }
2106
2107         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2108                 int ret;
2109
2110                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2111                 if (!ret || ret == -EBUSY)
2112                         return;
2113         }
2114 }
2115
2116 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2117                 const struct dwc3_event_depevt *event)
2118 {
2119         struct dwc3_ep          *dep;
2120         u8                      epnum = event->endpoint_number;
2121
2122         dep = dwc->eps[epnum];
2123
2124         if (!(dep->flags & DWC3_EP_ENABLED))
2125                 return;
2126
2127         if (epnum == 0 || epnum == 1) {
2128                 dwc3_ep0_interrupt(dwc, event);
2129                 return;
2130         }
2131
2132         switch (event->endpoint_event) {
2133         case DWC3_DEPEVT_XFERCOMPLETE:
2134                 dep->resource_index = 0;
2135
2136                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2137                         dwc3_trace(trace_dwc3_gadget,
2138                                         "%s is an Isochronous endpoint\n",
2139                                         dep->name);
2140                         return;
2141                 }
2142
2143                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2144                 break;
2145         case DWC3_DEPEVT_XFERINPROGRESS:
2146                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2147                 break;
2148         case DWC3_DEPEVT_XFERNOTREADY:
2149                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2150                         dwc3_gadget_start_isoc(dwc, dep, event);
2151                 } else {
2152                         int active;
2153                         int ret;
2154
2155                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2156
2157                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2158                                         dep->name, active ? "Transfer Active"
2159                                         : "Transfer Not Active");
2160
2161                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2162                         if (!ret || ret == -EBUSY)
2163                                 return;
2164
2165                         dwc3_trace(trace_dwc3_gadget,
2166                                         "%s: failed to kick transfers\n",
2167                                         dep->name);
2168                 }
2169
2170                 break;
2171         case DWC3_DEPEVT_STREAMEVT:
2172                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2173                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2174                                         dep->name);
2175                         return;
2176                 }
2177
2178                 switch (event->status) {
2179                 case DEPEVT_STREAMEVT_FOUND:
2180                         dwc3_trace(trace_dwc3_gadget,
2181                                         "Stream %d found and started",
2182                                         event->parameters);
2183
2184                         break;
2185                 case DEPEVT_STREAMEVT_NOTFOUND:
2186                         /* FALLTHROUGH */
2187                 default:
2188                         dwc3_trace(trace_dwc3_gadget,
2189                                         "unable to find suitable stream\n");
2190                 }
2191                 break;
2192         case DWC3_DEPEVT_RXTXFIFOEVT:
2193                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2194                 break;
2195         case DWC3_DEPEVT_EPCMDCMPLT:
2196                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2197                 break;
2198         }
2199 }
2200
2201 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2202 {
2203         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2204                 spin_unlock(&dwc->lock);
2205                 dwc->gadget_driver->disconnect(&dwc->gadget);
2206                 spin_lock(&dwc->lock);
2207         }
2208 }
2209
2210 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2211 {
2212         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2213                 spin_unlock(&dwc->lock);
2214                 dwc->gadget_driver->suspend(&dwc->gadget);
2215                 spin_lock(&dwc->lock);
2216         }
2217 }
2218
2219 static void dwc3_resume_gadget(struct dwc3 *dwc)
2220 {
2221         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2222                 spin_unlock(&dwc->lock);
2223                 dwc->gadget_driver->resume(&dwc->gadget);
2224                 spin_lock(&dwc->lock);
2225         }
2226 }
2227
2228 static void dwc3_reset_gadget(struct dwc3 *dwc)
2229 {
2230         if (!dwc->gadget_driver)
2231                 return;
2232
2233         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2234                 spin_unlock(&dwc->lock);
2235                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2236                 spin_lock(&dwc->lock);
2237         }
2238 }
2239
2240 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2241 {
2242         struct dwc3_ep *dep;
2243         struct dwc3_gadget_ep_cmd_params params;
2244         u32 cmd;
2245         int ret;
2246
2247         dep = dwc->eps[epnum];
2248
2249         if (!dep->resource_index)
2250                 return;
2251
2252         /*
2253          * NOTICE: We are violating what the Databook says about the
2254          * EndTransfer command. Ideally we would _always_ wait for the
2255          * EndTransfer Command Completion IRQ, but that's causing too
2256          * much trouble synchronizing between us and gadget driver.
2257          *
2258          * We have discussed this with the IP Provider and it was
2259          * suggested to giveback all requests here, but give HW some
2260          * extra time to synchronize with the interconnect. We're using
2261          * an arbitrary 100us delay for that.
2262          *
2263          * Note also that a similar handling was tested by Synopsys
2264          * (thanks a lot Paul) and nothing bad has come out of it.
2265          * In short, what we're doing is:
2266          *
2267          * - Issue EndTransfer WITH CMDIOC bit set
2268          * - Wait 100us
2269          */
2270
2271         cmd = DWC3_DEPCMD_ENDTRANSFER;
2272         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2273         cmd |= DWC3_DEPCMD_CMDIOC;
2274         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2275         memset(&params, 0, sizeof(params));
2276         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2277         WARN_ON_ONCE(ret);
2278         dep->resource_index = 0;
2279         dep->flags &= ~DWC3_EP_BUSY;
2280         udelay(100);
2281 }
2282
2283 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2284 {
2285         u32 epnum;
2286
2287         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2288                 struct dwc3_ep *dep;
2289
2290                 dep = dwc->eps[epnum];
2291                 if (!dep)
2292                         continue;
2293
2294                 if (!(dep->flags & DWC3_EP_ENABLED))
2295                         continue;
2296
2297                 dwc3_remove_requests(dwc, dep);
2298         }
2299 }
2300
2301 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2302 {
2303         u32 epnum;
2304
2305         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2306                 struct dwc3_ep *dep;
2307                 int ret;
2308
2309                 dep = dwc->eps[epnum];
2310                 if (!dep)
2311                         continue;
2312
2313                 if (!(dep->flags & DWC3_EP_STALL))
2314                         continue;
2315
2316                 dep->flags &= ~DWC3_EP_STALL;
2317
2318                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2319                 WARN_ON_ONCE(ret);
2320         }
2321 }
2322
2323 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2324 {
2325         int                     reg;
2326
2327         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2328         reg &= ~DWC3_DCTL_INITU1ENA;
2329         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2330
2331         reg &= ~DWC3_DCTL_INITU2ENA;
2332         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2333
2334         dwc3_disconnect_gadget(dwc);
2335
2336         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2337         dwc->setup_packet_pending = false;
2338         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2339 }
2340
2341 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2342 {
2343         u32                     reg;
2344
2345         /*
2346          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2347          * would cause a missing Disconnect Event if there's a
2348          * pending Setup Packet in the FIFO.
2349          *
2350          * There's no suggested workaround on the official Bug
2351          * report, which states that "unless the driver/application
2352          * is doing any special handling of a disconnect event,
2353          * there is no functional issue".
2354          *
2355          * Unfortunately, it turns out that we _do_ some special
2356          * handling of a disconnect event, namely complete all
2357          * pending transfers, notify gadget driver of the
2358          * disconnection, and so on.
2359          *
2360          * Our suggested workaround is to follow the Disconnect
2361          * Event steps here, instead, based on a setup_packet_pending
2362          * flag. Such flag gets set whenever we have a SETUP_PENDING
2363          * status for EP0 TRBs and gets cleared on XferComplete for the
2364          * same endpoint.
2365          *
2366          * Refers to:
2367          *
2368          * STAR#9000466709: RTL: Device : Disconnect event not
2369          * generated if setup packet pending in FIFO
2370          */
2371         if (dwc->revision < DWC3_REVISION_188A) {
2372                 if (dwc->setup_packet_pending)
2373                         dwc3_gadget_disconnect_interrupt(dwc);
2374         }
2375
2376         dwc3_reset_gadget(dwc);
2377
2378         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2379         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2380         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2381         dwc->test_mode = false;
2382
2383         dwc3_stop_active_transfers(dwc);
2384         dwc3_clear_stall_all_ep(dwc);
2385
2386         /* Reset device address to zero */
2387         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2388         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2389         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2390 }
2391
2392 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2393 {
2394         u32 reg;
2395         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2396
2397         /*
2398          * We change the clock only at SS but I dunno why I would want to do
2399          * this. Maybe it becomes part of the power saving plan.
2400          */
2401
2402         if ((speed != DWC3_DSTS_SUPERSPEED) &&
2403             (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2404                 return;
2405
2406         /*
2407          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2408          * each time on Connect Done.
2409          */
2410         if (!usb30_clock)
2411                 return;
2412
2413         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2414         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2415         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2416 }
2417
2418 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2419 {
2420         struct dwc3_ep          *dep;
2421         int                     ret;
2422         u32                     reg;
2423         u8                      speed;
2424
2425         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2426         speed = reg & DWC3_DSTS_CONNECTSPD;
2427         dwc->speed = speed;
2428
2429         dwc3_update_ram_clk_sel(dwc, speed);
2430
2431         switch (speed) {
2432         case DWC3_DCFG_SUPERSPEED_PLUS:
2433                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2434                 dwc->gadget.ep0->maxpacket = 512;
2435                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2436                 break;
2437         case DWC3_DCFG_SUPERSPEED:
2438                 /*
2439                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2440                  * would cause a missing USB3 Reset event.
2441                  *
2442                  * In such situations, we should force a USB3 Reset
2443                  * event by calling our dwc3_gadget_reset_interrupt()
2444                  * routine.
2445                  *
2446                  * Refers to:
2447                  *
2448                  * STAR#9000483510: RTL: SS : USB3 reset event may
2449                  * not be generated always when the link enters poll
2450                  */
2451                 if (dwc->revision < DWC3_REVISION_190A)
2452                         dwc3_gadget_reset_interrupt(dwc);
2453
2454                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2455                 dwc->gadget.ep0->maxpacket = 512;
2456                 dwc->gadget.speed = USB_SPEED_SUPER;
2457                 break;
2458         case DWC3_DCFG_HIGHSPEED:
2459                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2460                 dwc->gadget.ep0->maxpacket = 64;
2461                 dwc->gadget.speed = USB_SPEED_HIGH;
2462                 break;
2463         case DWC3_DCFG_FULLSPEED2:
2464         case DWC3_DCFG_FULLSPEED1:
2465                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2466                 dwc->gadget.ep0->maxpacket = 64;
2467                 dwc->gadget.speed = USB_SPEED_FULL;
2468                 break;
2469         case DWC3_DCFG_LOWSPEED:
2470                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2471                 dwc->gadget.ep0->maxpacket = 8;
2472                 dwc->gadget.speed = USB_SPEED_LOW;
2473                 break;
2474         }
2475
2476         /* Enable USB2 LPM Capability */
2477
2478         if ((dwc->revision > DWC3_REVISION_194A) &&
2479             (speed != DWC3_DCFG_SUPERSPEED) &&
2480             (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2481                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2482                 reg |= DWC3_DCFG_LPM_CAP;
2483                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2484
2485                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2486                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2487
2488                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2489
2490                 /*
2491                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2492                  * DCFG.LPMCap is set, core responses with an ACK and the
2493                  * BESL value in the LPM token is less than or equal to LPM
2494                  * NYET threshold.
2495                  */
2496                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2497                                 && dwc->has_lpm_erratum,
2498                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2499
2500                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2501                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2502
2503                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2504         } else {
2505                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2506                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2507                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2508         }
2509
2510         dep = dwc->eps[0];
2511         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2512                         false);
2513         if (ret) {
2514                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2515                 return;
2516         }
2517
2518         dep = dwc->eps[1];
2519         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2520                         false);
2521         if (ret) {
2522                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2523                 return;
2524         }
2525
2526         /*
2527          * Configure PHY via GUSB3PIPECTLn if required.
2528          *
2529          * Update GTXFIFOSIZn
2530          *
2531          * In both cases reset values should be sufficient.
2532          */
2533 }
2534
2535 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2536 {
2537         /*
2538          * TODO take core out of low power mode when that's
2539          * implemented.
2540          */
2541
2542         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2543                 spin_unlock(&dwc->lock);
2544                 dwc->gadget_driver->resume(&dwc->gadget);
2545                 spin_lock(&dwc->lock);
2546         }
2547 }
2548
2549 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2550                 unsigned int evtinfo)
2551 {
2552         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2553         unsigned int            pwropt;
2554
2555         /*
2556          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2557          * Hibernation mode enabled which would show up when device detects
2558          * host-initiated U3 exit.
2559          *
2560          * In that case, device will generate a Link State Change Interrupt
2561          * from U3 to RESUME which is only necessary if Hibernation is
2562          * configured in.
2563          *
2564          * There are no functional changes due to such spurious event and we
2565          * just need to ignore it.
2566          *
2567          * Refers to:
2568          *
2569          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2570          * operational mode
2571          */
2572         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2573         if ((dwc->revision < DWC3_REVISION_250A) &&
2574                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2575                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2576                                 (next == DWC3_LINK_STATE_RESUME)) {
2577                         dwc3_trace(trace_dwc3_gadget,
2578                                         "ignoring transition U3 -> Resume");
2579                         return;
2580                 }
2581         }
2582
2583         /*
2584          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2585          * on the link partner, the USB session might do multiple entry/exit
2586          * of low power states before a transfer takes place.
2587          *
2588          * Due to this problem, we might experience lower throughput. The
2589          * suggested workaround is to disable DCTL[12:9] bits if we're
2590          * transitioning from U1/U2 to U0 and enable those bits again
2591          * after a transfer completes and there are no pending transfers
2592          * on any of the enabled endpoints.
2593          *
2594          * This is the first half of that workaround.
2595          *
2596          * Refers to:
2597          *
2598          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2599          * core send LGO_Ux entering U0
2600          */
2601         if (dwc->revision < DWC3_REVISION_183A) {
2602                 if (next == DWC3_LINK_STATE_U0) {
2603                         u32     u1u2;
2604                         u32     reg;
2605
2606                         switch (dwc->link_state) {
2607                         case DWC3_LINK_STATE_U1:
2608                         case DWC3_LINK_STATE_U2:
2609                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2610                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2611                                                 | DWC3_DCTL_ACCEPTU2ENA
2612                                                 | DWC3_DCTL_INITU1ENA
2613                                                 | DWC3_DCTL_ACCEPTU1ENA);
2614
2615                                 if (!dwc->u1u2)
2616                                         dwc->u1u2 = reg & u1u2;
2617
2618                                 reg &= ~u1u2;
2619
2620                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2621                                 break;
2622                         default:
2623                                 /* do nothing */
2624                                 break;
2625                         }
2626                 }
2627         }
2628
2629         switch (next) {
2630         case DWC3_LINK_STATE_U1:
2631                 if (dwc->speed == USB_SPEED_SUPER)
2632                         dwc3_suspend_gadget(dwc);
2633                 break;
2634         case DWC3_LINK_STATE_U2:
2635         case DWC3_LINK_STATE_U3:
2636                 dwc3_suspend_gadget(dwc);
2637                 break;
2638         case DWC3_LINK_STATE_RESUME:
2639                 dwc3_resume_gadget(dwc);
2640                 break;
2641         default:
2642                 /* do nothing */
2643                 break;
2644         }
2645
2646         dwc->link_state = next;
2647 }
2648
2649 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2650                 unsigned int evtinfo)
2651 {
2652         unsigned int is_ss = evtinfo & BIT(4);
2653
2654         /**
2655          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2656          * have a known issue which can cause USB CV TD.9.23 to fail
2657          * randomly.
2658          *
2659          * Because of this issue, core could generate bogus hibernation
2660          * events which SW needs to ignore.
2661          *
2662          * Refers to:
2663          *
2664          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2665          * Device Fallback from SuperSpeed
2666          */
2667         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2668                 return;
2669
2670         /* enter hibernation here */
2671 }
2672
2673 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2674                 const struct dwc3_event_devt *event)
2675 {
2676         switch (event->type) {
2677         case DWC3_DEVICE_EVENT_DISCONNECT:
2678                 dwc3_gadget_disconnect_interrupt(dwc);
2679                 break;
2680         case DWC3_DEVICE_EVENT_RESET:
2681                 dwc3_gadget_reset_interrupt(dwc);
2682                 break;
2683         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2684                 dwc3_gadget_conndone_interrupt(dwc);
2685                 break;
2686         case DWC3_DEVICE_EVENT_WAKEUP:
2687                 dwc3_gadget_wakeup_interrupt(dwc);
2688                 break;
2689         case DWC3_DEVICE_EVENT_HIBER_REQ:
2690                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2691                                         "unexpected hibernation event\n"))
2692                         break;
2693
2694                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2695                 break;
2696         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2697                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2698                 break;
2699         case DWC3_DEVICE_EVENT_EOPF:
2700                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2701                 break;
2702         case DWC3_DEVICE_EVENT_SOF:
2703                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2704                 break;
2705         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2706                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2707                 break;
2708         case DWC3_DEVICE_EVENT_CMD_CMPL:
2709                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2710                 break;
2711         case DWC3_DEVICE_EVENT_OVERFLOW:
2712                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2713                 break;
2714         default:
2715                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2716         }
2717 }
2718
2719 static void dwc3_process_event_entry(struct dwc3 *dwc,
2720                 const union dwc3_event *event)
2721 {
2722         trace_dwc3_event(event->raw);
2723
2724         /* Endpoint IRQ, handle it and return early */
2725         if (event->type.is_devspec == 0) {
2726                 /* depevt */
2727                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2728         }
2729
2730         switch (event->type.type) {
2731         case DWC3_EVENT_TYPE_DEV:
2732                 dwc3_gadget_interrupt(dwc, &event->devt);
2733                 break;
2734         /* REVISIT what to do with Carkit and I2C events ? */
2735         default:
2736                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2737         }
2738 }
2739
2740 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2741 {
2742         struct dwc3 *dwc = evt->dwc;
2743         irqreturn_t ret = IRQ_NONE;
2744         int left;
2745         u32 reg;
2746
2747         left = evt->count;
2748
2749         if (!(evt->flags & DWC3_EVENT_PENDING))
2750                 return IRQ_NONE;
2751
2752         while (left > 0) {
2753                 union dwc3_event event;
2754
2755                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2756
2757                 dwc3_process_event_entry(dwc, &event);
2758
2759                 /*
2760                  * FIXME we wrap around correctly to the next entry as
2761                  * almost all entries are 4 bytes in size. There is one
2762                  * entry which has 12 bytes which is a regular entry
2763                  * followed by 8 bytes data. ATM I don't know how
2764                  * things are organized if we get next to the a
2765                  * boundary so I worry about that once we try to handle
2766                  * that.
2767                  */
2768                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2769                 left -= 4;
2770
2771                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2772         }
2773
2774         evt->count = 0;
2775         evt->flags &= ~DWC3_EVENT_PENDING;
2776         ret = IRQ_HANDLED;
2777
2778         /* Unmask interrupt */
2779         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2780         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2781         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2782
2783         return ret;
2784 }
2785
2786 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2787 {
2788         struct dwc3_event_buffer *evt = _evt;
2789         struct dwc3 *dwc = evt->dwc;
2790         unsigned long flags;
2791         irqreturn_t ret = IRQ_NONE;
2792
2793         spin_lock_irqsave(&dwc->lock, flags);
2794         ret = dwc3_process_event_buf(evt);
2795         spin_unlock_irqrestore(&dwc->lock, flags);
2796
2797         return ret;
2798 }
2799
2800 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2801 {
2802         struct dwc3 *dwc = evt->dwc;
2803         u32 count;
2804         u32 reg;
2805
2806         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2807         count &= DWC3_GEVNTCOUNT_MASK;
2808         if (!count)
2809                 return IRQ_NONE;
2810
2811         evt->count = count;
2812         evt->flags |= DWC3_EVENT_PENDING;
2813
2814         /* Mask interrupt */
2815         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2816         reg |= DWC3_GEVNTSIZ_INTMASK;
2817         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2818
2819         return IRQ_WAKE_THREAD;
2820 }
2821
2822 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2823 {
2824         struct dwc3_event_buffer        *evt = _evt;
2825
2826         return dwc3_check_event_buf(evt);
2827 }
2828
2829 /**
2830  * dwc3_gadget_init - Initializes gadget related registers
2831  * @dwc: pointer to our controller context structure
2832  *
2833  * Returns 0 on success otherwise negative errno.
2834  */
2835 int dwc3_gadget_init(struct dwc3 *dwc)
2836 {
2837         int                                     ret;
2838
2839         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2840                         &dwc->ctrl_req_addr, GFP_KERNEL);
2841         if (!dwc->ctrl_req) {
2842                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2843                 ret = -ENOMEM;
2844                 goto err0;
2845         }
2846
2847         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2848                         &dwc->ep0_trb_addr, GFP_KERNEL);
2849         if (!dwc->ep0_trb) {
2850                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2851                 ret = -ENOMEM;
2852                 goto err1;
2853         }
2854
2855         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2856         if (!dwc->setup_buf) {
2857                 ret = -ENOMEM;
2858                 goto err2;
2859         }
2860
2861         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2862                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2863                         GFP_KERNEL);
2864         if (!dwc->ep0_bounce) {
2865                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2866                 ret = -ENOMEM;
2867                 goto err3;
2868         }
2869
2870         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2871         if (!dwc->zlp_buf) {
2872                 ret = -ENOMEM;
2873                 goto err4;
2874         }
2875
2876         dwc->gadget.ops                 = &dwc3_gadget_ops;
2877         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2878         dwc->gadget.sg_supported        = true;
2879         dwc->gadget.name                = "dwc3-gadget";
2880         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2881
2882         /*
2883          * FIXME We might be setting max_speed to <SUPER, however versions
2884          * <2.20a of dwc3 have an issue with metastability (documented
2885          * elsewhere in this driver) which tells us we can't set max speed to
2886          * anything lower than SUPER.
2887          *
2888          * Because gadget.max_speed is only used by composite.c and function
2889          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2890          * to happen so we avoid sending SuperSpeed Capability descriptor
2891          * together with our BOS descriptor as that could confuse host into
2892          * thinking we can handle super speed.
2893          *
2894          * Note that, in fact, we won't even support GetBOS requests when speed
2895          * is less than super speed because we don't have means, yet, to tell
2896          * composite.c that we are USB 2.0 + LPM ECN.
2897          */
2898         if (dwc->revision < DWC3_REVISION_220A)
2899                 dwc3_trace(trace_dwc3_gadget,
2900                                 "Changing max_speed on rev %08x\n",
2901                                 dwc->revision);
2902
2903         dwc->gadget.max_speed           = dwc->maximum_speed;
2904
2905         /*
2906          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2907          * on ep out.
2908          */
2909         dwc->gadget.quirk_ep_out_aligned_size = true;
2910
2911         /*
2912          * REVISIT: Here we should clear all pending IRQs to be
2913          * sure we're starting from a well known location.
2914          */
2915
2916         ret = dwc3_gadget_init_endpoints(dwc);
2917         if (ret)
2918                 goto err5;
2919
2920         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2921         if (ret) {
2922                 dev_err(dwc->dev, "failed to register udc\n");
2923                 goto err5;
2924         }
2925
2926         return 0;
2927
2928 err5:
2929         kfree(dwc->zlp_buf);
2930
2931 err4:
2932         dwc3_gadget_free_endpoints(dwc);
2933         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2934                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2935
2936 err3:
2937         kfree(dwc->setup_buf);
2938
2939 err2:
2940         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2941                         dwc->ep0_trb, dwc->ep0_trb_addr);
2942
2943 err1:
2944         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2945                         dwc->ctrl_req, dwc->ctrl_req_addr);
2946
2947 err0:
2948         return ret;
2949 }
2950
2951 /* -------------------------------------------------------------------------- */
2952
2953 void dwc3_gadget_exit(struct dwc3 *dwc)
2954 {
2955         usb_del_gadget_udc(&dwc->gadget);
2956
2957         dwc3_gadget_free_endpoints(dwc);
2958
2959         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2960                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2961
2962         kfree(dwc->setup_buf);
2963         kfree(dwc->zlp_buf);
2964
2965         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2966                         dwc->ep0_trb, dwc->ep0_trb_addr);
2967
2968         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2969                         dwc->ctrl_req, dwc->ctrl_req_addr);
2970 }
2971
2972 int dwc3_gadget_suspend(struct dwc3 *dwc)
2973 {
2974         int ret;
2975
2976         if (!dwc->gadget_driver)
2977                 return 0;
2978
2979         ret = dwc3_gadget_run_stop(dwc, false, false);
2980         if (ret < 0)
2981                 return ret;
2982
2983         dwc3_disconnect_gadget(dwc);
2984         __dwc3_gadget_stop(dwc);
2985
2986         return 0;
2987 }
2988
2989 int dwc3_gadget_resume(struct dwc3 *dwc)
2990 {
2991         int                     ret;
2992
2993         if (!dwc->gadget_driver)
2994                 return 0;
2995
2996         ret = __dwc3_gadget_start(dwc);
2997         if (ret < 0)
2998                 goto err0;
2999
3000         ret = dwc3_gadget_run_stop(dwc, true, false);
3001         if (ret < 0)
3002                 goto err1;
3003
3004         return 0;
3005
3006 err1:
3007         __dwc3_gadget_stop(dwc);
3008
3009 err0:
3010         return ret;
3011 }